Tunable filter embedded in cavity

Abstract

A tunable filter integrated with a high quality and high capacitance tuning ratio varactor, a metal-insulator-metal (MIM) capacitor, and an embedded cavity having a 3D inductor with through vias through an alumina ceramic substrate is disclosed. The varactor and the MIM capacitor die are embedded into a blind alumina cavity (BAC) of the alumina ceramic substrate.

Description

[0001] public domain

[0002] The present disclosure relates generally to die packages or modules, and more particularly, but not exclusively, to die packages / modules including tunable filters embedded in cavities in substrates such as alumina ceramic substrates and techniques for manufacturing the same. Background Art

[0003] Integrated circuit technology has made significant progress in increasing computing power through the miniaturization of active components. Packaged devices can be found in many electronic devices, including processors, servers, and radio frequency (RF) integrated circuits. Packaging technology becomes more cost-effective for high-pin-count devices and / or high-volume components.

[0004] Tunable filters with variable capacitors (varactors), which are a type of voltage-controlled capacitor, are desirable in RF front-end (RFFE) applications for both cellular and Wi-Fi communications to cover multiple bands and multiple frequencies. Varactors with large Cmax / Cmin tuning ratios (TR), good isolation, linearity, and Q-factor, as well as high power handling capabilities, are among the key performance indicators (KPIs) used for technology benchmarking.

[0005] For high-performance varactor devices with RF KPIs, there are few technology options for RFFE considerations. For example, silicon-on-insulator (SOI) and microelectromechanical systems (MEMS) varactors on silicon substrates and MEMS varactors on glass substrates have been developed. MEMS varactors have demonstrated high tuning capabilities (e.g., TR > 8). Unfortunately, they require a high-voltage charge pump (e.g., > 20V) for capacitor tuning.

[0006] High-Q 3D through-substrate via (TSV) inductors built on low-loss and high-thermal-conductivity substrates are also desirable for RF filters used in TX paths, allowing not only low insertion loss but also high power handling capabilities. Among the available 3D TSV substrates, neither silicon nor glass can meet the high-Q and high-power handling requirements. Sapphire or alumina can be used as substrates. However, their low TSV etch rates using conventional photolithography (batch processing) mean the use of a sequential laser scanning / drilling process, resulting in low yields.

[0007] Accordingly, a need exists for systems, apparatus, and methods, including those provided herein, that overcome the shortcomings of conventional multi-die modules.

[0008] Overview

[0009] The following is a simplified summary of one or more aspects and / or examples associated with each device and method disclosed herein. As such, the following summary should not be considered an exhaustive overview of all contemplated aspects and / or examples, nor should it be considered to identify key or decisive elements associated with all contemplated aspects and / or examples or to delineate the scope associated with any particular aspect and / or example. Accordingly, the sole purpose of the following summary is to present certain concepts related to one or more aspects and / or examples of the devices and methods disclosed herein in a simplified form prior to the detailed description given below.

[0010] An exemplary tunable filter is disclosed. The tunable filter may include a substrate having a blind substrate cavity (BSC) formed therein. The BSC may penetrate a depth from the front side of the substrate. The tunable filter may also include a varactor / capacitor die within the BSC. The varactor / capacitor die may include a varactor and a capacitor. The tunable filter may further include one or more through-substrate vias (TSVs) in the substrate. Each TSV may extend from the front side of the substrate to the back side of the substrate. The tunable filter may also include one or more front redistribution layer (RDL) metals on the front side of the substrate. The one or more front RDL metals may be electrically connected to the one or more TSVs, the varactors, and the capacitors. The tunable filter may further include one or more backside RDL metals on the back side of the substrate. The one or more backside RDL metals may be electrically connected to the one or more TSVs. The one or more TSVs, the one or more frontside RDL metals, and the one or more backside RDL metals may be configured to form one or more inductors.

[0011] A method for manufacturing an exemplary multi-die module is disclosed. The method may include providing a substrate having a blind substrate cavity (BSC) formed therein. The BSC may penetrate a depth from the front side of the substrate. The method may also include providing a varactor / capacitor die within the BSC. The varactor / capacitor die may include a varactor and a capacitor. The method may further include forming one or more through-substrate vias (TSVs) in the substrate. Each TSV may extend from the front side of the substrate to the back side of the substrate. The method may also include forming one or more front redistribution layer (RDL) metals on the front side of the substrate. The one or more front RDL metals may be electrically connected to the one or more TSVs, the varactors, and the capacitors. The method may further include forming one or more backside RDL metals on the back side of the substrate. The one or more backside RDL metals may be electrically connected to the one or more TSVs. The one or more TSVs, the one or more frontside RDL metals, and the one or more backside RDL metals may be configured to form one or more inductors.

[0012] Other features and advantages associated with the various apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete appreciation of the various aspects of the present disclosure and its many attendant advantages will be readily obtained as the same becomes better understood by reference to the following detailed description considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and do not constitute a limitation of the present disclosure in any way.

[0015] Figure 1 The frequency response of an example tunable filter is illustrated.

[0016] Figure 2 Circuit topologies of example tunable filters are illustrated.

[0017] Figure 3 An example of a conventional tunable filter is illustrated.

[0018] Figure 4 Examples of tunable filters according to one or more aspects of the present disclosure are illustrated.

[0019] Figure 5A Examples of tunable filters according to one or more aspects of the present disclosure are illustrated.

[0020] Figure 5B Illustrated is an expanded view of a 3D inductor of a tunable filter according to one or more aspects of the present disclosure.

[0021] Figure 5C and 5D Illustrated is a front-side view of a tunable filter in accordance with one or more aspects of the present disclosure.

[0022] Figure 6 Examples of varactor / capacitor dies according to one or more aspects of the present disclosure are illustrated.

[0023] Figures 7A-7I An example of various stages in fabricating a tunable filter according to one or more aspects of the present disclosure is illustrated.

[0024] Figure 8 and 9 A flow chart illustrating an example method of fabricating a multi-die module according to one or more aspects of the present disclosure.

[0025] Figure 10 Various electronic devices are illustrated that may utilize one or more aspects of the present disclosure.

[0026] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. As is customary, the features depicted in the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As is customary, certain drawings have been simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Furthermore, similar reference numerals are used throughout the specification and drawings to indicate similar features.

[0027] Detailed description

[0028] Various aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the present teachings. Additionally, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted so as not to obscure the relevant details taught in the present disclosure.

[0029] In some of the described example implementations, examples are identified where various component structures and portions of operations may be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such examples, internal details of known conventional component structures and / or portions of operations may be omitted to help avoid potential confusion of the concepts illustrated in the illustrative embodiments disclosed herein.

[0030] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "having," "includes," and / or "comprising" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] It was mentioned above that tunable filters are desirable for both cellular and Wi-Fi communications in their RF front-end (RFFE) applications to cover multiple bands and multiple frequencies. Figure 1 The frequency response of an example tunable filter is illustrated. As can be seen, by tuning the tunable filter, a desired frequency response pattern can be selected. Desirable characteristics of the tunable filter include (but are not limited to) the following:

[0032] ●Low routing parasitic components;

[0033] ●High adjustable ratio capacitor;

[0034] HQ and precision inductors;

[0035] ●Compact / small footprint;

[0036] ●Performance (low insertion loss);

[0037] ●Low bias voltage.

[0038] Figure 2 The circuit topology of an example tunable filter with five inductors L1-L5 is illustrated. In this example, it is desired that the second and fourth inductors (L2, L4) are very precise. For example, the inductances of L2 and L4 may be within 3% of their desired values. Alternatively or in addition, the inductances of L2 and L4 may be within 3% of each other. The first, third, and fifth inductors (L1, L3, L5) do not need to be as precise as L2 and L4. Nevertheless, high precision is desired. For example, the inductances of L1, L3, and L5 may be within 5% of their desired values. Alternatively or in addition, the inductances of L1, L3, and L5 may be within 5% of each other. This precision of inductors L1-L5 allows for precise tuning of the tunable filter.

[0039] Figure 3 An example of an existing tunable filter 300 is illustrated. As can be seen, the conventional tunable filter 300 includes a varactor die 310, an SMT device 320, a laminate substrate 330, and a ball grid array (BGA) 340. The varactor die 310 and the SMT device 320 are mounted on the laminate substrate. The L2 and L4 inductors are implemented in the SMT device 320, and the L1, L3, and L5 inductors are implemented within the laminate substrate 330. Therefore, large parasitic losses may occur (e.g., due to long paths). In addition, the tuning ratio (TR) (Cmax / Cmin) of the varactor die may be less than 4. In addition, the inductor variation may be greater than 10%. Thermal management may be poor because the varactor die 310 and the SMT device 320 are far away from the BGA 340. In addition, the module size may be large (e.g., greater than 150 μm thick). Furthermore, the cost may be high (the SMT device may be expensive).

[0040] According to various aspects disclosed herein, in order to address the problems associated with conventional tunable filters, a compact cavity-embedded tunable filter is proposed. The proposed tunable filter can be integrated with high-quality (HQ) and high capacitance tuning ratio (HTR) varactors, metal-insulator-metal (MIM) capacitors, and 3D solenoid inductors with through-alumina ceramic substrate vias (TAVs) for next-generation Wi-Fi RFFE applications. The varactor(s) and MIM capacitor die can be embedded in a 3D blind alumina cavity (BAC) ceramic substrate die-to-wafer (D2W) followed by a thermally conductive (TC) dry film filler to planarize the embedded varactor die(s) and alumina surface. The 3D TAV inductor can be formed after device construction, for example, by a copper (Cu) redistribution layer (RDL) process on a thin alumina substrate.

[0041] Some of the different features of the proposed tunable filter include:

[0042] ●Compact cavity embedded tunable filter.

[0043] • Low parasitic integrated inductor (L) and capacitor(s) (C).

[0044] • High capacitance tuning ratio (HTR) varactor (eg, GaAs hyperabrupt (HA) varactor).

[0045] ●HQ and precision inductors achieved through TA V 3D inductors.

[0046] ●High thermal conductivity alumina ceramic substrate and blind cavity.

[0047] Thermally conductive dry film in blind alumina cavity (BAC).

[0048] ●High performance filter with low insertion loss.

[0049] Figure 4 An example of a tunable filter according to one or more aspects of the present disclosure is illustrated. Tunable filter 400 may include a varactor / capacitor die 410 in a substrate 430. Substrate 430 may be a thermally conductive substrate, such as an alumina ceramic substrate. Varactor / capacitor die 410 may be embedded in a BAC 415 of substrate 430. Varactor / capacitor die 410 may include a III-V varactor, such as a GaAs varactor, having a hyperabrupt (HA) junction active layer, which can achieve high TR with a relatively low bias voltage (e.g., ~5V). In one aspect, varactor / capacitor die 410 may also include MIM capacitor(s).

[0050] One or more through substrate vias (TSVs) 450 may also be formed in the substrate 430. It should be noted that the substrate of the TSVs 450 may include materials used for packaging substrates, such as silicon (Si), glass, germanium (Ge), gallium arsenide (GaAs), III-V materials, metal oxides, ceramics, aluminum nitride (AlN), silicon carbide (SiC), etc. When the substrate 430 is an alumina ceramic substrate, the TSVs 450 may also be referred to as through alumina vias (TAVs) 450. The tunable filter 400 may also include two TSVs on the front and back sides of the substrate 430, respectively. Figure 4 4 and 5. The front side RDL metal 474 and the back side RDL metal 424 are formed on the lower side and the upper side of the substrate 430. The front side and / or back side redistribution layer (RDL) metal 474, 424 can be formed of a metal such as copper (Cu), aluminum (Al), etc. The front side RDL metal 474 can be formed in the process of providing the redistribution layer (RDL). One or more inductors 460 can be formed by connecting the TAV 450 with the front side and back side RDL metal 474, 424 to form a loop. As seen, the inductor 460 can be a 3D inductor. External connectors 440 can be formed on the front side RDL metal 474 to provide connections to devices outside the tunable filter 500. Bumps, solder balls, land grid arrays (LGA), etc. can be examples of external connectors 440.

[0051] The illustrated tunable filter 400 (and other proposed tunable filters) can be a cavity embedded in an alumina ceramic substrate 430 and co-integrated with the cavity. Alumina with TAV and BAC can result in low insertion loss (e.g., less than 0.6 dB). Other technical advantages include high TR varactors (e.g., GaAs about 6, MEMS about 8), HQ and precision 3D TAV inductors (e.g., HQ greater than 100, variance less than 3%), improved thermal management (high TC alumina (30 W / mk), vertical Cu TAV paths), size (e.g., less than 100 μm due to the die being embedded in the substrate), and cost (lower cost due to high integration with reduced components).

[0052] Figure 5A Another example of a tunable filter according to one or more aspects of the present disclosure is illustrated. In one aspect, the tunable filter 500 of FIG. 5 can be considered to provide Figure 45. A more detailed view of the tunable filter 400 of FIG. 5. The tunable filter 500 may include a varactor / capacitor die 510 in a substrate 530. The substrate 530 may be thermally conductive, i.e., having a thermal conductivity greater than 2 W / mK. Note that the thermal conductivity of an alumina ceramic substrate is 30 W / mK. The varactor / capacitor die 510 may be embedded in a BSC 515 of the substrate 530 with the aid of an adhesive 580. When the substrate 530 is an alumina ceramic substrate, the BSC 515 may also be referred to as a BAC 515. The BSC / BAC 515 may penetrate a depth from the front side of the substrate 530. The varactor / capacitor die 510 may include a III-V varactor (e.g., a GaAs varactor) having a hyperabrupt (HA) junction active layer. The varactor / capacitor die 510 may also include one or more MIM capacitors.

[0053] One or more TSVs 550 (or TAVs when formed in alumina) may also be formed in substrate 530. Each TAV 550 may extend from the front side of substrate 530 to the back side of substrate 530. On the front side, the exposed front side surfaces of substrate 530 and TAVs 550 may be planar. On the back side, the exposed back side surfaces of substrate 530 and TAVs 550 may be planar.

[0054] One or more backside RDL metals 524 may be formed on the backside of the substrate 530. A backside interlayer dielectric (ILD) 522 may also be formed on the backside of the substrate 530. Figure 5A The backside ILD 522 may encapsulate the backside RDL metal 524. The backside RDL metal 524 may be electrically connected to the TAV 550. For example, the backside RDL metal 524 may be in direct contact with the TAV 550 on the backside.

[0055] The first front side ILD 572 may be formed on the front side of the substrate 530 ( Figure 5A The first front side ILD 572 may be formed such that one or more TAVs 550 are exposed at the front side of the substrate. The first front side ILD 572 may also be formed such that connections to the varactor / capacitor die 510 are exposed.

[0056] One or more front side RDL metals 574 may be formed on the first front side ILD 572 and on the front side of the substrate 530 through the exposed portion of the front side ILD 572. The front side RDL metals 574 may be electrically connected to the TAVs 550. The front side RDL metals 574 may also be electrically connected to the connections of the varactor / capacitor die 510. For example, the front side RDL metals 574 may be in direct contact with the TAVs 550 and / or the connections to the varactor / capacitor die 510 on the front side.

[0057] A second front-side ILD 576 may be formed on the front-side RDL metal 574 and the first front-side ILD 572. Portions of the second front-side ILD 576 may be removed to expose the front-side RDL metal 574. Underbump metallization (UBM) 545 may be formed within the exposed portions of the second front-side ILD 576. External connectors 540 may be formed on corresponding UBMs 545. For example, the external connectors 540 may be in direct contact with the UBMs 545. In this manner, the external connectors 540 provide a means of electrically connecting the tunable filter 500 to devices external to the tunable filter 500. Bumps, solder balls, land grid arrays (LGAs), etc. may be examples of external connectors 540.

[0058] Figure 5B An expanded view of a 3D inductor 560 of a tunable filter according to one or more aspects of the present disclosure is illustrated. It can be seen that the 3D inductor 560 can be formed by forming a conductive loop with the TAV 550, the front-side RDL metal 574, and the back-side RDL metal 524. Generally, there can be one or more 3D inductors 560. Each 3D inductor 560 can include one or more loops, and each loop can include at least one TAV 550 electrically connected to at least one front-side RDL metal 574 and at least one back-side RDL metal 524.

[0059] Figure 5C 5 illustrates a view from the front side of the substrate 530. As can be seen, there may be one or more 3D inductors 560. When there are multiple 3D inductors 560, the multiple 3D inductors 560 may correspond to Figure 2 The inductor of the circuit topology explained. Figure 5B Not shown, one or more 2D inductors may also be formed by connecting some of the frontside RDL metal 574 into one or more loops on the front side of the substrate 530 and / or by connecting some of the backside RDL metal 524 into one or more loops on the back side of the substrate 530.

[0060] It should be noted that different techniques can also be mixed. Figure 5D Another view from the front side of substrate 530 is illustrated. As seen, controller 512 may also be provided within substrate 530. That is, controller 512 may also be embedded within the BAC of substrate 530, and electrical connections to controller 512 may be provided through external connectors 540, UMBs 545, and front-side RDL metal 574. Controller 512 may be formed of a different technology than varactor / capacitor die 510. For example, controller 512 may be CMOS-based.

[0061] Note that controller 512 is merely an example of another die that may be embedded in BSC / BAC 515. Furthermore, while one BSC / BAC 515 is illustrated, there may be any number of BSC / BACs 515. For example, to enhance isolation between varactor / capacitor die 510 and another die (such as CMOS controller 512), two BSC / BACs 515 may be formed, and varactor / capacitor die 510 may be embedded within a first BSC / BAC 515, and another die may be embedded within a second BSC / BAC 515.

[0062] Figure 6 1 illustrates an example of a varactor / capacitor die 510 according to one or more aspects of the present disclosure. As seen, the varactor / capacitor die 510 may include a varactor 610 formed on a first side of a varactor / capacitor substrate 630. Figure 5A As seen in FIG, a second side (opposite the first side) of the varactor / capacitor substrate 630 can be on a lateral surface of the substrate 530 within the BSC / BAC 515. To more securely position the varactor / capacitor die 510, an adhesive 580 can be utilized.

[0063] The varactor 610 may include a hyperabrupt junction active layer. Figure 6 In the embodiment of the present invention, varactor 610 is illustrated as a GaAs varactor. However, in general, varactor 610 is not so limited. For example, varactor 610 can be formed from other III-V materials. Similarly, varactor / capacitor substrate 630 can be formed from III-V materials such as GaAs.

[0064] The varactor / capacitor die 510 may include a MIM capacitor 620 also formed on a first side of a varactor / capacitor substrate 630. The varactor / capacitor connector 640 may be electrically connected to the varactor / capacitor die 510 and / or to the MIM capacitor 620. Figure 5A As seen in FIG, varactor / capacitor connector 640 may also be electrically connected to frontside RDL metal 574. Varactor / capacitor connector 640 may be formed of a metal such as Cu, Al, etc.

[0065] The process flow for manufacturing a tunable filter, such as tunable filters 400, 500, can generally be described as follows:

[0066] ● Form TAV (generally TSV) holes and BAC (generally BSC).

[0067] ●Embed the varactor / capacitor die in the BAC (BSC) of the substrate.

[0068] ● Apply thermally conductive dry film, and apply the first ILD.

[0069] • Forming TAVs (TSVs), backside RDL metal, and frontside RDL metal (e.g., by electroplating);

[0070] ● Apply backside ILD, frontside ILD and frontside passivation /

[0071] ●Form UBM and external connectors.

[0072] Figures 7A-7H Illustrated are examples of stages in manufacturing a tunable filter, such as tunable filters 400 , 500 , in accordance with one or more aspects of the present disclosure. Figure 7A The stage in which the BAC / BSC 515 and TAV / TSV holes 750 may be formed in the substrate 530 is illustrated. Although not illustrated, the back side ( Figure 7A The lower side of the support frame may be supported on a temporary carrier.

[0073] Figure 7B Illustrated is a stage where TAV / TSV holes 750 may be filled with metal (e.g., Cu, Al, W, Pd, Ni, Au, Ta, Ti, Sb, Mo, Ru, etc.) to form TAV / TSV 550. For example, metals such as Cu are preferred because of their low resistance / high conductivity and can be electroplated.

[0074] Figure 7C Illustrated is a stage where varactor / capacitor die 510 may be embedded within substrate 530. Adhesive 580 may be used to attach varactor / capacitor die 510 to BAC 515. In particular, adhesive 580 may be used to attach the second side of varactor / capacitor substrate 630 to a lateral surface of substrate 530 within BAC 515.

[0075] Figure 7D The stage in which a thermally conductive dry film 555 and a first front-side ILD 572 can be formed is illustrated. The dry film 555 can fill the gap between the side surfaces of the BAC 515 and the varactor / capacitor die 510. In one aspect, the thermally conductive dry film 555 and the first front-side ILD 572 can be formed from the same dielectric material. For example, the dielectric material can be applied so that the dry film 555 and the first front-side ILD 572 are integrally formed. In one aspect, the thermal conductivity of the dry film 555 can be at least 2 W / mK.

[0076] Figure 7E Illustrated is a stage where the first frontside ILD 572 may be patterned (eg, by a photomask) to expose the TAVs / TSVs 550 and the varactor / capacitor connections 640 on the frontside of the substrate 530 .

[0077] Figure 7FIllustrated is a stage where frontside RDL metal 574 and backside RDL metal 524 may be formed on the front and back sides, respectively, of substrate 530. In one aspect, double-sided plating / metallization (eg, with Cu, Al, W, etc.) may be performed.

[0078] Figure 7G A stage is illustrated where the front side may be passivated. For example, a second backside ILD 576 may be formed on the front side of the substrate 530. In one aspect, the second backside ILD 576 may be patterned to form openings that expose the frontside RDL metal 574.

[0079] Figure 7H The stage in which connections to external devices are provided is illustrated. For example, a UBM 545 may be formed on the front-side RDL metal 574 within the exposed portion of the second backside ILD 576. External connectors 540 (e.g., bumps, solder balls, land grid array (LGA), C4, CuP, etc.) may then be formed on the UBM 545.

[0080] Figure 8 A flow chart illustrating an example method 800 of manufacturing a tunable filter, such as tunable filters 400 and / or 500 , according to one or more aspects of the present disclosure.

[0081] In block 810, a substrate 530 may be provided. A blind substrate cavity (BSC) 515 may be formed within the substrate 530. The BSC 515 may penetrate a depth from the front side of the substrate 530. In one aspect, block 810 may correspond to Figure 7A The stages explained in .

[0082] At block 820, a varactor / capacitor die 510 may be provided within the BSC 515. The varactor / capacitor die 510 may include a varactor 610 and a capacitor 620 (eg, a MIM capacitor). In one aspect, block 820 may correspond to Figure 7C The stages explained in .

[0083] At block 830, one or more through substrate vias (TSVs) 550 may be formed in the substrate 530. Each TSV 550 may extend from the front side of the substrate 530 to the back side of the substrate 530. In one aspect, block 830 may correspond to Figure 7B The stages explained in .

[0084] At block 840, one or more front side RDL metals 574 may be formed on the front side of substrate 530. Front side RDL metals 574 may be electrically connected to one or more TSVs 550, varactors 610, and capacitors 620. In one aspect, block 840 may correspond to Figure 7F The stages explained in .

[0085] At block 850, one or more backside RDL metals 524 may be formed on the backside of the substrate 530. The backside RDL metals 524 may be electrically connected to the one or more TSVs 550. The one or more TSVs 550, the one or more frontside RDL metals 574, and the one or more backside RDL metals 524 may be configured to form one or more inductors 560. In one aspect, block 850 may correspond to Figure 7F The stages explained in .

[0086] Figure 9 A flow chart illustrating an example method 900 of manufacturing a tunable filter, such as tunable filters 400 and / or 500 , according to one or more aspects of the present disclosure. Figure 6 Can be considered more comprehensive than Figure 5.

[0087] Block 910 may be similar to block 810. That is, in block 910, a substrate 530 may be provided. A blind substrate cavity (BSC) 515 may be formed within the substrate 530. The BSC 515 may penetrate a depth from the front side of the substrate 530. In one aspect, block 910 may correspond to Figure 7A The stages explained in .

[0088] Block 920 may be similar to block 820. That is, at block 920, a varactor / capacitor die 510 may be provided within the BSC 515. The varactor / capacitor die 510 may include a varactor 610 and a capacitor 620 (eg, a MIM capacitor). In one aspect, block 920 may correspond to Figure 7C The stages explained in .

[0089] At block 922 (which is optional), another die 512 may be placed within the BSC 515. In one aspect, block 920 may correspond to Figure 5D .

[0090] At block 925, a thermally conductive dry film 555 and a first front side ILD 572 may be formed. The dry film 555 may be formed to fill the gap between the side surface of the BAC 515 and the varactor / capacitor die 510. The first front side ILD 572 may be formed on the front side of the substrate 530 and patterned to expose the TSVs 550 and the varactor / capacitor connectors 640 of the varactor / capacitor die 510. Block 925 may correspond to Figure 7D and 7E Although not shown, if another die 512 is also provided in the BAC 515, the dry film 555 may also fill the gap between the side surface of the BAC 515 and the other die 512. If desired, the dry film 555 may further fill the gap between the varactor / capacitor die 510 and the other die 512.

[0091] Block 930 may be similar to block 830. That is, at block 930, one or more through substrate vias (TSVs) 550 may be formed in substrate 530. Each TSV 550 may extend from the front side of substrate 530 to the back side of substrate 530. In one aspect, block 930 may correspond to Figure 7B The stages explained in .

[0092] Block 940 may be similar to block 840. That is, at block 940, one or more front side RDL metals 574 may be formed on the front side of substrate 530. Front side RDL metals 574 may be electrically connected to one or more TSVs 550, varactors 610, and capacitors 620. In one aspect, block 940 may correspond to Figure 7F The stages explained in .

[0093] Block 950 may be similar to block 850. That is, at block 950, one or more backside RDL metals 524 may be formed on the backside of the substrate 530. The backside RDL metals 524 may be electrically connected to the one or more TSVs 550. The one or more TSVs 550, the one or more frontside RDL metals 574, and the one or more backside RDL metals 524 may be configured to form one or more inductors 560. In one aspect, block 950 may correspond to Figure 7F The stages explained in .

[0094] In block 960, a second front side ILD 576 may be formed on the front side of the substrate 530, and a back side ILD 522 may be formed on the back side of the substrate 530. The second front side ILD 576 may be patterned to expose a surface of one or more front side RDL metals 574. In one aspect, block 950 may correspond to Figure 7H The stages explained in .

[0095] At block 970, UBM 545 may be formed on the exposed surface of the front side RDL metal 574. Additionally, external connectors 545 may be formed on the UBM 545. In one aspect, block 950 may correspond to Figure 7I The stages explained in .

[0096] Figure 10 Various electronic devices 1000 are illustrated that may be integrated with any of the aforementioned tunable filters in accordance with various aspects of the present disclosure. For example, mobile phone device 1002, laptop computer device 1004, and fixed location terminal device 1006 may each be generally considered user equipment (UE) and may include one or more tunable filters (e.g., tunable filters 400 and / or 500) as described herein. Figure 10The devices 1002, 1004, 1006 illustrated in FIG are merely exemplary. Other electronic devices may also include a die package, such electronic devices including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0097] The devices and functionalities disclosed above can be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all of these files can be provided to a manufacturing facility that manufactures devices based on these files. The resulting products can include semiconductor wafers that are then diced into semiconductor dies and packaged into glass-based antenna devices. The glass-based antenna devices can then be used in the devices described herein.

[0098] Implementation examples are described in the following numbered clauses:

[0099] Item 1: A tunable filter comprising: a substrate having a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a front side of the substrate; a varactor / capacitor die within the BSC, the varactor / capacitor die comprising a varactor and a capacitor; one or more through substrate vias (TSVs) in the substrate, each TSV extending from the front side of the substrate to the back side of the substrate; one or more front side redistribution layer (RDL) metals, the one or more front side RDL metals being on the front side of the substrate and electrically connected to the one or more TSVs, the varactor, and the capacitor; and one or more back side RDL metals being on the back side of the substrate and electrically connected to the one or more TSVs, wherein the one or more TSVs, the one or more front side RDL metals, and the one or more back side RDL metals are configured to form one or more inductors.

[0100] Item 2: The tunable filter of Item 1, wherein the thermal conductivity of the substrate is greater than 2 W / mK.

[0101] Clause 3: The tunable filter of any of clauses 1-2, wherein the substrate is an alumina ceramic substrate, and wherein the one or more TSVs are one or more through-alumina vias (TAVs).

[0102] Clause 4: The tunable filter of any of clauses 1-4, wherein the at least one inductor is a 3D inductor comprising one or more loops, each loop comprising at least one TAV electrically connected to at least one frontside RDL metal and at least one backside RDL metal.

[0103] Clause 5: The tunable filter of clause 4, wherein the one or more inductors comprise a plurality of 3D inductors.

[0104] Item 6: A tunable filter as in any of items 1-5, wherein the one or more TSVs are formed of any one or more of copper (Cu), aluminum (Al), and tungsten (W), or wherein the one or more front-side RDL metals are formed of any one or more of Cu, Al, and W, or wherein the one or more back-side RDL metals are formed of any one or more of Cu, Al, and W, or any combination thereof.

[0105] Clause 7: The tunable filter of any of clauses 1-7, wherein the varactor is a III-V varactor.

[0106] Item 8: The tunable filter of Item 7, wherein the varactor is a gallium arsenide (GaAs) varactor.

[0107] Item 9: The tunable filter of any of items 7-8, wherein the varactor comprises a hyperabrupt junction active layer.

[0108] Item 10: The tunable filter of any of items 7-9, wherein the bias voltage of the varactor is 5V or less.

[0109] Clause 11: The tunable filter of any of clauses 1-10, wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

[0110] Clause 12: The tunable filter of any of clauses 1-11, wherein the varactor / capacitor die further comprises: one or more varactor / capacitor connectors electrically connected to the varactor and capacitor and to the at least one frontside RDL metal.

[0111] Clause 13: A tunable filter as in any of clauses 1-12, wherein the varactor / capacitor die further comprises: a varactor / capacitor substrate, wherein the varactors and capacitors are formed on a first side of the varactor / capacitor substrate, and wherein a second side of the varactor / capacitor substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor / capacitor substrate being opposite to the first side of the varactor / capacitor substrate.

[0112] Clause 14: The tunable filter of any of clauses 1-13, further comprising: another die within the BSC, wherein the another die is made of a technology different from that of the varactor / capacitor die.

[0113] Item 15: The tunable filter of Item 14, wherein the technology of the other die is CMOS.

[0114] Clause 16: A tunable filter as in any of clauses 1-15, wherein the tunable filter is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0115] Item 17: A method of manufacturing a tunable filter, the method comprising: providing a substrate having a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a front side of the substrate; providing a varactor / capacitor die within the BSC, the varactor / capacitor die comprising a varactor and a capacitor; forming one or more through substrate vias (TSVs) in the substrate, each TSV extending from the front side of the substrate to the back side of the substrate; forming one or more front side redistribution layer (RDL) metals on the front side of the substrate and electrically connected to the one or more TSVs, the varactor, and the capacitor; and forming one or more back side RDL metals on the back side of the substrate and electrically connected to the one or more TSVs, wherein the one or more TSVs, the one or more front side RDL metals, and the one or more back side RDL metals are configured to form one or more inductors.

[0116] Item 18: The method of Item 17, wherein the thermal conductivity of the substrate is greater than 2 W / mK.

[0117] Item 19: The method of any of Items 17-18, wherein the substrate is an alumina ceramic substrate, and wherein the one or more TSVs are one or more through-alumina vias (TAVs).

[0118] Clause 20: The method of any of clauses 17-19, wherein the at least one inductor is a 3D inductor comprising one or more loops, each loop comprising at least one TAV electrically connected to at least one frontside RDL metal and to at least one backside RDL metal.

[0119] Clause 21: The method of clause 20, wherein the one or more inductors comprise a plurality of 3D inductors.

[0120] Item 22: The method of any of items 17-21, wherein the one or more TSVs are formed of any one or more of copper (Cu), aluminum (Al), and tungsten (W), or wherein the one or more frontside RDL metals are formed of any one or more of Cu, Al, and W, or wherein the one or more backside RDL metals are formed of any one or more of Cu, Al, and W, or any combination thereof.

[0121] Clause 23: The method of any of clauses 17-22, wherein the varactor is a III-V varactor.

[0122] Item 24: The method of Item 23, wherein the varactor is a gallium arsenide (GaAs) varactor.

[0123] Item 25: The method of any of Items 23-24, wherein the varactor comprises a hyperabrupt junction active layer.

[0124] Clause 26: The method of any of clauses 23-25, wherein the bias voltage of the varactor is 5V or less.

[0125] Clause 27: The method of any of clauses 17-26, wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

[0126] Clause 28: The method of any of clauses 17-27, wherein the varactor / capacitor die further comprises: one or more varactor / capacitor connections electrically connected to the varactor and capacitor and to the at least one frontside RDL metal.

[0127] Clause 29: The method of any of clauses 17-28, wherein the varactor / capacitor die further comprises: a varactor / capacitor substrate, wherein the varactors and capacitors are formed on a first side of the varactor / capacitor substrate, and wherein a second side of the varactor / capacitor substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor / capacitor substrate being opposite to the first side of the varactor / capacitor substrate.

[0128] Clause 30: The method of any of clauses 17-28, further comprising: providing another die within the BSC, wherein the another die is formed of a technology different from that of the varactor / capacitor die.

[0129] As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communication device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, devices carried onboard a motor vehicle, and / or devices typically carried by an individual and / or having communication capabilities. Other types of portable electronic devices (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that is capable of receiving wireless communications and / or navigation signals (such as via short-range wireless, infrared, a wired connection, or other connection), regardless of whether satellite signal reception, assistance data reception, and / or positioning-related processing occurs at the device or the other device. In addition, these terms are intended to include all devices, including wireless and wired communication devices, that are capable of communicating with a core network via a radio access network (RAN), and through the core network, the UE is able to connect to external networks (such as the Internet) and to other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as over a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.). The UE can be implemented by any of several types of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired phones, smartphones, tablets, tracking devices, asset tags, etc. The communication link by which the UE can send signals to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link by which the RAN can send signals to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0130] Wireless communication between electronic devices may be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to provide significantly reduced power consumption and cost while maintaining a similar communication range. BLE was incorporated into the main Bluetooth standard in 2010 with the adoption of Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0131] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as preferred over other examples. Likewise, the term "exemplary" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, a particular feature and / or structure may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the method described herein.

[0132] It should be noted that the terms “connect,” “couple,” or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements via which the two elements are “connected” or “coupled” together, unless the connection is explicitly disclosed as a direct connection.

[0133] Any reference to an element herein using designations such as "first," "second," etc. does not limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Likewise, unless otherwise stated, a set of elements may include one or more elements.

[0134] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0135] Nothing described or illustrated in this application is intended to confer upon the public any component, act, feature, benefit, advantage, or equivalent, regardless of whether such component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0136] In the above detailed description, it can be seen that different features are grouped together in the examples. This manner of disclosure should not be understood as reflecting an intention that the claimed examples have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include fewer than all the features of the individual examples disclosed. Therefore, the appended claims should therefore be considered to be incorporated into this description, with each claim itself being a separate example. Although each claim may be a separate example in itself, it should be noted that although a dependent claim in the claims may refer to a specific combination with one or more claims, other examples may also cover or include a combination of the dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly expressed that a specific combination is not the target. In addition, it is intended that features of a claim may be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0137] Furthermore, it should be noted that the methods, systems, and apparatus disclosed in the present description or claims may be implemented by devices that include means for performing the corresponding actions and / or functionalities of the disclosed methods.

[0138] Furthermore, in some examples, an individual action may be subdivided into or include one or more sub-actions. Such sub-actions may be included in and may be part of the disclosure of the individual action.

[0139] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of the present disclosure as defined in the appended claims. The functions and / or actions in the method claims according to the various examples of the present disclosure described herein do not necessarily have to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid obscuring the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural is also contemplated unless explicitly stated to be limited to the singular.

Claims

1. A tunable filter comprising: a substrate having a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a front side of the substrate; a varactor / capacitor die within the BSC, the varactor / capacitor die comprising a varactor and a capacitor; one or more through-substrate vias (TSVs) in the substrate, each TSV extending from the front side of the substrate to the back side of the substrate; one or more front-side redistribution layer (RDL) metals on the front side of the substrate and electrically connected to the one or more TSVs, the varactor, and the capacitor; as well as one or more backside RDL metals on the backside of the substrate and electrically connected to the one or more TSVs, Wherein the one or more TSVs, the one or more front-side RDL metals, and the one or more back-side RDL metals are configured to form one or more inductors. 2 . The tunable filter according to claim 1 , wherein the thermal conductivity of the substrate is greater than 2 W / mK.

3. The tunable filter according to claim 1, wherein the substrate is an alumina ceramic substrate, and The one or more TSVs are one or more through-aluminum vias (TAVs).

4. The tunable filter of claim 1 , wherein the at least one inductor is a 3D inductor comprising one or more loops, each loop comprising at least one TAV electrically connected to at least one frontside RDL metal and to at least one backside RDL metal.

5. The tunable filter of claim 4, wherein the one or more inductors comprise a plurality of 3D inductors.

6. The tunable filter according to claim 1, wherein the one or more TSVs are formed of any one or more of copper (Cu), aluminum (Al), and tungsten (W), or wherein the one or more front-side RDL metals are formed of any one or both of Cu, Al and W, or wherein the one or more backside RDL metals are formed of any one or both of Cu, Al and W, or Any combination of the above.

7. The tunable filter of claim 1, wherein the varactor is a III-V varactor.

8. The tunable filter of claim 7, wherein the varactor is a gallium arsenide (GaAs) varactor.

9. The tunable filter of claim 7, wherein the varactor comprises a hyperabrupt junction active layer.

10. The tunable filter of claim 7, wherein a bias voltage of the varactor is 5V or less.

11. The tunable filter of claim 1 , wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

12. The tunable filter of claim 1 , wherein the varactor / capacitor die further comprises: One or more varactor / capacitor connectors electrically connected to the varactor and the capacitor and to at least one frontside RDL metal.

13. The tunable filter of claim 1 , wherein the varactor / capacitor die further comprises: Varactor / capacitor substrates, wherein the varactor and the capacitor are formed on a first side of the varactor / capacitor substrate, and The second side of the varactor / capacitor substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor / capacitor substrate being opposite to the first side of the varactor / capacitor substrate.

14. The tunable filter of claim 1 , further comprising: another die within the BSC, wherein the other die is made of a different technology than that of the varactor / capacitor die.

15. The tunable filter of claim 14, wherein the technology of the another die is CMOS.

16. The tunable filter of claim 1 , wherein the tunable filter is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

17. A method of manufacturing a tunable filter, the method comprising: providing a substrate having a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a front side of the substrate; Providing a varactor / capacitor die within the BSC, the varactor / capacitor die comprising a varactor and a capacitor; forming one or more through substrate vias (TSVs) in the substrate, each TSV extending from the front side of the substrate to the back side of the substrate; forming one or more front-side redistribution layer (RDL) metals on the front side of the substrate and in electrical connection with the one or more TSVs, the varactors, and the capacitors; as well as forming one or more backside RDL metals on the backside of the substrate and in electrical connection with the one or more TSVs, Wherein the one or more TSVs, the one or more front-side RDL metals, and the one or more back-side RDL metals are configured to form one or more inductors. The method of claim 17 , wherein the thermal conductivity of the substrate is greater than 2 W / mK.

19. The method according to claim 17, wherein the substrate is an alumina ceramic substrate, and The one or more TSVs are one or more through-aluminum vias (TAVs).

20. The method of claim 17, wherein the at least one inductor is a 3D inductor comprising one or more loops, each loop comprising at least one TAV electrically connected to at least one frontside RDL metal and to at least one backside RDL metal.

21. The method of claim 20, wherein the one or more inductors comprise a plurality of 3D inductors.

22. The method of claim 17, wherein the one or more TSVs are formed of any one or more of copper (Cu), aluminum (Al), and tungsten (W), or wherein the one or more front-side RDL metals are formed of any one or both of Cu, Al and W, or wherein the one or more backside RDL metals are formed of any one or both of Cu, Al and W, or Any combination of the above.

23. The method of claim 17, wherein the varactor is a III-V varactor.

24. The method of claim 23, wherein the varactor is a gallium arsenide (GaAs) varactor.

25. The method of claim 23, wherein the varactor comprises a hyperabrupt junction active layer.

26. The method of claim 23, wherein the bias voltage of the varactor is 5V or less.

27. The method of claim 17, wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

28. The method of claim 17, wherein the varactor / capacitor die further comprises: One or more varactor / capacitor connectors electrically connected to the varactor and the capacitor and to at least one frontside RDL metal.

29. The method of claim 17, wherein the varactor / capacitor die further comprises: Varactor / capacitor substrates, wherein the varactor and the capacitor are formed on a first side of the varactor / capacitor substrate, and The second side of the varactor / capacitor substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor / capacitor substrate being opposite to the first side of the varactor / capacitor substrate.

30. The method of claim 17, further comprising: providing another die within the BSC, wherein the other die is made of a different technology than that of the varactor / capacitor die.

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