SiC semiconductor device

Abstract

This SiC semiconductor device is provided with: a SiC layer of a first conductivity type, which includes a main surface and has an axial channel along the thickness direction; an impurity region of a second conductivity type extending along the axial channel in the SiC layer; a body region of a second conductivity type formed in a region on the main surface side with respect to the impurity region; and a gate structure having a trench penetrating the body region in the main surface, an embedded electrode disposed closer to the bottom wall side of the trench than the main surface, and an embedded insulator disposed closer to the bottom wall side of the trench than the main surface and covering the embedded electrode.

Description

Technical Field

[0001] This application claims priority from Patent Application No. 2022-212611 filed with the Japan Patent Office on December 28, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a SiC semiconductor device. Background Art

[0002] Patent Document 1 (US 2015 / 0028351 A1) discloses an electronic device having an impurity region introduced into a silicon carbide layer by a channel implantation method.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0028351 Summary of the Invention

[0006] The present disclosure provides a novel SiC semiconductor device.

[0007] The present disclosure provides a semiconductor device including: a chip having a side surface; and a decorative pattern formed on the side surface.

[0008] The present disclosure provides a SiC semiconductor device comprising: a first SiC layer of a first conductivity type having a first axial channel along a stacking direction; a second SiC layer of the first conductivity type having a second axial channel along the stacking direction, stacked on the first SiC layer; a first region of the second conductivity type extending along the first axial channel within the first SiC layer in a cross-sectional view and extending in a first extension direction in a top view; and a second region of the second conductivity type extending along the second axial channel within the second SiC layer in a cross-sectional view and extending in a second extension direction intersecting the first extension direction so as to intersect the first region in a top view.

[0009] The present disclosure provides a SiC semiconductor device comprising: a first-conductivity-type SiC layer having a main surface; an active region located in an inner portion of the main surface; a peripheral region located in a peripheral portion of the main surface; and a second-conductivity-type pillar region comprising a plurality of impurity regions formed in the SiC layer at intervals in a horizontal direction along the main surface and located in both the active region and the peripheral region.

[0010] The present disclosure provides a semiconductor device, comprising: a semiconductor layer of a first conductivity type, which includes a main surface and has an axial channel along the thickness direction; an impurity region of a second conductivity type, which extends along the axial channel in the semiconductor layer; a main region of a second conductivity type, which is formed in a region on the main surface side relative to the impurity region; and a gate structure, which has a groove penetrating the main region in the main surface, a buried electrode arranged on the bottom wall side of the groove closer to the main surface, and a buried insulator arranged on the bottom wall side of the groove closer to the main surface and covering the buried electrode.

[0011] The above and other objects, features and effects will become more apparent from the detailed description given with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a plan view showing a SiC semiconductor device according to a first embodiment.

[0013] Figure 2A It is along Figure 1 A cross-sectional view taken along line IIA-IIA is shown.

[0014] Figure 2B It is along Figure 1 A cross-sectional view taken along line IIB-IIB is shown.

[0015] Figure 3A This is a top view showing an example of the layout of a chip (first layer).

[0016] Figure 3B This is a top view showing an example of the layout of a chip (second layer).

[0017] Figure 4A This is a perspective view showing the chip together with the decorative pattern of the first embodiment.

[0018] Figure 4B This is a perspective view showing the chip together with the decorative pattern of the first embodiment.

[0019] Figure 5 This is a three-dimensional diagram showing the main parts of the decorative pattern.

[0020] Figure 6A This is a perspective view showing a chip together with a decorative pattern according to a second embodiment.

[0021] Figure 6B This is a perspective view showing a chip together with a decorative pattern according to a third embodiment.

[0022] Figure 6C This is a perspective view showing a chip together with a decorative pattern according to a fourth embodiment.

[0023] Figure 6DThis is a perspective view showing a chip together with a decorative pattern according to a fifth embodiment.

[0024] Figure 7 This is a cross-sectional perspective view showing a first basic embodiment of the column region.

[0025] Figure 8A 1 is a plan view showing a first layout example of the first basic embodiment.

[0026] Figure 8B 1 is a plan view showing a second layout example of the first basic embodiment.

[0027] Figure 9 This is a cross-sectional perspective view showing a second basic embodiment of the column region.

[0028] Figure 10A 1 is a plan view showing a first layout example of the second basic embodiment.

[0029] Figure 10B 1 is a plan view showing a second layout example of the second basic embodiment.

[0030] Figure 11 This is a cross-sectional perspective view showing a third basic embodiment of the column region.

[0031] Figure 12A 1 is a plan view showing a first layout example of the third basic embodiment.

[0032] Figure 12B 1 is a plan view showing a second layout example of the third basic embodiment.

[0033] Figure 12C 1 is a plan view showing a third layout example of the third basic embodiment.

[0034] Figure 13A This is a graph showing an example of the concentration gradient in the second region (first region).

[0035] Figure 13B This is a graph showing an example of the concentration gradient in the second region (first region).

[0036] Figure 13C This is a graph showing an example of the concentration gradient in the second region (first region).

[0037] Figure 13D This is a graph showing an example of the concentration gradient in the second region (first region).

[0038] Figure 13E This is a graph showing an example of the concentration gradient in the second region (first region).

[0039] Figure 14This is a graph showing a comparative example of the concentration gradient in the second region (first region).

[0040] Figure 15 It is a cross-sectional perspective view showing the column region of the first embodiment.

[0041] Figure 16 Yes Figure 15 Graph showing an example of the concentration gradient in the column region shown.

[0042] Figure 17 It is a cross-sectional perspective view showing a column region of a second embodiment.

[0043] Figure 18 Yes Figure 17 Graph showing an example of the concentration gradient in the column region shown.

[0044] Figure 19 It is a cross-sectional perspective view showing a column region of a third embodiment.

[0045] Figure 20 Yes Figure 19 Graph showing an example of the concentration gradient in the column region shown.

[0046] Figure 21 It is a cross-sectional perspective view showing a column region of a fourth embodiment.

[0047] Figure 22 Yes Figure 21 Graph showing an example of the concentration gradient in the column region shown.

[0048] Figure 23 It is a cross-sectional perspective view showing a column region of a fifth embodiment.

[0049] Figure 24 Yes Figure 23 Graph showing an example of the concentration gradient in the column region shown.

[0050] Figure 25 It is a cross-sectional perspective view showing a column region of a sixth embodiment.

[0051] Figure 26 Yes Figure 25 Graph showing an example of the concentration gradient in the column region shown.

[0052] Figure 27 It is a cross-sectional perspective view showing a column region of a seventh embodiment.

[0053] Figure 28 Yes Figure 27 Graph showing an example of the concentration gradient in the column region shown.

[0054] Figure 29It is a cross-sectional perspective view showing a column region of an eighth embodiment.

[0055] Figure 30 Yes Figure 29 Graph showing an example of the concentration gradient in the column region shown.

[0056] Figure 31 It is a cross-sectional perspective view showing a column region of a ninth embodiment.

[0057] Figure 32 It is a cross-sectional perspective view showing a column region of a tenth embodiment.

[0058] Figure 33 It is a cross-sectional perspective view showing a column region of an eleventh embodiment.

[0059] Figure 34 It is a cross-sectional perspective view showing a column region of a twelfth embodiment.

[0060] Figure 35 It is a top view showing a main part of the active area.

[0061] Figure 36 It is a cross-sectional perspective view showing the gate structure of the first embodiment.

[0062] Figure 37 It is a perspective view showing the structure of the outer peripheral area.

[0063] Figure 38A It is a cross-sectional view showing a main part of the outer peripheral area.

[0064] Figure 38B It is a cross-sectional view showing a main part of the outer peripheral area.

[0065] Figure 39 It is a cross-sectional perspective view showing a gate structure according to a second embodiment.

[0066] Figure 40 This is a schematic diagram showing a wafer used in manufacturing a SiC semiconductor device.

[0067] Figure 41 This is a flowchart showing an example of a method for manufacturing a SiC semiconductor device.

[0068] Figure 42A It is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device.

[0069] Figure 42B Yes Figure 42A A sectional perspective view of the subsequent steps.

[0070] Figure 42C Yes Figure 42B A sectional perspective view of the subsequent steps.

[0071] Figure 42D Yes Figure 42C A sectional perspective view of the subsequent steps.

[0072] Figure 42E Yes Figure 42D A sectional perspective view of the subsequent steps.

[0073] Figure 42F Yes Figure 42E A sectional perspective view of the subsequent steps.

[0074] Figure 42G Yes Figure 42F A sectional perspective view of the subsequent steps.

[0075] Figure 42H Yes Figure 42G A sectional perspective view of the subsequent steps.

[0076] Figure 43A This is a schematic diagram for explaining the crystal orientation measurement process.

[0077] Figure 43B This is a schematic diagram for explaining the crystal orientation measurement process.

[0078] Figure 44A This is a schematic diagram for explaining the ion implantation process.

[0079] Figure 44B This is a schematic diagram for explaining the ion implantation process.

[0080] Figure 45 is a plan view showing a SiC semiconductor device according to a second embodiment.

[0081] Figure 46A It is along Figure 45 A cross-sectional view taken along line XLVIA-XLVIA is shown.

[0082] Figure 46B It is along Figure 45 A cross-sectional view taken along line XLVIB-XLVIB is shown.

[0083] Figure 47A This is a top view showing an example of the layout of a chip (first layer).

[0084] Figure 47B This is a top view showing an example of the layout of a chip (second layer).

[0085] Figure 48 It is a perspective view showing an example of chip layout.

[0086] Figure 49 It is a top view showing a main part of the active area.

[0087] Figure 50 It is a cross-sectional perspective view showing the gate structure of the first embodiment.

[0088] Figure 51 It is a perspective view showing the structure of the outer peripheral area.

[0089] Figure 52A It is a cross-sectional view showing a main part of the outer peripheral area.

[0090] Figure 52B It is a cross-sectional view showing a main part of the outer peripheral area.

[0091] Figure 53 It is a cross-sectional perspective view showing a gate structure according to a second embodiment.

[0092] Figure 54 It is a cross-sectional perspective view showing a gate structure according to a third embodiment.

[0093] Figure 55 It is a cross-sectional perspective view showing a gate structure according to a fourth embodiment.

[0094] Figure 56 It is a cross-sectional perspective view showing a gate structure according to a fifth embodiment.

[0095] Figure 57 FIG. 1 is a top view showing a SiC semiconductor device according to a third embodiment.

[0096] Figure 58A It is along Figure 57 A cross-sectional view taken along line LVIIIA-LVIIIA is shown.

[0097] Figure 58B It is along Figure 57 A cross-sectional view taken along line LVIIIB-LVIIIB is shown.

[0098] Figure 59A It is a top view showing an example of chip layout.

[0099] Figure 59B It is a top view showing an example of chip layout.

[0100] Figure 60 It is a perspective view showing an example of chip layout.

[0101] Figure 61 It is a perspective view showing the structure of the outer peripheral area.

[0102] Figure 62 It is a cross-sectional perspective view showing the diode structure of the first embodiment.

[0103] Figure 63It is a cross-sectional perspective view showing a diode structure according to a second embodiment.

[0104] Figure 64 It is a cross-sectional perspective view showing a diode structure according to a third embodiment.

[0105] Figure 65 It is a cross-sectional perspective view showing a diode structure according to a fourth embodiment.

[0106] Figure 66 It is a cross-sectional perspective view showing a diode structure according to a fifth embodiment.

[0107] Figure 67 This is a perspective view showing a chip together with a decorative pattern according to a first modification.

[0108] Figure 68 This is a perspective view showing a chip together with a decorative pattern according to a second modification.

[0109] Figure 69 This is a perspective view showing a chip together with a decorative pattern according to a third modification.

[0110] Figure 70 This is a perspective view showing a chip together with a decorative pattern according to a fourth modification.

[0111] Figure 71 It is a cross-sectional perspective view showing a column region of a modified example.

[0112] Figure 72 It is a cross-sectional view showing a main part of the outer peripheral area. DETAILED DESCRIPTION

[0113] The following describes specific embodiments in detail with reference to the accompanying drawings. The drawings are schematic and not strictly illustrative, and relative positions, scales, ratios, angles, and the like may not necessarily be consistent. Corresponding structures between the drawings are denoted by the same reference numerals, and duplicate descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions before the omission or simplification apply.

[0114] When the term "substantially" is used in this specification, this term includes not only values (forms) equal to the values (forms) of the comparison object, but also numerical errors (form errors) within a range of ±10% based on the values (forms) of the comparison object. In the following description, terms such as "first," "second," and "third" are used. However, these are symbols given to the names of various structures to clarify the order of description and are not intended to limit the names of various structures.

[0115] In the following description, "p-type" or "n-type" is used to indicate the conductivity type of the semiconductor (impurity), but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth, unless otherwise specified.

[0116] Figure 1 1A is a plan view showing a SiC semiconductor device 1A according to the first embodiment. Figure 2A It is along Figure 1 A cross-sectional view taken along line IIA-IIA is shown. Figure 2B It is along Figure 1 A cross-sectional view taken along line IIB-IIB is shown. Figure 3A It is a plan view showing a layout example of the chip 2 (first layer 8 ). Figure 3B It is a plan view showing a layout example of the chip 2 (second layer 9 ). Figure 4A It is a perspective view showing the chip 2 together with the decorative pattern PT of the first embodiment. Figure 4B It is a perspective view showing the chip 2 together with the decorative pattern PT of the first embodiment.

[0117] Figure 5 It is a perspective view showing the main part of the decorative pattern PT. Figure 6A It is a perspective view showing the chip 2 together with the decorative pattern PT of the second embodiment. Figure 6B 1 is a perspective view showing the chip 2 together with the decorative pattern PT of the third embodiment. Figure 6C It is a perspective view showing the chip 2 together with the decorative pattern PT of the fourth embodiment. Figure 7 1 is a cross-sectional perspective view showing a main portion of the chip 2 together with the pillar region 12 in a first basic form.

[0118] Reference Figures 1 to 7 , SiC semiconductor device 1A includes a chip 2 comprising a SiC single crystal. Chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is composed of a hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape. Hexagonal SiC single crystals include various polytypes, such as 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 is composed of a 4H-SiC single crystal, but chip 2 may also be composed of other polytypes.

[0119] The chip 2 has a first principal surface 3 on one side, a second principal surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first principal surface 3 and the second principal surface 4. The first principal surface 3 and the second principal surface 4 are formed into a quadrilateral when viewed from above (hereinafter referred to as "top view") as viewed from the vertical direction Z. The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first principal surface 3 (second principal surface 4). The first principal surface 3 and the second principal surface 4 can also be formed into a square or a rectangle when viewed from above.

[0120] The first principal surface 3 and the second principal surface 4 are preferably formed by the c-plane of SiC single crystal. In this case, the first principal surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second principal surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0121] In the circumferential direction of the chip 2 (at Figure 1 In the embodiment shown in FIG. 3 , the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first principal surface 3 and face each other in a second direction Y that intersects (specifically, is orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X.

[0122] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. That is, the first side surface 5A and the third side surface 5C are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Furthermore, the second side surface 5B and the fourth side surface 5D are each formed by the a-plane ((11-20) plane) of the SiC single crystal.

[0123] The a-plane is a crystal plane perpendicular to the a-axis, and the m-plane is a crystal plane perpendicular to the m-axis. Of course, the first direction X can also be the m-axis of the SiC single crystal, and the second direction Y can be the a-axis of the SiC single crystal. The first to fourth side surfaces 5A to 5D can also each be formed by a ground surface. The first to fourth side surfaces 5A to 5D can also each be formed by a cleaved surface.

[0124] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Furthermore, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction also extends along the first principal surface 3.

[0125] Reference Figure 7The chip 2 (first principal surface 3 and second principal surface 4) has an off angle θoff, tilted at a predetermined angle toward a predetermined off direction Doff relative to the c-plane of the SiC single crystal. Specifically, the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff. Furthermore, the c-plane of the SiC single crystal is tilted relative to the horizontal plane by the amount of the off angle θoff.

[0126] The off direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X). The off angle θoff may be greater than 0° and less than 10°. The off angle θoff may have a value within any range of greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0127] The off angle θoff is preferably 5° or less. The off angle θoff is particularly preferably 2° or more and 4.5° or less. The off angle θoff is typically set within the range of 4°±0.1°. Of course, this specification does not exclude an off angle θoff of 0° (i.e., an embodiment in which the first principal surface 3 is the front surface relative to the c-plane).

[0128] Chip 2 includes an n-type base layer 6 composed of SiC single crystal. Base layer 6 may also be referred to as a "base SiC layer," "base region," or the like. Base layer 6 extends horizontally in a layered manner, forming a portion of second principal surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, base layer 6 is formed from a substrate made of SiC single crystal (i.e., a SiC substrate). Base layer 6 has the aforementioned off direction Doff and off angle θoff.

[0129] The base layer 6 has a base axis channel CHB extending in the stacking direction. The base axis channel CHB is a region (channel) where the interatomic distance (atomic spacing) is relatively wide relative to the SiC single crystal constituting the base layer 6 and is surrounded by atomic rows forming the crystal axis extending in the stacking direction (crystal growth direction).

[0130] That is, the base axis channel CHB is a region in which the atomic rows are sparse and extend in the stacking direction, and the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The base axis channel CHB is preferably a region surrounded by atomic rows along the low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", "a3", and "c" are all less than 2 (preferably less than 1) with respect to the Miller indices (a1, a2, a3, c) (hereinafter, the same in this specification).

[0131] In this embodiment, the base-axis channel CHB consists of a region surrounded by atomic rows oriented along the c-axis ((0001) axis) of the SiC single crystal. Specifically, the base-axis channel CHB extends along the c-axis and has the aforementioned off direction Doff and off angle θoff. In other words, the base-axis channel CHB is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff.

[0132] The base layer 6 may also have a 1×10 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentration is taken as the peak value. The base layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted using a single pentavalent element. The n-type impurity concentration of the base layer 6 is particularly preferably adjusted using a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted using nitrogen.

[0133] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value within any range of 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0134] The chip 2 includes a stacked portion 7 stacked on a base layer 6. The stacked portion 7 may also be referred to as a "semiconductor layer," "SiC layer," "SiC stacked portion," "semiconductor stacked portion," or the like. The stacked portion 7 has a stacked structure in which a plurality of (two or more) semiconductor layers composed of SiC single crystals are stacked. In this embodiment, a plurality of semiconductor layers are provided as formation layers of a superjunction structure SJ. The number of stacked layers of the plurality of semiconductor layers (superjunction structure SJ) is arbitrary and is appropriately adjusted according to the electrical characteristics to be achieved. Examples of electrical characteristics include withstand voltage (breakdown voltage) and resistance value.

[0135] The number of stacked semiconductor layers (superjunction structure SJ) is typically 2 or more and 5 or less (2, 3, 4, or 5 layers). In this embodiment, stacked portion 7 has a two-layer structure comprising an n-type first layer 8 made of SiC single crystal and an n-type second layer 9 made of SiC single crystal. First layer 8 may also be referred to as "first SiC layer," "first semiconductor layer," etc. Second layer 9 may also be referred to as "second SiC layer," "second semiconductor layer," etc.

[0136] First layer 8 is stacked on base layer 6. First layer 8 extends horizontally in a layered manner, forming the middle portion of chip 2 and portions of first to fourth side surfaces 5A to 5D. First layer 8 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from base layer 6.

[0137] The first layer 8 has a lower end and an upper end. The lower end of the first layer 8 is the starting point of crystal growth, and the upper end of the first layer 8 is the end point of crystal growth. The first layer 8 continuously crystallizes and grows from the base layer 6, so the lower end of the first layer 8 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the first layer 8 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The first layer 8 has an offset direction Doff and an offset angle θoff that are substantially consistent with those of the base layer 6.

[0138] The first layer 8 has a first-axis channel CH1 along the stacking direction. The first-axis channel CH1 is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the first layer 8 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0139] Specifically, the first-axis channel CH1 is a region where atomic rows are sparsely spaced in the stacking direction and where atomic rows (interatomic distance / atomic density) are sparsely spaced in the horizontal direction when viewed from above. The first-axis channel CH1 is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0140] In this method, the first-axis channel CH1 is formed by a region surrounded by atomic rows aligned along the c-axis of the SiC single crystal. Specifically, the first-axis channel CH1 extends along the c-axis and has an off direction Doff and an off angle θoff. In other words, the first-axis channel CH1 is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff.

[0141] The n-type impurity concentration of the first layer 8 is preferably lower than that of the base layer 6. The first layer 8 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the first layer 8 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the first layer 8 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0142] The first layer 8 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the first layer 8 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The first layer 8 preferably includes a pentavalent element other than phosphorus.

[0143] The n-type impurity concentration of first layer 8 is preferably adjusted by at least nitrogen. When first layer 8 includes two or more pentavalent elements, first layer 8 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, first layer 8 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0144] The first layer 8 has a first thickness T1. The first thickness T1 is preferably less than the base thickness TB. The first thickness T1 is preferably 1 μm or greater. The first thickness T1 is preferably 5 μm or less. The first thickness T1 may have a value falling within any range of 1 μm or greater and 1.5 μm or less, 1.5 μm or greater and 2 μm or less, 2 μm or greater and 2.5 μm or less, 2.5 μm or greater and 3 μm or less, 3 μm or greater and 3.5 μm or less, 3.5 μm or greater and 4 μm or less, 4 μm or greater and 4.5 μm or less, and 4.5 μm or greater and 5 μm or less.

[0145] Second layer 9 is stacked on first layer 8. Second layer 9 extends horizontally in a layered manner, forming first principal surface 3 and portions of first to fourth side surfaces 5A to 5D. Second layer 9 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from first layer 8.

[0146] The second layer 9 has a lower end and an upper end. The lower end of the second layer 9 is the starting point of crystal growth, and the upper end of the second layer 9 is the end point of crystal growth. Since the second layer 9 grows continuously from the first layer 8, the lower end of the second layer 9 coincides with the upper end of the first layer 8. The boundary between the first layer 8 and the second layer 9 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The second layer 9 has an offset direction Doff and an offset angle θoff that are substantially consistent with those of the first layer 8.

[0147] The second layer 9 has a second-axis channel CH2 along the stacking direction. The second-axis channel CH2 is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the second layer 9 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0148] Specifically, the second-axis channel CH2 is a region where the atomic rows are sparse, extending in the stacking direction, and the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The second-axis channel CH2 is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0149] In this method, the secondary-axis channel CH2 is formed by a region surrounded by atomic rows oriented along the c-axis of the SiC single crystal. Specifically, the secondary-axis channel CH2 extends along the c-axis and has an off direction Doff and an off angle θoff. In other words, the secondary-axis channel CH2 is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff.

[0150] The n-type impurity concentration of the second layer 9 is preferably lower than that of the base layer 6. The second layer 9 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the second layer 9 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second layer 9 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0151] The n-type impurity concentration of the second layer 9 is preferably substantially equal to the n-type impurity concentration of the first layer 8. Of course, the n-type impurity concentration of the second layer 9 may be different from the n-type impurity concentration of the first layer 8. In this case, the n-type impurity concentration (peak value) of the second layer 9 may be higher than or lower than the n-type impurity concentration (peak value) of the first layer 8.

[0152] The second layer 9 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second layer 9 can be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The second layer 9 preferably includes a pentavalent element other than phosphorus.

[0153] The n-type impurity concentration of second layer 9 is preferably adjusted by at least nitrogen. When second layer 9 includes two or more pentavalent elements, second layer 9 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, second layer 9 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0154] The second layer 9 has a second thickness T2. The second thickness T2 is preferably less than the base thickness TB. The second thickness T2 may be substantially equal to the first thickness T1 or different from the first thickness T1. The second thickness T2 may be greater than the first thickness T1 or less than the first thickness T1.

[0155] The second thickness T2 is preferably 1 μm or greater. The second thickness T2 is preferably 5 μm or less. The second thickness T2 may have a value within any range of 1 μm or greater and 1.5 μm or less, 1.5 μm or greater and 2 μm or less, 2 μm or greater and 2.5 μm or less, 2.5 μm or greater and 3 μm or less, 3 μm or greater and 3.5 μm or less, 3.5 μm or greater and 4 μm or less, 4 μm or greater and 4.5 μm or less, and 4.5 μm or greater and 5 μm or less.

[0156] SiC semiconductor device 1A includes an active region 10 defined within chip 2. Active region 10 is spaced apart from the periphery of chip 2 (first to fourth side surfaces 5A to 5D) in a plan view, within chip 2. Active region 10 is configured in a polygonal shape (in this embodiment, a quadrilateral shape) having four sides parallel to the periphery of chip 2 in a plan view. The planar area of active region 10 is preferably 50% to 90% of the planar area of first principal surface 3.

[0157] SiC semiconductor device 1A includes a peripheral region 11 provided outside active region 10 in chip 2. Peripheral region 11 is provided in a region between the periphery of chip 2 and active region 10 in a plan view. Peripheral region 11 extends in a band along active region 10 in a plan view and is provided in a polygonal ring shape (a quadrilateral ring shape in this embodiment) surrounding active region 10.

[0158] Reference Figure 4A 、 Figure 4B as well as Figure 5 SiC semiconductor device 1A includes a decorative pattern PT according to the first embodiment, formed on at least one of first to fourth side surfaces 5A to 5D. The decorative pattern PT facilitates identification and estimation of the internal structure of the device, as well as identification of other products, based on the appearance of chip 2, thereby improving the usability of SiC semiconductor device 1A. For example, the decorative pattern PT can also be identified through non-destructive inspection (visual inspection) of chip 2.

[0159] In this embodiment, the decorative pattern PT includes at least one (or multiple) first marks Mk1 and at least one (or multiple) second marks Mk2. The decorative pattern PT does not necessarily need to include both the first mark Mk1 and the second mark Mk2, and may be composed of only one of the first mark Mk1 and the second mark Mk2.

[0160] Multiple first marks Mk1 are formed on at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, multiple first marks Mk1 are formed on either or both (in this embodiment, both) of the first side surface 5A and the third side surface 5C extending along the first direction X. The structure on the third side surface 5C is the same as that on the first side surface 5A, so the structure on the first side surface 5A will be described below. The structure on the third side surface 5C is obtained by replacing "first side surface 5A" with "third side surface 5C" in the following description.

[0161] In this embodiment, each of the plurality of first marks Mk1 is formed of a p-type impurity region exposed from first side surface 5A. Each of the plurality of first marks Mk1 is formed in a portion of first side surface 5A that is formed by stacked portion 7. Specifically, the plurality of first marks Mk1 are formed in a region on the stacked portion 7 side relative to base layer 6, such that base layer 6 is exposed from first side surface 5A.

[0162] The plurality of first marks Mk1 are formed in a lower range of the first side surface 5A, which is offset from the upper range of the upper side of the laminated portion 7 in the thickness direction toward the lower side of the laminated portion 7. When the upper range is defined as the first thickness range, the lower range is defined as the second thickness range. When the lower range is defined as the first thickness range, the upper range is defined as the second thickness range. The upper range is the portion of the first to fourth side surfaces 5A to 5D consisting of the second layer 9, and the lower range is the portion of the first to fourth side surfaces 5A to 5D consisting of the first layer 8.

[0163] In this embodiment, the plurality of first marks Mk1 are arranged at intervals in the first direction X within the lower range, defining a plurality of n-type first spaces Sp1 each formed by a portion of the laminated portion 7. Specifically, the plurality of first marks Mk1 are formed on the portion of the first layer 8 on the first side surface 5A, and the plurality of first spaces Sp1 are each formed by a portion of the first layer 8. The plurality of first marks Mk1 and the plurality of first spaces Sp1 form a pn junction.

[0164] The plurality of first marks Mk1 have electrical characteristics (impurities = trivalent elements) that are different from the electrical characteristics (impurities = pentavalent elements) of the plurality of first spaces Sp1. Therefore, the plurality of first marks Mk1 and the plurality of first spaces Sp1 are determined by measuring the electrical characteristics (impurities, concentrations, resistance values, etc.) of the plurality of first marks Mk1 and the plurality of first spaces Sp1. For example, the plurality of first marks Mk1 and the plurality of first spaces Sp1 can be determined using an electron microscope such as a SEM (Scanning Electron Microscope) or a TEM (Transmission Electron Microscope), EBIC (Electron Beam Induced Current) analysis, and the like.

[0165] The plurality of first marks Mk1 are formed in the area on the side of the first layer 8 (lower area) relative to the second layer 9 (upper area). Therefore, the plurality of first marks Mk1 expose the portion formed by the second layer 9 on the first side surface 5A, facing the first main surface 3 via the second layer 9. The plurality of first marks Mk1 expose the entire area formed by the second layer 9 on the first side surface 5A. In other words, the plurality of first marks Mk1 are not formed on the second layer 9. On the other hand, the plurality of first spaces Sp1 are connected to the portion formed by the second layer 9 on the first side surface 5A.

[0166] The first marks Mk1 extend in a vertically long column shape along the stacking direction, forming stripe marks extending along the stacking direction on the first side surface 5A together with the first spaces Sp1. The first marks Mk1 extend along the first axial groove CH1 on the surface of the first side surface 5A.

[0167] Each of the plurality of first marks Mk1 has a lower end portion on the lower side of the first layer 8 and an upper end portion on the upper side of the first layer 8. The lower ends of the plurality of first marks Mk1 are located in a region on the lower side of the first layer 8 relative to the middle of the thickness range of the first layer 8, and the upper ends of the plurality of first marks Mk1 are located in a region on the upper side of the first layer 8 relative to the middle of the thickness range of the first layer 8. In other words, each of the plurality of first marks Mk1 is composed of a single impurity region having a thickness (depth) that crosses the middle of the first layer 8 in the thickness direction.

[0168] The lower ends of the plurality of first marks Mk1 may be formed spaced apart from the lower end of the first layer 8 toward the upper end, facing the base layer 6 across a portion (the lower end) of the first layer 8. In other words, the plurality of first marks Mk1 may expose the entire area of the portion formed by the base layer 6 on the first side surface 5A. The lower ends of the plurality of first marks Mk1 may also be substantially aligned with the lower end of the first layer 8 and connected to the base layer 6.

[0169] The lower ends of the plurality of first markings Mk1 may have an extension portion that crosses the boundary between base layer 6 and first layer 8 and is located within base layer 6. In this case, the extension portion of the plurality of first markings Mk1 is preferably located on the surface portion of the upper end side of base layer 6, exposing substantially the entire area of the portion of first side surface 5A formed by base layer 6. The extension portion of the plurality of first markings Mk1 is preferably formed closer to laminated portion 7 than the middle of the thickness range of base layer 6.

[0170] The upper end of the first mark Mk1 may be formed spaced apart from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may be opposed to the upper end of the first layer 8 across a portion (the upper end) of the first layer 8. The upper end of the first mark Mk1 may also be substantially aligned with the upper end of the first layer 8 and connected to the second layer 9.

[0171] A plurality of second marks Mk2 are formed on at least one side of the first to fourth side surfaces 5A to 5D that is different from the plurality of first marks Mk1. In this embodiment, a plurality of second marks Mk2 are formed on either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D extending along the second direction Y. The structure of the fourth side surface 5D is the same as that of the second side surface 5B, so the structure of the second side surface 5B will be described below. The structure of the fourth side surface 5D is obtained by replacing "second side surface 5B" with "fourth side surface 5D" in the following description.

[0172] In this embodiment, each of the plurality of second marks Mk2 is formed of a p-type impurity region exposed from second side surface 5B. Each of the plurality of second marks Mk2 is formed in a portion of second side surface 5B that is formed by stacked portion 7. Specifically, the plurality of second marks Mk2 are formed in a region on the stacked portion 7 side relative to base layer 6, such that base layer 6 is exposed from second side surface 5B.

[0173] The plurality of second marks Mk2 are formed on the second side surface 5B, offset from the lower area to the upper area. In this manner, the plurality of second marks Mk2 are spaced apart in the second direction Y within the upper area, defining a plurality of n-type second spaces Sp2, each formed by a portion of the laminated portion 7. Specifically, the plurality of second marks Mk2 are formed on the portion of the second layer 9 on the second side surface 5B, and the plurality of second spaces Sp2 are formed by a portion of the second layer 9. The plurality of second marks Mk2 and the plurality of second spaces Sp2 form a pn junction.

[0174] The plurality of second marks Mk2 are formed within a thickness range different from that of the plurality of first marks Mk1 and in an arrangement direction different from that of the plurality of first marks Mk1. The plurality of second spaces Sp2 are formed within a thickness range different from that of the plurality of first spaces Sp1 and in an arrangement direction different from that of the plurality of first spaces Sp1.

[0175] The plurality of second marks Mk2 have electrical properties (impurities = trivalent elements) that differ from the electrical properties (impurities = pentavalent elements) of the plurality of second spaces Sp2. Therefore, the plurality of second marks Mk2 and the plurality of second spaces Sp2 are identified by measuring the electrical properties (impurities, concentrations, resistance values, etc.) of the plurality of second marks Mk2 and the plurality of second spaces Sp2. For example, the plurality of second marks Mk2 and the plurality of second spaces Sp2 can be identified using an electron microscope such as a SEM or TEM, or using EBIC analysis.

[0176] The plurality of second marks Mk2 are formed in an area on the second layer 9 (upper range) relative to the first layer 8 (lower range), facing the base layer 6 via the first layer 8. The plurality of second marks Mk2 expose the portion formed by the first layer 8 on the second side surface 5B. The plurality of second spaces Sp2 are respectively connected to the portion formed by the first layer 8 on the second side surface 5B.

[0177] The second marks Mk2 extend in a vertical columnar shape along the stacking direction and form stripe marks extending in the stacking direction together with the second spaces Sp2 on the second side surface 5B. The second marks Mk2 extend along the second axial channels CH2 on the surface of the second side surface 5B.

[0178] The plurality of second marks Mk2 each have a lower end portion on the lower end side of the second layer 9 and an upper end portion on the upper end side of the second layer 9. The lower ends of the plurality of second marks Mk2 are located in a region on the lower end side of the second layer 9 relative to the middle portion of the thickness range of the second layer 9, and the upper ends of the plurality of second marks Mk2 are located in a region on the upper end side of the second layer 9 relative to the middle portion of the thickness range of the second layer 9. In other words, the plurality of second marks Mk2 each consist of a single impurity region having a thickness (depth) that crosses the middle portion of the second layer 9 along the thickness direction.

[0179] The lower end of the second mark Mk2 may be formed spaced apart from the lower end of the second layer 9 toward the upper end, facing the first layer 8 across a portion (the lower end) of the second layer 9. In other words, the plurality of second marks Mk2 may be formed so that the entire area of the portion formed by the first layer 8 is exposed on the second side surface 5B. The lower end of the second mark Mk2 may also be substantially aligned with the lower end of the first layer 8 and connected to the first layer 8.

[0180] The lower end portion of the second mark Mk2 may have an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In this case, it is preferred that the plurality of extension portions of the second mark Mk2 are located on the surface portion of the upper end side of the first layer 8, so that substantially the entire area of the portion of the second side surface 5B formed by the first layer 8 is exposed.

[0181] The upper end of the second mark Mk2 may be formed spaced apart from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may be opposed to the upper end of the second layer 9 via a portion (the upper end) of the second layer 9. The upper end of the second mark Mk2 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).

[0182] Reference Figure 6A The SiC semiconductor device 1A may include a decorative pattern PT of the second embodiment formed on at least one of the first to fourth side surfaces 5A to 5D. The decorative pattern PT of the second embodiment includes a first difference mark Md1 in addition to the structure of the first embodiment.

[0183] The first difference mark Md1 is formed on one or both of the first side surface 5A and the third side surface 5C in a different thickness range from that of the first mark Mk1 and in a different layout from that of the first mark Mk1. Figure 6A , an example is shown in which the first difference mark Md1 is formed on the first side surface 5A. The structure on the third side surface 5C side is obtained by replacing "the first side surface 5A" with "the third side surface 5C" in the following description.

[0184] In this embodiment, first differential mark Md1 is formed of a p-type impurity region exposed from first side surface 5A. First differential mark Md1 is formed in a portion of first side surface 5A that is formed by stacked portion 7. Specifically, first differential mark Md1 is formed in a region on the stacked portion 7 side relative to base layer 6, exposing base layer 6 from first side surface 5A.

[0185] More specifically, the first difference mark Md1 is formed in the upper range relative to the lower range, overlapping at least one first mark Mk1 in the thickness direction. In this manner, the first difference mark Md1 extends in a stripe shape along the first direction X in the upper range, overlapping multiple first marks Mk1 in the thickness direction.

[0186] In this manner, the first difference mark Md1 extends from one corner of the first side surface 5A to the other corner of the first side surface 5A in the first direction X, and is exposed from both the one corner and the other corner of the first side surface 5A. In other words, the first difference mark Md1 overlaps all of the first mark Mk1 in the thickness direction.

[0187] The first difference mark Md1 has portions protruding from the corners of the second side surface 5B and the fourth side surface 5D. The first difference mark Md1 is formed at the corners of the second side surface 5B (fourth side surface 5D), spaced apart from the outermost second mark Mk2 in the second direction Y, and faces the outermost second mark Mk2 in the second direction Y. The first difference mark Md1 is formed in the portion of the first side surface 5A formed by the second layer 9 and, together with the plurality of first marks Mk1, defines a plurality of first spaces Sp1.

[0188] The first difference mark Md1 has electrical characteristics (impurities = trivalent elements) that differ from the electrical characteristics (impurities = pentavalent elements) of the plurality of first spaces Sp1. Therefore, the plurality of first difference marks Md1 and the plurality of first spaces Sp1 are identified by measuring the electrical characteristics (impurities, concentrations, resistance values, etc.) of the first difference mark Md1 and the plurality of first spaces Sp1. For example, the first difference mark Md1 and the plurality of first spaces Sp1 can be identified using an electron microscope such as a SEM or TEM, or using EBIC analysis.

[0189] The first difference mark Md1 has a lower end portion on the lower side of the second layer 9 and an upper end portion on the upper side of the second layer 9. The lower end portion of the first difference mark Md1 is located in a region on the lower side of the second layer 9 relative to the middle of the thickness range of the second layer 9, while the upper end portion of the first difference mark Md1 is located in a region on the upper side of the second layer 9 relative to the middle of the thickness range of the second layer 9. In other words, the first difference mark Md1 is composed of a single impurity region having a thickness (depth) that crosses the middle of the second layer 9 in the thickness direction.

[0190] The lower end of the first difference mark Md1 may be formed spaced apart from the plurality of first marks Mk1 toward the upper end (first major surface 3) of the second layer 9, so as to face the plurality of first marks Mk1 (plurality of first spaces Sp1) across a portion (lower end) of the second layer 9. The lower end of the first difference mark Md1 may also be substantially aligned with the lower end of the first layer 8.

[0191] In this case, the lower end of the first difference mark Md1 may be formed spaced apart from the upper end of the plurality of first marks Mk1 toward the upper end of the second layer 9, so as to face the plurality of first marks Mk1 across a portion (the lower end) of the second layer 9. Of course, the lower end of the plurality of first difference marks Md1 may also be connected to the upper end of the plurality of first marks Mk1 (the plurality of first spaces Sp1).

[0192] The lower end of the first differential mark Md1 may have an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In this case, the lower end (extension portion) of the first differential mark Md1 may be connected to the plurality of first marks Mk1 within the first layer 8. Of course, the lower end (extension portion) of the first differential mark Md1 may also be formed spaced apart from the plurality of first marks Mk1 toward the upper end of the second layer 9.

[0193] The upper end of the first differential mark Md1 may be formed spaced apart from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may be opposed to the upper end of the second layer 9 via a portion (the upper end) of the second layer 9. The upper end of the first differential mark Md1 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).

[0194] Reference Figure 6B The SiC semiconductor device 1A may include a decorative pattern PT of a third embodiment formed on at least one of the first to fourth side surfaces 5A to 5D. The decorative pattern PT of the third embodiment includes a second difference mark Md2 in addition to the structure of the first embodiment.

[0195] The second difference mark Md2 is formed on one or both of the second side surface 5B and the fourth side surface 5D in a different thickness range from that of the second mark Mk2 and in a different layout from that of the second mark Mk2. Figure 6B , an example in which the second difference mark Md2 is formed on the second side surface 5B is shown. The structure on the fourth side surface 5D side is obtained by replacing "the second side surface 5B" with "the fourth side surface 5D" in the following description.

[0196] In this embodiment, second differential mark Md2 is formed of a p-type impurity region exposed from second side surface 5B. Second differential mark Md2 is formed in the portion of second side surface 5B that is formed by stacked portion 7. Specifically, second differential mark Md2 is formed in a region on the stacked portion 7 side relative to base layer 6, exposing base layer 6 from second side surface 5B.

[0197] More specifically, the second difference mark Md2 is formed in the lower range relative to the upper range, overlapping at least one second mark Mk2 in the thickness direction. In this manner, the second difference mark Md2 extends in a strip-like shape along the second direction Y in the lower range, overlapping multiple second marks Mk2 in the thickness direction.

[0198] In this manner, the second difference mark Md2 extends from one corner of the second side surface 5B to the other corner of the second side surface 5B in the second direction Y, and is exposed from both the one corner and the other corner of the second side surface 5B. In other words, the second difference mark Md2 overlaps all of the second mark Mk2 in the thickness direction.

[0199] The second difference mark Md2 has portions exposed from the corners of the first side surface 5A and the third side surface 5C. The second difference mark Md2 is formed at the corners of the first side surface 5A (third side surface 5C), spaced apart from the outermost first mark Mk1 in the first direction X, and faces the outermost first mark Mk1 in the first direction X. The second difference mark Md2 is formed in the portion of the second side surface 5B formed by the first layer 8, and together with the plurality of second marks Mk2, defines a plurality of second spaces Sp2.

[0200] The second difference mark Md2 has electrical characteristics (impurities = trivalent elements) that differ from the electrical characteristics (impurities = pentavalent elements) of the plurality of second spaces Sp2. Therefore, the plurality of second difference marks Md2 and the plurality of second spaces Sp2 are identified by measuring the electrical characteristics (impurities, concentrations, resistance values, etc.) of the second difference mark Md2 and the plurality of second spaces Sp2. For example, the second difference mark Md2 and the plurality of second spaces Sp2 can be identified using an electron microscope such as a SEM or TEM, or using EBIC analysis.

[0201] The second difference mark Md2 has a lower end portion on the lower end side of the first layer 8 and an upper end portion on the upper end side of the first layer 8. The lower end portion of the second difference mark Md2 is located in a region on the lower end side of the first layer 8 relative to the middle of the thickness range of the first layer 8, while the upper end portion of the second difference mark Md2 is located in a region on the upper end side of the first layer 8 relative to the middle of the thickness range of the first layer 8. In other words, the second difference mark Md2 is composed of a single impurity region having a thickness (depth) that traverses the middle portion of the first layer 8 along the first axial channel CH1.

[0202] The lower end of the second differentiating mark Md2 may be formed spaced apart from the lower end of the first layer 8 (i.e., the base layer 6) toward the upper end (second layer 9) of the first layer 8, so as to face the base layer 6 across a portion (the lower end) of the first layer 8. The lower end of the second differentiating mark Md2 may also be substantially aligned with the lower end of the first layer 8 and connected to the base layer 6. The lower end of the second differentiating mark Md2 may also have an extension portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.

[0203] The upper end of the second difference mark Md2 may be formed spaced apart from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may be opposed to the plurality of second marks Mk2 across a portion (the upper end) of the first layer 8. The upper end of the second difference mark Md2 may be exposed from the upper end of the first layer 8 (i.e., the first main surface 3).

[0204] In this case, the upper end of the second difference mark Md2 may be connected to the lower ends of the plurality of second marks Mk2. Of course, the upper end of the second difference mark Md2 may be formed spaced apart from the lower ends of the plurality of second marks Mk2 toward the lower end of the first layer 8, and may be opposed to the plurality of second marks Mk2 across a portion (lower end) of the first layer 8.

[0205] Reference Figure 6C The SiC semiconductor device 1A may also include a decorative pattern PT according to a fourth embodiment, formed on at least one of the first to fourth side surfaces 5A to 5D. The decorative pattern PT according to the fourth embodiment, in addition to the configuration of the first embodiment, further includes the first difference mark Md1 according to the second embodiment and the second difference mark Md2 according to the third embodiment. The second difference mark Md2 extends within a thickness range different from that of the first difference mark Md1 and in a direction different from that of the first difference mark Md1.

[0206] Reference Figure 6D The SiC semiconductor device 1A may include a decorative pattern PT of the fifth embodiment formed on at least one of the first to fourth side surfaces 5A to 5D. The decorative pattern PT of the fifth embodiment has a structure in which the positions of the plurality of first marks Mk1 and the plurality of second marks Mk2 are reversed.

[0207] Specifically, multiple first marks Mk1 are arranged at intervals in the second direction Y within the lower area of the second side surface 5B, defining multiple n-type first spaces Sp1, each formed by a portion of the laminated portion 7. The multiple first marks Mk1 are formed on the portion of the second side surface 5B formed by the first layer 8, and the multiple first spaces Sp1 are each formed by a portion of the first layer 8. The structure of the first marks Mk1 (first spaces Sp1) of the fifth embodiment is the same as that of the first marks Mk1 (first spaces Sp1) of the first embodiment, except that they are formed on the second side surface 5B.

[0208] On the other hand, multiple second marks Mk2 are arranged at intervals in the first direction X within the upper range of the first side surface 5A, thereby defining multiple n-type second spaces Sp2, each formed by a portion of the laminated portion 7. The multiple second marks Mk2 are each formed on the portion of the first side surface 5A formed by the second layer 9, and the multiple second spaces Sp2 are each formed by a portion of the second layer 9. The structure of the second marks Mk2 (second spaces Sp2) of the fifth embodiment is the same as that of the second marks Mk2 (second spaces Sp2) of the first embodiment, except that they are formed on the first side surface 5A.

[0209] Of course, the structures of the decorative patterns PT of the second to fourth embodiments can also be applied to the decorative pattern PT of the fifth embodiment. In this case, the first difference mark Md1 is formed on the upper side of the second side surface 5B. Furthermore, the second difference mark Md2 is formed on the lower side of the first side surface 5B.

[0210] Refer to Figure 2~ Figure 7 SiC semiconductor device 1A includes, at least in active region 10, p-type pillar regions 12 formed in laminated portion 7. Pillar regions 12 may also be referred to as "pillar layer," "support layer (region)," "p-type layer (region)," "p-type region," etc. Pillar regions 12 are formed in a three-dimensional lattice pattern within laminated portion 7, defining a three-dimensional lattice-shaped n-type drift region 13 formed by a portion of laminated portion 7.

[0211] Pillar region 12 is formed in at least one of the plurality of semiconductor layers constituting stacked portion 7, and forms a superjunction structure SJ with drift region 13 within stacked portion 7. In this embodiment, pillar region 12 has a stacked structure including a plurality of p-type first regions 14 and a plurality of p-type second regions 15.

[0212] The plurality of first regions 14 are formed horizontally spaced apart within the first layer 8, defining a plurality of n-type first drift regions 16 each formed from a portion of the first layer 8. The plurality of first regions 14 and the plurality of first drift regions 16 together form a plurality of first pn junctions with charge balance.

[0213] That is, the plurality of first regions 14 and the plurality of first drift regions 16 form a first superjunction structure SJ1. A charge-balanced state means that, with respect to the plurality of adjacent first regions 14, the depletion layer extending from one first pn junction and the depletion layer extending from another first pn junction are connected within the plurality of first drift regions 16.

[0214] The plurality of first regions 14 are arranged in the first layer 8 at intervals along the first arrangement direction Da1, and are each formed into a stripe shape extending along a first extension direction De1. The first extension direction De1 is a direction intersecting or orthogonal to the first arrangement direction Da1. Specifically, the plurality of first regions 14 are formed into stripes extending along the first extension direction De1, and the plurality of first drift regions 16 are formed into stripes extending along the first extension direction De1.

[0215] In this manner, a plurality of first regions 14 are drawn out from the active region 10 toward the peripheral region 11 (see Figure 3AThat is, the plurality of first regions 14 extend from the portion of the first layer 8 located within the active region 10 to the portion of the first layer 8 located within the peripheral region 11. The plurality of first regions 14 are also arranged in the peripheral region 11 at intervals in the first arrangement direction Da1 and are each formed into a strip extending in the first extension direction De1.

[0216] In addition, the plurality of first regions 14 each have a portion extending from the peripheral region 11 toward either or both (in this embodiment, both) the first side face 5A and the third side face 5C and exposed from either or both (in this embodiment, both) the first side face 5A and the third side face 5C.

[0217] The portions of the plurality of first regions 14 exposed from first side face 5A form a plurality of first marks Mk1 on first side face 5A, and the portions of the plurality of first regions 14 exposed from third side face 5C form a plurality of first marks Mk1 on third side face 5C. In other words, the plurality of first regions 14 include either or both of the plurality of first marks Mk1 exposed from first side face 5A and the plurality of first marks Mk1 exposed from third side face 5C.

[0218] In other words, the plurality of first marks Mk1 are formed using a portion (exposed portion) of each of the plurality of first regions 14. The layout (exposed portion, arrangement direction) of the plurality of first marks Mk1 with respect to the first side surface 5A (third side surface 5C) is appropriately adjusted according to the layout (first arrangement direction Da1, first extension direction De1) of the plurality of first regions 14.

[0219] The plurality of first marks Mk1 do not necessarily need to be formed continuously from the main body of the plurality of first regions 14, and may be formed as separate portions separated from the main body of the plurality of first regions 14. In this case, the plurality of first marks Mk1 are preferably separated from the main body of the plurality of first regions 14 in the peripheral region 11. The description of the first region 14 also applies to the first marks Mk1 (the portion of the first region 14 exposed from the first side surface 5A / third side surface 5C).

[0220] The plurality of first regions 14 are composed of channel regions (first channel regions) extending along the first-axis channel CH1 in the first layer 8 when viewed in cross section. Specifically, the first regions 14 are impurity regions introduced parallel or substantially parallel to the region within the first layer 8 surrounded by atomic rows along the low-index crystal axis (first-axis channel CH1), and extend obliquely with respect to the first principal surface 3.

[0221] Therefore, the first regions 14 have an off direction Doff and an off angle θoff substantially consistent with those of the first axial channel CH1. In other words, the first regions 14 are inclined from the vertical axis toward the off direction Doff by the off angle θoff.

[0222] Each of the plurality of first regions 14 includes a first lower end portion 14a on the lower side of the first layer 8 and a first upper end portion 14b on the upper side of the first layer 8. The first lower end portion 14a is located on the lower side of the first layer 8 relative to the middle of the thickness range of the first layer 8, and the first upper end portion 14b is located on the upper side of the first layer 8 relative to the middle of the thickness range of the first layer 8. In other words, each of the plurality of first regions 14 is composed of a single impurity region having a thickness (depth) that extends across the middle of the first layer 8 along the first axial channel CH1.

[0223] The first lower end portion 14a may be formed spaced apart from the lower end of the first layer 8 toward the upper end, and may face the base layer 6 via a portion (lower end) of the first layer 8. The first lower end portion 14a may also be substantially aligned with the lower end of the first layer 8 and connected to the base layer 6.

[0224] The distance between the lower end of the first layer 8 and the first lower end portion 14a may be 0 μm or more and 2 μm or less. The distance between the lower end of the first layer 8 and the first lower end portion 14a may have a value within any range of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0225] The first lower end portion 14a may include an extension portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. In this case, the thickness of the extension portion of the first lower end portion 14a may be greater than 0 μm and less than 2 μm, relative to the upper end of the base layer 6. The thickness of the extension portion of the first lower end portion 14a may also be within any of the following ranges: greater than 0 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, and greater than 1.5 μm and less than 2 μm.

[0226] The first upper end portion 14b may be formed spaced apart from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may be opposed to the upper end of the first layer 8 across a portion (the upper end) of the first layer 8. The first upper end portion 14b may also be substantially aligned with the upper end of the first layer 8 and connected to the second layer 9.

[0227] The distance between the upper end of the first layer 8 and the first upper end portion 14b may be 0 μm or more and 1 μm or less. The distance between the upper end of the first layer 8 and the first upper end portion 14b may have a value within any range of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0228] The plurality of first regions 14 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The p-type impurity concentration of the first region 14 is preferably adjusted by at least one trivalent element. The p-type impurity concentration of the first region 14 is particularly preferably adjusted by a trivalent element that is heavier than carbon. That is, the first region 14 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first region 14 is adjusted by aluminum.

[0229] Each of the plurality of first regions 14 has a first width W1. The first width W1 is the width of the first region 14 along the first arrangement direction Da1. The first width W1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be greater than the first thickness T1. The first width W1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be greater than the second thickness T2.

[0230] The first width W1 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The first width W1 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The first width W1 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0231] Each of the plurality of first regions 14 has a first region thickness TR1 (first region depth). The first region thickness TR1 may be less than the first thickness T1 of the first layer 8. The first region thickness TR1 may be greater than the first thickness T1. The first region thickness TR1 may be substantially equal to the first thickness T1. The first region thickness TR1 may be less than the second thickness T2 of the second layer 9. The first region thickness TR1 may be greater than the second thickness T2. The first region thickness TR1 may be substantially equal to the second thickness T2.

[0232] The first region thickness TR1 is preferably 1 μm or greater. The first region thickness TR1 is preferably 5 μm or less. The first region thickness TR1 may have a value within any range of 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0233] The first width W1 is preferably smaller than the first thickness T1 of the first layer 8, and the first region thickness TR1 is preferably greater than the first width W1. Specifically, the plurality of first regions 14 preferably each have a first aspect ratio TR1 / W1 extending in a longitudinally elongated columnar shape along the first axial channel CH1. The first aspect ratio TR1 / W1 is the ratio of the first region thickness TR1 to the first width W1. In this case, it is particularly preferred that the first region thickness TR1 is greater than the first thickness T1. For example, the first aspect ratio TR1 / W1 may be greater than 1 and less than 100.

[0234] The plurality of first regions 14 are formed at intervals of a first pitch P1 in the first arrangement direction Da1. The first pitch P1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be greater than the first thickness T1. The first pitch P1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be greater than the second thickness T2.

[0235] The first pitch P1 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The first pitch P1 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The first pitch P1 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0236] The plurality of second regions 15 are formed horizontally spaced apart in the second layer 9, defining a plurality of n-type second drift regions 17 each formed from a portion of the second layer 9. The plurality of second regions 15 and the plurality of second drift regions 17 together form a plurality of second pn junctions with charge balance.

[0237] That is, the plurality of second regions 15 constitute the second layer 9 and the second superjunction structure SJ2. The charge-balanced state means that, for the plurality of adjacent second regions 15, the depletion layer extending from one second pn junction and the depletion layer extending from another second pn junction are connected within the plurality of second drift regions 17.

[0238] The plurality of second regions 15 are formed in the second layer 9 so as to overlap with the plurality of first regions 14 in the stacking direction. Specifically, the plurality of second regions 15 are arranged in the second layer 9 at intervals in a second arrangement direction Da2 that is different from the first arrangement direction Da1, and are each formed in a strip shape extending in the second extension direction De2 that is different from the first extension direction De1.

[0239] The second arrangement direction Da2 intersects the first arrangement direction Da1, and the second extension direction De2 intersects the first extension direction De1. The second extension direction De2 intersects or is orthogonal to the second arrangement direction Da2. Specifically, the plurality of second regions 15 are formed in a stripe shape extending along the second extension direction De2, and the plurality of second drift regions 17 are formed in a stripe shape extending along the second extension direction De2.

[0240] The plurality of second regions 15 intersect the plurality of first regions 14 in a plan view. Specifically, the plurality of second drift regions 17 are connected to the plurality of first drift regions 16 in a lattice pattern at the boundary between the first layer 8 and the second layer 9, and together with the plurality of first drift regions 16 form a three-dimensional lattice-shaped drift region 13. Together with the plurality of first drift regions 16, the plurality of second drift regions 17 form a three-dimensional lattice-shaped current path.

[0241] In this manner, a plurality of second regions 15 are drawn out from the active region 10 toward the peripheral region 11 (see Figure 3B That is, the plurality of second regions 15 extend from the portion of the second layer 9 located within the active region 10 to the portion of the second layer 9 located within the peripheral region 11. The plurality of second regions 15 are also arranged in the peripheral region 11 at intervals in the second arrangement direction Da2, each forming a strip extending in the second extension direction De2. That is, the plurality of second regions 15 also intersect the plurality of first regions 14 in the peripheral region 11.

[0242] In addition, the plurality of second regions 15 each have a portion extending from the peripheral region 11 toward either or both (in this embodiment, both) the second side face 5B and the fourth side face 5D and exposed from either or both (in this embodiment, both) the second side face 5B and the fourth side face 5D.

[0243] The portions of the plurality of second regions 15 exposed from the second side surface 5B form the plurality of second marks Mk2 on the second side surface 5B, and the portions of the plurality of second regions 15 exposed from the fourth side surface 5D form the plurality of second marks Mk2 on the fourth side surface 5D. In other words, the plurality of second regions 15 include either or both of the plurality of second marks Mk2 exposed from the second side surface 5B as the exposed portions and the plurality of second marks Mk2 exposed from the fourth side surface 5D as the exposed portions.

[0244] In other words, the plurality of second marks Mk2 are formed using a portion (exposed portion) of each of the plurality of second regions 15. The layout (exposed portion, arrangement direction) of the plurality of second marks Mk2 with respect to the second side surface 5B (fourth side surface 5D) is appropriately adjusted according to the layout (second arrangement direction Da2, second extension direction De2) of the plurality of second regions 15.

[0245] The plurality of second marks Mk2 do not necessarily need to be formed continuously from the main body of the plurality of second regions 15, and may be formed as separate portions separated from the main body of the plurality of second regions 15. In this case, the plurality of second marks Mk2 are preferably separated from the main body of the plurality of second regions 15 in the peripheral region 11. The description of the second region 15 also applies to the second mark Mk2 (the portion of the second region 15 exposed from the second side surface 5B / fourth side surface 5D).

[0246] The plurality of second regions 15 are formed of channel regions (second channel regions) extending along the second-axis channel CH2 in the second layer 9 when viewed in cross section. Specifically, the second regions 15 are impurity regions introduced parallel or substantially parallel to the region within the second layer 9 surrounded by atomic rows along the low-index crystal axis (second-axis channel CH2), and extend obliquely with respect to the first principal surface 3.

[0247] Therefore, the second regions 15 have an off direction Doff and an off angle θoff substantially consistent with those of the second axial channel CH2. In other words, the second regions 15 are inclined from the vertical axis toward the off direction Doff by the off angle θoff.

[0248] Each of the plurality of second regions 15 includes a second lower end portion 15a on the lower side of the second layer 9 and a second upper end portion 15b on the upper side of the second layer 9. The second lower end portion 15a is located on the lower side of the second layer 9 relative to the middle of the thickness range of the second layer 9, and the second upper end portion 15b is located on the upper side of the second layer 9 relative to the middle of the thickness range of the second layer 9. In other words, each of the plurality of second regions 15 is composed of a single impurity region having a thickness (depth) that extends across the middle of the second layer 9 along the second axial channel CH2.

[0249] The second lower end portion 15a may be formed spaced apart from the lower end of the second layer 9 toward the upper end, and may be opposed to the first layer 8 (plural first regions 14) across a portion (lower end portion) of the second layer 9. The second lower end portion 15a may also be substantially aligned with the lower end of the second layer 9 and connected to the first layer 8.

[0250] The distance between the lower end of the second layer 9 and the second lower end portion 15a may be 0 μm or more and 2 μm or less. The distance between the lower end of the second layer 9 and the second lower end portion 15a may have a value within any range of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0251] The second lower end portion 15a may include an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In this case, the thickness of the extension portion of the second lower end portion 15a may be greater than 0 μm and less than 2 μm, relative to the upper end of the first layer 8. The thickness of the extension portion of the second lower end portion 15a may be within any of the following ranges: greater than 0 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, and greater than 1.5 μm and less than 2 μm.

[0252] The second upper end portion 15b may also be formed spaced apart from the upper end (i.e., first principal surface 3) of the second layer 9 toward the lower end, so as to face the upper end of the second layer 9 across a portion (the upper end) of the second layer 9. In this case, the space between the first principal surface 3 of the second layer 9 and the second upper end portion 15b may also be used as a region for forming device structures (such as other impurity regions). Of course, the second upper end portion 15b may also be exposed from the upper end (i.e., first principal surface 3) of the second layer 9.

[0253] The distance between the upper end of the second layer 9 and the second upper end portion 15b may be 0 μm or more and 1 μm or less. The distance between the upper end of the second layer 9 and the second upper end portion 15b may have a value within any range of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0254] The second regions 15 may also have a size of 1×10 15 cm -3 Above and 1×10 18 cm -3 The p-type impurity concentration (peak value) of the second region 15 may be equal to or greater than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the second region 15 may be lower than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the second region 15 may be substantially equal to the p-type impurity concentration (peak value) of the first region 14.

[0255] The p-type impurity concentration in the second region 15 is preferably adjusted by at least one trivalent element. The p-type impurity concentration in the second region 15 is particularly preferably adjusted by a trivalent element heavier than carbon. Specifically, the second region 15 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration in the second region 15 is adjusted by aluminum.

[0256] Each of the plurality of second regions 15 has a second width W2. The second width W2 is the width of the second region 15 along the second arrangement direction Da2. The second width W2 is preferably smaller than the second thickness T2 of the second layer 9. Of course, the second width W2 may also be greater than the second thickness T2.

[0257] The second width W2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second width W2 may also be greater than the first thickness T1. The second width W2 is preferably substantially equal to the first width W1 of the first region 14. Of course, the second width W2 may be greater than or less than the first width W1.

[0258] The second width W2 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The second width W2 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The second width W2 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0259] Each of the plurality of second regions 15 has a second region thickness TR2 (region depth). The second region thickness TR2 may be less than the second thickness T2 of the second layer 9. The second region thickness TR2 may be greater than the second thickness T2. The second region thickness TR2 may be substantially equal to the second thickness T2.

[0260] The second region thickness TR2 may be less than the first thickness T1 of the first layer 8. The second region thickness TR2 may be greater than the first thickness T1. The second region thickness TR2 may be approximately equal to the first thickness T1. The second region thickness TR2 may be less than the first region thickness TR1 of the first region 14. The second region thickness TR2 may be greater than the first region thickness TR1. The second region thickness TR2 may be approximately equal to the first region thickness TR1.

[0261] The second region thickness TR2 is preferably 1 μm or greater. The second region thickness TR2 is preferably 5 μm or less. The second region thickness TR2 may have a value within any range of 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0262] The second width W2 is preferably smaller than the second thickness T2 of the second layer 9, and the second region thickness TR2 is preferably greater than the second width W2. Specifically, the plurality of second regions 15 preferably each have a second aspect ratio TR2 / W2 extending in a longitudinally elongated columnar shape along the second axial channel CH2. The second aspect ratio TR2 / W2 is the ratio of the second region thickness TR2 to the second width W2. In this case, it is particularly preferred that the second region thickness TR2 is greater than the second thickness T2. For example, the second aspect ratio TR2 / W2 may be greater than 1 and less than 100.

[0263] The plurality of second regions 15 are formed at intervals of a second pitch P2 in the second arrangement direction Da2. The second pitch P2 is preferably less than the second thickness T2 of the second layer 9. Of course, the second pitch P2 may be greater than the second thickness T2 of the second layer 9. The second pitch P2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second pitch P2 may be greater than the first thickness T1.

[0264] The second pitch P2 may be substantially equal to or different from the first pitch P1. The second pitch P2 may be larger or smaller than the first pitch P1.

[0265] The second pitch P2 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The second pitch P2 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The second pitch P2 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0266] This embodiment shows a superstructure SJ having a two-layer structure. However, a superstructure SJ having a stacked structure of three or more layers can also be employed. That is, a stacked portion 7 having a stacked structure of three or more layers can be formed, and a pillar region 12 having a stacked structure of three or more layers can be formed.

[0267] In this case, the semiconductor layers from the third layer onwards in the stacked portion 7 are formed with the same structure as the second layer 9. On the other hand, the region of the semiconductor layer formed in the odd-numbered (2n+1: n is 1 or greater and a natural number) layers in the pillar region 12 is formed with the same structure as the first region 14 (first reference numeral Mk1), and the region of the semiconductor layer formed in the even-numbered (2n+2) layers is formed with the same structure as the second region 15 (second reference numeral Mk2). The region of the (n+2)th layer in the pillar region 12 is formed in the semiconductor layer of the (n+2)th layer with the same relationship as the region of the (n+1)th layer with respect to the region of the nth layer.

[0268] Below, refer to Figure 7 、 Figure 8A as well as Figure 8B, a description will be given of a layout example of the first region 14 and the second region 15. The decorative pattern PT (a plurality of first marks Mk1 and a plurality of second marks Mk2) is formed in a layout corresponding to the layout example of the first region 14 and the second region 15 described below.

[0269] Figure 8A 1 is a plan view showing a first layout example of the pillar region 12 according to the first basic embodiment. Figure 8B 1 is a top view showing a second layout example of the column region 12 according to the first basic embodiment. Figure 8A as well as Figure 8B In FIG. 1 , the first region 14 is indicated by a dotted line and the second region 15 is indicated by a hatching.

[0270] Reference Figure 7 、 Figure 8A as well as Figure 8B The first arrangement direction Da1 of the first regions 14 can be the a-axis direction (first direction X), and the first extension direction De1 of the first regions 14 can be the m-axis direction (second direction Y). In this case, because the first extension direction De1 intersects (specifically, is perpendicular to) the off direction Doff of the first layer 8, the plurality of first regions 14 are tilted from the vertical axis toward the off direction Doff by approximately the amount of the off angle θoff in a cross-sectional view viewed from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.

[0271] On the other hand, refer to Figure 7 as well as Figure 8A Alternatively, the plurality of second regions 15 may be orthogonal to the plurality of first regions 14 when viewed from above. That is, the second arrangement direction Da2 of the second regions 15 may be the m-axis direction (second direction Y), and the second extension direction De2 of the second regions 15 may be the a-axis direction (first direction X). In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is orthogonal to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is orthogonal to the first extension direction De1.

[0272] In this case, since the second extension direction De2 coincides with the off direction Doff of the second layer 9, the plurality of second regions 15 extend substantially in the vertical direction Z when viewed in cross section from the a-plane ((11-20) plane) of the SiC single crystal. The a-plane of the SiC single crystal is a direction perpendicular to the a-axis. The plurality of second regions 15 are tilted from the vertical axis toward the off direction Doff by approximately the amount of the off angle θoff when viewed in cross section from the m-plane of the SiC single crystal.

[0273] Of course, refer to Figure 8B, the plurality of second regions 15 may also intersect the plurality of first regions 14 non-orthogonally when viewed from above. That is, the second arrangement direction Da2 of the second regions 15 may be a direction other than the m-axis and the a-axis directions, and the second extension direction De2 of the second regions 15 may be a direction other than the m-axis and the a-axis directions. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off direction Doff of the second layer 9.

[0274] The second extension direction De2 may also be inclined from the a-axis toward one side (left side of the drawing) or the other side (right side of the drawing) of the m-axis when viewed from above. With the a-axis as a reference (0°), the plurality of second regions 15 have a second extension direction De2 that forms an extension angle θa with the a-axis.

[0275] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value within any range of greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°. The absolute value of the extension angle θa is typically set to a value within any range of 30°±5°, 45°±5°, and 60°±5°.

[0276] The column region 12 may also have Figure 9 、 Figure 10A as well as Figure 10B The method shown. Figure 9 It is a cross-sectional perspective view showing a second basic embodiment of the column region 12 . Figure 10A as well as Figure 10B 1 and 2 are top views showing a first layout example and a second layout example of the column region 12 according to the second basic embodiment. Figure 10A as well as Figure 10B In FIG. 1 , the first region 14 is indicated by a dotted line and the second region 15 is indicated by a hatching.

[0277] Reference Figure 9 、 Figure 10A as well as Figure 10B The first arrangement direction Da1 of the first regions 14 can be the m-axis direction (first direction X), and the first extension direction De1 of the first regions 14 can be the a-axis direction (second direction Y). In this case, since the first extension direction De1 coincides with the off direction Doff of the first layer 8, the plurality of first regions 14 extend substantially along the vertical direction Z when viewed in cross section from the a-plane of the SiC single crystal. The plurality of first regions 14 are tilted from the vertical axis toward the off direction Doff by substantially the amount of the off angle θoff when viewed in cross section from the m-plane of the SiC single crystal.

[0278] On the other hand, refer to Figure 9 as well as Figure 10A Alternatively, the plurality of second regions 15 may be orthogonal to the plurality of first regions 14 in a plan view. Specifically, the second arrangement direction Da2 of the second regions 15 may be the a-axis direction (second direction Y), and the second extension direction De2 of the second regions 15 may be the m-axis direction (first direction X). In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is orthogonal to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is orthogonal to the first extension direction De1.

[0279] In this case, since the second extension direction De2 intersects (specifically, is orthogonal to) the off direction Doff of the second layer 9, the plurality of second regions 15 are tilted from the vertical axis toward the off direction Doff by approximately the off angle θoff in a cross-section viewed from the m-plane of the SiC single crystal.

[0280] Of course, refer to Figure 10B The plurality of second regions 15 may also intersect the plurality of first regions 14 non-orthogonally when viewed from above. That is, the second arrangement direction Da2 of the second regions 15 may be a direction other than the a-axis and the m-axis, and the second extension direction De2 of the second regions 15 may be a direction other than the a-axis and the m-axis. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off direction Doff of the second layer 9.

[0281] The second extension direction De2 may also be inclined from the a-axis toward one side (left side of the drawing) or the other side (right side of the drawing) of the m-axis when viewed from above. With the a-axis as a reference (0°), the plurality of second regions 15 have a second extension direction De2 that forms an extension angle θa with the a-axis.

[0282] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value within any range of greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°. The absolute value of the extension angle θa is typically set to a value within any range of 30°±5°, 45°±5°, and 60°±5°.

[0283] The column region 12 may have Figure 11 、 Figure 12A 、 Figure 12B as well as Figure 12C The form shown. Figure 11 It is a cross-sectional perspective view showing a third basic embodiment of the column region 12 . Figure 12A 、 Figure 12B as well as Figure 12C 1 and 2 are top views showing a first layout example, a second layout example, and a third layout example of the column region 12 according to the third basic embodiment. Figures 12A to 12C In FIG. 1 , the first region 14 is indicated by a dotted line and the second region 15 is indicated by a hatching.

[0284] Reference Figure 11 as well as Figures 12A to 12C , the first arrangement direction Da1 of the first region 14 may be a direction other than the a-axis direction (first direction X) and the m-axis direction (second direction Y), and the first extension direction De1 of the first region 14 may be a direction other than the a-axis direction and the m-axis direction. That is, the plurality of first regions 14 may also intersect both the a-axis direction and the m-axis direction. Figures 12A to 12C , an example is shown in which the first region 14 is inclined toward the m-axis side (left side of the paper) with respect to the a-axis.

[0285] In this case, since the first extension direction De1 intersects the offset direction Doff, the plurality of first regions 14 are tilted from the vertical axis toward the offset direction Doff by approximately the offset angle θoff in the cross-section viewed from the a-plane of the SiC single crystal and the cross-section viewed from the m-plane of the SiC single crystal.

[0286] With the a-axis as a reference (0°), the first extension direction De1 forms a first extension angle θ1 with the a-axis. The absolute value of the first extension angle θ1 may be greater than 0° and less than 90°. The first extension angle θ1 may have a value within any range of greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°.

[0287] The absolute value of the first extension angle θ1 is typically set to a value within the range of 30°±5°, 45°±5°, and 60°±5°. Figure 12A FIG shows a layout example in which the absolute value of the first extension angle θ1 is approximately 45°. Figure 12B FIG shows a layout example in which the absolute value of the first extension angle θ1 is approximately 30°. Figure 12C 2 shows a layout example in which the absolute value of the first extension angle θ1 is approximately 60°.

[0288] On the other hand, refer to Figure 11 as well as Figures 12A to 12CThe first arrangement direction Da1 of the second regions 15 can be a direction other than the a-axis direction (first direction X) and the m-axis direction (second direction Y), and the first extension direction De1 of the second regions 15 can be a direction other than the a-axis direction and the m-axis direction. In other words, the plurality of second regions 15 can intersect both the a-axis direction and the m-axis direction. In this example, the second regions 15 are inclined with respect to the a-axis toward the other side of the m-axis (the right side of the drawing).

[0289] In this case, since the second extension direction De2 intersects the off direction Doff, the plurality of second regions 15 are inclined from the vertical axis toward the off direction Doff by approximately the off angle θoff in cross sections viewed from the a-plane and the m-plane of the SiC single crystal.

[0290] With the a-axis as a reference (0°), the second extension direction De2 forms a second extension angle θ2 with the a-axis. If the first extension angle θ1 is defined as a positive value, the second extension angle θ2 is a negative value. On the other hand, if the first extension angle θ1 is defined as a negative value, the second extension angle θ2 is a positive value.

[0291] The absolute value of the second extension angle θ2 may be greater than 0° and less than 90°. The second extension angle θ2 may have a value within any of the following ranges: greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°.

[0292] The absolute value of the second extension angle θ2 is typically set to a value within the range of 30°±5°, 45°±5°, and 60°±5°. The absolute value of the second extension angle θ2 is preferably approximately equal to the absolute value of the first extension angle θ1. Specifically, the plurality of second regions 15 preferably have a layout that is substantially line-symmetrical with the plurality of first regions 14 with respect to the a-axis in a top view per unit area (i.e., a local top view). In other words, the plurality of second regions 15 preferably have a layout that is substantially symmetrical with the plurality of first regions 14 with respect to the vertical axis in a top view per unit area (i.e., a local top view).

[0293] exist Figure 12A FIG shows a layout example in which the absolute value of the second extension angle θ2 is approximately 45° (≈θ1). Figure 12B FIG shows a layout example in which the absolute value of the second extension angle θ2 is approximately 30° (≈θ1). Figure 12C 2 shows a layout example in which the absolute value of the second extension angle θ2 is approximately 60° (≈θ1).

[0294] That is, in Figure 12AIn the layout example of , the plurality of second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction and are orthogonal to the plurality of first regions 14. The sum of the absolute values of the first extension angle θ1 and the second extension angle θ2 is approximately a right angle (approximately 90°).

[0295] On the other hand, Figure 12B In the layout example of , the plurality of second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and intersect the plurality of first regions 14 non-orthogonally. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is an acute angle (approximately 60°). On the other hand, in Figure 12C In the layout example of , the plurality of second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and intersect the plurality of first regions 14 non-orthogonally. The sum of the absolute values of the first extension angle θ1 and the second extension angle θ2 is an obtuse angle (approximately 120°).

[0296] Of course, the absolute value of the second extension angle θ2 may be greater than or less than the absolute value of the first extension angle θ1. That is, the plurality of second regions 15 may have a layout that is non-line-symmetrical with the plurality of first regions 14 with respect to the a-axis in a plan view per unit area (i.e., a local plan view). In other words, the plurality of second regions 15 may have a layout that is non-point-oriented with the plurality of first regions 14 with respect to the vertical axis in a plan view per unit area (i.e., a local plan view).

[0297] The following specifically describes the p-type impurity concentration gradients in the first region 14 and the second region 15. Since the concentration gradients in the first region 14 and the second region 15 are substantially the same, the concentration gradient in the second region 15 is described below.

[0298] The concentration gradient of the first region 14 can be described by replacing "first layer 8" with "underlayer 6," "second layer 9" with "first layer 8," "second region 15 (second lower end 15a and second upper end 15b)" with "first region 14 (first lower end 14a and first upper end 14b)," and "second axial channel CH2" with "first axial channel CH1" as needed in the following description. In other words, the relative or absolute positional relationship of the second region 15 with respect to the first layer 8 and the second layer 9 applies to the relative or absolute positional relationship of the first region 14 with respect to the underlayer 6 and the first layer 8.

[0299] Figures 13A to 13E This is a graph showing an example of the concentration gradient in the second region 15 (first region 14 ). Figure 1413 and 14 are graphs showing a comparative example of the concentration gradient of the second region 15 (first region 14). Figure 14 In FIG. 1 , the vertical axis represents the p-type impurity concentration of the second region 15 , and the horizontal axis represents the depth of the channel CH2 along the second axis with the upper end (first main surface 3 ) of the second layer 9 as a reference (zero point).

[0300] exist Figures 13A to 13E as well as Figure 14 In the middle, there are 1×10 15 cm -3 The region with the above p-type impurity concentration is defined as the second region 15 and is illustrated as a graph. The numerical values of impurity concentration, thickness, etc. shown below are provided for illustrative purposes only to illustrate the basic structure of the second region 15 based on the concentration gradient and are not intended to uniquely define the structure of the second region 15. The impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the trivalent element (dose, implantation temperature, implantation energy, etc.).

[0301] Figures 13A to 13E These are graphs when the second region 15 is formed by a channel implantation method. Figures 13A to 13E Indicates that the 190KeV ( Figure 13A )、380KeV( Figure 13B )、650KeV( Figure 13C )、960KeV( Figure 13D ) or 2000KeV( Figure 13E ) with an implantation energy of 1×10 , and a concentration gradient of the second region 15 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 in parallel or substantially parallel to the second axis channel CH2. The second thickness T2 of the second layer 9 is about 3 μm, and the dose of the trivalent element is 1×10 13 cm -2 .

[0302] on the other hand, Figure 14 This is a graph when the second region 15 is formed by a random implantation method. Figure 14 The concentration gradient of the second region 15 is shown when a predetermined trivalent element (here, aluminum) is introduced into the semiconductor layer 9 in a random direction using an implantation energy of 190 KeV, 380 KeV, 650 KeV, 960 KeV, or 2000 KeV. The random direction is a direction that is not parallel (substantially parallel) to the second axial channel CH2 (e.g., the vertical direction Z). The second thickness T2 of the second layer 9 is approximately 3 μm, and the dose of the trivalent element is 1×10 13 cm -2 .

[0303] Reference Figure 13AThe second region 15 (190 KeV) has a second region thickness TR2 of 1.5 μm or more and 1.8 μm or less, a second lower end portion 15 a separated from the lower end of the second layer 9 toward the upper end, and a second upper end portion 15 b exposed from the upper end (first main surface 3) of the second layer 9. The distance between the lower end of the second layer 9 and the second lower end portion 15 a is 1.2 μm or more and 1.5 μm or less.

[0304] The p-type impurity concentration in second region 15 has a concentration gradient from the upper end toward the lower end of second layer 9, including a gradually increasing portion 20, a peak portion 21, a gradually decreasing portion 22, and a gradually decreasing portion 23. Gradually increasing portion 20 forms second upper end portion 15b of second region 15, and is the portion where the p-type impurity concentration gradually increases at a relatively steep rate from second upper end portion 15b toward the lower end of second layer 9 to peak portion 21.

[0305] Peak portion 21 is the portion with the peak value P (maximum value) of the p-type impurity concentration. Peak portion 21 is also a convex main concentration transition region, including a series of concentration changes (inflection points) where the p-type impurity concentration transitions from increasing (increasing trend) to decreasing (decreasing trend). The depth of peak portion 21 is 0.1 μm or more and 0.5 μm or less.

[0306] Gradual portion 22 is formed in a region closer to second lower end portion 15a than peak portion 21. It is a portion where the impurity concentration gradually decreases at a relatively slow rate. Specifically, gradual portion 22 maintains a constant p-type impurity concentration within a certain depth range and forms the bulk of second region 15. The p-type impurity concentration in gradual portion 22 decreases gradually within a concentration range that is lower than that of peak portion 21.

[0307] The slow portion 22 is defined by a portion having a concentration reduction rate of 50% or less within a thickness range of at least 0.5 μm. In this example, the slow portion 22 has a thickness of 0.7 μm to 0.8 μm, and has a concentration reduction rate of 50% or less within this thickness range. In this example, the p-type impurity concentration of the slow portion 22 converges to 4.5×10 16 cm -3 Above and 9×10 16 cm -3 The following concentration range.

[0308] The gradually decreasing portion 23 is a portion forming the second lower end portion 15a of the second region 15. The gradually decreasing portion 23 has a concentration reduction rate greater than the concentration reduction rate in the slow portion 22, and is a portion where the p-type impurity concentration gradually decreases from the slow portion 22 toward the lower end of the second layer 9. The concentration reduction rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration reduction rate per unit thickness of the slow portion 22. The p-type impurity concentration in the gradually decreasing portion 23 gradually decreases from the slow portion 22 to 1×10 15 cm -3 .

[0309] Reference Figure 13B The second region 15 (380 KeV) has a second region thickness TR2 of 2.2 μm or more and 2.4 μm or less, a second lower end portion 15a separated from the lower end of the second layer 9 toward the upper end, and a second upper end portion 15b separated from the upper end (first principal surface 3) of the second layer 9 toward the lower end (first layer 8 side). The distance between the lower end of the second layer 9 and the second lower end portion 15a is 0.5 μm or more and 0.8 μm or less. The distance between the upper end of the second layer 9 and the second upper end portion 15b of the second region 15 is 0.01 μm or more and 0.2 μm or less.

[0310] and Figure 13A Similarly to the example, the p-type impurity concentration in second region 15 has a concentration gradient from the upper end toward the lower end of second layer 9, including a gradually increasing portion 20, a peak portion 21, a slow portion 22, and a gradually decreasing portion 23. In this example, gradually increasing portion 20 also increases at a relatively steep rate from second upper end portion 15b toward the lower end of second layer 9 to peak portion 21. The depth of peak portion 21 is not less than 0.3 μm and not more than 0.7 μm.

[0311] The slow portion 22 has a thickness of 0.8 μm or more and 1.1 μm or less, and has a concentration reduction rate of 50% or less within this thickness range. In this example, the p-type impurity concentration of the slow portion 22 converges to 3.5×10 16 cm -3 Above and 7×10 16 cm -3 The concentration range of the p-type impurity in the gradually decreasing portion 23 gradually decreases from the slow portion 22 to 1×10 15 cm -3 .

[0312] Reference Figure 13C The second region 15 (650 KeV) has a second region thickness TR2 of 2.5 μm or more and 2.8 μm or less, a second lower end 15a separated from the lower end of the second layer 9 toward the upper end, and a second upper end 15b separated from the upper end (first principal surface 3) of the second layer 9 toward the lower end (first layer 8 side). The distance between the lower end of the second layer 9 and the second lower end 15a is 0.01 μm or more and 0.1 μm or less. The distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.1 μm or more and 0.4 μm or less.

[0313] and Figure 13ASimilarly to the example, the p-type impurity concentration of the second region 15 has a concentration gradient from the second upper end 15b toward the second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a slow portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases at a relatively steep rate from the second upper end 15b of the second region 15 to the peak portion 21. The depth of the peak portion 21 is not less than 0.6 μm and not more than 1 μm.

[0314] The slow portion 22 has a thickness of 1 μm or more and 1.3 μm or less, and has a concentration reduction rate of 50% or less within this thickness range. In this example, the p-type impurity concentration of the slow portion 22 converges to 3×10 16 cm -3 Above and 6×10 16 cm -3 The concentration range of the p-type impurity in the gradually decreasing portion 23 gradually decreases from the slow portion 22 to 1×10 15 cm -3 .

[0315] Reference Figure 13D The second region 15 (960 KeV) has a second region thickness TR2 of 3.1 μm or more and 3.3 μm or less, and includes a second upper end portion 15 b spaced apart from the upper end (first principal surface 3) of the second layer 9 toward the lower end (toward the first layer 8), and a second lower end portion 15 a located within the first layer 8. In other words, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 (=3 μm) of the second layer 9.

[0316] Furthermore, the second lower end portion 15a includes an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and extends within the first layer 8. The extension portion of the second lower end portion 15a has a thickness of 0.4 μm to 0.7 μm, relative to the upper end of the first layer 8. The distance between the upper end of the second layer 9 and the second upper end portion 15b of the second region 15 is 0.3 μm to 0.6 μm.

[0317] and Figure 13A Similarly to the example, the p-type impurity concentration of the second region 15 has a concentration gradient from the second upper end 15b toward the second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a slow portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases at a relatively steep rate from the second upper end 15b of the second region 15 to the peak portion 21. The depth of the peak portion 21 is not less than 0.7 μm and not more than 1.3 μm.

[0318] The slow portion 22 has a thickness of 1.3 μm or more and 1.7 μm or less, and has a concentration reduction rate of 50% or less within this thickness range. In this example, the p-type impurity concentration of the slow portion 22 converges to 2.2×10 16 cm-3 Above and 4.5×10 16 cm -3 The concentration range of the p-type impurity in the gradually decreasing portion 23 gradually decreases from the slow portion 22 to 1×10 15 cm -3 .

[0319] Reference Figure 13E The second region 15 (2000 KeV) has a second region thickness TR2 of 3.5 μm or more and 3.8 μm or less, and includes a second upper end 15 b separated from the upper end (first main surface 3) of the second layer 9 toward the lower end (first layer 8 side), and a second lower end 15 a located within the first layer 8. In other words, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 (=3 μm) of the second layer 9.

[0320] Furthermore, the second lower end portion 15a includes an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and extends within the first layer 8. The extension portion of the second lower end portion 15a has a thickness of 1.4 μm to 1.8 μm, relative to the upper end of the first layer 8. The distance between the upper end of the second layer 9 and the second upper end portion 15b of the second region 15 is 0.7 μm to 1 μm.

[0321] and Figure 13A Similarly to the example, the p-type impurity concentration of the second region 15 has a concentration gradient from the second upper end 15b toward the second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a slow portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases at a relatively steep rate from the second upper end 15b of the second region 15 to the peak portion 21. The depth of the peak portion 21 is not less than 1.3 μm and not more than 1.9 μm.

[0322] The slow portion 22 has a thickness of 1.5 μm or more and 1.8 μm or less, and has a concentration reduction rate of 50% or less within this thickness range. In this example, the slow portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In other words, the extension of the second region 15 includes a portion of the slow portion 22. In this example, the p-type impurity concentration of the slow portion 22 converges to 2×10 16 cm -3 Above and 4×10 16 cm -3 The concentration range of the p-type impurity in the gradually decreasing portion 23 gradually decreases from the slow portion 22 to 1×10 15 cm -3 .

[0323] Reference Figures 13A to 13EThe p-type impurity concentration in the second region 15 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy. Furthermore, the second region thickness TR2 (depth) of the second region 15 increases with increasing implantation energy. Furthermore, the depth of the second upper end portion 15b of the second region 15 relative to the upper end of the second layer 9 increases with increasing implantation energy.

[0324] The thicknesses of the gradually increasing portion 20, the peak portion 21, the slow portion 22, and the gradually decreasing portion 23 all increase with increasing implantation energy. Meanwhile, the peak value P of the second region 15 decreases with increasing implantation energy. This is because, as implantation energy increases, the trivalent element is introduced into deeper regions, increasing the p-type impurity concentration in these deeper regions.

[0325] The slow portion 22 occupies at least one-quarter of the thickness of the second region 15 (second region thickness TR2) and is located within the second layer 9. Specifically, the slow portion 22 occupies at least one-third of the second region 15. The slow portion 22 typically occupies less than one-half of the second region 15. Alternatively, the slow portion 22 may occupy at least one-half of the second region 15.

[0326] On the other hand, refer to Figure 14 In the case of random implantation, the second region 15 has a gradually increasing portion 20, a peak portion 21 (peak P), and a gradually decreasing portion 23 within a range of 0.5 μm. However, it does not have a gradually decreasing portion 22 with a thickness exceeding 0.5 μm. Furthermore, in the case of random implantation, the depth position of the peak portion 21 (peak P) relative to the upper end of the second layer 9 increases with increasing implantation energy. However, the second region thickness TR2 of the second region 15 remains less than 2 μm at all implantation energies. In other words, even with increasing implantation energy, the second region thickness TR2 does not change significantly.

[0327] As can be seen from this, in the case of random implantation, for second layer 9 having a relatively large second thickness T2 (e.g., a second thickness T2 of 1 μm or greater), it is difficult to improve charge balance accuracy by using second region 15 consisting of a single impurity region. Unlike Si single crystal, SiC single crystal has the physical property of making impurities difficult to diffuse. Therefore, this problem is typically eliminated through multi-epitaxial growth methods and multi-stage random implantation methods.

[0328] In the multi-epitaxial growth method, the process of introducing trivalent elements into an epitaxial layer having a relatively small thickness (for example, less than 1 μm) by random implantation is repeated multiple times. In this process, the number of epitaxial growth steps and the number of random implantation steps increase, thus complicating the manufacturing process.

[0329] In the multi-stage random implantation method, a process is performed to introduce trivalent elements into different depth positions in multiple stages using multiple implantation energies. Figure 14 For example, when forming a 1μm thick second layer 9, a trivalent element is introduced into the second layer 9 at five implantation energies (190KeV, 380KeV, 650KeV, and 960KeV). This process allows the trivalent element to be introduced at the desired depth, but the depth at which the trivalent element can be introduced is shallow. Consequently, the number of epitaxial growth steps and the number of random implantation steps must be increased, resulting in the same problems as the multi-epitaxial growth method.

[0330] In contrast, in the case of the channel implantation method, the second region 15 having a slow portion 22 with a thickness of 0.5 μm to 2 μm is formed in the second layer 9 having a relatively large thickness (e.g., 1 μm to 5 μm). Therefore, the second region 15 having a balanced charge can be formed with fewer steps than when the random implantation method is used.

[0331] Of course, this specification does not exclude the technical concept of forming a single second region 15 by introducing multiple second regions 15 at different depths in multiple stages using a channel implantation method using multiple implantation energies. In this case, each second region 15 is composed of an integrated region of multiple impurity regions (second regions 15) formed in the second layer 9 along the second-axis channel CH2 so as to traverse the middle portion of the second layer 9.

[0332] In this case, the p-type impurity concentration (concentration gradient) of each second region 15 becomes the sum of the p-type impurity concentrations (concentration gradients) of the plurality of impurity regions (second regions 15). For example, the p-type impurity concentration of each second region 15 has such a value that Figures 13A to 13E At least two of the five graphs shown have overlapping concentration gradients (additive concentration gradients).

[0333] exist Figures 13A to 13E In the example of the channel implantation method, the upper limit of the implantation energy is 2000 KeV, but the second region 15 can also be formed by an implantation energy greater than 2000 KeV. In this case, Figure 13E The position where the concentration gradient is deep forms a relatively thick second region 15 .

[0334] However, when achieving an injection energy greater than 2000 KeV, the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the empty region on the upper end side (i.e., the distance between the first main surface 3 and the second region 15) increases, thereby increasing the difficulty of designing the pillar region 12. In addition, when achieving an injection energy greater than 2000 KeV, the size of the ion accelerator may reach tens of meters, which is unrealistic from the perspective of cost-effectiveness (installation space, equipment investment).

[0335] Therefore, when forming the relatively thick pillar region 12 by the channel implantation method, it is preferable to limit the implantation energy to 2000 KeV or less to increase the number of stacked layers 7 (the number of stacked layers of the superjunction structure SJ).

[0336] Below, refer to Figures 15 to 35 , showing first to twelfth embodiments of the column region 12. The column region 12 of the first to third basic embodiments may also have at least one of the multiple features shown in the first to twelfth embodiments. The column region 12 of the first to third basic embodiments may also have a feature that is a combination of multiple (two or more) features shown in the first to twelfth embodiments.

[0337] Hereinafter, the "gradually increasing portion 20," "peak portion 21 (peak value P)," "slow portion 22," and "gradually decreasing portion 23" of the first region 14 are referred to as the "first gradually increasing portion 20A," "first peak portion 21A (first peak value PA)," "first slow portion 22A," and "first gradually decreasing portion 23A." Furthermore, the "gradually increasing portion 20," "peak portion 21 (peak value P)," "slow portion 22," and "gradually decreasing portion 23" of the second region 15 are referred to as the "second gradually increasing portion 20B," "second peak portion 21B (second peak value PB)," "second slow portion 22B," and "second gradually decreasing portion 23B."

[0338] Figure 15 It is a cross-sectional perspective view showing the column region 12 according to the first embodiment. Figure 16 It shows Figure 15 FIG. 1 is a graph showing an example of a concentration gradient in the column region 12 .

[0339] Reference Figure 15 as well as Figure 16 The first region 14 has a first region thickness TR1 that is smaller than the first thickness T1 of the first layer 8, and is formed within the first layer 8 at a distance from both the lower end and the upper end of the first layer 8. Specifically, the first lower end portion 14a of the first region 14 is formed at a distance from the lower end (base layer 6) of the first layer 8 toward the upper end, and is opposed to the base layer 6 via a portion (the lower end portion) of the first layer 8.

[0340] On the other hand, first upper end portion 14b of first region 14 is formed spaced apart from the upper end (second layer 9) of first layer 8 toward the lower end, and faces second layer 9 across a portion (upper end) of first layer 8. First gradually increasing portion 20A, first peak portion 21A, first slow portion 22A, and first gradually decreasing portion 23A of first region 14 are located within first layer 8.

[0341] exist Figure 16 , an example is shown in which the first layer 8 has a first thickness T1 of 3 μm and the first region 14 is formed in the first layer 8 by implantation energy of 650 KeV. Of course, the first region 14 may also be formed by implantation energy of less than 650 KeV.

[0342] The second region 15 has a second region thickness TR2 that is smaller than the second thickness T2 of the second layer 9, and is formed within the second layer 9 at a distance from both the lower end and the upper end of the second layer 9. Specifically, the second lower end portion 15a of the second region 15 is formed at a distance from the lower end (first layer 8) of the second layer 9 toward the upper end, and is opposed to the first layer 8 across a portion (the lower end) of the second layer 9.

[0343] On the other hand, second upper end portion 15b of second region 15 is formed spaced apart from the upper end (first major surface 3) of second layer 9 toward the lower end, and faces first major surface 3 across a portion (upper end) of second layer 9. Second gradually increasing portion 20B, second peak portion 21B, second slow portion 22B, and second gradually decreasing portion 23B of second region 15 are located within second layer 9.

[0344] exist Figure 16 , an example is shown in which the second layer 9 has a second thickness T2 of 3 μm and the second region 15 is formed in the second layer 9 using an implantation energy of 650 KeV. Of course, the second region 15 can also be formed using an implantation energy of less than 650 KeV. Furthermore, the implantation energy of the second region 15 can also be different from the implantation energy of the first region 14.

[0345] That is, the second region thickness TR2 of the second region 15 may be different from the first region thickness TR1 of the first region 14. The second region thickness TR2 may be smaller than the first region thickness TR1 or larger than the first region thickness TR1.

[0346] Figure 17 It is a cross-sectional perspective view showing the column region 12 according to the second embodiment. Figure 18 It shows Figure 17 Graph showing an example of the concentration gradient of the column region 12. Figure 17 as well as Figure 18The column region 12 of the second embodiment has a configuration that deforms the second region 15 of the first embodiment. The configuration of the first region 14 of the second embodiment is the same as that of the first region 14 of the first embodiment.

[0347] The second region 15 is formed in the second layer 9 at intervals from the upper end toward the lower end thereof, and includes a portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In other words, the second lower end portion 15a of the second region 15 includes an extension portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.

[0348] The second axial channel CH2 is substantially aligned with the first axial channel CH1, and thus an extension of the second lower end portion 15a is formed along the first axial channel CH1 within the first layer 8. The extension of the second lower end portion 15a is preferably located on the upper side of the first layer 8 relative to the middle of the thickness range of the first layer 8. The extension of the second lower end portion 15a is connected to the first region 14 (first upper end portion 14b) within the first layer 8.

[0349] In this structure, a portion (extension) of the second region 15 is provided in the space between the upper end of the first layer 8 and the first upper end portion 14b of the first region 14. Thus, the first region 14 and the second region 15 form a single column region 12 extending continuously in a three-dimensional lattice pattern. This improves the accuracy of charge balancing.

[0350] In this example, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9. Furthermore, the second region thickness TR2 is greater than the first thickness T1 of the first layer 8. Furthermore, the second region thickness TR2 is greater than the first region thickness TR1 of the first region 14. Of course, the second region thickness TR2 may be less than the second thickness T2. Furthermore, the second region thickness TR2 may be less than the first region thickness TR1. Furthermore, the second region thickness TR2 may be less than the first region thickness TR1.

[0351] The second gradually increasing portion 20B, the second peak portion 21B, the second slow portion 22B and the second gradually decreasing portion 23B of the second region 15 are located in the second layer 9. At least a portion of the second gradually decreasing portion 23B is located in the first layer 8. That is, the extension portion of the second lower end portion 15a includes the second gradually decreasing portion 23B. Of course, a portion of the second slow portion 22B may also be located in the first layer 8 (see Figure 13E ) That is, the extension portion of the second lower end portion 15a may also include a portion of the second slow portion 22B and the second gradually decreasing portion 23B.

[0352] exist Figure 18, an example is shown in which the second layer 9 has a first thickness T1 of 3 μm and the second region 15 is formed in the second layer 9 by an implantation energy of 960 KeV. Of course, the second region 15 can also be formed by an implantation energy of 960 KeV or more. For example, the second thickness T2 can also be greater than 3 μm and less than 5 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV or more (also refer to Figures 13F to 13F). Figure 13E ).

[0353] Figure 19 It is a cross-sectional perspective view showing the column region 12 according to the third embodiment. Figure 20 It shows Figure 19 Graph showing an example of the concentration gradient of the column region 12. Figure 19 as well as Figure 20 The column region 12 of the third embodiment has a configuration obtained by deforming the second region 15 of the second embodiment. The first region 14 of the third embodiment has the same configuration as the first region 14 of the first embodiment.

[0354] The second region 15 of the second embodiment is formed in the second layer 9 having a second thickness T2 that is substantially equal to the first thickness T1 of the first layer 8. In contrast, the second region 15 of the third embodiment is formed in the second layer 9 having a second thickness T2 that is less than the first thickness T1 of the first layer 8. In this example, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.

[0355] exist Figure 19 , an example is shown in which the second layer 9 has a second thickness T2 less than 3 μm (here, 2 μm), and the second region 15 is formed in the second layer 9 by implantation energy of 650 KeV. Of course, the second region 15 can also be formed by implantation energy below 650 KeV.

[0356] For example, the second thickness T2 may be greater than or equal to 1 μm and less than or equal to 2 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by an implantation energy of 190 KeV or more (also refer to FIG. Figures 13A to 13E For example, the second thickness T2 may be greater than or equal to 2 μm and less than or equal to 3 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by an implantation energy of 380 KeV or greater (also refer to FIG. Figures 13B to 13E ).

[0357] In this structure, the concentration gradient formed at the connection between the first region 14 and the second region 15 is relaxed, improving the accuracy of charge balance. In addition, the second layer 9 having a relatively small second thickness T2 allows the second region 15 connected to the first region 14 to be formed with relatively low implantation energy. This reduces manufacturing costs.

[0358] For example, by using a relatively small second thickness T2, it is possible to set the first region thickness TR1 (implantation energy) of the first region 14 and the second region thickness TR2 (implantation energy) of the second region 15 to be the same, while forming the second region 15 connected to the first region 14 within the first layer 8. In this case, process management of the manufacturing process is simplified. In these cases, the second thickness T2 of the second layer 9 can also be set to be smaller than the first thickness T1 of the first layer 8, forming the second region 15 having a second region thickness TR2 greater than the second thickness T2.

[0359] Figure 21 It is a cross-sectional perspective view showing the column region 12 according to the fourth embodiment. Figure 22 It shows Figure 21 Graph showing an example of the concentration gradient of the column region 12. Figure 21 as well as Figure 22 The column region 12 of the fourth embodiment has a configuration that deforms the first region 14 of the second embodiment. The second region 15 of the fourth embodiment has the same configuration as the second region 15 of the second embodiment. Of course, the second region 15 of the fourth embodiment may also have the same configuration as the second region 15 of the third embodiment.

[0360] The first region 14 is formed in the first layer 8 at intervals from the upper end toward the lower end of the first layer 8, and includes a portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. In other words, the first lower end portion 14a of the first region 14 includes an extension portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.

[0361] The first axial channel CH1 is substantially aligned with the base axial channel CHB, and thus the extension of the first lower end portion 14a is formed along the base axial channel CHB within the base layer 6. The extension of the first lower end portion 14a is preferably located on the upper side of the base layer 6 relative to the middle of the thickness range of the base layer 6. The extension of the first lower end portion 14a is connected to the base layer 6 within the base layer 6.

[0362] In this example, the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 of the first layer 8. Furthermore, the first region thickness TR1 is greater than the second thickness T2 of the second layer 9. Furthermore, the first region thickness TR1 is greater than the second region thickness TR2 of the second region 15. Of course, the first region thickness TR1 may be less than the first thickness T1. Furthermore, the first region thickness TR1 may be less than the second thickness T2. Furthermore, the first region thickness TR1 may be less than the second region thickness TR2.

[0363] The first gradually increasing portion 20A, the first peak portion 21A, the first slow portion 22A, and the first gradually decreasing portion 23A of the first region 14 are located in the first layer 8. At least a portion of the first gradually decreasing portion 23A is located in the base layer 6. That is, the extension portion of the first lower end portion 14a includes the first gradually decreasing portion 23A. Of course, a portion of the first slow portion 22A may also be located in the base layer 6 (see Figure 13E ). That is, the extension portion of the first lower end portion 14a may include a portion of the first slow portion 22A and the first tapering portion 23A.

[0364] exist Figure 22 , an example is shown in which the first layer 8 has a first thickness T1 of 3 μm and the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV. Of course, the first region 14 can also be formed by an implantation energy of 960 KeV or more. For example, the first thickness T1 can also be greater than 3 μm and less than 5 μm. In this case, the first region 14 partially located in the base layer 6 is formed by an implantation energy of 960 KeV or more (also refer to FIG. 13F to FIG. 13F). Figure 13E ).

[0365] Figure 23 It is a cross-sectional perspective view showing the column region 12 according to the fifth embodiment. Figure 24 It shows Figure 23 Graph showing an example of the concentration gradient of the column region 12. Figure 23 as well as Figure 24 The column region 12 of the fifth embodiment has a configuration that deforms the first region 14 of the fourth embodiment. The second region 15 of the fifth embodiment has the same configuration as the second region 15 of the second embodiment. Of course, the second region 15 of the fifth embodiment may also have the same configuration as the second region 15 of the third embodiment.

[0366] In the fourth embodiment, the first layer 8 has a first thickness T1 of 3 μm, and the first region 14 is formed in the first layer 8 using an implantation energy of 960 KeV or greater. In contrast, in the fifth embodiment, the first layer 8 has a first thickness T1 of less than 3 μm, and the first region 14 is formed in the first layer 8 using an implantation energy of 650 KeV or greater. In this example, the first region 14 has a first region thickness TR1 that is greater than the first thickness T1. In this example, the first thickness T1 is less than the second thickness T2 of the second layer 9.

[0367] For example, the first thickness T1 may be greater than or equal to 1 μm and less than or equal to 2 μm. In this case, the first region 14 partially located in the base layer 6 is formed by implantation energy of 190 KeV or more (also refer to FIG. Figures 13A to 13E For example, the first thickness T1 may be greater than 2 μm and less than 3 μm. In this case, the first region 14 partially located in the base layer 6 is formed by implantation energy of 380 KeV or more (also refer to Figures 13B to 13E ).

[0368] Figure 25 It is a cross-sectional perspective view showing the column region 12 according to the sixth embodiment. Figure 26 It shows Figure 25 Graph showing an example of the concentration gradient of the column region 12. Figure 25 as well as Figure 26 In addition to the first region 14 and the second region 15 , the pillar region 12 further includes a p-type intermediate region 25 between the first region 14 and the second region 15 .

[0369] The first region 14 may have the same configuration as any of the first region 14 in the first to fifth embodiments. In this example, the first region 14 has the same configuration as the first region 14 in the fourth embodiment. The second region 15 may have the same configuration as any of the second region 15 in the first to fifth embodiments. In this example, the second region 15 has the same configuration as the second region 15 in the fourth embodiment (second embodiment).

[0370] The plurality of intermediate regions 25 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be located at least at the plurality of intersections between the plurality of first regions 14 and the plurality of second regions 15, and overlap with the corresponding first regions 14 and second regions 15 in the stacking direction. In this manner, the plurality of intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 so as to overlap with the plurality of first regions 14 in a one-to-one correspondence in the stacking direction, and are each formed in a strip shape extending along the first extension direction De1.

[0371] In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y). Of course, the arrangement direction and extension direction of the plurality of intermediate regions 25 vary depending on the first arrangement direction Da1 and first extension direction De1 of the plurality of first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis and m-axis directions, and the first extension direction De1 may be a direction other than the a-axis and m-axis directions.

[0372] The plurality of intermediate regions 25, together with the plurality of first regions 14, extend from the active region 10 to the peripheral region 11. Specifically, the plurality of intermediate regions 25 extend from the portion of the first layer 8 located within the active region 10 to the portion of the first layer 8 located within the peripheral region 11. The plurality of intermediate regions 25 are also arranged in the peripheral region 11 at intervals in the first arrangement direction Da1, and are each formed into a strip extending in the first extension direction De1.

[0373] Each of the plurality of intermediate regions 25 has a portion extending from the outer peripheral region 11 toward one or both (in this embodiment, both) of the first side surface 5A and the third side surface 5C and exposed from one or both (in this embodiment, both) of the first side surface 5A and the third side surface 5C.

[0374] The portions of the plurality of intermediate regions 25 exposed from the first side surface 5A form a portion (upper end portion) of the plurality of first marks Mk1 on the first side surface 5A, and the portions of the plurality of intermediate regions 25 exposed from the third side surface 5C form a portion (upper end portion) of the plurality of first marks Mk1 on the third side surface 5C. In other words, the plurality of intermediate regions 25 include either or both of the portion (upper end portion) of the plurality of first marks Mk1 exposed from the first side surface 5A as the exposed portion and the portion (upper end portion) of the plurality of first marks Mk1 exposed from the third side surface 5C as the exposed portion.

[0375] In other words, the plurality of first marks Mk1 are formed using the plurality of first regions 14 and the plurality of intermediate regions 25. That is, the layout (exposed portion, arrangement direction) of the plurality of first marks Mk1 with respect to the first side surface 5A (third side surface 5C) is also appropriately adjusted based on the layout (first arrangement direction Da1, first extension direction De1) of the plurality of first regions 14 and the plurality of intermediate regions 25.

[0376] The first marks Mk1 do not necessarily need to be formed continuously from the main body of the intermediate regions 25 and may be formed as separate portions separated from the main body of the intermediate regions 25. In this case, the first marks Mk1 are preferably separated from the main body of the intermediate regions 25 in the outer peripheral region 11.

[0377] Of course, the plurality of intermediate regions 25 do not necessarily need to form a portion (upper end portion) of the plurality of first markings Mk1. Specifically, the plurality of intermediate regions 25 may be formed on the inner side of the first layer 8, spaced apart from the first to fourth side surfaces 5A to 5D in a plan view. The description of the intermediate regions 25 also applies to the first markings Mk1 (the portion of the intermediate regions 25 exposed from the first side surface 5A / third side surface 5C).

[0378] Multiple intermediate regions 25 are formed within the first layer 8 in the region between the upper end of the first layer 8 and the first upper end portion 14b of the first region 14. The multiple intermediate regions 25 are preferably located toward the upper end of the first layer 8 relative to the middle of the thickness range of the first layer 8. The multiple intermediate regions 25 may be exposed from the upper end of the first layer 8 or may be formed spaced apart from the upper end toward the lower end of the first layer 8. Each intermediate region 25 may also be formed in a horizontally elongated columnar shape extending in a cross-sectional view. Of course, each intermediate region 25 may also be formed in a vertically elongated columnar shape extending in the vertical direction Z.

[0379] The plurality of intermediate regions 25, together with the first layer 8, form a plurality of intermediate pn junctions with charge balance. In other words, the plurality of intermediate regions 25 constitute a portion of the plurality of first drift regions 16 and the first superjunction structure SJ1. This charge balance means that, for the plurality of adjacent intermediate regions 25, the depletion layer extending from one intermediate pn junction and the depletion layer extending from another intermediate pn junction are connected within the plurality of first drift regions 16.

[0380] Reference Figure 26 Each intermediate region 25 may also include a single or multiple region elements 25a. Figure 26 , an example is shown in which each intermediate region 25 includes a plurality (two) of region elements 25a. When each intermediate region 25 is composed of a single region element 25a, the single region element 25a is formed in a region between the upper end of the first layer 8 and the first upper end portion 14b of the first region 14, and is connected to the first upper end portion 14b of the first region 14.

[0381] When each intermediate region 25 is composed of multiple region elements 25a, the multiple region elements 25a are formed at different depths in the region between the upper end of the first layer 8 and the first upper end portion 14b of the first region 14. In this case, the multiple region elements 25a are formed so as to be connected to each other in the stacking direction. Furthermore, at least the lowest region element 25a is connected to the first upper end portion 14b of the first region 14.

[0382] The region element 25a is composed of a random impurity region introduced into the surface portion of the first layer 8 by a random implantation method into the first layer 8 (also refer to Figure 14). That is, the region element 25a is not formed in the second layer 9. Furthermore, the region element 25a has a thickness along the first-axis channel CH1 that is smaller than the first region thickness TR1 of the first region 14. Furthermore, the thickness of the region element 25a is smaller than the second region thickness TR2 of the second region 15.

[0383] Unlike the first region 14 and the like, the domain elements 25a do not have a slow portion 22 having a thickness of 0.5 μm or greater, but instead have a concentration gradient within a range of 0.5 μm that includes a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23. When each intermediate region 25 includes a plurality of domain elements 25a, each intermediate region 25 has a plurality of peaks 21 (peaks P) corresponding to the number of domain elements 25a in the thickness direction of the first layer 8.

[0384] The area element 25a may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. Figure 26 In FIG. 1 , it is shown that the peak value P of the p-type impurity concentration of the region element 25a is 1×10 16 cm -3 Above and 1×10 17 cm -3 The following example.

[0385] The p-type impurity concentration in the intermediate region 25 is preferably adjusted by at least one trivalent element. The trivalent element in the intermediate region 25 may be the same as or different from the trivalent element in the first region 14 and the like. The trivalent element in the intermediate region 25 may be at least one of boron, aluminum, gallium, and indium.

[0386] Each of the plurality of intermediate regions 25 has an intermediate width WM. The intermediate width WM is the width along the first arrangement direction Da1. The intermediate width WM is preferably less than the first thickness T1 of the first layer 8. Of course, the intermediate width WM may be greater than the first thickness T1. The intermediate width WM is preferably less than the second thickness T2 of the second layer 9. Of course, the intermediate width WM may be greater than the second thickness T2.

[0387] The intermediate width WM is preferably substantially equal to the first width W1 of the first region 14. Of course, the intermediate width WM may be greater than or less than the first width W1. The intermediate width WM is preferably greater than or equal to 1 μm. The intermediate width WM is preferably less than or equal to 5 μm.

[0388] The middle width WM can have a value belonging to any range of 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0389] Each of the plurality of intermediate regions 25 has a median thickness TM. The median thickness TM is preferably greater than or equal to the distance between the upper end of the first layer 8 and the first upper end portion 14b of the first region 14. The median thickness TM may be greater than or equal to 0.1 μm and less than or equal to 2 μm. The median thickness TM may have a value within any range of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0390] The plurality of intermediate regions 25 are formed at intervals of intermediate pitch PM in the first arrangement direction Da1. The intermediate pitch PM is preferably substantially equal to the first pitch P1 of the first region 14. Of course, the intermediate pitch PM can be greater than or less than the first pitch P1. Figure 25 , for clarity, an intermediate pitch PM that is larger than the first pitch P1 is shown.

[0391] The intermediate pitch PM may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The intermediate pitch PM may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm. Preferably, the intermediate pitch PM is greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0392] In such a configuration, the second region 15 preferably has an extension located within the first layer 8 and is connected to the intermediate region 25 within the first layer 8. That is, the second region 15 is preferably electrically connected to the first region 14 via the intermediate region 25 within the first layer 8. In this case, the second region 15, the first region 14, and the intermediate region 25 together form a single drift region 13 that extends continuously in the stacking direction.

[0393] Of course, the extension of the second region 15 may be connected to both the intermediate region 25 and the first region 14 within the first layer 8. In a structure having the intermediate region 25, the concentration gradient between the first region 14 and the second region 15 is mitigated by the intermediate region 25, thereby improving the accuracy of charge balance.

[0394] Figure 27 It is a cross-sectional perspective view showing the column region 12 of the seventh embodiment. Figure 28 It shows Figure 27 Graph showing an example of the concentration gradient of the column region 12. Figure 27 as well as Figure 28 The column region 12 of the seventh embodiment is a deformed version of the first region 14 of the first to sixth embodiments. The second region 15 of the seventh embodiment may have the same configuration as any of the second regions 15 of the first to sixth embodiments.

[0395] In this example, the first region 14 is exposed from the upper end of the first layer 8. The first region 14 does not have a part or all of the first gradually increasing portion 20A. Figure 28 , an example is shown in which the first region 14 does not include all of the first gradually increasing portion 20A and the first peak portion 21A. That is, in this example, the first upper end portion 14b includes the first slow portion 22A exposed from the upper end of the first layer 8.

[0396] The first region 14 has a first peak PA at the upper end of the first layer 8 and has a concentration gradient that gradually decreases toward the lower end of the first layer 8. Of course, the first upper end portion 14b may also include a portion of the first gradually increasing portion 20A or a portion of the first peak portion 21A, and a portion of the first gradually increasing portion 20A or a portion of the first peak portion 21A may be exposed from the upper end of the first layer 8.

[0397] In this structure, the second region 15 preferably has an extension located within the first layer 8 and is connected to the first region 14 within the first layer 8. In a structure in which the first region 14 is exposed from the upper end of the first layer 8, the concentration gradient formed in the region between the first region 14 and the second region 15 is mitigated by the exposed portion of the first region 14, thereby improving the accuracy of charge balance.

[0398] This structure is achieved by partially removing the upper end of the first layer 8 after forming the first region 14 until a portion or all of the first gradually increasing portion 20A of the first region 14 disappears. For example, the upper end of the first layer 8 can also be partially removed by grinding. The grinding method can be mechanical grinding and / or chemical mechanical grinding. In this case, the upper end of the first layer 8 comprises a ground surface, and the first region 14 is exposed from this ground surface. The second layer 9 is laminated on the ground surface of the first layer 8.

[0399] For example, the upper end of first layer 8 may be partially removed by etching. The etching method may be wet etching and / or dry etching. In this case, the upper end of first layer 8 is formed by an etched surface, and first region 14 is exposed from this etched surface. Second layer 9 is laminated on the etched surface of first layer 8.

[0400] Figure 29 It is a cross-sectional perspective view showing the column region 12 according to the eighth embodiment. Figure 30 It shows Figure 29 Graph showing an example of the concentration gradient of the column region 12. Figure 29 as well as Figure 30 The column region 12 of the eighth embodiment has a deformed form of the second region 15 of the first to seventh embodiments. The first region 14 of the eighth embodiment may also have the same form as any of the first regions 14 of the first to seventh embodiments. Figure 29 as well as Figure 30 , the first region 14 of the seventh embodiment is shown.

[0401] In this example, the second region 15 is exposed from the upper end (first main surface 3) of the second layer 9. The second region 15 does not have a part or all of the second gradually increasing portion 20B. Figure 30 , an example is shown in which the second region 15 does not include all of the second gradually increasing portion 20B and the second peak portion 21B. That is, in this example, the second upper end portion 15b includes the second slow portion 22B exposed from the upper end of the second layer 9.

[0402] The second region 15 has a second peak PB at the upper end of the second layer 9 and has a concentration gradient that gradually decreases toward the lower end of the second layer 9. Of course, the second upper end 15b may also include a portion of the second gradually increasing portion 20B or a portion of the second peak portion 21B, and a portion of the second gradually increasing portion 20B or a portion of the second peak portion 21B may be exposed from the upper end of the second layer 9.

[0403] The structure in which the second region 15 is exposed from the upper end of the second layer 9 is effective in adjusting the electrical characteristics of the device structure using the second region 15 when forming a device structure using the second layer 9 (first main surface 3 ).

[0404] This structure is achieved by partially removing the upper end of the second layer 9 after forming the second region 15 until a portion or all of the second gradually increasing portion 20B of the second region 15 disappears. For example, the upper end (first main surface 3) of the second layer 9 can also be partially removed by grinding. The grinding method can be mechanical grinding and / or chemical mechanical grinding. In this case, the upper end of the second layer 9 is formed by a ground surface, and the second region 15 is exposed from this ground surface.

[0405] For example, the upper end (first main surface 3) of the second layer 9 may be partially removed by etching. The etching method may be wet etching and / or dry etching. In this case, the upper end of the second layer 9 is formed by an etched surface, and the second region 15 is exposed from the etched surface.

[0406] Figure 31 It is a cross-sectional perspective view showing the column region 12 according to the ninth embodiment. Figure 32 1 is a perspective view showing a cross section of the column region 12 according to the tenth embodiment. Figure 31 as well as Figure 32 The laminated portion 7 may have a laminated structure including a buffer layer 26, a first layer 8, and a second layer 9 laminated in order from the base layer 6. The buffer layer 26 may also be referred to as a "buffer SiC layer," a "buffer region," or the like.

[0407] Buffer layer 26 is composed of SiC single crystal and has n-type conductivity. Buffer layer 26 is stacked on base layer 6. Buffer layer 26 extends horizontally in a layered manner, forming the center portion of chip 2 and a portion of first to fourth side surfaces 5A to 5D. Buffer layer 26 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from base layer 6.

[0408] The buffer layer 26 has a lower end and an upper end. The lower end of the buffer layer 26 is the starting point of crystal growth, and the upper end of the buffer layer 26 is the end point of crystal growth. The buffer layer 26 continuously crystallizes and grows from the base layer 6, so the lower end of the buffer layer 26 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 26 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The buffer layer 26 has an offset direction Doff and an offset angle θoff that are substantially consistent with those of the base layer 6.

[0409] The buffer layer 26 has a buffer axis channel CHBu along the stacking direction. The buffer axis channel CHBu is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the buffer layer 26 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0410] That is, the buffer axis channel CHBu is a region where the atomic rows are sparsely distributed and extends in the stacking direction. When viewed from above, the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse. The buffer axis channel CHBu is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0411] In this method, the buffer axis channel CHBu is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. Specifically, the buffer axis channel CHBu extends along the c-axis and has an off direction Doff and an off angle θoff. In other words, the buffer axis channel CHBu is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff.

[0412] The n-type impurity concentration of the buffer layer 26 is preferably lower than that of the base layer 6. The buffer layer 26 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the buffer layer 26 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 26 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0413] The buffer layer 26 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 26 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 26 preferably includes a pentavalent element other than phosphorus.

[0414] The n-type impurity concentration of buffer layer 26 is preferably adjusted by at least nitrogen. When buffer layer 26 includes two or more pentavalent elements, buffer layer 26 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, buffer layer 26 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0415] The buffer layer 26 has a buffer thickness TBu. The buffer thickness TBu is preferably less than the base thickness TB. The buffer thickness TBu is preferably 1 μm or greater. The buffer thickness TBu is preferably 5 μm or less. The buffer thickness TBu may have a value within any range of 1 μm or greater and 1.5 μm or less, 1.5 μm or greater and 2 μm or less, 2 μm or greater and 2.5 μm or less, 2.5 μm or greater and 3 μm or less, 3 μm or greater and 3.5 μm or less, 3.5 μm or greater and 4 μm or less, 4 μm or greater and 4.5 μm or less, and 4.5 μm or greater and 5 μm or less.

[0416] In this embodiment, first layer 8 is stacked on buffer layer 26, and second layer 9 is stacked on first layer 8. First layer 8 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) crystallized and grown from buffer layer 26 and has n-type conductivity. Therefore, first layer 8 has an off direction Doff and an off angle θoff that are substantially consistent with those of buffer layer 26. Furthermore, first axial channel CH1 is substantially consistent with buffer axial channel CHBu.

[0417] The first thickness T1 of the first layer 8 is preferably greater than the buffer thickness TBu. Of course, the first thickness T1 may be less than the buffer thickness TBu. Alternatively, the first thickness T1 may be approximately equal to the buffer thickness TBu. The second thickness T2 of the second layer 9 is preferably greater than the buffer thickness TBu. Of course, the second thickness T2 may be less than the buffer thickness TBu. Alternatively, the second thickness T2 may be approximately equal to the buffer thickness TBu.

[0418] The first region 14 has the same configuration as that of the first region 14 in the first to eighth embodiments and is formed in the first layer 8. The second region 15 has the same configuration as that of the first region 14 in the first to eighth embodiments and is formed in the second layer 9.

[0419] Reference Figure 31 The first lower end portion 14a of the first region 14 may be formed spaced apart from the lower end of the first layer 8 toward the upper end, and may be opposed to the buffer layer 26 via a portion (the lower end portion) of the first layer 8. In other words, the entire first region 14 (the first gradually increasing portion 20A, the first peak portion 21A, the first slow portion 22A, and the first gradually decreasing portion 23A) may be located within the first layer 8. Of course, the first lower end portion 14a may also be substantially aligned with the lower end of the first layer 8 and connected to the buffer layer 26.

[0420] Reference Figure 32 The first lower end portion 14a may also have an extension portion that crosses the boundary between the buffer layer 26 and the first layer 8 and is located within the buffer layer 26. The first axial channel CH1 and the buffer axial channel CHBu are substantially consistent, so the extension portion of the first lower end portion 14a is formed within the buffer layer 26 along the buffer axial channel CHBu.

[0421] The extension of the first lower end portion 14a is preferably located on the upper side of the buffer layer 26 relative to the middle of the thickness range of the buffer layer 26. The extension of the first lower end portion 14a includes the first tapering portion 23A. Of course, the extension of the first lower end portion 14a may also include a portion of the first slow portion 22A and the first tapering portion 23A.

[0422] Figure 33 1 is a perspective view showing a cross section of the column region 12 of the eleventh embodiment. In the above embodiment, the main idea that a superstructure SJ having a stacked structure of three or more layers can be adopted is described. Figure 33 , as an example, the stacked portion 7 having a three-layer structure and the pillar region 12 having a three-layer structure are shown.

[0423] Specifically, the laminated portion 7 includes an n-type third layer 27 made of SiC single crystal laminated on the second layer 9. The third layer 27 may also be referred to as a "third SiC layer," a "third semiconductor layer," or the like. In this example, the second layer 9 forms the middle portion of the chip 2 and forms a portion of the first to fourth side surfaces 5A to 5D. The third layer 27 extends in a layered manner in the horizontal direction, forming the first principal surface 3 and forming a portion of the first to fourth side surfaces 5A to 5D. The third layer 27 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from the second layer 9.

[0424] The third layer 27 has a lower end and an upper end. The lower end of the third layer 27 is the starting point of crystal growth, and the upper end of the third layer 27 is the end point of crystal growth. The third layer 27 grows continuously from the second layer 9, so the lower end of the third layer 27 coincides with the upper end of the second layer 9. The boundary between the second layer 9 and the third layer 27 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The third layer 27 has an offset direction Doff and an offset angle θoff that are substantially consistent with those of the second layer 9.

[0425] The third layer 27 has a third-axis channel CH3 along the stacking direction. The third-axis channel CH3 is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the buffer layer 27 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0426] Specifically, the third-axis channel CH3 is a region where the atomic rows are sparsely spaced, extending in the stacking direction. When viewed from above, the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse. The third-axis channel CH3 is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0427] In this method, the third-axis channel CH3 is formed by a region surrounded by atomic rows oriented along the c-axis of the SiC single crystal. Specifically, the third-axis channel CH3 extends along the c-axis and has an off direction Doff and an off angle θoff. In other words, the third-axis channel CH3 is tilted from the vertical axis toward the off direction Doff by the amount of the off angle θoff.

[0428] The n-type impurity concentration of the third layer 27 is preferably lower than that of the base layer 6. The third layer 27 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the third layer 27 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the third layer 27 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0429] The third layer 27 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the third layer 27 can be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The third layer 27 preferably includes a pentavalent element other than phosphorus.

[0430] The n-type impurity concentration of the third layer 27 is preferably adjusted by at least nitrogen. When the third layer 27 includes two or more pentavalent elements, the third layer 27 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, the third layer 27 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0431] The third layer 27 has a third thickness T3. The third thickness T3 is preferably less than the base thickness TB. The third thickness T3 can be approximately equal to the second thickness T2, or greater than the second thickness T2, or less than the second thickness T2. The third thickness T3 can be approximately equal to the first thickness T1, or greater than the first thickness T1, or less than the first thickness T1.

[0432] The third thickness T3 is preferably not less than 1 μm. The third thickness T3 is preferably not more than 5 μm. The third thickness T3 may have a value within any range of not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, not less than 2.5 μm and not more than 3 μm, not less than 3 μm and not more than 3.5 μm, not less than 3.5 μm and not more than 4 μm, not less than 4.5 μm and not more than 4.5 μm, or not less than 5 μm.

[0433] The pillar region 12 includes a third region 28 formed in the third layer 27. Multiple third regions 28 are formed horizontally spaced apart within the third layer 27, defining multiple n-type third drift regions 29, each formed from a portion of the third layer 27. The multiple third regions 28 and the multiple third drift regions 29 together form multiple third pn junctions with balanced charge.

[0434] That is, the plurality of third regions 28 constitute the third layer 27 and the third superjunction structure SJ2. The charge-balanced state means that, for the plurality of adjacent third regions 28, the depletion layer extending from one third pn junction and the depletion layer extending from another third pn junction are connected within the plurality of third drift regions 29.

[0435] The plurality of third regions 28 are formed within the third layer 27 so as to overlap with the plurality of second regions 15 in the stacking direction. Specifically, the plurality of third regions 28 are arranged at intervals within the third layer 27 in a third arrangement direction Da3, which is different from the second arrangement direction Da2, and are each formed in a stripe shape extending in a third extension direction De3, which is different from the second extension direction De2. In other words, the plurality of third regions 28 are formed in a stripe shape extending along the third extension direction De3, and the plurality of third drift regions 29 are formed in a stripe shape extending along the third extension direction De3.

[0436] The plurality of third regions 28 intersect the plurality of second regions 15 in a plan view. Therefore, the plurality of third drift regions 29 connect to the plurality of second drift regions 17 at the boundary between the second layer 9 and the third layer 27, and together with the plurality of first drift regions 16 and the plurality of second drift regions 17, form a three-dimensional lattice-shaped drift region 13. Together with the plurality of first drift regions 16 and the plurality of second drift regions 17, the plurality of third drift regions 29 form a three-dimensional lattice-shaped current path extending in the stacking direction.

[0437] The third arrangement direction Da3 may also coincide with the first arrangement direction Da1. Furthermore, the third extension direction De3 may also coincide with the first extension direction De1. That is, the plurality of third regions 28 may extend in the same direction as the plurality of first regions 14 when viewed from above. In this case, the plurality of third regions 28 may also be arranged in a one-to-one correspondence with the plurality of first regions 14 in the stacking direction.

[0438] Of course, the plurality of third regions 28 may also be arranged staggered from the plurality of first regions 14 in the first arrangement direction Da1, and opposed to either or both of the first regions 14 and the first drift region 16 in the stacking direction. Of course, the third arrangement direction Da3 may also be different from the first arrangement direction Da1. Furthermore, the third extension direction De3 may also be different from the first extension direction De1. In other words, the plurality of third regions 28 may also intersect (e.g., be orthogonal to) the plurality of first regions 14 when viewed from above.

[0439] Although not shown in detail, in this embodiment, the plurality of third regions 28 extend from the active region 10 to the peripheral region 11. That is, the plurality of third regions 28 extend from the portion of the third layer 27 located within the active region 10 to the portion of the third layer 27 located within the peripheral region 11. The plurality of third regions 28 are also arranged in the peripheral region 11 at intervals in the third arrangement direction Da3 and are each formed in a strip shape extending in the third extension direction De3.

[0440] In addition, the plurality of third regions 28 each have a portion extending from the outer peripheral region 11 toward either or both (in this embodiment, both) the first side face 5A and the third side face 5C and exposed from either or both (in this embodiment, both) the first side face 5A and the third side face 5C.

[0441] The portions of the plurality of third regions 28 exposed from the first side surface 5A form a plurality of third marks (not shown) on the first side surface 5A, and the portions of the plurality of third regions 28 exposed from the third side surface 5C form a plurality of third marks on the third side surface 5C. In other words, the plurality of third regions 28 include either or both of the plurality of third marks exposed from the first side surface 5A and the plurality of third marks exposed from the third side surface 5C.

[0442] In other words, the plurality of third marks are formed using a portion (exposed portion) of the plurality of third regions 28. The plurality of third marks define a plurality of third spaces on the first side surface 5A (third side surface 5C). The plurality of third marks and the plurality of third spaces are formed on the first side surface 5A (third side surface 5C) in the same layout as the plurality of first marks Mk1 and the plurality of first spaces Sp1.

[0443] Therefore, the description of the plurality of first marks Mk1 (plurality of first spaces Sp1) applies to the description of the plurality of third marks (plurality of third spaces). The layout (exposed locations, arrangement direction) of the plurality of third marks relative to the first side surface 5A (third side surface 5C) is appropriately adjusted based on the layout (third arrangement direction Da3, third extension direction De3) of the plurality of third regions 28.

[0444] The plurality of third marks do not necessarily need to be formed continuously from the main body of the plurality of third regions 28, and may be formed as separate portions separated from the main body of the plurality of third regions 28. In this case, the plurality of third marks are preferably separated from the main body of the plurality of third regions 28 in the peripheral region 11. The description of the third region 28 also applies to the third marks (the portion of the third region 28 exposed from the first side surface 5A / third side surface 5C).

[0445] The plurality of third regions 28 are formed of channel regions (third channel regions) extending along the third-axis channel CH3 within the third layer 27 when viewed in cross section. Specifically, the third regions 28 are impurity regions introduced parallel or substantially parallel to the region within the third layer 27 surrounded by atomic rows along the low-index crystal axis (third-axis channel CH3), and extend obliquely with respect to the first principal surface 3.

[0446] Each of the plurality of third regions 28 includes a third lower end portion 28a located at the lower end of the third layer 27 and a third upper end portion 28b located at the upper end of the third layer 27. The third lower end portion 28a is located at the lower end of the third layer 27 relative to the middle of the thickness range of the third layer 27, while the third upper end portion 28b is located at the upper end of the third layer 27 relative to the middle of the thickness range of the third layer 27. In other words, each of the plurality of third regions 28 is composed of a single impurity region having a thickness (depth) that extends across the middle of the third layer 27 along the third-axis channel CH3.

[0447] The third lower end portion 28a may be formed spaced apart from the lower end of the third layer 27 toward the upper end, and may face the second layer 9 via a portion (lower end portion) of the third layer 27. The third lower end portion 28a may also be substantially aligned with the lower end of the third layer 27 and connected to the second layer 9.

[0448] The distance between the lower end of the third layer 27 and the third lower end portion 28a may be 0 μm or more and 2 μm or less. The distance between the lower end of the third layer 27 and the third lower end portion 28a may have a value within any range of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0449] The third lower end portion 28a may include an extension portion that crosses the boundary between the second layer 9 and the third layer 27 and is located within the second layer 9. In this case, the thickness of the extension portion of the third lower end portion 28a may be greater than 0 μm and less than 2 μm relative to the upper end of the second layer 9. The thickness of the extension portion of the third lower end portion 28a may also be within any of the following ranges: greater than 0 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, and greater than 1.5 μm and less than 2 μm.

[0450] The third upper end portion 28b may be formed spaced apart from the upper end (i.e., first main surface 3) of the third layer 27 toward the lower end, and may be opposed to the upper end of the third layer 27 via a portion (upper end) of the third layer 27. The third upper end portion 28b may be exposed from the upper end (i.e., first main surface 3) of the third layer 27.

[0451] The distance between the upper end of the third layer 27 and the third upper end portion 28b may be 0 μm or more and 1 μm or less. The distance between the upper end of the third layer 27 and the third upper end portion 28b may have a value within any range of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0452] The third regions 28 may also have a 1×1015 cm -3 Above and 1×10 18 cm -3 The p-type impurity concentration (peak value) of the third region 28 may be equal to or greater than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the third region 28 may be lower than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the third region 28 may be substantially equal to the p-type impurity concentration (peak value) of the first region 14.

[0453] The p-type impurity concentration in the third region 28 is preferably adjusted by at least one trivalent element. The p-type impurity concentration in the third region 28 is particularly preferably adjusted by a trivalent element heavier than carbon. Specifically, the third region 28 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration in the third region 28 is adjusted by aluminum.

[0454] Each of the plurality of third regions 28 has a third width W3. The third width W3 is the width along the third arrangement direction Da3. The third width W3 is preferably less than the third thickness T3 of the third layer 27. Of course, the third width W3 may be greater than the third thickness T3. The third width W3 is preferably less than the first thickness T1 of the first layer 8. Of course, the third width W3 may be greater than the first thickness T1. The third width W3 is preferably less than the second thickness T2 of the second layer 9. Of course, the third width W3 may be greater than the second thickness T2.

[0455] The third width W3 may be greater than or less than the first width W1 of the first region 14. The third width W3 is preferably substantially equal to the first width W1. The third width W3 may be greater than or less than the second width W2 of the second region 15. The third width W3 is preferably substantially equal to the second width W2.

[0456] The third width W3 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The third width W3 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The third width W3 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0457] Each of the plurality of third regions 28 has a third region thickness TR3. The third region thickness TR3 may be smaller than the third thickness T3 of the third layer 27. The third region thickness TR3 may be larger than the third thickness T3. The third region thickness TR3 may be substantially equal to the third thickness T3.

[0458] The third region thickness TR3 may be smaller than the first thickness T1 of the first layer 8. The third region thickness TR3 may be larger than the first thickness T1. The third region thickness TR3 may be approximately equal to the first thickness T1. The third region thickness TR3 may be smaller than the second thickness T2 of the second layer 9. The third region thickness TR3 may be larger than the second thickness T2. The third region thickness TR3 may be approximately equal to the second thickness T2.

[0459] The third region thickness TR3 is preferably 1 μm or greater. The third region thickness TR3 is preferably 5 μm or less. The third region thickness TR3 may have a value within any range of 1 μm or greater and 1.5 μm or less, 1.5 μm or greater and 2 μm or less, 2 μm or greater and 2.5 μm or less, 2.5 μm or greater and 3 μm or less, 3 μm or greater and 3.5 μm or less, 3.5 μm or greater and 4 μm or less, 4 μm or greater and 4.5 μm or less, and 4.5 μm or greater and 5 μm or less.

[0460] The third width W3 is preferably smaller than the third thickness T3 of the third layer 27, and the third region thickness TR3 is preferably greater than the third width W3. Specifically, the plurality of third regions 28 preferably each have a third aspect ratio TR3 / W3 extending in a vertically elongated columnar shape along the third axial channel CH3. The third aspect ratio TR3 / W3 is the ratio of the third region thickness TR3 to the third width W3. In this case, the third region thickness TR3 is particularly preferably greater than the third thickness T3. For example, the third aspect ratio TR3 / W3 may be greater than 1 and less than 100.

[0461] The plurality of third regions 28 are formed at intervals of a third pitch P3 in the third arrangement direction Da3. The third pitch P3 is preferably less than the third thickness T3 of the third layer 27. Of course, the third pitch P3 may be greater than the third thickness T3. The third pitch P3 is preferably less than the first thickness T1 of the first layer 8. Furthermore, the third pitch P3 is preferably less than the second thickness T2 of the second layer 9. Of course, the third pitch P3 may be greater than the first thickness T1. Furthermore, the third pitch P3 may be greater than the second thickness T2.

[0462] The third pitch P3 can be approximately equal to or different from the first pitch P1. The third pitch P3 can be larger or smaller than the first pitch P1. The third pitch P3 can be approximately equal to or different from the second pitch P2. The third pitch P3 can be larger or smaller than the second pitch P2.

[0463] The third pitch P3 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The third pitch P3 may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm and less than or equal to 5 μm. The third pitch P3 is preferably greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

[0464] also, Figures 13A to 13E The description of the concentration gradient shown applies to the description of the concentration gradient of the third region 28. In addition, the structures of the first region 14 (first layer 8) and the second region 15 (second layer 9) shown in the first to twelfth embodiments apply to the structure of the third region 28 (third layer 27).

[0465] Figure 34 1 is a perspective view showing a cross section of the column region 12 according to the twelfth embodiment. Figure 34 In this example, laminated portion 7 includes a single-crystalline n-type SiC cap layer 30 laminated on second layer 9. Cap layer 30 is formed to separate first principal surface 3 from pillar region 12. Specifically, cap layer 30 forms at least a portion of the region between first principal surface 3 and second upper end portions 15b of the plurality of second regions 15. Cap layer 30 can also be considered to form the upper end portion of second layer 9.

[0466] In this example, the top layer 30 has an n-type conductivity, but the conductivity type of the top layer 30 can be appropriately adjusted according to the properties of the device structure formed on the first main surface 3. Therefore, the conductivity type of the top layer 30 is not necessarily limited to n-type and can also be p-type.

[0467] The top layer 30 is stacked on the second layer 9. The top layer 30 extends horizontally in a layered manner, forming the first main surface 3 and forming a portion of the first to fourth side surfaces 5A to 5D. The top layer 30 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from the second layer 9.

[0468] The top layer 30 is continuously crystallized and grown from the second layer 9. Therefore, the lower end of the top layer 30 coincides with the upper end of the second layer 9. The boundary between the top layer 30 and the second layer 9 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The top layer 30 has an offset direction Doff and an offset angle θoff that are substantially consistent with those of the second layer 9.

[0469] The top layer 30 has an axial trench CHT along the stacking direction. The axial trench CHT is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the top layer 30 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0470] In other words, the apical channel CHT is a region where the atomic rows are sparse, extending in the stacking direction, and the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The apical channel CHT is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0471] In this method, the apical channel CHT is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. Specifically, the apical channel CHT extends along the c-axis and has an off direction Doff and an off angle θoff. In other words, the apical channel CHT is tilted from the vertical axis toward the off direction Doff by the off angle θoff.

[0472] The n-type impurity concentration of the top layer 30 is preferably lower than that of the base layer 6. The top layer 30 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the top layer 30 can be approximately equal to the n-type impurity concentration of the first layer 8 (second layer 9). The n-type impurity concentration of the top layer 30 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the top layer 30 can also have a concentration gradient that gradually increases and / or decreases in the stacking direction (crystal growth direction).

[0473] The top layer 30 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the top layer 30 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The top layer 30 preferably includes a pentavalent element other than phosphorus.

[0474] The n-type impurity concentration of the top layer 30 is preferably adjusted by at least nitrogen. When the top layer 30 includes two or more pentavalent elements, the top layer 30 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, the top layer 30 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0475] The top layer 30 has a top thickness TT. The top thickness TT is preferably less than the base thickness TB. The top thickness TT is preferably less than the first thickness T1 (second thickness T2). Of course, the top thickness TT can also be greater than the first thickness T1 (second thickness T2).

[0476] The top thickness TT may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The top thickness TT may have a value falling within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm.

[0477] An example of a device structure formed in the active region 10 will be described below. Figure 35 FIG. 1 is a top view showing a main portion of the active region 10 . Figure 36 : is a cross-sectional perspective view showing the gate structure 35 of the first embodiment. Figure 36 In the embodiment, the structure of the column region 12 of the first basic embodiment is applied to the column region 12 of the second embodiment. Figure 36 In the embodiment, a structure in which any one or more of the pillar regions 12 of the first to twelfth embodiments are applied to any one of the pillar regions 12 of the first to third basic embodiments may be applied.

[0478] Reference Figure 35 as well as Figure 36 In this embodiment, the SiC semiconductor device 1A includes a MIS structure 31 (Metal Insulator Semiconductor structure) as an example of a device structure formed in the active region 10. The MIS structure 31 may also be called a "field effect transistor structure."

[0479] Here, an example is shown in which the MIS structure 31 is formed on the second layer 9 (first main surface 3). When the top layer 30 is formed, the MIS structure 31 is formed on the top layer 30 (first main surface 3). This embodiment can be achieved by replacing "second layer 9" with "top layer 30" as needed in the following description. The following configuration is described as a component of the SiC semiconductor device 1A, but it is also a component of the MIS structure 31.

[0480] The SiC semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. The plurality of body regions 32 are formed in the surface layer portion of the first main surface 3 so as to overlap with the plurality of second regions 15 in the stacking direction. In this manner, the plurality of body regions 32 are arranged at intervals in the second arrangement direction Da2 so as to overlap with the plurality of second regions 15 in a one-to-one correspondence in the stacking direction, and are each formed in a strip shape extending along the second extension direction De2.

[0481] In this example, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X). Of course, the arrangement direction and extension direction of the plurality of main body regions 32 vary depending on the second arrangement direction Da2 and second extension direction De2 of the plurality of second regions 15. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis and the m-axis directions, and the second extension direction De2 may be a direction other than the a-axis and the m-axis directions.

[0482] When the plurality of second regions 15 are formed spaced apart from the first main surface 3, the plurality of main regions 32 are formed in the region between the first main surface 3 and the second upper end portions 15b of the plurality of second regions 15. The plurality of main regions 32 are preferably formed on the first main surface 3 side relative to the middle portion of the thickness range of the second layer 9 and exposed from the first main surface 3. The plurality of main regions 32 are preferably connected to the corresponding second regions 15 (second upper end portions 15b).

[0483] The plurality of body regions 32 are each formed to be wider than the second region 15 directly below them, and are spaced apart from the adjacent plurality of second regions 15 toward the second region 15 directly below them. The plurality of body regions 32 expose a portion of the second drift region 17 from the region between the adjacent plurality of second regions 15 on the first major surface 3.

[0484] The plurality of body regions 32 are composed of random impurity regions introduced into the surface portion of the second layer 9 by a random implantation method into the second layer 9 (also refer to FIG. Figure 14 Therefore, the plurality of body regions 32 have a thickness along the second axis channel CH2 that is smaller than the second region thickness TR2 of the second region 15. The thickness of the plurality of body regions 32 is smaller than the first region thickness TR1 of the first region 14.

[0485] The plurality of main body regions 32 are different from the second region 15 and the like, and do not have a slow portion 22 having a thickness of 0.5 μm or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. The plurality of main body regions 32 may also have a concentration gradient of 1×10 15cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are taken as peak values.

[0486] The p-type impurity concentration of the plurality of body regions 32 is preferably adjusted by at least one trivalent element. The trivalent element in the body regions 32 may be the same as or different from the trivalent element in the second regions 15 and the like. The trivalent element in the body regions 32 may be at least one of boron, aluminum, gallium, and indium.

[0487] The SiC semiconductor device 1A includes one or more n-type source regions 33 formed in the surface portion of each of the plurality of body regions 32 in the active region 10. In this embodiment, a plurality (two in this embodiment) of source regions 33 are formed at intervals in the surface portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 9 (the plurality of second drift regions 17). The plurality of source regions 33 may also have a 1×10 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentrations are taken as peak values.

[0488] The plurality of source regions 33 may also extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of source regions 33 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The plurality of source regions 33, together with the plurality of second drift regions 17, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.

[0489] SiC semiconductor device 1A includes one or more p-type contact regions 34 formed on the surface of each of the plurality of body regions 32 in active region 10. Contact region 34 may also be referred to as a "back gate region." In this embodiment, a single contact region 34 is formed on the surface of each body region 32, between adjacent source regions 33.

[0490] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15. The plurality of contact regions 34 may also have a 1×10 18 cm -3 Above and 1×10 21cm -3 The following p-type impurity concentrations are taken as peak values.

[0491] The plurality of contact regions 34 may extend in a strip shape along the extension direction of the corresponding main body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding main body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding main body region 32 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding main body region 32 toward the inside.

[0492] The SiC semiconductor device 1A includes multiple planar electrode-type gate structures 35 disposed on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The multiple gate structures 35 are arranged on the first main surface 3 at intervals so as to overlap with at least one body region 32 (channel) in the stacking direction. A gate potential serving as a control potential is applied to the multiple gate structures 35. The multiple gate structures 35 control the inversion and non-inversion of the channel (current path) within the body region 32 in response to the gate potential.

[0493] In this embodiment, the plurality of gate structures 35 are arranged at intervals in the second arrangement direction Da2, and are each formed into a strip shape extending in the second extension direction De2. In this example, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).

[0494] Of course, the arrangement direction and extension direction of the plurality of gate structures 35 vary depending on the second arrangement direction Da2 and second extension direction De2 of the plurality of second regions 15 (body regions 32). Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis and the m-axis directions, and the second extension direction De2 may be a direction other than the a-axis and the m-axis directions.

[0495] The plurality of gate structures 35 are arranged offset from the plurality of second regions 15 toward the plurality of second drift regions 17, overlapping the plurality of second drift regions 17 in a one-to-one correspondence in the stacking direction. In this manner, the plurality of gate structures 35 are arranged so as to straddle two adjacent body regions 32, respectively covering the plurality of source regions 33 located in one and the other body regions 32.

[0496] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film, and the gate electrode 37 may include conductive polysilicon.

[0497] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap with the second region 15 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap with the second region 15 in the stacking direction.

[0498] The structure on the outer peripheral region 11 side is shown below. Figure 37 It is a perspective view showing the structure of the outer peripheral area 11. Figure 38A 1 is a cross-sectional view taken along the first direction X, showing a main portion of the outer peripheral region 11 . Figure 38B 1 is a cross-sectional view of a main portion of the outer peripheral region 11 in the second direction Y. Figure 37 In the figure, the pillar region 12 is omitted.

[0499] SiC semiconductor device 1A includes at least one (preferably two or more and twenty or less) p-type field region 38 formed in the surface portion of first main surface 3 in peripheral region 11. The number of field regions 38 is typically four or more and eight or less. Field regions 38 are electrically floating and mitigate the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, and p-type impurity concentration of field regions 38 are arbitrary and can take various values depending on the electric field to be mitigated.

[0500] Multiple field regions 38 are formed at intervals in the region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in a strip shape extending along the active region 10 in a plan view. Each of the multiple field regions 38 includes a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this manner, the multiple field regions 38 are formed in a ring shape (specifically, a four-sided ring shape) surrounding the active region 10 in a plan view.

[0501] The plurality of field regions 38 overlap with the pillar regions 12 in the stacking direction in the peripheral region 11. That is, the plurality of field regions 38 are formed in the region above the plurality of intersections of the plurality of first regions 14 and the plurality of second regions 15. In a plan view, the plurality of field regions 38 intersect with the plurality of second regions 15 in portions extending along the first extension direction De1, and intersect with the plurality of first regions 14 in portions extending along the second extension direction De2.

[0502] Multiple field regions 38 are formed in second layer 9 at intervals extending from the lower end of second layer 9 toward first principal surface 3, each forming a pn junction with second layer 9. Multiple field regions 38 preferably have a bottom portion located toward first principal surface 3 relative to the middle of the thickness range of second layer 9. The bottom portion of multiple field regions 38 is particularly preferably located toward first principal surface 3 relative to the middle of the thickness range of second region 15.

[0503] The bottoms of the plurality of field regions 38 may be located closer to the second lower end 15a of the second region 15 than the depth position of the second upper end 15b of the second region 15. In this case, the plurality of field regions 38 may be connected to the plurality of second regions 15 in the portion extending along the second extension direction De2. Of course, the plurality of field regions 38 may be formed horizontally spaced apart from the plurality of second regions 15 in the portion extending along the second extension direction De2, without being connected to the plurality of second regions 15.

[0504] For example, when the distance between the first principal surface 3 and the second upper end portion 15b is sufficiently wide, the bottoms of the plurality of field regions 38 may be located closer to the first principal surface 3 than the depth position of the second upper end portion 15b of the second region 15. Of course, when the top layer 30 is formed, the bottoms of the plurality of field regions 38 may be located closer to the first principal surface 3 than the depth position of the second upper end portion 15b of the second region 15.

[0505] The plurality of field regions 38 may also have a thickness substantially equal to that of the plurality of body regions 32. In this case, the plurality of field regions 38 can be formed simultaneously with the plurality of body regions 32. Of course, the thickness of the plurality of field regions 38 may also be greater than the thickness of the plurality of body regions 32. In addition, the thickness of the plurality of field regions 38 may also be less than the thickness of the plurality of body regions 32.

[0506] The plurality of field regions 38 are composed of random impurity regions introduced into the surface portion of the second layer 9 by a random implantation method into the second layer 9 (also refer to FIG. Figure 14 Thus, the plurality of field regions 38 have a thickness along the second axis channel CH2 that is smaller than the second region thickness TR2 of the second region 15 . The thickness of the plurality of field regions 38 is smaller than the first region thickness TR1 of the first region 14 .

[0507] The plurality of field regions 38 are different from the second region 15 and the like, and do not have a slow portion 22 having a thickness of 0.5 μm or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. The plurality of field regions 38 may also have a concentration gradient of 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are taken as peak values.

[0508] The p-type impurity concentration of the field regions 38 may be substantially equal to the p-type impurity concentration of the body regions 32. Of course, the p-type impurity concentration of the plurality of field regions 38 may be higher than the p-type impurity concentration of the plurality of body regions 32. Furthermore, the p-type impurity concentration of the plurality of field regions 38 may be lower than the p-type impurity concentration of the plurality of body regions 32.

[0509] The p-type impurity concentration of the plurality of field regions 38 is preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as or different from the trivalent element in the second regions 15 and the like. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0510] The plurality of field regions 38 preferably have a width different from the second width W2 of the second region 15 (the first width W1 of the first region 14 ). In other words, the electric field relaxation effect of the plurality of field regions 38 is preferably adjusted separately from the pillar region 12 .

[0511] The width of the plurality of field regions 38 is preferably greater than the second width W2 (first width W1) of the second region 15. Of course, the width of the plurality of field regions 38 may also be less than the second width W2 (first width W1). Furthermore, the width of the pillar region 12 may also be substantially equal to the second width W2 (first width W1).

[0512] The plurality of field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second region 15 (the first pitch P1 of the first region 14). The pitch between the plurality of field regions 38 is particularly preferably greater than the second pitch P2 (the first pitch P1). Of course, the pitch between the plurality of field regions 38 may also be less than the second pitch P2 (the first pitch P1). Furthermore, the pitch between the plurality of field regions 38 may also be substantially equal to the second pitch P2 (the first pitch P1).

[0513] SiC semiconductor device 1A includes an interlayer insulating film 40 covering first main surface 3. Interlayer insulating film 40 may also be referred to as an "insulating film," "interlayer film," or "intermediate insulating film." In this embodiment, interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42. First insulating film 41 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. First insulating film 41 preferably includes a silicon oxide film formed from the oxide of chip 2 (second layer 9).

[0514] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers the plurality of field regions 38 in the peripheral region 11.

[0515] In this embodiment, the first insulating film 41 is continuous with the periphery of the first principal surface 3 (the first to fourth side surfaces 5A to 5D). Therefore, the first insulating film 41 overlaps with the plurality of second marks Mk2 (the plurality of second regions 15) at the periphery of the first principal surface 3. Of course, the first insulating film 41 can also be formed spaced inward from the periphery of the first principal surface 3, so that the second layer 9 is exposed from the periphery of the first principal surface 3.

[0516] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11 via the first insulating film 41.

[0517] The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 in the peripheral region 11 via the first insulating film 41. In this manner, the second insulating film 42 is connected to the periphery of the first main surface 3. The second insulating film 42 may also overlap with the plurality of second marks Mk2 (plurality of second regions 15) via the first insulating film 41 at the periphery of the first main surface 3. Of course, the second insulating film 42 may also be formed spaced inward from the periphery of the first main surface 3 so that the periphery of the first main surface 3 is exposed together with the first insulating film 41.

[0518] The SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose the plurality of gate structures 35 (gate electrodes 37) and a plurality of contact openings 43 that expose the plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in the region between the plurality of adjacent gate structures 35, exposing the plurality of source regions 33 and the plurality of contact regions 34.

[0519] Reference Figure 1 SiC semiconductor device 1A includes a gate pad 45 disposed on interlayer insulating film 40. Gate pad 45 is an electrode to which a gate potential is externally applied. Gate pad 45 may also be referred to as a "gate pad electrode," "first pad electrode," or the like. Gate pad 45 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked sequentially from the interlayer insulating film 40 side.

[0520] In this embodiment, gate pad 45 is disposed on the portion of interlayer insulating film 40 that covers active region 10. Gate pad 45 may also be disposed on the active region 10 side at a distance from peripheral region 11. In this embodiment, gate pad 45 is disposed on the peripheral portion of active region 10 in a plan view.

[0521] exist Figure 1 , an example is shown in which gate pad 45 is arranged in a region along the center of first side surface 5A at the periphery of active region 10. Of course, gate pad 45 may also be arranged in a region along the center of any of first to fourth side surfaces 5A to 5D. Of course, gate pad 45 may also be arranged at any corner of active region 10 when viewed from above. Furthermore, gate pad 45 may also be arranged in the center of active region 10 when viewed from above. In this embodiment, gate pad 45 is formed into a quadrilateral shape when viewed from above.

[0522] SiC semiconductor device 1A includes at least one (or in this embodiment, multiple) gate wiring 46 extending from gate pad 45 onto interlayer insulating film 40. Gate wiring 46 may also be referred to as "wiring," "wiring electrode," or the like. Multiple gate wirings 46 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked sequentially from the interlayer insulating film 40 side. In this embodiment, multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0523] A first gate wiring line 46A extends from the gate pad 45 toward the second side surface 5B and extends linearly along the periphery of the active area 10, intersecting (specifically, orthogonally) a portion (specifically, one end) of the plurality of gate structures 35. The first gate wiring line 46A penetrates the interlayer insulating film 40 via a plurality of contact openings 43 and is electrically connected to one end of the plurality of gate structures 35.

[0524] The second gate wiring 46B extends from the gate pad 45 toward the fourth side surface 5D and extends linearly along the periphery of the active area 10 so as to intersect (specifically, be perpendicular to) a portion (specifically, the other end portions) of the plurality of gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via a plurality of contact openings 43 and is electrically connected to the other end portions of the plurality of gate structures 35.

[0525] SiC semiconductor device 1A includes a source pad 47 disposed on interlayer insulating film 40, spaced apart from gate pad 45 and gate wiring 46. Source pad 47 is an electrode to which a source potential is externally applied. Source pad 47 may also be referred to as a "source pad electrode," "second pad electrode," or the like. Source pad 47 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked sequentially from the interlayer insulating film 40 side.

[0526] Source pad 47 is disposed on the portion of interlayer insulating film 40 that covers active region 10. Source pad 47 may also be disposed on the active region 10 side, spaced apart from peripheral region 11. In this embodiment, source pad 47 is formed into a polygonal shape having a recessed portion along gate pad 45 when viewed from above. Of course, source pad 47 may also be formed into a quadrilateral shape when viewed from above.

[0527] Source pad 47 penetrates interlayer insulating film 40 via contact openings 43 and is electrically connected to body regions 32 , source regions 33 , and contact regions 34 . That is, source pad 47 is electrically connected to pillar region 12 via body regions 32 .

[0528] The SiC semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is externally applied. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4. Specifically, the drain pad 48 is electrically connected to the first layer 8 (the plurality of first drift regions 16) and the second layer 9 (the plurality of second drift regions 17) via the base layer 6.

[0529] Alternatively, drain pad 48 may cover the entire area of second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of chip 2. Alternatively, drain pad 48 may cover second main surface 4 at intervals inward from the periphery of chip 2 so as to expose the periphery of chip 2.

[0530] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) can be 500 V or more and 3000 V or less. The breakdown voltage can have a value falling within any range of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0531] When the laminated portion 7 having a two-layer structure is used, the breakdown voltage is preferably set to a value within any range of 500 V to 1000 V, 1000 V to 1500 V, and 1500 V to 2000 V. When the laminated portion 7 having a three-layer structure is used, the breakdown voltage is preferably set to a value within any range of 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0532] Figure 391 is a cross-sectional perspective view showing a gate structure 35 according to a second embodiment. The gate structures 35 of the first embodiment extend along the second extension direction De2 of the second regions 15. In contrast, the gate structures 35 of the second embodiment extend in a direction other than the second extension direction De2, intersecting the second regions 15.

[0533] In this embodiment, the plurality of main body regions 32 extend in directions other than the second extension direction De2, intersecting the plurality of second regions 15 in the stacking direction. In this embodiment, the plurality of main body regions 32 are arranged at intervals in the first arrangement direction Da1 of the first regions 14 and extend in the first extension direction De1 of the first regions 14. That is, the plurality of main body regions 32 are orthogonal to the plurality of second regions 15. In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).

[0534] The plurality of body regions 32 may also be arranged in a one-to-one correspondence with the plurality of first regions 14 in the stacking direction. Of course, each body region 32 may also be arranged in a one-to-one correspondence with the plurality of first regions 14 in the stacking direction. The plurality of body regions 32 may also be arranged in a one-to-one correspondence with the plurality of first drift regions 16 in the stacking direction.

[0535] Of course, each body region 32 may also be opposite to the plurality of first drift regions 16 in the stacking direction. Alternatively, the plurality of body regions 32 may be arranged staggered from the plurality of first regions 14 in the first arrangement direction Da1 and opposite to either or both of the first regions 14 and the first drift region 16 in the stacking direction.

[0536] Of course, the arrangement direction and extension direction of the plurality of main body regions 32 vary depending on the first arrangement direction Da1 and the first extension direction De1 of the plurality of first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis and the m-axis directions, and the first extension direction De1 may be a direction other than the a-axis and the m-axis directions.

[0537] Of course, the arrangement direction of the plurality of main body regions 32 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the plurality of main body regions 32 may be a direction other than the first extension direction De1 and the second extension direction De2. That is, the plurality of main body regions 32 may intersect both the plurality of first regions 14 and the plurality of second regions 15 when viewed from above. In this case, it is also possible for the arrangement direction of the plurality of main body regions 32 to be one of the a-axis direction and the m-axis direction, while the extension direction of the plurality of main body regions 32 to be the other of the a-axis direction and the m-axis direction.

[0538] For example, the angle (absolute value) between the extension direction of the main body region 32 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the main body region 32 may have a value within any range of greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°. The angle (absolute value) of the main body region 32 may also be set to a value within any range of 30°±5°, 45°±5°, and 60°±5°.

[0539] The aforementioned plurality of source regions 33 and plurality of contact regions 34 are formed along the extending direction of the corresponding body regions 32 , and respectively face the plurality of second regions 15 and the plurality of second drift regions 17 via a portion of the corresponding body region 32 in the stacking direction.

[0540] In this embodiment, the plurality of gate structures 35 are arranged at intervals in a first arrangement direction Da1 of the first region 14 and extend in a first extension direction De1 of the first region 14. That is, the plurality of gate structures 35 are orthogonal to the plurality of second regions 15. In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).

[0541] The plurality of gate structures 35 may also be disposed opposite the plurality of first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may also be disposed opposite the plurality of first regions 14 in the stacking direction. The plurality of gate structures 35 may also be disposed opposite the plurality of first drift regions 16 in a one-to-one correspondence in the stacking direction.

[0542] Of course, each gate structure 35 may also be opposite to the plurality of first drift regions 16 in the stacking direction. The plurality of gate structures 35 may also be arranged staggered from the plurality of first regions 14 in the first arrangement direction Da1, and opposite to either or both of the first regions 14 and the first drift region 16 in the stacking direction.

[0543] Of course, the arrangement direction and extension direction of the multiple gate structures 35 vary depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis and the m-axis directions, and the first extension direction De1 may be a direction other than the a-axis and the m-axis directions.

[0544] Of course, the arrangement direction of the multiple gate structures 35 may also be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the multiple gate structures 35 may also be a direction other than the first extension direction De1 and the second extension direction De2. That is, the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 when viewed from above. In this case, it is also possible for the arrangement direction of the multiple gate structures 35 to be one of the a-axis direction and the m-axis direction, and for the extension direction of the multiple gate structures 35 to be the other of the a-axis direction and the m-axis direction.

[0545] For example, the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the gate structure 35 may also have a value within any range of greater than 0° and less than 18°, greater than 18° and less than 36°, greater than 36° and less than 54°, greater than 54° and less than 72°, and greater than 72° and less than 90°. The angle (absolute value) of the gate structure 35 may also be set to a value within any range of 30°±5°, 45°±5°, and 60°±5°.

[0546] In this embodiment, the plurality of gate structures 35 are arranged so as to straddle two adjacent body regions 32, respectively covering the plurality of source regions 33 located in one and the other body regions 32. Furthermore, the plurality of gate structures 35 are opposed to the plurality of second regions 15 (second regions 15) and the plurality of second drift regions 17 in the stacking direction.

[0547] Figure 40 This is a schematic diagram showing a wafer 50 used in the manufacture of SiC semiconductor device 1A. Wafer 50 is the base material of base layer 6 and is composed of SiC single crystal. Wafer 50 is formed into a flat disk shape. Of course, wafer 50 can also be formed into a flat rectangular parallelepiped shape. Wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0548] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the aforementioned off direction Doff and off angle θoff.

[0549] Wafer 50 has a mark 54 on wafer side 53 indicating the crystal orientation of the SiC single crystal. Mark 54 may include either or both an orientation flat and an orientation notch. The orientation flat is formed by a notch that appears linear when viewed from above. The orientation notch is formed by a notch that is cut into a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 51 when viewed from above.

[0550] The mark 54 may also include either or both of a first orientation flat extending along the m-axis direction and a second orientation flat extending along the a-axis direction. The mark 54 may also include either or both of an orientation notch recessed toward the m-axis direction and an orientation notch recessed toward the a-axis direction. Figure 40 , an orientation plane extending along the a-axis direction when viewed from above is shown.

[0551] For example, a plurality of device regions 55 and a plurality of planned cutting lines 56 are defined on the wafer 50 by alignment marks, etc. Each device region 55 corresponds to the SiC semiconductor device 1A and is defined in a rectangular shape in a plan view.

[0552] In this method, multiple device regions 55 are arranged in a matrix along the first direction X and the second direction Y when viewed from above. The multiple device regions 55 are spaced inward from the periphery of the first wafer main surface 51 when viewed from above. Multiple planned cutting lines 56 are arranged in a grid pattern extending along the first direction X and the second direction Y to divide the multiple device regions 55.

[0553] Figure 41 This is a flowchart showing an example of a method for manufacturing the SiC semiconductor device 1A. Figures 42A to 42H It is a cross-sectional perspective view showing an example of a method for manufacturing the SiC semiconductor device 1A. Figures 43A and 43B This is a schematic diagram for explaining the crystal orientation measurement process. Figures 44A and 44B This is a schematic diagram for explaining the ion implantation process. Figures 42A to 42H A cross-sectional perspective view of a portion of the active region 10 showing one device region 55 .

[0554] First, refer to Figure 42A , implement the aforementioned preparation process of the wafer 50 ( Figure 41Next, whether to implement the n-type buffer layer 26 (refer to Figure 31 as well as Figure 32 ) forming process determination process ( Figure 41 Step S2). In the case of forming the buffer layer 26 ( Figure 41 Step S2: Yes), a buffer layer 26 ( Figure 41 Step S3). In the case where the buffer layer 26 formation step is not performed ( Figure 41 Step S2: No), this process is omitted.

[0555] Next, refer to Figure 42B , implement the formation process of the n-type first layer 8 ( Figure 41 In step S4 of the embodiment of the present invention, if the buffer layer 26 formation step is omitted, the first layer 8 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50). If the buffer layer 26 is formed, the first layer 8 is formed by epitaxial growth starting from the buffer layer 26. In this case, the first layer 8 can also be formed by continuous crystal growth from the buffer layer 26 after the buffer layer 26 formation step.

[0556] Next, a step of measuring the crystal orientation of the first layer 8 is performed ( Figure 41 The crystal orientation of the first layer 8 includes a step of measuring the off angle θoff of the first layer 8. That is, this step includes a step of measuring the crystal orientation of the first-axis channel CH1 of the first layer 8.

[0557] Wafer 50 is cut from an ingot (SiC ingot) as a crystal block, but there is a risk of errors in the off angle θoff due to process errors. If the off angle θoff of wafer 50 is distorted, the off angle θoff of first layer 8 will also be distorted, causing obstacles during the channel implantation process. Therefore, it is preferable to obtain data (information) on the off angle θoff before the channel implantation process and perform the channel implantation process based on this data (information) on the off angle θoff.

[0558] Reference Figure 43A In this step, the crystal orientation of the first layer 8 is measured by X-ray diffraction (so-called ω-2θ measurement method) using an X-ray diffraction device 57. The X-ray diffraction device 57 may also be called an "XRD (X-ray Diffraction) device."

[0559] The X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59, and performs a rocking curve measurement method. The irradiation unit 58 irradiates the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50) with incident X-rays L1 having a predetermined incident angle ω. The incident angle ω is defined by the angle between the incident X-rays L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).

[0560] Detection unit 59 is positioned at a diffraction angle 2θ (θ is the Bragg angle) relative to the irradiation position of incident X-ray L1 on wafer 50, and detects diffracted X-ray L2. Diffraction angle 2θ is the angle between the incident direction of incident X-ray L1 and the diffraction direction of diffracted X-ray L2.

[0561] In the rocking curve measurement method, while the diffraction angle 2θ is fixed, the incident angle ω is varied within a small angular range to measure a rocking curve representing the intensity of the diffracted X-ray L2 (the intensity distribution of the diffracted X-ray L2). The rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is determined at the angular position where the intensity of the diffracted X-ray L2 reaches its peak.

[0562] In this step, the rocking curve measurement method is performed on only one portion (e.g., the center portion) of the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50). If in-plane variation of the off angle θoff is assumed, the rocking curve measurement method may be performed on multiple portions (e.g., the center portion and the peripheral portion) of the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).

[0563] exist Figure 43B , the measurement positions when the rocking curve measurement method is performed on multiple positions (here, 5 positions) of the upper end of the first layer 8 are shown. The off angle θoff of the first layer 8 is set to about 4°. Figure 43B In FIG, the first to fifth measurement points Po1 to Po5 are shown.

[0564] The first measurement point Po1 is set at the center of the first layer 8. The second measurement point Po2 is set at the peripheral edge of the first layer 8 at a distance from the first measurement point Po1 to one side in the second direction Y (the side opposite to the mark 54). The third measurement point Po3 is set at the peripheral edge of the first layer 8 at a distance from the first measurement point Po1 to one side in the first direction X (the right side with respect to the mark 54).

[0565] The fourth measurement point Po4 is set at a distance from the first measurement point Po1 toward the other side in the second direction Y (toward the mark 54) at the peripheral edge of the first layer 8. The fifth measurement point Po5 is set at a distance from the first measurement point Po1 toward the other side in the first direction X (to the left of the mark 54) at the peripheral edge of the first layer 8.

[0566] The measurement results of the incident angle ω, diffraction angle 2θ, and deviation angle θoff at the first to fifth measurement points Po1 to Po5 are shown in Table 1 below. The deviation angle θoff was calculated using the incident angle ω and diffraction angle 2θ using the formula "ω - (2θ × 1 / 2)".

[0567] Table 1

[0568] Table 1

[0569]

[0570] As shown in Table 1, the average value of the off angle θoff at the first to fifth measurement points Po1 to Po5 is 4.036°, and the standard deviation of these off angles θoff is 0.009° (±0.01°). This shows that the in-plane variation of the off angle θoff generated at the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50) is extremely small and does not hinder the channel implantation process.

[0571] Therefore, it can be understood that there is no problem with measuring at least one location at the top end of the first layer 8 (the first wafer main surface 51 of the wafer 50). For example, the measurement location can also be any one or more (or all) of the first to fifth measurement points Po1 to Po5. For example, the measurement location can also be only the first measurement point Po1. By reducing the number of measurement locations (the number of measurements), manufacturing man-hours (manufacturing costs) can be reduced.

[0572] Of course, it is also possible to measure the off angle θoff at multiple locations on the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50) and set the implantation angle corresponding to the in-plane variation of the off angle θoff during the channel implantation process. In this case, while the manufacturing man-hours (manufacturing costs) increase, the in-plane variation of the first region 14 formed in the first layer 8 is appropriately suppressed.

[0573] The off angle θoff of the first layer 8 is substantially consistent with the off angle θoff of the wafer 50 and the off angle θoff of the buffer layer 26. Therefore, the crystal orientation measurement step can be performed on the wafer 50 or the buffer layer 26 before the step of forming the first layer 8. However, from the perspective of desired accuracy, it is preferable to perform the crystal orientation measurement step on the first layer 8.

[0574] Next, refer to Figure 42C , a step of forming a first mask 60 having a predetermined pattern is performed ( Figure 41 Step S6). The first mask 60 is preferably an organic mask (resist mask). The first mask 60 is arranged on the upper end of the first layer 8 and has a plurality of first openings 61 in the first layer 8 that expose areas where the plurality of first regions 14 are to be formed.

[0575] Specifically, multiple first openings 61 are formed across the entire surface of the upper end of the first layer 8 at intervals in the first arrangement direction Da1, each of which is divided into stripes extending along the first extension direction De1. In other words, the multiple first openings 61 traverse the multiple device regions 55 and the multiple planned cutting lines 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple planned cutting lines 56 in a stripe-like pattern. The multiple first openings 61 expose both the portion of the upper end of the first layer 8 located within the active region 10 and the portion located within the peripheral region 11 in each device region 55.

[0576] Next, refer to Figure 42D , implement the formation process of multiple first regions 14 ( Figure 41 The step of forming the plurality of first regions 14 includes a channel implantation step of implanting a trivalent element (p-type impurity) into the first layer 8. The first layer 8 (wafer 50) has an off angle θoff, which is tilted at a predetermined angle in a predetermined off direction Doff relative to the first wafer main surface 51. The channel implantation step is performed based on data (information) regarding the off angle θoff.

[0577] Reference Figure 44A In the random implantation method, a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axis channel CH1 (off angle θoff) (also refer to Figure 14 For example, in the random implantation method, the trivalent element is implanted along the vertical direction Z perpendicular to the upper end of the first layer 8 (the first wafer main surface 51 ).

[0578] In the case of the random injection method, the trivalent element is introduced along the direction in which the atomic array is relatively dense when viewed from above, so the trivalent element collides with the atomic array at a relatively shallow depth. Therefore, the introduction of the trivalent element to a relatively deep depth position of the first layer 8 is hindered by the atomic array. As a result, the first region 14 without the slow portion 22 is formed (also refer to Figure 14 ).

[0579] On the other hand, refer to Figure 44B In the channel implantation method, the injection angle of the trivalent element relative to the first layer 8 is controlled, and the trivalent element is introduced into the first layer 8 at a predetermined injection energy along the first axis channel CH1 (in this method, the c-axis of the SiC single crystal) (also refer to Figures 13A to 13E In this case, either or both of the injection angle of the trivalent element with respect to the first layer 8 and the tilt angle of the first layer 8 with respect to the injection angle of the trivalent element are adjusted.

[0580] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the first layer 8 along the first axis channel CH1. Of course, the wafer 50 may be supported in a state tilted by an offset angle θoff relative to the horizontal, and the trivalent element may be introduced into the first layer 8 along the first axis channel CH1. By any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (the temperature of the wafer 50), a plurality of first regions 14 having a predetermined thickness are formed at predetermined depth positions (also refer to FIG. Figures 13A to 13E ).

[0581] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV. The implantation energy may have a value falling within any range of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0582] The implantation temperature of the trivalent element can be adjusted within a range of 0° C. to 1500° C. The implantation temperature may have a value falling within any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0583] The injection angle of the trivalent element is preferably set within a range of ±2° relative to the axis along the first-axis channel CH1 (in this embodiment, the c-axis of the SiC single crystal) (0°). The injection angle of the trivalent element is particularly preferably set within a range of ±1° relative to the axis along the first-axis channel CH1 (in this embodiment, the c-axis of the SiC single crystal) (0°).

[0584] In the case of the channel implantation method, the trivalent element is introduced along the first-axis channel CH1, where the atomic array is relatively sparse when viewed from above. The trivalent element propagates within the first-axis channel CH1 while repeatedly performing small-angle scattering due to the channeling effect, reaching a relatively deep position in the first layer 8. In other words, in the case of the channel implantation method, the probability of the trivalent element colliding with the atomic array of the SiC single crystal is reduced.

[0585] In this case, a trivalent element heavier than carbon is preferably introduced into the first layer 8. Specifically, the trivalent element is preferably a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0586] The first extension direction De1 may also be the a-axis direction or the m-axis direction. The first extension direction De1 may also be a direction other than the a-axis direction and the m-axis direction. When the first extension direction De1 is consistent with the m-axis direction (also refer to Figure 8A The trivalent element is introduced into the first layer 8 through the plurality of first openings 61 in a cross-sectional view along the first arrangement direction Da1, which are inclined approximately by an angle θoff relative to the upper end of the first layer 8.

[0587] When the first extending direction De1 coincides with the a-axis direction (offset direction Doff) (also refer to Figure 10A The trivalent element is introduced into the first layer 8 through the plurality of first openings 61 in a cross-sectional view along the first arrangement direction Da1, approximately perpendicularly relative to the upper end of the first layer 8. Therefore, the plurality of first regions 14 are prevented from being formed in the first layer 8 in an inclined posture. Furthermore, the wall surfaces of the plurality of first openings 61 are prevented from becoming shields against the incident path of the trivalent element.

[0588] When the first extending direction De1 is a direction other than the a-axis direction and the m-axis direction (also refer to Figures 12A to 12C etc.), there is no need to strictly control the alignment deviation of the plurality of first regions 14 relative to the crystal orientation of the SiC single crystal.

[0589] After the trivalent element implantation step, annealing can be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like generated in the first layer 8. The annealing temperature for the first layer 8 can be between 500°C and 2000°C. This allows the formation of the first regions 14 and the first superjunction structure SJ1.

[0590] The plurality of first regions 14 are arranged at intervals in the first arrangement direction Da1 across the entire area of the first layer 8, and are each formed to extend in a stripe shape in the first extension direction De1. Specifically, the plurality of first regions 14 are formed in a stripe shape so as to cross the plurality of device regions 55 and the plurality of planned cutting lines 56 along the first extension direction De1. After the formation step of the plurality of first regions 14, the first mask 60 is removed.

[0591] Next, a determination step of whether to implement the thickness adjustment step of the first layer 8 is performed ( Figure 41 Step S8). In the case where the thickness of the first layer 8 is adjusted ( Figure 41 Step S8: Yes), the first layer 8 is thinned from the upper end side ( Figure 41 Step S9).

[0592] The thickness adjustment step (thinning step) may include a step of partially removing the upper end portion of the first layer 8 by grinding. The grinding method may be mechanical polishing and / or chemical mechanical polishing. The thickness adjustment step may include a step of partially removing the upper end portion of the first layer 8 by etching. The etching method may be wet etching and / or dry etching.

[0593] The thickness adjustment step may also include a step of exposing the plurality of first regions 14 from the upper end of the first layer 8 (also refer to Figures 27 to 30 That is, the thickness adjustment process may also include a process of removing part or all of the first gradually increasing portions 20A of the plurality of first regions 14. In the case where the thickness adjustment process is not performed ( Figure 41 Step S8: No), omit this process.

[0594] Next, whether to implement multiple intermediate areas 25 (also refer to Figure 25 as well as Figure 26 ) forming process determination process ( Figure 41 In the case of forming a plurality of intermediate regions 25 ( Figure 41 Step S10: Yes), a plurality of intermediate regions 25 are formed on the surface portion of the first layer 8 ( Figure 41 Step S11).

[0595] The step of forming the plurality of intermediate regions 25 includes placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8. The mask (not shown) is preferably an organic mask (resist mask). The mask (not shown) has a plurality of openings that expose the areas of the first layer 8 where the plurality of first regions 14 are formed.

[0596] Specifically, multiple openings are formed across the entire surface of the upper end of the first layer 8 at intervals in the first arrangement direction Da1, each of which is divided into stripes extending along the first extension direction De1. In other words, the multiple openings traverse the multiple device regions 55 and the multiple planned cutting lines 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple planned cutting lines 56 in a stripe-like pattern. In each device region 55, the multiple openings expose both the portion of the upper end of the first layer 8 located within the active region 10 and the portion located within the peripheral region 11.

[0597] The step of forming the plurality of intermediate regions 25 includes the step of introducing a trivalent element into the first layer 8 at a predetermined implantation energy in a direction intersecting the first axis channel CH1 (off angle θoff) by a random implantation method through a mask (not shown) (also refer to Figure 14The trivalent element may be introduced into the first layer 8 once or multiple times. When the trivalent element is introduced multiple times, the trivalent element may be introduced into the first layer 8 at different depths in multiple stages with multiple implantation energies.

[0598] The plurality of intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 across the entire area of the first layer 8, and are each formed to extend in a stripe shape in the first extension direction De1. Specifically, the plurality of intermediate regions 25 are formed in a stripe shape so as to cross the plurality of device regions 55 and the plurality of planned cutting lines 56 along the first extension direction De1. After the formation step of the plurality of intermediate regions 25, the mask (not shown) is removed.

[0599] Without performing the aforementioned thickness adjustment step of the first layer 8, the step of forming the plurality of intermediate regions 25 may be performed consecutively from the step of forming the plurality of first regions 14. In this case, the plurality of intermediate regions 25 may also be formed using the aforementioned first mask 60.

[0600] Next, refer to Figure 42E , implement the formation process of the second layer 9 ( Figure 41 Step S12). The second layer 9 is formed by epitaxial growth with the first layer 8 as the starting point. Figure 41 The same method as step S4 is used to implement the measurement process of the crystal orientation (off angle θoff) of the second layer 9 (also refer to Figure 43A as well as Figure 43B ).

[0601] Next, refer to Figure 42F , a step of forming a second mask 62 having a predetermined pattern is performed ( Figure 41 The second mask 62 is preferably an organic mask (resist mask). The second mask 62 is arranged on the upper end of the second layer 9 and has a plurality of second openings 63 in the second layer 9 to expose the areas where the plurality of second regions 15 are to be formed.

[0602] Specifically, multiple second openings 63 are formed across the entire surface of the upper end of the second layer 9 at intervals in a second arrangement direction Da2, which differs from the first arrangement direction Da1, and are each divided into stripes extending in a second extension direction De2, which differs from the first extension direction De1. In other words, the multiple second openings 63 traverse the multiple device regions 55 and the multiple planned cutting lines 56 in the second extension direction De2, exposing the multiple device regions 55 and the multiple planned cutting lines 56 in a stripe-like pattern. The multiple second openings 63 expose both the portion of the upper end of the second layer 9 located within the active region 10 and the portion located within the peripheral region 11 in each device region 55.

[0603] Next, refer to Figure 42G, implement the formation process of multiple second regions 15 ( Figure 41 The step of forming the plurality of second regions 15 includes a channel implantation step of implanting a trivalent element (p-type impurity) into the second layer 9. The channel implantation step is performed based on the data (information) of the off angle θoff.

[0604] In the channel implantation method, the trivalent element is implanted into the second layer 9 at a predetermined implantation energy along the second axis channel CH2 (in this method, the c-axis of the SiC single crystal) by controlling the implantation angle of the trivalent element relative to the second layer 9 (also refer to Figures 13A to 13E In this case, either or both of the injection angle of the trivalent element into the second layer 9 and the tilt angle of the second layer 9 relative to the injection angle of the trivalent element are adjusted.

[0605] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the second layer 9 along the second axis channel CH2. Of course, the wafer 50 may be supported in a state tilted by an offset angle θoff relative to the horizontal, and the trivalent element may be introduced into the second layer 9 along the second axis channel CH2. By any combination of the implantation energy and the implantation temperature of the trivalent element, a plurality of second regions 15 having a predetermined thickness are formed at predetermined depth positions (also refer to FIG. Figures 13A to 13E ).

[0606] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV. The implantation energy may have a value falling within any range of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0607] The implantation energy of the second region 15 may be substantially equal to or different from the implantation energy of the first region 14. The implantation energy of the second region 15 may be greater than the implantation energy of the first region 14. Furthermore, the implantation energy of the second region 15 may be less than the implantation energy of the first region 14.

[0608] The implantation temperature of the trivalent element can be adjusted within a range of 0° C. to 1500° C. The implantation temperature may have a value falling within any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0609] The injection temperature of the second region 15 may be substantially equal to or different from the injection temperature of the first region 14. The injection temperature of the second region 15 may be higher than the injection temperature of the first region 14. Furthermore, the injection temperature of the second region 15 may be lower than the injection temperature of the first region 14.

[0610] The injection angle of the trivalent element is preferably set within a range of ±2° relative to the axis along the second-axis channel CH2 (in this embodiment, the c-axis of the SiC single crystal) (0°). The injection angle of the trivalent element is particularly preferably set within a range of ±1° relative to the axis along the second-axis channel CH2 (in this embodiment, the c-axis of the SiC single crystal) (0°).

[0611] In the case of the channel implantation method, the trivalent element is introduced along the second-axis channel CH2, where the atomic array is relatively sparse when viewed from above. The trivalent element propagates within the second-axis channel CH2 while repeatedly performing small-angle scattering due to the channeling effect, reaching a relatively deep position in the second layer 9. In other words, in the case of the channel implantation method, the probability of the trivalent element colliding with the atomic array of the SiC single crystal is reduced.

[0612] In this case, a trivalent element heavier than carbon is preferably introduced into the second layer 9. Specifically, the trivalent element is preferably a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0613] The second extension direction De2 may also be the a-axis direction or the m-axis direction. The second extension direction De2 may also be a direction other than the a-axis direction and the m-axis direction. When the second extension direction De2 is consistent with the a-axis direction (deviation direction Doff) (also refer to Figure 8A The trivalent element is introduced into the second layer 9 through the plurality of second openings 63 in a cross-sectional view along the second arrangement direction Da2, approximately perpendicularly relative to the upper end of the second layer 9. Therefore, the plurality of second regions 15 are prevented from being formed in the second layer 9 in an inclined posture. Furthermore, the wall surfaces of the plurality of second openings 63 are prevented from becoming shields against the incident path of the trivalent element.

[0614] When the second extending direction De2 is consistent with the m-axis direction (also refer to Figure 10A The trivalent element is introduced into the second layer 9 through the plurality of second openings 63 in a cross-sectional view along the second arrangement direction Da2, which are inclined approximately by an angle θoff relative to the upper end of the second layer 9.

[0615] When the second extending direction De2 is a direction other than the a-axis direction and the m-axis direction (also refer to Figures 12A to 12C etc.), there is no need to strictly control the alignment deviation of the plurality of second regions 15 relative to the crystal orientation of the SiC single crystal.

[0616] When the first extension direction De1 of the first region 14 is a direction other than the a-axis and the m-axis, the second extension direction De2 is also preferably a direction other than the a-axis and the m-axis. In this case, the plurality of first regions 14 have a first extension angle θ1 that is inclined toward one side of the a-axis toward the m-axis, and the plurality of second regions 15 have a second extension angle θ2 that is inclined toward the other side of the a-axis toward the m-axis.

[0617] The absolute value of the second extension angle θ2 may be different from the absolute value of the first extension angle θ1. However, in this case, the relative injection angle conditions for the trivalent element during the formation step of the second region 15 differ from the relative injection angle conditions for the trivalent element during the formation step of the first region 14. Therefore, the shielding area of the plurality of second openings 63 with respect to the incident path of the trivalent element differs from the shielding area of the plurality of first openings 61 with respect to the incident path of the trivalent element.

[0618] That is, the process error of the plurality of second regions 15 caused by shielding of the plurality of second openings 63 is different from the process error of the plurality of first regions 14 caused by shielding of the plurality of first openings 61. Therefore, the absolute value of the second extension angle θ2 is preferably approximately equal to the absolute value of the first extension angle θ1. In this case, the process error of the plurality of second regions 15 is approximately the same as the process error of the plurality of first regions 14. Therefore, the accuracy of charge balancing is improved.

[0619] As an example, the first extension angle θ1 may be +45°±5°, and the second extension angle θ2 may be -45°±5° (see Figure 12A As an example, the first extension angle θ1 may be +30°±5°, and the second extension angle θ2 may be -30°±5° (see Figure 12B As an example, the first extension angle θ1 may be +60°±5°, and the second extension angle θ2 may be -60°±5° (see Figure 12C ).

[0620] After the trivalent element implantation step, annealing can be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like generated in the second layer 9. The annealing temperature for the second layer 9 can be between 500°C and 2000°C. This allows the formation of the plurality of second regions 15 and the second superjunction structure SJ2.

[0621] The plurality of second regions 15 are arranged at intervals in the second arrangement direction Da2 across the entire area of the second layer 9, and are each formed to extend in a stripe shape in the second extension direction De2. Specifically, the plurality of second regions 15 are formed in a stripe shape so as to cross the plurality of device regions 55 and the plurality of planned cutting lines 56 along the second extension direction De2.

[0622] The annealing method for the plurality of second regions 15 may also serve as the annealing method for the plurality of first regions 14. In this case, the annealing method for the plurality of first regions 14 before the step of forming the second regions 15 may be omitted.

[0623] Next, a determination step of whether to implement the thickness adjustment step of the second layer 9 is performed ( Figure 41 Step S15). In the case where the thickness of the second layer 9 is adjusted ( Figure 41 Step S15: Yes), the second layer 9 is thinned from the upper end side ( Figure 41 Step S16).

[0624] The thickness adjustment step (thinning step) may include a step of partially removing the upper end portion of the second layer 9 by grinding. The grinding method may be mechanical polishing and / or chemical mechanical polishing. The thinning step of the second layer 9 may include a step of partially removing the upper end portion of the second layer 9 by etching. The etching method may be wet etching and / or dry etching.

[0625] The thickness adjustment step may also include a step of exposing the plurality of second regions 15 from the upper end of the second layer 9 (also refer to Figures 27 to 30 That is, the thickness adjustment process may also include a process of removing part or all of the second gradually increasing portions 20B of the plurality of second regions 15. In the case where the thickness adjustment process is not performed ( Figure 41 Step S15: No), omit this process.

[0626] Next, a determination step is performed to determine whether or not to further perform a superjunction structure SJ formation step on the second layer 9 ( Figure 41 For example, when implementing the third superstructure SJ3 (also refer to Figure 33 ) in the case of the formation process ( Figure 41 Step S17: Yes), after Figure 41In the same process as steps S12 to S14, a third layer 27 is formed on the second layer 9, and a plurality of third regions 28 ( Figure 41 Step S18).

[0627] Of course, it is also possible to undergo the same process as above before the formation of the superstructure SJ. Figure 41 In the same process as step S11, a plurality of intermediate regions 25 are formed on the surface portion of the second layer 9 (also refer to Figure 25 as well as Figure 26 Without further superstructure SJ formation process ( Figure 41 Step S17: No), omit this process.

[0628] Next, whether to implement the top 30 (also refer to Figure 34 ) forming process determination process ( Figure 41 Step S19). When the top layer 30 forming process is implemented ( Figure 41 Step S19: Yes), a top layer 30 is formed by epitaxial growth with the second layer 9 as a starting point ( Figure 41 Step S20). In the case where the formation process of the top layer 30 is not performed ( Figure 41 Step S19: No), omit this process.

[0629] Then, the MIS structure 31, a plurality of field regions 38, an interlayer insulating film 40, a gate pad 45, a gate wiring 46, a source pad 47, a drain pad 48, etc. are formed ( Figure 41 Step S21).

[0630] Then, the wafer 50 is cut along the plurality of planned cutting lines 56. Portions of the plurality of first regions 14 located on the plurality of planned cutting lines 56 are exposed from the first side surface 5A (third side surface 5C) as a plurality of first markings Mk1. If a plurality of intermediate regions 25 are formed, portions of the plurality of intermediate regions 25 located on the plurality of planned cutting lines 56 are exposed from the first side surface 5A (third side surface 5C) as a portion (upper end) of the plurality of first markings Mk1. Portions of the plurality of second regions 15 located on the plurality of planned cutting lines 56 are exposed from the second side surface 5B (fourth side surface 5D) as a plurality of second markings Mk2.

[0631] Furthermore, when the middle portion of the second region 15 is cut along the second extending direction De2, a portion of the second region 15 is exposed from the first side face 5A (third side face 5C) as the first difference mark Md1. Furthermore, when the middle portion of the first region 14 is cut along the first extending direction De1, a portion of the first region 14 is exposed from the second side face 5B (fourth side face 5D) as the second difference mark Md2.

[0632] The wafer 50 cutting step may include a cutting step of the wafer 50. In this case, the wafer 50 is cut along a plurality of planned cutting lines 56 by a dicing blade. This forms chips 2 having first to fourth side surfaces 5A to 5D each consisting of a ground surface.

[0633] The wafer 50 cutting step may include a cleaving step. In this case, a plurality of modified layers (damaged layers) are formed along a plurality of planned cutting lines 56 within the wafer 50 by laser irradiation, and the wafer 50 is cleaved along the plurality of planned cutting lines 56 starting from the plurality of modified layers. Thus, chips 2 are formed, each having first to fourth side surfaces 5A to 5D formed of cleaved surfaces.

[0634] In the case of the cleaving step of the wafer 50, it is preferable that the plurality of modified layers are formed in the thickness range of the wafer 50 (base layer 6) relative to the thickness range of the laminated portion 7. Specifically, it is preferable that the plurality of modified layers are formed in the wafer 50 (base layer 6) at intervals from the thickness range of the laminated portion 7 toward the second wafer main surface 52 side of the wafer 50.

[0635] According to this manufacturing method, multiple modified layers are formed (or remain) on the portions of the base layer 6 that form the first to fourth side surfaces 5A to 5D after cleavage. This prevents the multiple modified layers from overlapping with the decorative pattern PT (the multiple first markings Mk1 and the multiple second markings Mk2). This improves the visibility of the decorative pattern PT and reduces the electrical effects of the multiple modified layers on the multiple first regions 14 and the multiple second regions 15 via the decorative pattern PT.

[0636] When the cleavage step is performed, the first to fourth side surfaces 5A to 5D are each formed of a cleavage plane and each have a plurality of modified layers. Therefore, the plurality of modified layers can also be regarded as one component of the SiC semiconductor device 1A (chip 2).

[0637] The above-mentioned various determination processes ( Figure 41 Steps S2, S8, S10, S15, S17 and S19) can also be performed in the preparation process of the wafer 50 ( Figure 41 The stages of step S1 are predetermined. That is, the SiC semiconductor device 1A can also be manufactured along a predetermined production line. Through the above-mentioned steps, a plurality of SiC semiconductor devices 1A are manufactured from a single wafer 50.

[0638] Figure 45 1 is a plan view showing a SiC semiconductor device 1B according to a second embodiment. Figure 46A It is along Figure 45 A cross-sectional view taken along line XLVIA-XLVIA is shown. Figure 46B It is along Figure 45A cross-sectional view taken along line XLVIB-XLVIB is shown. Figure 47A 2 is a top view showing a layout example of the chip 2 (first layer 8 ). Figure 47B 2 is a top view showing a layout example of the chip 2 (second layer 9 ). Figure 48 is a perspective view showing a layout example of the chip 2 .

[0639] Reference Figures 45 to 48 Similar to the SiC semiconductor device 1A, the SiC semiconductor device 1B includes a chip 2 , a base layer 6 , a stacked portion 7 (a first layer 8 and a second layer 9 ), an active region 10 , and a peripheral region 11 .

[0640] In this embodiment, SiC semiconductor device 1B includes an active surface 71 (active surface), an outer surface 72 (outer surface), and first to fourth connecting surfaces 73A to 73D (connecting surfaces) formed on first main surface 3. Active surface 71, outer surface 72, and first to fourth connecting surfaces 73A to 73D define an active terrace 74 on first main surface 3.

[0641] The active surface 71 may also be referred to as the "first surface," the outer peripheral surface 72 as the "second surface," the first to fourth connecting surfaces 73A to 73D as the "connection surface," and the active terrace 74 as the "terrace surface." The active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D (i.e., the active terrace 74) may be considered components of the chip 2 (first main surface 3).

[0642] The active surface 71 is formed in the active region 10. Specifically, the active surface 71 is formed spaced inward from the periphery of the first principal surface 3 (the first to fourth side surfaces 5A to 5D). The active surface 71 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 71 is formed by a c-plane (Si plane). In this embodiment, the active surface 71 is formed into a quadrilateral having four sides parallel to the first to fourth side surfaces 5A to 5D when viewed from above.

[0643] The outer peripheral surface 72 is formed in the outer peripheral region 11. That is, the outer peripheral surface 72 is formed outside the active surface 71. The outer peripheral surface 72 is recessed relative to the active surface 71 in the thickness direction of the chip 2 (on the side of the second main surface 4). Specifically, in this embodiment, the outer peripheral surface 72 is recessed to a depth less than the thickness of the second layer 9 so that the second layer 9 is exposed. The outer peripheral surface 72 extends in a band-like shape along the active surface 71 when viewed from above, forming a ring (specifically, a four-sided ring) surrounding the active surface 71.

[0644] The outer peripheral surface 72 is a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 71. In this embodiment, the outer peripheral surface 72 is formed by a c-plane (Si plane). The outer peripheral surface 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 72 has an outer peripheral depth DO.

[0645] The peripheral depth DO may be greater than or equal to 0.1 μm and less than or equal to 2 μm. The peripheral depth DO may have a value within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, and greater than or equal to 1.5 μm and less than or equal to 2 μm. The peripheral depth DO is preferably greater than or equal to 0.1 μm and less than or equal to 1.5 μm.

[0646] The first to fourth connecting surfaces 73A to 73D extend along the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72. The first connecting surface 73A is located on the first side surface 5A side, the second connecting surface 73B is located on the second side surface 5B side, the third connecting surface 73C is located on the third side surface 5C side, and the fourth connecting surface 73D is located on the fourth side surface 5D side. The first and third connecting surfaces 73A and 73C extend in the first direction X and face each other in the second direction Y. The second and fourth connecting surfaces 73B and 73D extend in the second direction Y and face each other in the first direction X.

[0647] The first to fourth connecting surfaces 73A to 73D may extend substantially perpendicularly between the active surface 71 and the outer peripheral surface 72, defining quadrangular prism-shaped active terraces 74. Alternatively, the first to fourth connecting surfaces 73A to 73D may be arranged to slope downwardly from the active surface 71 toward the outer peripheral surface 72, defining quadrangular pyramid-shaped active terraces 74. In this manner, the active terraces 74 are defined as protrusions on the first principal surface 3 by the second layer 9. The active terraces 74 are formed only in the second layer 9 and not in the first layer 8.

[0648] SiC semiconductor device 1B, like SiC semiconductor device 1A, includes decorative pattern PT of the first embodiment on first to fourth side surfaces 5A to 5D. Decorative pattern PT includes a plurality of first marks Mk1 and a plurality of second marks Mk2.

[0649] The plurality of first marks Mk1 and the plurality of second marks Mk2 are formed in the same manner as in the case of the SiC semiconductor device 1A. The plurality of first marks Mk1 are preferably formed at intervals from the outer peripheral surface 72 toward the lower end of the first layer 8. On the other hand, the plurality of second marks Mk2 are preferably exposed from the upper end of the outer peripheral surface 72. The plurality of second marks Mk2 may have a thickness smaller than that of the plurality of first marks Mk1. Of course, the plurality of second marks Mk2 may also have a thickness greater than that of the plurality of first marks Mk1.

[0650] Of course, the SiC semiconductor device 1B may also include the decorative pattern PT of the second to fifth embodiments. In the case where the decorative pattern PT includes the first difference mark Md1 (see Figure 6A 、 Figure 6C It is preferred that the first difference mark Md1 is located between the outer peripheral surface 72 and the region between the plurality of first marks Mk1 and is exposed from the outer peripheral surface 72 .

[0651] In the case where the decorative pattern PT includes the second difference mark Md2 (refer to Figure 6B 、 Figure 6C It is preferred that the second difference mark Md2 is formed at intervals from the outer peripheral surface 72 toward the lower end side of the first layer 8 and faces the outer peripheral surface 72 via a plurality of second marks Mk2.

[0652] SiC semiconductor device 1B includes a p-type pillar region 12 formed in stacked portion 7 within active region 10. Pillar region 12 is formed in the same layout as in SiC semiconductor device 1A. Specifically, multiple first regions 14 are formed in first layer 8 in the same layout as multiple first regions 14 in SiC semiconductor device 1A, defining multiple first drift regions 16. Furthermore, multiple second regions 15 are formed in second layer 9 in the same layout as multiple second regions 15 in SiC semiconductor device 1A, defining multiple second drift regions 17.

[0653] The pillar region 12 may have at least one of the features described in the first to twelfth embodiments. The pillar region 12 may have a feature that is a combination of a plurality (two or more) of the features described in the first to twelfth embodiments.

[0654] The plurality of first regions 14 are formed in a region surrounded by at least the periphery of the active surface 71 (the first to fourth connection surfaces 73A to 73D) when viewed from above. In this embodiment, the plurality of first regions 14 extend from the active region 10 across the region immediately below the first to fourth connection surfaces 73A to 73D to the peripheral region 11 (see FIG. Figure 47A ).

[0655] Specifically, the plurality of first regions 14 extend from the portion of the first layer 8 facing the active surface 71 toward the portion of the first layer 8 facing the outer peripheral surface 72. The plurality of first regions 14 are also arranged at intervals in the first arrangement direction Da1 within the outer peripheral region 11, each formed in a strip shape extending in the first extension direction De1. The plurality of first regions 14 are formed at intervals from the outer peripheral surface 72 toward the lower end of the first layer 8 within the outer peripheral region 11, facing the outer peripheral surface 72 with the second layer 9 interposed therebetween.

[0656] Furthermore, each of the plurality of first regions 14 includes a portion extending from the outer peripheral region 11 toward one or both (in this embodiment, both) of the first side surface 5A and the third side surface 5C and exposed from one or both (in this embodiment, both) of the first side surface 5A and the third side surface 5C. The portions of the plurality of first regions 14 exposed from the first side surface 5A form a plurality of first marks Mk1 on the first side surface 5A, and the portions of the plurality of first regions 14 exposed from the third side surface 5C form a plurality of first marks Mk1 on the third side surface 5C.

[0657] The plurality of second regions 15 are each formed within a region surrounded by at least the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 when viewed from above. In this embodiment, the plurality of second regions 15 extend from a portion of the second layer 9 located within the active region 10 to a portion of the second layer 9 located in the peripheral region 11.

[0658] The portion of the plurality of second regions 15 located in the outer peripheral region 11 may have a thickness less than that of the plurality of first regions 14. Of course, the portion of the plurality of second regions 15 located in the outer peripheral region 11 may have a thickness greater than that of the plurality of first regions 14. The second lower end portions 15a of the plurality of second regions 15 are located in an area closer to the lower end of the second layer 9 than the depth position of the outer peripheral surface 72 in the thickness direction of the second layer 9. Furthermore, the second upper end portions 15b of the plurality of second regions 15 are located in an area closer to the active surface 71 than the outer peripheral surface 72 in the thickness direction of the second layer 9.

[0659] Therefore, the plurality of second regions 15 are exposed from at least one of the first to fourth connecting surfaces 73A to 73D that is perpendicular to the second extending direction De2. In this embodiment, the plurality of second regions 15 are exposed from both the second connecting surface 73B and the fourth connecting surface 73D.

[0660] Of course, when the first connection surface 73A is formed from the middle portion of the second region 15 along the second extension direction De2, the second region 15 may be exposed from the entire area of the first connection surface 73A. In addition, when the third connection surface 73C is formed from the middle portion of the second region 15 along the second extension direction De2, the second region 15 may be exposed from the entire area of the third connection surface 73C.

[0661] Furthermore, when the second extension direction De2 is perpendicular to the first connecting surface 73A and the third connecting surface 73C, the plurality of second regions 15 may be exposed from one or both of the first connecting surface 73A and the third connecting surface 73C. Furthermore, in these cases, the second regions 15 may be exposed from the entire area of one or both of the second connecting surface 73B and the fourth connecting surface 73D.

[0662] The plurality of second regions 15 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11 and are each formed in a strip shape extending in the second extension direction De2. The plurality of second regions 15 are exposed from the outer peripheral surface 72 in the outer peripheral region 11.

[0663] Furthermore, each of the plurality of second regions 15 includes a portion extending from the outer peripheral region 11 toward either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D and exposed from either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D. The portions of the plurality of second regions 15 exposed from the second side surface 5B form a plurality of second marks Mk2 on the second side surface 5B, and the portions of the plurality of second regions 15 exposed from the fourth side surface 5D form a plurality of second marks Mk2 on the fourth side surface 5D.

[0664] Figure 49 FIG. 1 is a top view showing a main portion of the active region 10 . Figure 50 1 is a perspective view showing a cross-section of the gate structure 35 according to the first embodiment. Figure 49 as well as Figure 50 The SiC semiconductor device 1B includes a MIS structure 31 formed in the active region 10 . The following configurations are described as components of the SiC semiconductor device 1B, but are also components of the MIS structure 31 .

[0665] SiC semiconductor device 1B includes a p-type body region 32 formed in the surface portion of first principal surface 3 (active surface 71). In this embodiment, body region 32 is formed as a layer extending along active surface 71. Alternatively, body region 32 may be formed over the entire active surface 71, exposed from first to fourth connecting surfaces 73A to 73D.

[0666] The main body region 32 is formed at intervals from the lower end of the second layer 9 toward the active surface 71, overlapping with the pillar region 12 (the plurality of second regions 15) in the stacking direction. The main body region 32 is preferably formed at intervals from a depth position of the outer peripheral surface 72 toward the active surface 71, and exposed from the first principal surface 3. When the plurality of second regions 15 are formed at intervals from the first principal surface 3, the main body region 32 is formed in the region between the active surface 71 and the second upper end portions 15b of the plurality of second regions 15. The main body region 32 is preferably connected to the plurality of second regions 15 (the second upper end portions 15b).

[0667] The main region 32 is composed of a random impurity region introduced into the surface portion of the second layer 9 by a random implantation method into the second layer 9 (also refer to Figure 14Therefore, the body region 32 has a thickness in the direction along the second axis channel CH2 that is smaller than the second region thickness TR2 of the second region 15. The thickness of the body region 32 is smaller than the first region thickness TR1 of the first region 14.

[0668] The main region 32 is different from the second region 15 and the like, and does not have a slow portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. The main region 32 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are taken as peak values.

[0669] The p-type impurity concentration in the body region 32 is preferably adjusted using at least one trivalent element. The trivalent element in the body region 32 may be the same as or different from the trivalent element in the second region 15 and the like. The trivalent element in the body region 32 may be at least one of boron, aluminum, gallium, and indium. Of course, the body region 32 may also be formed using a portion of the p-type top layer 30.

[0670] The SiC semiconductor device 1B includes multiple trench electrode-type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10. The gate structures 35 may also be referred to as "trench gate structures." A gate potential, serving as a control potential, is applied to the multiple gate structures 35. The multiple gate structures 35 control the inversion and non-inversion of the channel (current path) within the body region 32 in response to the gate potential.

[0671] Multiple gate structures 35 are arranged in the active region 10 at intervals inward from the periphery of the active surface 71 (the first to fourth connection surfaces 73A to 73D). In this embodiment, the multiple gate structures 35 are arranged at intervals in the second arrangement direction Da2 and are each formed into a stripe shape extending in the second extension direction De2. In other words, ...

Claims

1. A SiC semiconductor device, characterized in that: include: a first conductivity type SiC layer including a main surface and having an axial channel along a thickness direction; an impurity region of a second conductivity type extending along the axial channel in the SiC layer; a second conductivity type body region formed on the main surface side relative to the impurity region; as well as The gate structure includes a trench penetrating the main body region in the main surface, a buried electrode arranged on the bottom wall side of the trench relative to the main surface, and a buried insulator arranged on the bottom wall side of the trench relative to the main surface and covering the buried electrode.

2. The SiC semiconductor device according to claim 1, wherein The impurity region is composed of a single region that crosses the middle portion of the SiC layer along the axial channel. The gate structure is shallower than the impurity region.

3. The SiC semiconductor device according to claim 1 or 2, wherein: The impurity region includes a peak on the upper end side of the SiC layer and a slow portion in which the impurity concentration gradually decreases at a slow decreasing rate in a region on the lower end side of the SiC layer relative to the peak.

4. The SiC semiconductor device according to claim 3, wherein The slow portion occupies more than 1 / 4 of the thickness of the impurity region.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein The gate structure extends in a strip shape when viewed from above.

6. The SiC semiconductor device according to claim 5, wherein The gate structure extends in the a-axis direction in the crystal orientation of SiC.

7. The SiC semiconductor device according to claim 5 or 6, wherein: The impurity region extends in a band shape when viewed from above. The gate structure extends in an extending direction of the impurity region and is formed spaced apart from the impurity region.

8. The SiC semiconductor device according to claim 5 or 6, wherein: The impurity region extends in a band shape when viewed from above. The gate structure extends in an extending direction of the impurity region and overlaps with the impurity region in a thickness direction of the SiC layer.

9. The SiC semiconductor device according to claim 5 or 6, wherein: The impurity region extends in a band shape when viewed from above. The gate structure extends in a direction other than an extending direction of the impurity region and intersects the impurity region.

10. The SiC semiconductor device according to any one of claims 1 to 9, wherein The embedded electrode has a multi-electrode structure including a plurality of electrodes arranged at intervals in a depth direction of the trench.

11. The SiC semiconductor device according to any one of claims 1 to 10, wherein Also includes: a lower SiC layer having a lower axial channel along a thickness direction; as well as a lower impurity region of the second conductivity type extending along the lower axial channel in the lower SiC layer; The SiC layer is stacked on the lower SiC layer, The impurity region is formed in the SiC layer so as to overlap with the lower impurity region in a stacking direction.

12. The SiC semiconductor device according to claim 11, wherein The lower impurity region is composed of a single region that crosses the middle portion of the lower SiC layer along the lower axial channel.

13. The SiC semiconductor device according to claim 11 or 12, wherein: The lower impurity region includes a lower peak on the upper side of the lower SiC layer and a lower slow portion where the impurity concentration gradually decreases at a slow decreasing rate in a region closer to the lower end of the lower SiC layer than the lower peak.

14. The SiC semiconductor device according to claim 13, wherein The lower slow portion occupies more than 1 / 4 of the thickness of the impurity region.

15. The SiC semiconductor device according to any one of claims 11 to 14, wherein The lower impurity region extends along a first extension direction when viewed from above. The impurity region extends along the first extension direction in a plan view.

16. The SiC semiconductor device according to any one of claims 11 to 15, wherein The lower impurity region extends along a first extension direction when viewed from above. The impurity region extends in a second extension direction other than the first extension direction in a plan view and intersects the lower impurity region.

17. The SiC semiconductor device according to any one of claims 1 to 16, wherein Also includes: a source region of a first conductivity type, formed along the gate structure at a surface portion of the body region; as well as A source pad is electrically connected to the source region on the main surface and is electrically insulated from the embedded electrode by the embedded insulator in the trench.

18. The SiC semiconductor device according to claim 17, wherein The source region has a portion exposed from a sidewall of the trench, The source pad is electrically connected to a portion of the source region exposed from a sidewall of the trench within the trench.

19. The SiC semiconductor device according to claim 17 or 18, wherein A plurality of gate structures are formed on the main surface at intervals. The source region is connected to the two adjacent gate structures.

20. The SiC semiconductor device according to any one of claims 17 to 19, wherein The device further includes a contact region of a second conductivity type, wherein the contact region of the second conductivity type is formed along the gate structure in a region different from the source region in a surface portion of the body region. The source pad is electrically connected to the contact region on the main surface.

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