Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention suppresses a decrease in reliability of an insulated gate semiconductor device (100) having a trench structure. A semiconductor device is provided with: a source electrode (11) electrically connected to a source region adjacent to a trench (6) in a first region; and a gate wiring (18) provided on the upper surface of the gate electrode (8) provided in the trench in the second region, the curvature radius (Re) of the gate insulating film provided in the upper corner of the trench in the second region being larger than the curvature radius (Rc) of the gate insulating film provided in the upper corner of the trench in the first region.

Description

Technical Field

[0001] The technology disclosed in this application specification relates to semiconductor technology. Background Art

[0002] In power electronic devices, insulated gate semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) are widely used as switching elements for controlling the power supply to loads such as motors.

[0003] Among these insulated-gate semiconductor devices, some have a trench structure in which a gate electrode is buried within the semiconductor layer. Compared to non-trench insulated-gate semiconductor devices (planar semiconductor devices) in which the gate electrode is formed on the surface of the semiconductor layer, these trench-structured insulated-gate semiconductor devices can increase the channel width density in the active region. Consequently, the electrical resistance per unit area of the semiconductor device can be reduced when in the on state.

[0004] Conventionally, insulated-gate semiconductor devices with trench structures have a termination area surrounding the active region, with a gate electrode and gate insulating film formed inside the trench and around the upper corners of the trench opening on the active region side. In this case, when a gate voltage is applied, turning the semiconductor device on, the electric field concentrates around the trench bottom and upper corners, causing insulation degradation of the gate insulating film around these areas. This can result in reduced reliability of the semiconductor device.

[0005] To solve this problem, a method is known in which an electric field relaxation region having conductivity is provided on the bottom surface of the trench to relax the electric field applied to the gate insulating film on the bottom surface of the trench (see, for example, Patent Document 1).

[0006] In addition, the following method is known: forming a structure having a narrow and deep trench in the active region and a wide and shallow trench in the terminal region, and in a subsequent CMP (Chemical Mechanical Polishing) process, or a combination of a CMP process and an etch-back process, flattening the gate electrodes of the trenches formed in the active region and the terminal region, thereby preventing the upper corners of the trenches from being covered by the gate electrodes (for example, see patent document 2).

[0007] Prior art literature

[0008] Patent Document 1: Japanese Patent Application No. 2001-511315

[0009] Patent Document 2: Japanese Patent Application No. 2006-520091 Summary of the Invention

[0010] As a method for setting the potential of the gate electrode, a gate contact (contact hole) must be provided for the gate electrode formed in the gate trench within the cell array. The gate trenches in the cell array are formed with minimum processing dimensions, so there is a concern about overlap and offset with the contact mask. Therefore, sometimes gate contacts are avoided within the cell and instead are provided on the upper surface of the polysilicon in the wide trench in the terminal region.

[0011] In this case, the upper corners of the trench cannot be avoided from being covered by polysilicon. As a result, the electric field concentrates on the gate insulating film at the portion of the upper corner of the trench covered by polysilicon, causing insulation degradation of the gate insulating film and reducing the reliability of the semiconductor device.

[0012] On the other hand, methods that provide an electric field relaxation region on the bottom surface of the trench sometimes fail to suppress insulation degradation around the upper corners of the trench. Furthermore, methods using a CMP process require minimizing the effects of semiconductor substrate warpage, substrate surface irregularities, in-plane thickness uniformity of a film formed on the semiconductor substrate, and film irregularities caused by the influence of particles, making this difficult to implement in practice.

[0013] Furthermore, when a wide trench is formed in the terminal region, resulting in a continuous accumulation of the gate insulating film and gate electrode, the exposed area of the gate electrode may be increased during the subsequent etch-back process, causing the gate electrode to be etched thinner or even disappear. Consequently, the operation of the insulated gate semiconductor device may become unstable (reducing the reliability of the semiconductor device). Furthermore, insulation degradation around the upper corners of the trench may not be suppressed.

[0014] The technology disclosed in this specification has been accomplished in view of the above-described problems, and is a technology for suppressing a decrease in the reliability of an insulated gate semiconductor device having a trench structure.

[0015] The semiconductor device of the first form of the technology disclosed in the present specification further comprises: a drift layer of the first conductivity type; a base region of the second conductivity type, provided on the surface layer of the drift layer; a plurality of source regions of the first conductivity type, provided on the surface layer of the base region; at least one trench extending from the upper surface of the drift layer through the base region into the drift layer; a protective layer of the second conductivity type, provided in the drift layer below the trench; a gate insulating film provided along the interior of the trench including the upper corner of the trench; and a gate electrode, which is protected by the gate insulating film. an insulating film surrounding and at least arranged in the trench; a source electrode electrically connected to the source region adjacent to the trench; and a gate wiring arranged on the upper surface of the gate electrode arranged in the trench, wherein, among the regions divided by the trench when viewed from above, the region where the source electrode is arranged is set as the first region, and the region where the gate wiring is arranged is set as the second region, and the curvature radius of the gate insulating film arranged at the upper corner of the trench in the second region is greater than the curvature radius of the gate insulating film arranged at the upper corner of the trench in the first region.

[0016] According to at least the first aspect of the technology disclosed in this specification, electric field concentration is suppressed even when a gate voltage is applied, so destruction of the gate insulating film is suppressed.

[0017] Furthermore, the objects, features, aspects, and advantages related to the technology disclosed in this specification will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a plan view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0019] Figure 2 This is a cross-sectional view showing a portion of the structure of a semiconductor device according to an embodiment.

[0020] Figure 3 This is a cross-sectional view showing a portion of the structure of a semiconductor device according to an embodiment.

[0021] Figure 4 It is a plan view showing a part of the structure of a semiconductor device according to an embodiment.

[0022] Figure 5 It is a cross-sectional view showing an example of the structure of the unit portion in the figure.

[0023] Figure 6 It shows Figure 3 sectional view of an example of the structure of the gate contact portion in the active region 20.

[0024] Figure 7 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0025] Figure 8 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0026] Figure 9 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0027] Figure 10 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0028] Figure 11 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0029] Figure 12 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0030] Figure 13 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0031] Figure 14 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0032] Figure 15 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0033] Figure 16 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0034] Figure 17 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0035] Figure 18 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0036] Figure 19 This is a plan view schematically showing an example of the structure of the semiconductor device according to this embodiment.

[0037] Figure 20 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0038] Figure 21 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0039] Figure 22 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0040] Figure 23 This is a plan view schematically showing an example of the structure of the semiconductor device according to this embodiment.

[0041] Figure 24 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0042] Figure 25 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0043] Figure 26 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0044] Figure 27 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0045] Figure 28 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0046] Figure 29 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0047] Figure 30 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0048] The following embodiments will be described with reference to the accompanying drawings. Detailed features and the like are shown in the following embodiments for technical explanation, but these are merely examples, and not all of the detailed features and the like are necessarily required to implement the embodiments.

[0049] The accompanying drawings are schematic diagrams, and for ease of explanation, structures may be omitted or simplified as appropriate. Furthermore, the sizes and positions of structures shown in different drawings are not necessarily accurately depicted and may be modified as appropriate. Furthermore, in drawings such as plan views, which are not cross-sectional views, hatching may be added to facilitate understanding of the embodiments.

[0050] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid redundancy.

[0051] In addition, in the descriptions described in the specification of the present application, when a certain component is described as “having”, “including”, or “having”, it does not constitute an exclusive expression that excludes the presence of other components unless otherwise specified.

[0052] In addition, in the description recorded in the specification of this application, even if there are cases where ordinal numbers such as "1st" or "2nd" are used, these words are appropriately used to facilitate understanding of the content of the implementation method, and the content of the implementation method is not limited to the order that can be generated by these ordinal numbers.

[0053] In addition, in the description recorded in the specification of this application, even if there are cases where words such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are used to indicate specific positions or directions, these words are appropriately used to facilitate understanding of the content of the implementation method and have nothing to do with the position or direction when the implementation method is actually implemented.

[0054] Furthermore, in the descriptions of this application, when references are made to "the upper surface of..." or "the lower surface of...", this includes not only the upper surface or lower surface of the component being addressed, but also states where other components are formed on the upper or lower surface of the component being addressed. That is, for example, when references are made to "B disposed on the upper surface of A," this does not preclude the presence of another component "C" between A and B.

[0055] <First embodiment>

[0056] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In each of the drawings, detailed descriptions of semiconductor layers and electrodes may be omitted for simplicity of description.

[0057] <Regarding the Structure of Semiconductor Device>

[0058] Figure 1 1 is a plan view schematically showing an example of the structure of the semiconductor device 100 according to this embodiment. Figure 1 As illustrated, the semiconductor device 100 includes an active region 20 and a termination region 30 .

[0059] The active region 20 has a plurality of gate trenches 6 arranged in a plan view. The termination region 30 has a termination trench 16 and a gate wiring 18 formed so as to overlap the termination trench 16 in a plan view. A gate trench 26 is formed in the inner portion of the termination region 30.

[0060] The active region 20 is provided in the central portion of the semiconductor device 100. The active region 20 is a region in which a current flows in the semiconductor device 100 when a voltage is applied to the gate trenches 6 formed in a stripe shape in the active region 20.

[0061] When a positive voltage is applied to the gate trench 6 in the on-state of the semiconductor device 100 , electrons are excited at the interface between the gate insulating film and the semiconductor layer, and current flows.

[0062] The termination region 30 is formed around the active region 20 in a plan view. The termination region 30 includes a termination trench 16, a gate insulating film 17, a gate electrode 8, a gate wiring 18, and a guard ring for electric field relaxation. The termination trench 16 is a trench provided in the termination region 30.

[0063] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, a semiconductor device in which the first conductivity type is p-type and the second conductivity type is n-type may be used.

[0064] In addition, this embodiment describes a case where the semiconductor device is a MOSFET, but the semiconductor device may also be an IGBT. In addition, this embodiment describes a case where the drift layer included in the semiconductor layer is formed of silicon carbide (SiC), but the drift layer may also be a wide-bandgap semiconductor such as gallium nitride (GaN) or diamond, which has a larger bandgap than silicon.

[0065] exist Figure 1 In the semiconductor layer of the semiconductor device 100, a gate trench 6 is formed in the active region 20, and a gate trench 26 and a termination trench 16 are formed in the termination region 30. The termination trench 16 surrounds the gate trench 6 and the gate trench 26 in a plan view and is formed to be isolated from the gate trench 6 and the gate trench 26.

[0066] like Figure 1 As shown in the example, the gate trench 6 is formed in a stripe shape in a plan view. A plurality of cells (cell portions) are formed in each region partitioned by the gate trench 6 within the active region 20, and the cells function as MOSFETs.

[0067] Figure 2 as well as Figure 3 This is a cross-sectional view showing a portion of the structure of the semiconductor device according to this embodiment. Figure 4 It is a plan view showing a part of the structure of the semiconductor device according to this embodiment. Figure 2 、 Figure 3 as well as Figure 4 The structure shown is Figure 1 The area 1000 surrounded by the dotted line in FIG. Figure 2 The cross section shown is Figure 4 The A-A' section shown corresponds to the same. Figure 3 The cross section shown is Figure 4 The BB' section shown corresponds to this.

[0068] like Figure 2 as well as Figure 3 As shown, semiconductor device 100 as a MOSFET includes an n-type silicon carbide semiconductor substrate 1 and a semiconductor layer 2 formed by epitaxial growth on the upper surface of silicon carbide semiconductor substrate 1. Semiconductor device 100 also includes a drain electrode 12 on the lower surface of silicon carbide semiconductor substrate 1.

[0069] The active region 20 in the semiconductor layer 2 is formed with: a drift layer 3 composed of an n-type silicon carbide semiconductor; a p-type base region 4 arranged on the surface of the drift layer 3; an n-type source region 5 selectively arranged on the surface of the base region 4; a gate trench 6 penetrating the source region 5 and the base region 4 so as to be formed with the bottom surface located within the drift layer 3; and a p-type diffusion protection layer 9 arranged below the bottom surface of the gate trench 6.

[0070] On the other hand, the terminal region 30 in the semiconductor layer 2 is formed with: a drift layer 3 composed of an n-type silicon carbide semiconductor; a p-type base region 4 arranged on the surface of the drift layer 3; a gate trench 26 and a terminal trench 16 formed in such a way that the bottom surface is deeper than the base region 4 and is located in the n-type drift layer 3; a p-type diffusion protection layer 9 arranged below the bottom surface of the gate trench 26; and a p-type terminal protection layer 19 arranged below the bottom surface of the terminal trench 16.

[0071] Furthermore, when the semiconductor device 100 is an IGBT, the conductivity type of the silicon carbide semiconductor substrate 1 may be a p-type.

[0072] Here, the n-type impurity concentration of the drift layer 3 may be, for example, 1×10 14 cm -3 Above and 1×10 17 cm -3 Hereinafter, the thickness of the drift layer 3 may be, for example, 5 μm or more and 200 μm or less.

[0073] In addition, the p-type impurity concentration of the base region 4 may be, for example, 1×10 17 cm -3 Above and 1×10 20 cm -3 the following.

[0074] In addition, the n-type impurity concentration of the source region 5 may be higher than the p-type impurity concentration of the base region 4 and 1×10 21 cm-3 the following.

[0075] In addition, the p-type impurity concentration of the diffusion protection layer 9 and the p-type impurity concentration of the termination protection layer 19 can be, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 The p-type impurity concentration of the diffusion protection layer 9 is preferably the same as the p-type impurity concentration of the termination protection layer 19 or higher than the p-type impurity concentration of the termination protection layer 19 .

[0076] In addition, if Figure 2 as well as Figure 3 As shown in the example, a gate insulating film 7 is formed on the side and bottom of the gate trench 6, and a gate electrode 8 made of polysilicon is buried in the gate trench 6 via the gate insulating film 7. Figure 3 In the embodiment, the gate insulating film 7 and the gate electrode 8 in the gate trench 6 overlapping with the gate wiring 18 in a plan view are formed to extend to the upper surface of the semiconductor layer 2 (the upper surface of the semiconductor layer 2 forming the base region 4 or the source region 5).

[0077] Similarly, a gate insulating film 7 having the same thickness as the gate insulating film 7 in the gate trench 6 is formed on the side and bottom surfaces of the gate trench 26, and a gate electrode 8 made of polysilicon is embedded in the gate trench 26 via the gate insulating film 7. The gate electrode 8 in the gate trench 26 is formed to reach the upper surface of the semiconductor layer 2. A gate wiring 18 is provided across the upper surfaces of the gate electrodes 8 provided in the plurality of gate trenches 6.

[0078] A gate electrode 8 is formed via a contact hole (gate contact portion 34) in the polysilicon formed to extend to the upper surface of the semiconductor layer 2. The gate electrode 8 extends to a bonding pad for wire bonding when the chip is mounted.

[0079] like Figure 2 、 Figure 3 as well as Figure 4 As illustrated, a gate trench 26 that does not function electrically is formed at the boundary between the termination region 30 and the active region 20 .

[0080] A termination trench 16 having a width wider than gate trench 6 and gate trench 26 is formed in termination region 30. A gate insulating film 7 having the same thickness as gate insulating film 7 in gate trench 6 is formed on the bottom and side surfaces of termination trench 16. Furthermore, an interlayer insulating film 13 (oxide film) is deposited in a portion of termination trench 16. Furthermore, a gate electrode 8 is formed in another portion of termination trench 16.

[0081] In addition, a gate electrode 8 is formed in the gate trench 6 of the cell portion. Polysilicon (gate electrode 8) is also deposited in the gate trench 26 at the boundary between the termination region 30 and the active region 20 .

[0082] Furthermore, an interlayer insulating film 13 is formed to cover the upper surface of the semiconductor layer 2 including the gate electrode 8. Furthermore, a gate wiring 18 is formed to contact the gate electrode 8 exposed through a gate contact portion 34, which is an opening formed in the interlayer insulating film 13. The gate contact portion 34 includes a portion in the termination region 30 that exposes the gate electrode 8 in the termination trench 16, and a portion in the active region 20 that exposes the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2. Furthermore, a source electrode 11 is formed to contact, via an ohmic electrode 32, the upper surface of the base region 4 and the upper surface of the source region 5, which are exposed through a source contact portion 31, which is an opening formed in the interlayer insulating film 13.

[0083] An oxide film (interlayer insulating film 13 ) is formed in the termination trench 16 of the termination region 30 , whereas polysilicon is formed in the gate trench 6 and the gate trench 26 , and both are formed of different materials.

[0084] Furthermore, while the termination trench 16 in the termination region 30 is fabricated with wide dimensions, the gate trench 6 or gate trench 26 in the cell portion is formed with the smallest process width. Due to these structural differences, the coefficient of expansion of the materials varies depending on the thermal history of the wafer process. This generates residual stress, resulting in variations in the electrical characteristics of the device and affecting the reliability of the semiconductor device.

[0085] In each cell arranged in the active region 20, stress increases toward the outermost portion of the gate trench. Due to this effect, the failure rate of the gate insulating film 7 increases toward the outermost portion of the gate trench. Therefore, by electrically isolating the outermost cells from the other cells and making the gate potential float, device failure can be suppressed.

[0086] Figure 5 It shows Figure 2 A cross-sectional view showing an example of the structure of a unit portion in FIG. Figure 5 As illustrated, the upper corner of the gate trench 6 has an arc shape (circular shape).

[0087] Figure 6 It shows Figure 3 sectional view of an example of the structure of the gate contact portion in the active region 20. Figure 6 As illustrated, the upper corner of the gate trench 6 has an arc shape (circular shape).

[0088] like Figure 5 As shown, the upper corner of the semiconductor layer 2 in the cell portion where the gate electrode 8 is embedded in the gate trench 6 has a shape whose roundness is represented by the curvature radius Rc. Therefore, the shape of the gate insulating film 7 formed in this portion is also a rounded shape represented by the curvature radius Rc.

[0089] In addition, if Figure 6 As shown, the upper corner of the semiconductor layer 2, which is the gate contact portion having the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2, has a shape whose roundness is represented by the curvature radius Re. Therefore, the shape of the gate insulating film 7 formed in this portion is also a rounded shape represented by the curvature radius Re.

[0090] When comparing the curvature radius of the gate trench 6 directly below the gate insulating film 7, Re > Rc, resulting in a more gradual shape at the gate contact site. The small curvature radius Rc of the cell portion is, for example, greater than 0 μm and less than 0.1 μm. The curvature radius Re of the gate contact site is, for example, greater than 0.1 μm and less than 2 μm. In particular, excellent characteristics are achieved when the curvature radius Re of the gate contact site is greater than 0.5 μm and less than 2 μm.

[0091] A gate insulating film 7 and a gate electrode 8 are formed at the upper corners of the gate trench 6 at the gate contact portion. The curvature radius Re is larger than the curvature radius Rc, so when the MOSFET is turned on, a high electric field can be suppressed from being applied to the gate insulating film 7 formed at the upper corners of the gate trench 6.

[0092] For example, when a gate voltage of 20 V is applied, if the thickness of the gate insulating film 7 is 50 nm, an electric field of 4 MV / cm is applied to the sidewall portion of the gate trench 6. In this case, if the gate contact portion is formed with a rounded gate insulating film 7 having a curvature radius Re, the application of a high electric field to the gate insulating film 7 formed at the upper corner of the gate trench 6 can be suppressed, thereby suppressing the destruction of the insulating film.

[0093] From the viewpoint of reliability of the gate insulating film 7 , it is preferable to design the curvature radius Re so as to suppress the electric field applied to the gate insulating film 7 near the gate trench 6 having the curvature radius Re to an increase of 5% or less.

[0094] also, Figure 6 The gate contact portion shown is assumed to be set in the active area 20, but the upper corner of the terminal groove 16 can also be made into an arc shape (circular shape) at the gate contact portion in the terminal area 30 (the portion where the gate wiring 18 and the gate electrode 8 are connected via the gate contact portion 34).

[0095] In this embodiment, when an ohmic electrode is provided between the source electrode and the semiconductor layer, the source electrode and the ohmic electrode are sometimes not distinguished and the two are collectively referred to as the source electrode. Similarly, when an ohmic electrode is provided between a gate bonding pad, which is a metal electrode, and a gate electrode composed of a semiconductor or the like, the gate bonding pad and the ohmic electrode are sometimes not distinguished and the two are collectively referred to as the gate bonding pad.

[0096] That is, in this embodiment, the source electrode and gate bonding pad are not limited to being composed of a single metal; they may also be configured such that a material suitable for bonding with the semiconductor layer is provided at the junction with the semiconductor layer. Furthermore, the ohmic electrode is not limited to being made of metal; it may also be a compound of a metal and a semiconductor, or a silicide. Furthermore, the ohmic electrode may also be configured to consist of multiple layers of conductive materials such as metals or semiconductors.

[0097] <About the Manufacturing Method of Semiconductor Device>

[0098] Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described.

[0099] Figures 7 to 18 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.

[0100] exist Figures 7 to 11 , an example of the process of forming the diffusion protection layer 9 below the bottom surface of the gate trench 6 and forming the termination protection layer 19 below the bottom surface of the termination trench 16 is shown. Figures 7 to 10 and Figure 11 Corresponding to the A-A' section.

[0101] exist Figures 12 to 15 , an example of the process from forming the diffusion protection layer 9 and the termination protection layer 19 to forming the gate electrode 8 is shown. Figure 12 as well as Figure 13 and Figure 15 In addition, Figure 14 and Figure 15 Corresponding to the B-B' section.

[0102] exist Figures 16 to 18 , an example of the process from forming the gate electrode 8 to completing the semiconductor device 100 is shown.

[0103] First, if Figure 7 As illustrated, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type semiconductor layer 2 is epitaxially grown on the upper surface thereof by chemical vapor deposition (CVD).

[0104] At this time, the n-type impurity concentration of the n-type semiconductor layer 2 is, for example, 1×10 14 cm -3 Above and 1×10 17 cm -3 Hereinafter, the thickness of the semiconductor layer 2 is, for example, 5 μm or more and 200 μm or less.

[0105] Next, if Figure 7 As shown in the example, aluminum (Al) is ion-implanted as a p-type impurity into the surface layer of the epitaxially grown semiconductor layer 2 to form the base region 4. The depth of the Al ion implantation is set within a range that does not exceed the thickness of the semiconductor layer 2, for example, 0.3 μm to 3 μm. The impurity concentration of the ion-implanted Al is higher than the n-type impurity concentration of the epitaxially grown semiconductor layer 2. The p-type impurity concentration of the base region 4 is set, for example, to 1×10 17 cm -3 Above and 1×10 20 cm -3 As a result, a region of the semiconductor layer 2 other than the base region 4 that is deeper than the Al ion implantation depth becomes the n-type drift layer 3 .

[0106] Alternatively, the base region 4 may be formed by epitaxially growing a p-type semiconductor. In this case, the p-type impurity concentration and thickness of the base region 4 may be the same as those in the case where the base region 4 is formed by ion implantation.

[0107] Next, if Figure 7 As shown in the example, nitrogen (N) ions are selectively implanted as n-type impurities into the surface layer of the base region 4 to form the source region 5. The source region 5 is formed in a pattern corresponding to the layout of the gate electrode 8 to be formed in a later step. The depth of the N ion implantation is shallower than the thickness of the base region 4. The impurity concentration of the implanted N ions is equal to or greater than the p-type impurity concentration of the base region 4 and 1×10 21 cm -3 the following.

[0108] Furthermore, the order of the Al ion implantation step to form the base region 4 and the N ion implantation step to form the source region 5 may be reversed. Alternatively, after N ion implantation is performed throughout the surface layer within the base region 4 to form an n-type semiconductor layer, a mask may be added to the portion remaining as the source region 5, and Al ion implantation may be performed again in the unmasked region (the region outside the source region 5) to return to the p-type base region 4. In this case, the impurity concentration of the re-implanted Al ion implantation may be made higher than the Al impurity concentration of the portion of the base region 4 adjacent to the drift layer 3, thereby reducing the contact resistance with the source electrode.

[0109] Next, if Figure 8 As shown in the example, a silicon oxide film 41 is formed on the upper surface of the semiconductor layer 2, and an etching mask 42 is formed on the upper surface of the silicon oxide film 41. The silicon oxide film 41 is deposited to a thickness of, for example, 1 μm or more and 2 μm or less, and then the etching mask 42 is formed on the upper surface of the silicon oxide film 41. In the etching mask 42, a pattern having openings corresponding to the regions where the gate trench 6, the gate trench 26, and the terminal trench 16 are to be formed is formed by photolithography technology.

[0110] Next, reactive ion etching (RIE) is performed using etching mask 42 as a mask to pattern silicon oxide film 41 . That is, the pattern of etching mask 42 is transferred to silicon oxide film 41 , so that silicon oxide film 41 serves as an etching mask for semiconductor layer 2 .

[0111] Next, if Figure 9 As illustrated, using the patterned silicon oxide film 41 as a mask, the gate trench 6 and gate trench 26 penetrating the source region 5 and the base region 4 and the termination trench 16 penetrating the base region 4 are formed in the semiconductor layer 2 by RIE processing.

[0112] The depths of the gate trench 6 , the gate trench 26 , and the termination trench 16 are greater than or equal to the depth of the base region 4 formed in the semiconductor layer 2 by ion implantation, and may be, for example, greater than or equal to 1.0 μm and less than or equal to 6.0 μm.

[0113] The gate trench 6, the gate trench 26 and the terminal trench 16 are formed by using the silicon oxide film 41 as a mask. After the gate trench 6, the gate trench 26 and the terminal trench 16 are formed, Figure 10 As shown in the example, an implantation mask 43 having an opening with the same pattern as the silicon oxide film 41 is formed, and a p-type diffusion protection layer 9 is formed at the bottom of the gate trench 6 and the bottom of the gate trench 26 by Al ion implantation. Similarly, a p-type termination protection layer 19 is formed at the bottom of the termination trench 16 by Al ion implantation. The impurity concentration of the ion-implanted Al is preferably, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 The depth of the ion implantation is preferably, for example, not less than 0.1 μm and not more than 2.0 μm. The impurity concentration of the Al implanted by the ion implantation can be determined by the electric field applied to the gate insulating film 7 when a voltage equal to the withstand voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.

[0114] Furthermore, by adjusting the thickness of the silicon oxide film 41 and the etching conditions so that the silicon oxide film 41 remains even after the gate trench 6 and the terminal trench 16 are formed using the silicon oxide film 41 as a mask, the remaining silicon oxide film 41 can be used as a mask instead of the implantation mask 43 when forming the diffusion protection layer 9 and the terminal protection layer 19. This simplifies the manufacturing process and reduces manufacturing costs.

[0115] Furthermore, when forming the diffusion protection layer 9, Al ions are implanted obliquely toward the opening of the gate trench 6, thereby forming a p-type semiconductor layer within the drift layer 3 in contact with the side surfaces of the gate trench 6. This p-type semiconductor layer connects the p-type diffusion protection layer 9 and the p-type base region 4. This allows the diffusion protection layer 9 to be electrically connected to the source electrode 11.

[0116] After the diffusion protection layer 9 and the termination protection layer 19 are formed, the implantation mask 43 used in the ion implantation is removed, and an annealing process is performed using a heat treatment apparatus to activate the ion-implanted impurities. The annealing process is performed by heating in an inert gas atmosphere such as argon (Ar) or in a vacuum at a temperature of, for example, 1300°C to 1900°C for 30 seconds to 1 hour.

[0117] Next, if Figure 12 As shown in the example, Figure 15 In the A-A' and BB' cross sections, the implantation mask 43 is removed, and the upper surface of the semiconductor layer 2 is oxidized. The thickness of the oxide film formed on the upper surface of the semiconductor layer 2 is preferably about 5 nm to 100 nm. The oxide film is then removed by wet etching with a hydrofluoric acid system. This process forms an arc shape (radius of curvature Rc) at the upper corner of each trench.

[0118] Next, if Figure 13 As shown in the example, the oxide film 41A is deposited, and then Figure 14 As illustrated, only the oxide film 41A in the portion of the active region 20 corresponding to the region where the gate contact portion is to be formed is opened.

[0119] Next, if Figure 14 As shown in the example, Figure 15 In the BB' cross section, the oxide film 41A is etched to expose a portion of the semiconductor layer 2, and the upper corner of the gate trench 6 in the exposed semiconductor layer 2 is formed into an arc shape (curvature radius Re). Figure 15 The BB′ cross section of FIG. 1 shows a state where a range spanning a plurality of gate trenches 6 is exposed from the oxide film 41A.

[0120] The arc shape may be formed by CDE (chemical dry etching: isotropic etching) etching or other etching processes (such as heat treatment in a hydrogen atmosphere). Thereafter, the oxide film 41A is removed.

[0121] About Figure 12 In the process shown in FIG, a circular arc shape (curvature radius Rc) is formed at the upper corner of the groove, which can be Figure 14 In the illustrated process, heat treatment is further performed in a CDE or hydrogen environment, thereby forming an arc shape with a larger curvature radius at the upper corner of the gate trench 6 .

[0122] As described above, the curvature radius Re of the gate insulating film 7 provided at the upper corner of the gate trench 6 (or terminal trench 16) in the region where the gate wiring 18 is provided on the upper surface is greater than the curvature radius Rc of the gate insulating film 7 provided at the upper corner of the gate trench 6 in the region where the source electrode 11 is electrically connected to the adjacent source region 5. With this structure, even when a gate voltage is applied to the gate insulating film 7 formed in an arc shape with a larger curvature radius (curvature radius Re), the larger curvature radius effectively suppresses electric field concentration, preventing the application of a high electric field. Consequently, damage to the gate insulating film 7 is suppressed.

[0123] Next, the gate electrode 8 is formed. Figure 16 and Figure 18 In addition, Figure 17 and Figure 18 Corresponding to the B-B' section.

[0124] like Figure 16 As shown in the example, a gate insulating film 7 and a gate electrode 8 are formed in gate trench 6, gate trench 26, and terminal trench 16, respectively. Specifically, after the gate insulating film 7 is deposited, polysilicon, which will become gate electrode 8, is deposited. The deposited polysilicon is then etched back using a resist as a mask. As a result, the polysilicon is etched back in areas without resist, forming polysilicon in gate trench 6, gate trench 26, and terminal trench 16.

[0125] On the other hand, Figure 17As illustrated, the area covered with the resist is the area where the arc shape (radius of curvature Re) is formed at the upper corner of gate trench 6. The polysilicon is not etched back, and polysilicon remains in the mesa region (the upper surface of semiconductor layer 2). Because the upper corner of gate trench 6 has a large arc shape (radius of curvature Re), there is no need to locally thicken gate insulating film 7 to suppress electric field concentration at the upper corner of gate trench 6. Therefore, a structure that suppresses electric field concentration at the upper corner of gate trench 6 can be manufactured through a single gate insulating film 7 formation step, without increasing the number of manufacturing steps and thus suppressing an increase in manufacturing cost.

[0126] Next, an interlayer insulating film 13 is formed on the upper surface of the semiconductor layer 2 by a reduced pressure CVD method so as to cover the gate electrode 8. Then, by patterning the interlayer insulating film 13, contact holes (gate contact portions 34) reaching the source region 5 and the base region 4 are formed in the active region 20 and the terminal region 30. In addition, a contact hole (source contact portion 31) reaching the gate electrode 8 is formed in the active region. Thereafter, an ohmic electrode 25 is formed in the gate contact portion 34 (see FIG. 2 ). Figure 6 ). In addition, an ohmic electrode 32 is formed in the source contact portion 31. Each ohmic electrode may be a silicide film formed by forming a metal film mainly composed of nickel (Ni) on the upper surface of the semiconductor layer 2 and the upper surface of the gate electrode 8, and then reacting Ni with the semiconductor by heat treatment at, for example, 600°C to 1100°C.

[0127] Thereafter, Al alloy or the like is deposited on the upper surface of the interlayer insulating film 13 and in the gate contact 34 and source contact 31 and then patterned to form the gate wiring 18 via the gate contact 34 and the source electrode 11 via the source contact 31 .

[0128] Then, Al alloy or the like is deposited on the surface of the silicon carbide semiconductor substrate 1 opposite to the side on which the semiconductor layer 2 is formed to form the drain electrode 12. Through the above steps, the semiconductor device 100 is formed.

[0129] <Regarding the Effects of Semiconductor Devices>

[0130] Next, the operation and effects of the semiconductor device 100 according to this embodiment will be described.

[0131] exist Figures 2 to 5 In the semiconductor device 100 of the present embodiment shown, the voltage applied between the gate electrode 8 and the source electrode 11 is controlled, thereby controlling the channel formed in the base region 4 opposite to the gate electrode 8 via the gate insulating film 7, thereby controlling the on-state and off-state of the semiconductor device 100.

[0132] When a voltage of a magnitude sufficient to turn on the semiconductor device 100 is applied between the gate electrode 8 and the source electrode 11, a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8. As a result, a channel is formed in the base region 4, which faces the gate electrode 8 via the gate insulating film 7, and a path for electrons, which serve as carriers, is formed between the n-type source region 5 and the n-type drift layer 3.

[0133] Then, electrons flowing from the source region 5 into the drift layer 3 are transferred to the drain electrode 12 via the drift layer 3 and the silicon carbide semiconductor substrate 1 by the electric field formed by the voltage applied between the drain electrode 12 and the source electrode 11. As a result, a voltage exceeding the threshold is applied to the gate electrode 8, causing current to flow from the drain electrode 12 to the source electrode 11. This state is the on-state of the semiconductor device 100.

[0134] On the other hand, when a voltage less than the threshold value is applied between the gate electrode 8 and the source electrode 11, no channel is formed in the base region 4 that faces the gate electrode 8 via the gate insulating film 7. In this case, since the p-type base region 4 exists between the n-type source region 5 and the n-type drift layer 3, no current flows from the drain electrode 12 to the source electrode 11. This state is the off-state of the semiconductor device 100.

[0135] When the semiconductor device 100 is in the off state, a high voltage supplied from an external electrical circuit is applied between the drain electrode 12 and the source electrode 11. When the semiconductor device 100 is in the off state, the depletion layer expands from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3. This prevents the electric field generated by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the bottom of the gate trench 6. This prevents the gate insulating film 7 from being destroyed even when a high electric field is applied to the gate insulating film 7 at the bottom of the gate trench 6.

[0136] On the other hand, when semiconductor device 100 is in the on-state, a voltage supplied from an external electrical circuit is applied between gate electrode 8 and source electrode 11. This voltage application applies an electric field to gate insulating film 7. The upper corners of semiconductor layer 2 in gate trench 6 are formed in an arc shape with a curvature radius Re, so gate insulating film 7 also has a rounded shape with a curvature radius Re. This prevents the electric field generated by the voltage applied between drain electrode 12 and source electrode 11 from concentrating on gate insulating film 7 at the upper corners of gate trench 6, thus preventing damage to gate insulating film 7 even when an electric field is applied.

[0137] Furthermore, when the semiconductor device 100 is in the on-state, a current generated by a voltage supplied from an external electrical circuit flows from the drain electrode 12 toward the source electrode 11. Therefore, the voltage between the drain electrode 12 and the source electrode 11 becomes the on-voltage, a voltage determined by the current flowing from the drain electrode 12 to the source electrode 11 and the on-resistance of the semiconductor device 100. This on-voltage is significantly lower than the voltage applied between the drain electrode 12 and the source electrode 11 in the off-state. Consequently, in the off-state, the depletion layer that expands from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 becomes conductive, thereby shrinking toward the diffusion protection layer 9 and the termination protection layer 19.

[0138] That is, when the semiconductor device 100 repeats the on state and the off state and performs switching, the depletion layer extending from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 expands and contracts with the switching.

[0139] The semiconductor device 100 functions by repeatedly switching between the off and on states. However, this repeated switching between the on and off states also applies voltage stress to the gate insulating film 7, accelerating degradation. The upper corners of the semiconductor layer 2 within the gate trench 6 are formed in an arc shape with a curvature radius Re, so the gate insulating film 7 in these locations also has a rounded shape with the curvature radius Re. This prevents the electric field between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the upper corners of the semiconductor layer 2. Consequently, accelerated degradation of the gate insulating film 7 can be suppressed, preventing its destruction.

[0140] In this embodiment, if Figure 4 As shown, an electrically nonfunctional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20. The termination region 30 and the active region 20 differ in both their stacked structures and their processed dimensions along the direction of the silicon carbide semiconductor substrate 1. Consequently, residual stress is generated at the boundary, affecting electrical characteristics or causing damage to the gate insulating film 7. Furthermore, the closer the gate insulating film 7 is to the outermost portion, the higher its failure rate. Therefore, by electrically isolating the outermost cells (corresponding to the gate trench 26) from the other cells as the termination region 30, and by not electrically connecting their gate electrodes 8 to the source electrode 11 and gate wiring 18, allowing the gate potential to float, damage to the device can be suppressed.

[0141] in addition, Figure 4 The increase in the number of gate trenches 26 improves the yield rate. That is, the quality of the semiconductor device 100 is improved by forming a plurality of gate trenches 26.

[0142] <Second embodiment>

[0143] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0144] <Regarding the Structure of Semiconductor Device>

[0145] Figure 19 1 is a plan view schematically showing an example of the structure of the semiconductor device 101 of this embodiment. Figure 19 As illustrated, the semiconductor device 101 includes an active region 20 and a termination region 30 .

[0146] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 is formed in the gate trenches 6, and a gate wiring 18 is connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed directly below the gate wiring 18 and directly above the gate electrode 8.

[0147] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the outer periphery of the chip. The gate bonding pad 58 and the gate electrode 8 are metal layers such as aluminum and are formed in the same process.

[0148] A source electrode 11 is formed on the upper surface of the source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact portion 31). The source electrode 11 extends to a source bonding pad 59.

[0149] In the termination region 30, a termination trench 16 and a gate wiring 18 are formed in a portion of the termination trench 16. A metal wiring 120 is formed on the upper surface of the gate wiring 18, with a gate contact 34 interposed therebetween. The metal wiring 120 is formed in the same process as the gate electrode 8 and the source electrode 11. Since the metal wiring 120 and the gate wiring 18 are connected in parallel, electrical resistance can be reduced. Semiconductor device 101 is constructed as described above.

[0150] <About the Manufacturing Method of Semiconductor Device>

[0151] Next, a method for manufacturing the semiconductor device 101 according to this embodiment will be described.

[0152] Figures 20 to 22 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.

[0153] Figure 20 The structure shown is Figure 10The structure shown corresponds to the plan view. The gate trench 6 is formed in the active region 20 , and the outermost gate trench 26 and the termination trench 16 are formed in the termination region 30 .

[0154] Figure 21 The structure shown is Figure 16 The structure shown corresponds to the top view. A gate wiring 18 is formed in the gate trench 6 of the active region 20. A gate wiring 18 is also formed in the gate trench 26 of the terminal region 30. Furthermore, a gate wiring 18 is formed in a portion of the terminal trench 16.

[0155] Polysilicon is deposited in the gate trench 6 , and a mask is formed in a partial region using a resist or the like, and the polysilicon is etched back to form the gate wiring 18 .

[0156] exist Figure 21 The regions 108 and 109 indicated by dashed lines are regions where the polysilicon is not etched back due to the configuration of the mask described above, and polysilicon remains on the upper surface of the semiconductor layer 2. The polysilicon in these regions not only exists within the gate trench 6 but also covers the upper corners of the gate trench 6 and is also formed in the mesa region (the upper surface of the semiconductor layer 2). The large radius of curvature Re of the upper corners of the gate trench 6 can suppress electric field concentration. Therefore, damage to the gate insulating film 7 is suppressed.

[0157] exist Figure 21 In the embodiment, the gate electrode 8 formed at the gate trench 26 of the terminal region 30 and the gate electrode 8 formed at the gate trench 6 arranged in a stripe shape in the central portion of the active region 20 are separated in a plan view. Figures 16 to 18 As shown, the gate wiring 18 is formed by etching back the accumulated polysilicon.

[0158] In the etch-back process, in the area with the trench step (the area where the top surface height is different due to the formation of the trench), polysilicon remains in the shape of the sidewall of the trench. In the structure where the remaining polysilicon is electrically connected, the electric field is also applied to the gate insulating film 7 under the polysilicon remaining in the shape of the sidewall, causing the gate insulating film 7 to be destroyed. In contrast, if Figure 21 In the structure shown, the potential of the polysilicon remaining along the sidewall becomes floating and is not electrically connected to the gate electrode. Therefore, the destruction of the gate insulating film 7 can be suppressed.

[0159] Figure 22 It is shown in Figure 21 This is a plan view of an example of a structure in which the interlayer insulating film 13 is formed and the source contact 31 and the gate contact 34 are formed after the steps shown.

[0160] exist Figure 22In the embodiment, a gate contact portion 34 is formed on the upper surface of the gate electrode 8 in the region 108 and the region 109. Figure 22 In the illustrated structure, gate contacts 34 and gate wiring 18 can be formed at positions overlapping the stripe-shaped gate trenches 6 in a plan view, eliminating the need for a separate area for forming gate contacts 34. This reduces the chip area and increases the degree of freedom in layout design.

[0161] Afterwards, if Figure 19 As shown, aluminum is deposited and patterned by etching using a resist mask. Then, gate wiring 18 is formed in region 108 and connected to gate bonding pad 58. In region 109, aluminum is patterned to form metal wiring 120, which extends to the upper surface of gate electrode 8 formed in termination region 30. Furthermore, metal wiring 120 is electrically connected to gate electrode 8 via contact holes (gate contacts 34). Gate electrode 8 in termination region 30 extends directly below gate bonding pad 58 and is electrically connected to gate electrode 8 via gate contact 34 within gate bonding pad 58.

[0162] The gate electrode 8 in the gate trench 6 within the cell array is electrically connected from the gate bonding pad 58 through the gate contact 34 in the center of the active region 20, and is also electrically connected to the gate electrode 8 formed in the terminal region 30, the aluminum layer (metal wiring 120), and other gate electrodes 8 within the active region 20. Therefore, the resistance value of the gate electrode 8 in the gate trench 6 within the active region 20 is reduced, and good electrical characteristics (switching characteristics, conduction characteristics) can be obtained.

[0163] The curvature radius Re of the upper corner of the gate trench 6 is formed large in the region 108 at the center of the active region 20 where the gate contact 34 is formed. Therefore, even when the gate voltage is applied during device operation, the electric field is suppressed from concentrating on the upper corner of the gate trench 6, thereby suppressing the destruction of the gate insulating film 7.

[0164] <Third embodiment>

[0165] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0166] <Regarding the Structure of Semiconductor Device>

[0167] Figure 23 1 is a plan view schematically showing an example of the structure of the semiconductor device 102 of this embodiment. Figure 23As illustrated, the semiconductor device 102 includes an active region 20 and a termination region 30 .

[0168] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 is formed in the gate trenches 6, and a gate wiring 18 is connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed directly below the gate wiring 18 and above the gate electrode 8.

[0169] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the outer periphery of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum and are formed in the same process.

[0170] A source electrode 11 is formed on the upper surface of the source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact portion 31). The source electrode 11 extends to a source bonding pad 59.

[0171] In the termination region 30, a termination trench 16 and a gate electrode 8 are formed in a portion of the termination trench 16. Metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. Metal wiring 122 is formed in the same process as gate wiring 18 and source electrode 11. Since metal wiring 122 and gate electrode 8 are connected in parallel, gate resistance can be reduced. Semiconductor device 102 is constructed as described above.

[0172] <About the Manufacturing Method of Semiconductor Device>

[0173] Next, a method for manufacturing the semiconductor device 102 according to this embodiment will be described.

[0174] Figure 24 as well as Figure 25 1 and 2 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.

[0175] Figure 24 The structure shown is Figure 16 The structure shown corresponds to the plan view. A gate electrode 8 is formed in the gate trench 6 of the active region 20. A gate electrode 8 is also formed in the gate trench 26 of the termination region 30. Furthermore, a gate electrode 8 is formed in a portion of the termination trench 16.

[0176] Polysilicon is deposited in the gate trench 6 , and a mask is formed in a partial region using a resist or the like, and the polysilicon is etched back to form the gate electrode 8 .

[0177] exist Figure 24The regions 108 and 109 indicated by dashed lines are regions where the polysilicon is not etched back due to the configuration of the mask described above, and polysilicon remains on the upper surface of the semiconductor layer 2. The polysilicon in these regions not only exists within the gate trench 6 but also covers the upper corners of the gate trench 6 and is also formed in the mesa region (the upper surface of the semiconductor layer 2). The large radius of curvature Re of the upper corners of the gate trench 6 can suppress electric field concentration. Therefore, damage to the gate insulating film 7 is suppressed.

[0178] Figure 24 The outermost end portion of the active region 20 (the portion corresponding to the region 109 ) can electrically connect the plurality of gate electrodes 8 arranged in stripes via the gate contact 34 , thereby reducing the gate resistance of the finely extending gate trench 6 .

[0179] Figure 25 It is shown in Figure 24 This is a plan view of an example of a structure in which the interlayer insulating film 13 is formed and the source contact 31 and the gate contact 34 are formed after the steps shown.

[0180] exist Figure 25 In the embodiment, the gate contact portion 34 is formed on the upper surface of the gate electrode 8 in the region 108 and the region 109 .

[0181] Afterwards, if Figure 23 As shown, aluminum is deposited and patterned by etching using a resist mask. Then, gate electrode 8 is formed in region 108 and connected to gate bonding pad 58 via gate wiring 18. In region 109, aluminum is patterned to form metal wiring 122 (gate wiring 18). Metal wiring 122 extends to the upper surface of gate electrode 8 formed in termination region 30. Furthermore, metal wiring 122 is electrically connected to gate electrode 8 via contact holes (gate contacts 34). Gate wiring 18 in termination region 30 extends to just below gate bonding pad 58 and is electrically connected to gate electrode 8 via gate contact 34 within gate bonding pad 58.

[0182] The gate electrode 8 in the gate trench 6 within the cell array is electrically connected from the gate bonding pad 58 via the gate contact portion 34 at the center of the active region 20. Furthermore, the gate electrode 8 in the gate trench 6 within the cell array is electrically connected to other gate wirings 18 within the active region 20 via the gate contact portion 34 formed at the end of the active region 20 and the aluminum layer (electrode portion 121). Therefore, the resistance value of the gate wiring 18 in the gate trench 6 within the active region 20 is reduced, and good electrical characteristics (switching characteristics, conduction characteristics) can be obtained.

[0183] The curvature radius Re of the upper corner of the gate trench 6 in the region 108 at the center of the active region 20 where the gate contact 34 is formed, and the curvature radius Re of the upper corner of the gate trench 6 in the region 109 at the end of the active region 20 are formed to be large. Therefore, even when the gate voltage is applied during device operation, it is possible to suppress the electric field from concentrating on the upper corner of the gate trench 6, thereby suppressing the destruction of the gate insulating film 7.

[0184] <Fourth embodiment>

[0185] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0186] <Regarding the Structure of Semiconductor Device>

[0187] Figures 26 to 30 1 is a cross-sectional view schematically showing an example of the structure of the semiconductor device 103 of this embodiment. Figures 26 to 30 As illustrated, the semiconductor device 103 includes an active region 20 and a termination region 30 .

[0188] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 is formed in the gate trenches 6, and a gate wiring 18 is connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed directly below the gate wiring 18 and above the gate electrode 8.

[0189] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the outer periphery of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum and are formed in the same process.

[0190] A source electrode 11 is formed on the upper surface of the source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact portion 31). The source electrode 11 extends to a source bonding pad 59.

[0191] In the termination region 30, a termination trench 16 and a gate electrode 8 are formed in a portion of the termination trench 16. Metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. Metal wiring 122 is formed in the same process as the gate electrode 8 and source electrode 11. Since the metal wiring 122 and the gate electrode 8 are connected in parallel, gate resistance can be reduced. Semiconductor device 103 is constructed as described above.

[0192] <About the Manufacturing Method of Semiconductor Device>

[0193] Next, a method for manufacturing the semiconductor device 103 according to this embodiment will be described.

[0194] Figure 26 The structure shown is Figures 7 to 9 The structure corresponds to the stage where the process ends.

[0195] And, as Figure 26 As shown in the example, after forming the gate trench 6, the gate trench 26, and the termination trench 16, impurities are implanted into the bottom surfaces of each trench. Specifically, at the bottom of the gate trench 6 and the bottom of the gate trench 26, a p-type diffusion protection layer 39 is formed by Al ion implantation. Similarly, at the bottom of the termination trench 16, a p-type termination protection layer 49 is formed by Al ion implantation. The impurity concentration of the implanted Al is preferably, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 Hereinafter, the depth of ion implantation is preferably, for example, not less than 0.1 μm and not more than 2.0 μm.

[0196] Afterwards, if Figure 27 As shown in the example, a resist mask 51 is formed in the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30. Furthermore, Al ions are additionally implanted into the exposed p-type diffusion protection layer 39 and the termination protection layer 49. The Al impurity concentration is preferably 1×10 16 cm -3 Above and 1×10 18 cm -3 Hereinafter, the depth of ion implantation is preferably, for example, not less than 0.1 μm and not more than 2.0 μm.

[0197] As a result of the above-described two ion implantations, the impurity concentrations of the gate trench 6 and the diffusion protection layer 39 in the gate trench 26 at the boundary between the active region 20 and the termination region 30 become lower than the impurity concentration of the diffusion protection layer 9 in the gate trench 6 (the trench formed at a portion other than the boundary) where the two ion implantations were performed. Similarly, the impurity concentration of the diffusion protection layer 39 becomes lower than the impurity concentration of the termination protection layer 19 in the termination trench 16 where the two ion implantations were performed.

[0198] After that, the resist is removed, and an annealing process is performed using a heat treatment apparatus to activate the ion-implanted impurities. The annealing process is performed in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, by heating at a temperature in the range of 1300°C to 1900°C for 30 seconds to 1 hour.

[0199] Next, if Figure 28 As shown in the example, a gate insulating film 97 is deposited. Furthermore, a resist mask 52 is formed in the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30. The gate insulating film 97 in the region not covered by the resist mask 52 is removed by wet processing using hydrofluoric acid or the like. Here, the thickness of the gate insulating film 97 is, for example, not less than 20 nm and not more than 150 nm.

[0200] Afterwards, if Figure 29 As shown in the example, a gate insulating film is further deposited on the entire surface. The film thickness of the gate insulating film further formed in the second deposition is, for example, not less than 20 nm and not more than 150 nm.

[0201] Through the above-mentioned two deposition steps, the gate insulating film 87 in a certain region is formed thicker than the other gate insulating films 7 .

[0202] Then, polysilicon is deposited to become the gate electrode 8. Then, the deposited polysilicon is etched back using the resist as a mask. Then, the interlayer insulating film 13, the source contact portion 31, the gate contact portion 34, the ohmic electrode 32, the source electrode 11, the gate wiring 18, etc. are formed through the same process as that described in the first embodiment, and the MOSFET is completed (see Figure 30 ).

[0203] In the region of the active region 20 where the gate contact 34 is formed, polysilicon also remains in the mesa region (the upper surface of the semiconductor layer 2), but this portion has a large arc shape (curvature radius Re). Therefore, as in the case of the first embodiment, electric field concentration at the upper corner of the gate trench 6 can be suppressed, and destruction of the gate insulating film 7 can be suppressed.

[0204] exist Figure 30 In the illustrated structure, the termination trench 16 in the termination region 30 is machined with wide dimensions. In contrast, the gate trenches 6 and 26 in the cell portion are formed with the minimum process width. Due to these structural differences, the coefficient of expansion of the materials varies depending on the thermal history during wafer processing. This generates residual stress, resulting in variations in the electrical characteristics of the device and affecting the reliability of the semiconductor device.

[0205] In each cell arranged in the active region 20 , the stress increases toward the outermost portion of the gate trench. Due to this influence, the failure rate of the gate insulating film 7 increases toward the outermost portion of the gate trench.

[0206] Therefore, it is effective to electrically isolate the outermost cells from the other cells and float the gate potential. However, in this case, the region does not function as a MOSFET.

[0207] Therefore, in this embodiment, by increasing the thickness of the gate insulating film 87 of the cells in the peripheral portion (the boundary between the active region 20 and the terminal region 30) or designing the impurity concentration of the diffusion protection layer 39 to be lower than the impurity concentration of the diffusion protection layer 9 of other cells within the active region 20, the concentrated electric field applied to the gate insulating film 87 can be reduced even when a gate voltage is applied and the semiconductor device is turned on. As a result, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0208] <Regarding the Effects Produced by the Multiple Embodiments Described Above>

[0209] Next, examples of the effects produced by the multiple embodiments described above are shown. Furthermore, in the following description, the effects are described based on the specific structures exemplified in the multiple embodiments described above. However, these effects can be replaced with other specific structures exemplified in this specification to the extent that the same effects are produced. That is, for ease of description, only one of the corresponding specific structures may be represented below as a representative example. However, the representatively represented specific structure can also be replaced with another corresponding specific structure.

[0210] Furthermore, this substitution may be performed across multiple embodiments. In other words, the same effects may be produced by combining various configurations exemplified in different embodiments.

[0211] According to the embodiment described above, the semiconductor device includes: a drift layer 3 of a first conductivity type (n-type); a base region 4 of a second conductivity type (p-type) provided on the surface of the drift layer 3; a plurality of n-type source regions 5 provided on the surface of the base region 4; at least one trench (e.g., gate trench 6, gate trench 26, termination trench 16) extending from the upper surface of the drift layer 3 through the base region 4 into the drift layer 3; a p-type protection layer (e.g., diffusion protection layer 9, diffusion protection layer 39, termination protection layer 19) provided within the drift layer 3 below the trench; a gate insulating film 7 provided along the interior of the trench, including the upper corner of the trench; and a gate electrode 8 surrounded by the gate insulating film 7 and provided at least within the trench. Here, the regions of the trench divided when viewed from above are referred to as the first region and the second region. The semiconductor device further includes a source electrode 11 electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region, and a gate wiring 18 provided on the upper surface of the gate electrode 8 provided in the trench (gate trench 6 or terminal trench 16) in the second region. Furthermore, the curvature radius Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or terminal trench 16) in the second region is larger than the curvature radius Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0212] With this structure, even when a gate voltage is applied to the gate insulating film 7 formed in a circular arc shape with a large curvature radius (curvature radius Re), the large curvature radius effectively suppresses electric field concentration, thus preventing the application of a high electric field. Therefore, destruction of the gate insulating film 7 is suppressed.

[0213] Furthermore, even when other structures exemplified in the present specification are appropriately added to the above-mentioned structure, that is, when other structures not mentioned as the above-mentioned structure in the present specification are appropriately added, the same effects can be produced.

[0214] Furthermore, according to the above-described embodiment, gate wiring 18 is provided on the upper surface of gate electrode 8 extending to the upper surface of source region 5. This structure suppresses destruction of the gate insulating film and improves the reliability of the semiconductor device.

[0215] Furthermore, according to the embodiment described above, gate wiring 18 is connected to the upper surface of gate electrode 8 extending to the upper surface of source region 5 via a plurality of contact holes (gate contact portions 34). This structure suppresses destruction of the gate insulating film and improves the reliability of the semiconductor device.

[0216] Furthermore, according to the embodiment described above, the thickness of the gate insulating film 7 provided in the trenches in the first region is equal to the thickness of the gate insulating film 7 provided in the trenches in the second region. With this structure, the gate insulating film 7 formed in multiple trenches can be formed in a single step.

[0217] Furthermore, according to the embodiment described above, multiple trenches are provided. Furthermore, at least one gate trench 6 is provided in the active region 20, and at least one gate trench 26 is provided in the termination region 30. Furthermore, the gate electrode 8 provided in the gate trench 26 provided in the termination region 30 is not electrically connected to the source electrode 11 or the gate wiring 18. With this structure, by floating the potential of the gate electrode 8 in the gate trench 26, it is possible to suppress device destruction.

[0218] Furthermore, according to the embodiment described above, multiple trenches are provided. Furthermore, multiple gate trenches 6 are arranged in a stripe shape when viewed from above. Furthermore, gate wiring 18 is provided across the upper surfaces of each gate electrode 8 provided within the multiple gate trenches 6. This structure suppresses damage to the gate insulating film, thereby improving the reliability of the semiconductor device.

[0219] Furthermore, according to the embodiment described above, multiple trenches are provided. Furthermore, at least one gate trench 6 is provided in the active region 20, and at least one termination trench 16 is provided in the termination region 30. Furthermore, the termination trench 16 provided in the termination region 30 is formed wider than the gate trench 6 (or gate trench 26) provided in the active region 20. This structure allows for a structure in which no polysilicon remains on the sidewalls of the termination trench 16. This reduces the risk of damage to the gate insulating film compared to a structure in which an electric field is applied to the underlying gate insulating film 7 via the polysilicon remaining on the sidewalls of the termination trench.

[0220] Furthermore, according to the embodiment described above, multiple trenches are provided. Furthermore, at least one gate trench 6 is provided in the active region 20, which is surrounded by the terminal region 30 when viewed from above. Furthermore, the thickness of the gate insulating film 87 provided in the trenches (gate trench 6 and gate trench 26) at the boundary between the active region 20 and the terminal region 30 is thicker than the thickness of the gate insulating film 7 provided in the trenches (gate trench 6 and terminal trench 16) in the active region 20 and the terminal region 30 outside the boundary. With such a structure, when a gate voltage is applied and the semiconductor device is turned on, the concentrated electric field applied to the gate insulating film 87 can be reduced. As a result, damage to the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0221] In addition, according to the embodiment described above, a plurality of trenches are provided. Furthermore, at least one gate trench 6 is provided in the active region 20 surrounded by the terminal region 30 when viewed from above. In addition, the impurity concentration of the protective layer (diffusion protection layer 39) provided below the gate trench 6 and the gate trench 26 in the boundary portion between the active region 20 and the terminal region 30 is lower than the impurity concentration of the protective layer (diffusion protection layer 9, terminal protection layer 19) provided below the trenches (gate trench 6, terminal trench 16) in the active region 20 and the terminal region 30 outside the boundary portion. According to such a structure, even when a gate voltage is applied and the semiconductor device is in the on state, the concentrated electric field applied to the gate insulating film 87 can be reduced. As a result, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0222] According to the embodiment described above, in a method for manufacturing a semiconductor device, a p-type base region 4 is provided on the surface of an n-type drift layer 3. Furthermore, multiple n-type source regions 5 are provided on the surface of the base region 4. Furthermore, at least one trench (e.g., gate trench 6, gate trench 26, or terminal trench 16) is provided, extending from the upper surface of the drift layer 3 through the base region 4 and into the interior of the drift layer 3. Furthermore, a p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, or terminal protective layer 19) is provided within the drift layer 3 below the trench. Here, the regions of the trench, as viewed from above, are defined as a first region and a second region. Furthermore, in the first and second regions, the upper corners of the trench (gate trench 6) are etched. Furthermore, in the second region, the upper corners of the trench (gate trench 6 or terminal trench 16) are etched. Furthermore, a gate insulating film 7 is provided along the interior of the trench, including the upper corners of the trench. Furthermore, a gate electrode 8 is provided in the trench surrounded by the gate insulating film 7. Furthermore, a source electrode 11 is provided so as to be electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region. Furthermore, a gate wiring 18 is provided on the upper surface of the gate electrode 8 provided in the trench (gate trench 6 or terminal trench 16) in the second region. Here, the curvature radius Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or terminal trench 16) in the second region is larger than the curvature radius Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0223] With this structure, even when a gate voltage is applied to the gate insulating film 7 formed in a circular arc shape with a large curvature radius (curvature radius Re), the large curvature radius effectively suppresses electric field concentration, thus preventing the application of a high electric field. Therefore, destruction of the gate insulating film 7 is suppressed.

[0224] Furthermore, the order in which each process is performed can be changed without particular limitation.

[0225] Furthermore, even when other structures exemplified in the present specification are appropriately added to the above-mentioned structure, that is, when other structures not mentioned as the above-mentioned structure in the present specification are appropriately added, the same effects can be produced.

[0226] <Regarding Modifications of the Multiple Embodiments Described Above>

[0227] In the above-described embodiments, the materials, dimensions, shapes, relative arrangements, or implementation conditions of each component are sometimes described, but these are merely examples in all respects and are not restrictive.

[0228] Therefore, numerous modifications and equivalents not shown in the examples are conceivable within the scope of the technology disclosed in this specification. For example, these include modifying at least one component, adding at least one component, omitting at least one component, and extracting at least one component from at least one embodiment and combining it with components from another embodiment.

[0229] In at least one embodiment described above, when a material name or the like is described without being particularly specified, the material is assumed to include other additives, such as an alloy, unless there is any contradiction.

[0230] Explanation of symbols

[0231] 3: Drift layer; 4: Base region; 5: Source region; 6: Gate trench; 7: Gate insulating film; 8: Gate electrode; 11: Source electrode; 16: Terminal trench; 18: Gate wiring; 20: Active region; 26: Gate trench; 30: Terminal region; 34: Gate contact; 87: Gate insulating film; 97: Gate insulating film; 100: Semiconductor device; 101: Semiconductor device; 102: Semiconductor device; 103: Semiconductor device; 108: Region; 109: Region; 1000: Region.

Claims

1. A semiconductor device further comprising: A drift layer of a first conductivity type; A base region of the second conductivity type is provided on the surface of the drift layer; A plurality of source regions of the first conductivity type are provided on the surface of the base region; at least one trench extending from the upper surface of the drift layer through the base region and into the drift layer; a second conductive type protection layer disposed in the drift layer below the trench; a gate insulating film provided along the interior of the trench including the upper corner of the trench; a gate electrode, surrounded by the gate insulating film and disposed at least in the trench; a source electrode electrically connected to the source region adjacent to the trench; as well as a gate wiring disposed on an upper surface of the gate electrode disposed in the trench, Among the regions divided in the trench in a plan view, a region where the source electrode is provided is defined as a first region, and a region where the gate wiring is provided is defined as a second region. The gate insulating film provided at the upper corner of the trench in the second region has a greater curvature radius than the gate insulating film provided at the upper corner of the trench in the first region.

2. The semiconductor device according to claim 1, wherein The gate wiring is provided on the upper surface of the gate electrode extending to the upper surface of the source region.

3. The semiconductor device according to claim 2, wherein The gate wiring is connected to the upper surface of the gate electrode extending to the upper surface of the source region through a plurality of contact holes.

4. The semiconductor device according to any one of claims 1 to 3, wherein The thickness of the gate insulating film provided in the trench in the first region is equal to the thickness of the gate insulating film provided in the trench in the second region.

5. The semiconductor device according to any one of claims 1 to 4, wherein A plurality of grooves are provided, At least one trench is provided in the active region and in the terminal region surrounding the active region in a plan view, respectively. The gate electrode provided in the trench provided in the termination region is not electrically connected to the source electrode and the gate wiring.

6. The semiconductor device according to any one of claims 1 to 5, wherein A plurality of grooves are provided, When viewed from above, a plurality of the grooves are arranged in strips. The gate wiring is provided across the upper surfaces of the respective gate electrodes provided in the plurality of trenches.

7. The semiconductor device according to any one of claims 1 to 6, wherein A plurality of grooves are provided, At least one of the trenches is separately provided in the active region and a terminal region surrounding the active region in a plan view. The trench provided in the terminal region is formed to have a width wider than the trench provided in the active region.

8. The semiconductor device according to any one of claims 1 to 7, wherein A plurality of grooves are provided, At least one of the trenches is provided in the active region surrounded by the terminal region in a plan view, The gate insulating film provided at the trench in a boundary portion between the active region and the terminal region is thicker than the gate insulating film provided at the trench in the active region and the terminal region outside the boundary portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein A plurality of grooves are provided, At least one of the trenches is provided in the active region surrounded by the terminal region in a plan view, The impurity concentration of the protective layer provided below the trench in the boundary portion between the active region and the termination region is lower than the impurity concentration of the protective layer provided below the trench in the active region and the termination region outside the boundary portion.

10. A method for manufacturing a semiconductor device, wherein: A base region of the second conductivity type is provided on the surface layer of the drift layer of the first conductivity type. A plurality of source regions of the first conductivity type are provided on the surface layer of the base region. providing at least one trench extending from the upper surface of the drift layer through the base region into the drift layer, A second conductive type protection layer is provided in the drift layer below the trench, and the trench is divided into a first region and a second region when viewed from above. In the first region and the second region, the upper corners of the trench are etched. In the second region, the upper corner of the trench is etched. providing a gate insulating film along the interior of the trench including the upper corner of the trench, A gate electrode is provided in the trench surrounded by the gate insulating film. providing a source electrode so as to be electrically connected to the source region adjacent to the trench in the first region; A gate wiring is provided on the upper surface of the gate electrode provided in the trench in the second region. The gate insulating film provided at the upper corner of the trench in the second region has a greater curvature radius than the gate insulating film provided at the upper corner of the trench in the first region.

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