Silicon carbide semiconductor device and method for manufacturing same

Abstract

Provided is a method for manufacturing a silicon carbide semiconductor device in which a semiconductor layer comprising silicon carbide can be brought into ohmic contact with an electrode without forming a silicide layer. A method for manufacturing a silicon carbide semiconductor device includes: performing ion implantation of an impurity on an upper surface of a first semiconductor layer formed of 4H-SiC silicon carbide so as to be inclined at an angle of 30 DEG or more and less than 90 DEG with respect to a normal line of the upper surface of the first semiconductor layer; thereby forming a second semiconductor layer on the upper surface side of the first semiconductor layer, said second semiconductor layer being formed of silicon carbide containing 3C-SiC on at least the upper surface; and forming a main electrode on the upper surface side of the second semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device as a semiconductor device using silicon carbide (SiC) and a method for manufacturing the same. Background Art

[0002] Patent document 1 discloses a method for forming a semiconductor structure, comprising the following steps: preparing a silicon carbide layer having a crystal axis; heating the silicon carbide layer to a temperature of approximately 300°C or higher; implanting dopant ions into the heated silicon carbide layer at an implantation angle of less than approximately 2° between the implantation direction and the crystal axis; and annealing the silicon carbide layer at a time-temperature product of less than approximately 30,000°C·hour to activate the implanted ions.

[0003] Patent Document 2 discloses a semiconductor device comprising a silicon carbide layer, a gate electrode, a silicon oxide layer between the silicon carbide layer and the gate electrode, and a silicon oxide layer between the silicon carbide layer and the silicon oxide layer having a nitrogen concentration of 1×10 21 cm -3 The silicon carbide layer comprises a first surface having an off-angle of not less than 0 degrees and not more than 8 degrees relative to the {0001} plane and a second surface opposite to the first surface, the silicon carbide layer having a 4H-SiC crystal structure, and the silicon carbide layer including: a p-type first silicon carbide region; an n-type second silicon carbide region located between the first silicon carbide region and the first surface; and a third silicon carbide region located between the first silicon carbide region and the first surface, the second silicon carbide region located between the third silicon carbide region and the first surface, and the third silicon carbide region containing oxygen.

[0004] Patent document 3 discloses an electronic device comprising: a silicon carbide drift region having a first conductivity type and a first doping concentration; a well region within the drift region, the well region having a second conductivity type opposite to the first conductivity type and having a second doping concentration; and a deeply implanted region below the well region, the well region having a second conductivity type and a third doping concentration that is higher than the first doping concentration and lower than the second doping concentration, wherein the drift region comprises a drift layer having the first doping concentration and a current spreading layer having a fourth doping concentration on the drift layer, the fourth doping concentration being higher than the first doping concentration of the drift layer and lower than the third doping concentration of the deeply implanted region, and the deeply implanted region extends to a depth shallower than the thickness of the current spreading layer.

[0005] Patent document 4 discloses a method for forming a semiconductor structure, comprising the following steps: preparing a silicon carbide layer having a crystal axis; heating the silicon carbide layer to a temperature of about 300°C or higher; implanting dopant ions into the heated silicon carbide layer at an implantation angle of less than about 2° between the implantation direction and the crystal axis; and annealing the silicon carbide layer at a time-temperature product of less than about 30,000°C / hour to activate the implanted ions, wherein the step of implanting the dopant ions comprises the following steps: implanting the dopant ions at an implantation energy of less than about 100 keV and at a temperature of less than 1E13 cm -2 Dopant ions are implanted at a dose of .

[0006] Patent Documents 5 and 6 disclose a SiC epitaxial wafer having a low-angle substrate of less than 4 degrees and a SiC epitaxial growth layer disposed on the substrate. The SiC epitaxial growth layer uses a Si compound as a Si supply source and a C compound as a C supply source, achieving a carrier density uniformity of less than 10% and a defect density of less than 1 / cm 2 The C / Si ratio of the Si compound to the C compound is in the range of 0.7 to 0.95.

[0007] Patent documents 7 and 8 disclose a method for manufacturing a SiC epitaxial wafer, comprising the following steps: preparing a SiC ingot, cutting and grinding it at an off-angle to form a SiC bare wafer with a (0001) plane as a surface; removing the cut surface of the SiC bare wafer to form a SiC substrate; and causing a SiC epitaxial growth layer to crystallize on the SiC substrate, wherein the raw material gas supplied during the epitaxial growth includes a Si compound as a supply source of Si and a C compound as a supply source of C, and both the Si compound and the C compound or the Si compound includes a compound containing fluorine, and controlling the crystal growth temperature so that the surface concave-convex defect density containing particles on the surface of the SiC epitaxial growth layer is less than 0.07 particles / cm 2 .

[0008] Patent document 9 discloses a semiconductor device comprising: an element region having an insulated gate type switching element; and a peripheral region adjacent to the element region, wherein a first trench and a second trench are formed in the peripheral region, a surface region of a second conductive type is formed between the first trench and the second trench, a first bottom region of a second conductive type is formed on the bottom surface of the first trench, a second bottom region of a second conductive type is formed on the bottom surface of the second trench, a first side region of a second conductive type connecting the surface region with the first bottom region is formed along the side surface of the first trench, a second side region of a second conductive type connecting the surface region with the second bottom region is formed along the side surface of the second trench, and a low surface density region is formed in at least a portion of the first side region and the second side region.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-31923

[0012] Patent Document 2: Japanese Patent Application Laid-Open No. 2022-144217

[0013] Patent Document 3: Japanese Patent No. 7015750

[0014] Patent Document 4: Japanese Patent No. 6391689

[0015] Patent Document 5: Japanese Patent No. 6584253

[0016] Patent Document 6: International Publication No. 2017 / 047350

[0017] Patent Document 7: Japanese Patent No. 6479347

[0018] Patent Document 8: International Publication No. 2015 / 186791

[0019] Patent Document 9: Japanese Patent No. 6169966 Summary of the Invention

[0020] Problems to be solved by the invention

[0021] In silicon carbide semiconductor devices, technologies have been studied that involve forming a silicide layer such as nickel silicide (NiSi) to achieve ohmic contact between the silicon carbide semiconductor layer and the electrode. However, the surface of the silicide layer is prone to unevenness, which may adversely affect reliability.

[0022] An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing the same, in which a semiconductor layer formed of silicon carbide can be brought into ohmic contact with an electrode without forming a silicide layer.

[0023] Solutions for solving problems

[0024] To achieve the above-mentioned object, one embodiment of the present disclosure is directed to a silicon carbide semiconductor device comprising: a first semiconductor layer formed of 4H-SiC silicon carbide; a second semiconductor layer provided on the upper surface side of the first semiconductor layer, the second semiconductor layer being formed of silicon carbide containing 3C-SiC at least on the upper surface; and a main electrode provided on the upper surface side of the second semiconductor layer, wherein the impurity concentration within a range from the upper surface of the second semiconductor layer to a depth of 0.3 μm is 1×10 18 / cm 3The impurity concentration in the depth range of 0.5 μm or more from the upper surface of the second semiconductor layer is 1×10 17 / cm 3 the following.

[0025] The main purpose of another embodiment of the present invention is a method for manufacturing a silicon carbide semiconductor device, comprising the following steps: ion implantation of impurities into the upper surface of a first semiconductor layer formed of 4H-SiC silicon carbide at an angle of not less than 30° and less than 90° relative to the normal to the upper surface of the first semiconductor layer, thereby forming a second semiconductor layer formed of silicon carbide containing 3C-SiC on at least the upper surface on the upper surface side of the first semiconductor layer; and forming a main electrode on the upper surface side of the second semiconductor layer.

[0026] Effects of the Invention

[0027] According to the present disclosure, it is possible to provide a silicon carbide semiconductor device in which a semiconductor layer composed of silicon carbide can be brought into ohmic contact with an electrode without forming a silicide layer, and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a top view of the silicon carbide semiconductor device according to the first embodiment.

[0029] Figure 2 It is from Figure 1 Cross-sectional view observed in the AA direction.

[0030] Figure 3 It is from Figure 1 Cross-sectional view observed in the BB direction.

[0031] Figure 4 These are cross-sectional views showing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0032] Figure 5 The method for manufacturing a silicon carbide semiconductor device according to the first embodiment is followed by Figure 4 of and Figure 2 Corresponding process cross-section diagram.

[0033] Figure 6 The method for manufacturing a silicon carbide semiconductor device according to the first embodiment is followed by Figure 4 of and Figure 3 Corresponding process cross-section diagram.

[0034] Figure 7 This is a cross-sectional view when ion implantation is performed obliquely toward the off-angle side of the semiconductor substrate.

[0035] Figure 8This is another cross-sectional view when ion implantation is performed obliquely toward the side opposite to the off angle of the semiconductor substrate.

[0036] Figure 9 is a cross-sectional view of a silicon carbide semiconductor device according to a first comparative example.

[0037] Figure 10 is a cross-sectional view of a silicon carbide semiconductor device according to a second comparative example.

[0038] Figure 11 This is a graph showing simulation results of impurity distribution obtained by ion implantation from a vertical direction when the acceleration energy is changed.

[0039] Figure 12 This is a graph showing simulation results of impurity distribution obtained by ion implantation from an oblique direction when the acceleration energy is changed.

[0040] Figure 13 This is a graph showing simulation results of impurity distribution obtained by ion implantation when the implantation angle is changed.

[0041] Figure 14 It is a cross-sectional view of a silicon carbide semiconductor device according to the second embodiment.

[0042] Figure 15 These are cross-sectional views showing steps of a method for manufacturing a silicon carbide semiconductor device according to the second embodiment.

[0043] Figure 16 It is a cross-sectional view of a silicon carbide semiconductor device according to a third embodiment.

[0044] Figure 17 These are cross-sectional views showing steps of a method for manufacturing a silicon carbide semiconductor device according to the third embodiment.

[0045] Figure 18 It is a cross-sectional view of a silicon carbide semiconductor device according to a fourth embodiment.

[0046] Figure 19 1 and 2 are cross-sectional views showing steps of a method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment.

[0047] Figure 20 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 19 Process cross-section diagram.

[0048] Figure 21 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 20 Process cross-section diagram.

[0049] Figure 22 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 21 Process cross-section diagram.

[0050] Figure 23 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 22 Process cross-section diagram.

[0051] Figure 24 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 23 Process cross-section diagram.

[0052] Figure 25 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 24 Process cross-section diagram.

[0053] Figure 26 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 25 Process cross-section diagram.

[0054] Figure 27 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 26 Process cross-section diagram.

[0055] Figure 28 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 27 Process cross-section diagram.

[0056] Figure 29 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 28 Process cross-section diagram.

[0057] Figure 30 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 29 Process cross-section diagram.

[0058] Figure 31 The method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment is followed by Figure 30 Process cross-section diagram.

[0059] Figure 32 It is a cross-sectional view of a silicon carbide semiconductor device according to a fifth embodiment.

[0060] Figure 33 This is a cross-sectional view of a silicon carbide semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION

[0061] Hereinafter, the first to sixth embodiments of the present disclosure will be described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar figure marks, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane size, the ratio of the thickness of each layer, etc. are sometimes different from the actual ones. In addition, the drawings may also contain parts with different dimensional relationships and ratios. In addition, the first to sixth embodiments shown below illustrate devices and methods for concretizing the technical ideas of the present disclosure. The technical ideas of the present disclosure do not specify the material, shape, structure, configuration, etc. of the structural components to the following materials, shapes, structures, configurations, etc.

[0062] In the present invention, the source region of a metal oxide semiconductor field effect transistor (MOSFET) is a "main region (first main region)" that can be selected as an emitter region in an insulated gate bipolar transistor (IGBT) and as a cathode region in a thyristor or diode such as a MOS-controlled electrostatic induction thyristor (SI thyristor). In addition, the drain region of a MOSFET is a "second main region" that can be selected as a collector region in an IGBT and as an anode region in a thyristor or diode. In this disclosure, when simply referred to as a "main region", it refers to either "one main region (first main region)" or "another main region (second main region)" that is appropriate based on the technical common sense of those skilled in the art.

[0063] Furthermore, the definitions of directions such as up and down in this disclosure are for ease of explanation only and do not limit the technical concepts of this disclosure. For example, if an object is rotated 90°, up and down will be read as left and right, while if it is rotated 180°, up and down will be read inversely. This is self-evident. Furthermore, the term "upper surface" can be replaced with "front surface," and the term "lower surface" can be replaced with "back surface."

[0064] In addition, in this disclosure, the case where the first conductivity type is n-type and the second conductivity type is p-type is exemplified. However, the conductivity types can also be selected to be opposite, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, the "+" or "-" attached to "n" or "p" refers to a semiconductor region with a relatively higher or relatively lower impurity concentration, respectively, compared to a semiconductor region not marked with "+" or "-". However, even if the semiconductor regions are attached with the same "n" and "n", it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0065] In addition, in the expression of the Miller index in the present disclosure, “-” refers to a bar added to the exponent immediately following it, and a negative exponent is indicated by adding “-” before the exponent.

[0066] SiC crystals have polymorphs, primarily cubic 3C structures (3C-SiC) and hexagonal 4H structures (4H-SiC) and 6H structures (6H-SiC). Reports indicate that the band gap at room temperature is 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. This disclosure primarily uses 4H-SiC and 3C-SiC as examples.

[0067] (First embodiment)

[0068] <Structure of Silicon Carbide Semiconductor Device>

[0069] A hybrid PN Schottky (MPS) structure diode is exemplified as the silicon carbide semiconductor device according to the first embodiment. The MPS structure is a structure in which a Schottky junction and a pn junction are mixed on the upper surface side of a semiconductor substrate.

[0070] Figure 1 This is a top view of a silicon carbide semiconductor device according to the first embodiment. The silicon carbide semiconductor device according to the first embodiment includes an active region 101 provided on a semiconductor substrate (semiconductor base) 100, and a termination region 102 provided on the semiconductor substrate 100 to surround the active region 101. The active region 101 is a region where current flows when the diode is in the on state. The termination region 102 is a region for relaxing the electric field applied to the ends of the active region 101 and maintaining a withstand voltage.

[0071] In the active region 101, a plurality of semiconductor layers of the second conductivity type (p type) are provided on the upper surface side of the drift layer 2 which is a semiconductor layer of the first conductivity type (n type). + The anode region 3 of the semiconductor layer of the type (type). In the plane pattern, the anode region 3 has a Figure 1 The anode region 3 is a portion of a straight line (striped shape) extending parallel to each other in the vertical direction). Figure 1 In addition, the number of the anode regions 3 arranged is not particularly limited.

[0072] exist Figure 2 Shown in Figure 1 The cross-sectional view is observed along the AA direction and perpendicular to the extending direction of the anode region 3. Figure 2 As shown, a first conductive type (n + The cathode region 1 is a (type) cathode region 1. The cathode region 1 is composed of a substrate (SiC substrate) formed of SiC such as 4H-SiC, for example.

[0073] A drift layer 2 of the first conductivity type (n-type) having an impurity concentration lower than that of the cathode region 1 is provided on the upper surface of the cathode region 1. The drift layer 2 is composed of, for example, an epitaxially grown layer formed of SiC such as 4H-SiC. Furthermore, an n-type buffer layer may be provided between the cathode region 1 and the drift layer 2. The impurity concentration of the n-type buffer layer may be lower than that of the cathode region 1 and higher than that of the drift layer 2.

[0074] A plurality of p-type transistors are provided on the upper surface of the drift layer 2 so as to be separated from each other. + Type of anode area 3. p + The anode region 3 of the p-type drift layer 2 forms a pn junction with the n-type drift layer 2. The anode region 3 is formed by ion implantation of p-type impurities such as aluminum (Al) or boron (B) into the drift layer 2. Figure 1 In a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3 when viewed in the AA direction, the anode region 3 has a substantially rectangular cross-sectional shape.

[0075] exist Figure 3 Shown in Figure 1 The cross-sectional view along the extension direction of the anode region 3 is observed in the BB direction. Figure 3 As shown, in a cross-sectional view along the extending direction of the planar pattern of the anode region 3, the anode region 3 has a substantially parallelogram-shaped cross-section. The upper surface and lower surface of the anode region 3 are substantially parallel, and the inclined side surfaces of the anode region 3 are substantially parallel. The angle θ0 formed between the normal line L1 of the upper surface of the semiconductor substrate 100 and the inclined side surface of the anode region 3 is, for example, greater than 30° and less than approximately 90°. The anode region 3 is formed to have a substantially parallelogram-shaped cross-section by ion implantation of p-type impurities from an inclined direction relative to the normal line L1 of the upper surface of the semiconductor substrate 100. The side surfaces of the anode region 3 are substantially parallel to the implantation direction of the ion implantation.

[0076] Although Figure 3 Although not shown, a p-type electric field relaxation layer is provided on the upper surface of the drift layer 2 in the termination region 102. When the electric field relaxation layer contacts or overlaps the end of the anode region 3, the anode region 3 does not need to have a substantially parallelogram cross-sectional shape.

[0077] The depth d1 of the anode region 3 is, for example, approximately 0.1 μm to 0.5 μm, or approximately 0.1 μm to 0.3 μm. The depth d1 of the anode region 3 may also be approximately 0.5 μm or greater. The greater the angle at which the ions implanted to form the anode region 3 are inclined relative to the normal line L1 to the upper surface of the semiconductor substrate 100, the shallower the depth d1 of the anode region 3.

[0078] The impurity concentration in the range of 0.3 μm from the upper surface of the anode region 3 is, for example, 1×10 18 / cm 3 Above and 1×10 22 / cm 3 Below, if 1×10 19 / cm 3 Above and 1×10 22 / cm 3 The impurity concentration on the upper surface of the anode region 3 can be 1×10 20 / cm 3 Above and 1×10 22 / cm 3 In the direction perpendicular to the upper surface of the anode region 3, i.e., in the depth direction, the impurity concentration may be the same within a depth range of approximately 0.3 μm from the upper surface of the anode region 3, and the impurity concentration may be the same within a depth range of approximately 0.4 μm from the upper surface of the anode region 3. "The same impurity concentration" not only includes the case where the impurity concentration is strictly the same, but also includes the range where the impurity concentration varies within ±10%.

[0079] In the direction perpendicular to the upper surface of the anode region 3, that is, in the depth direction, the impurity concentration in the depth range of 0.5 μm or more from the upper surface of the anode region 3 is lower than the impurity concentration in the depth range of 0.3 μm from the upper surface of the anode region 3. For example, the impurity concentration in the depth range of 0.5 μm or more from the upper surface of the anode region 3 is 1×10 17 / cm 3 Below left and right.

[0080] As in Figure 2 and Figure 3 As schematically indicated by "×" in the figure, during ion implantation to form anode region 3, damage 4 is generated in at least the upper surface side (also referred to as the "upper portion" or "surface layer") of anode region 3, destroying the crystalline structure of 4H-SiC and forming an amorphous structure. 3C-SiC is formed when the amorphous structure recrystallizes during subsequent heat treatment (activation annealing). Therefore, the surface layer of anode region 3 contains 3C-SiC.

[0081] The proportion of 3C-SiC contained in the surface layer of the anode region 3 is, for example, more than 10% and less than 100%. The surface layer of the anode region 3 can be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layer of the anode region 3 can also contain an amorphous structure, 4H-SiC, etc. 3C-SiC has a narrower band gap than 4H-SiC, so by including 3C-SiC in the surface layer of the anode region 3, it is possible to make ohmic contact with the anode electrode 5 on the upper surface side of the anode region 3 in a low-resistance manner. The lower part (lower part) of the surface layer of the anode region 3 can be composed of 4H-SiC.

[0082] As a method for measuring (observing) the crystal structure of 3C-SiC, 4H-SiC, etc., the area ratio of the surface crystal structure can be measured by, for example, field emission scanning electron microscopy (FE-SEM) and electron backscatter diffraction (EBSD).

[0083] like Figure 2 and Figure 3 As shown in FIG. 1 , an anode electrode (upper surface electrode) 5 is provided on the upper surface side of the drift layer 2 and the anode region 3. Figure 1 The anode electrode 5 is in contact with the upper surface of the drift layer 2 and the anode region 3. The anode electrode 5 is made of a metal such as aluminum (Al), an Al alloy, or molybdenum (Mo). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu), or Al-Si-Cu.

[0084] The anode electrode 5 may also include a barrier metal layer in the portion in contact with the anode region 3. The barrier metal layer may be composed of, for example, titanium nitride (TiN), titanium (Ti), or a TiN / Ti layered structure with Ti as the underlying layer. The metal material of the portion of the anode electrode 5 in contact with the anode region 3 may be, for example, aluminum (Al), an Al alloy, molybdenum (Mo), titanium (Ti), or titanium nitride (TiN).

[0085] The surface layer of the anode region 3 comprises 3C-SiC, so the anode region 3 is in ohmic contact with the anode electrode 5 in a low-resistance manner. Therefore, no silicide layer formed of nickel silicide (NiSi) or the like is provided between the anode electrode 5 and the anode region 3. On the other hand, the drift layer 2 sandwiched between adjacent anode regions 3 forms a Schottky junction with the anode electrode 5.

[0086] The silicon carbide semiconductor device according to the first embodiment has an MPS structure in which a plurality of pn junctions between the anode region 3 and the drift layer 2 and Schottky junctions between the drift layer 2 and the anode electrode 5 are mixed. This reduces the electric field strength at the junction surface between the semiconductor substrate 100 and the anode electrode 5, thereby suppressing reverse leakage current.

[0087] like Figure 2 and Figure 3 As shown, a cathode electrode (back electrode) 6 is provided on the lower surface side of the cathode region 1. The cathode electrode 6 is composed of, for example, a single layer film formed of a metal such as gold (Au), or a laminated film formed by stacking titanium (Ti), nickel (Ni), and gold (Au) in this order. In addition, a silicide layer may be provided between the cathode region 1 and the cathode electrode 6.

[0088] <Method for Manufacturing Silicon Carbide Semiconductor Device>

[0089] Next, we will focus on Figure 2 An example of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described with reference to the corresponding cross sections.

[0090] First, a first conductivity type (n) silicon carbide layer made of SiC such as 4H-SiC and doped with n-type impurities such as nitrogen (N) is prepared. + The SiC substrate of type) is used as the cathode region 1 (refer to Figure 4 ). The upper surface of the cathode region 1 may also have an angle of about 0° to 8° (for example, about 4°). Figure 4 As shown, epitaxial growth of a first conductivity type (n-type) drift layer 2, formed from SiC such as 4H-SiC and doped with n-type impurities such as N, is performed on cathode region 1. If the upper surface of cathode region 1 has an off-angle, the upper surface of drift layer 2 also has the same off-angle. Cathode region 1 and drift layer 2 form semiconductor substrate 100.

[0091] Next, a photoresist film 7 (see Figure 5 . ), the photoresist film 7 is patterned using photolithography technology. The patterned photoresist film 7 is used as a mask for ion implantation, such as Figure 5 As shown in FIG, ions of p-type impurities such as aluminum (Al) are implanted into the upper surface of the drift layer 2, thereby forming a p-type impurity on the upper surface side of the drift layer 2. + Type of anode region 3.

[0092] Figure 6 Show Figure 5 The ion implantation shown is Figure 3 The corresponding cross section. Figure 6 As shown, the p-type impurity ion implantation is performed at an angle θ1 relative to the normal line L1 of the upper surface of the semiconductor substrate 100. The angle θ1 is, for example, greater than or equal to 30° and less than about 90°, or greater than or equal to 45° and less than about 90°, or greater than or equal to 60° and less than about 90°. The greater the angle θ1, the shallower the anode region 3 is formed. Figure 6As shown, by tilting the implantation direction of ions in the longitudinal direction (extension direction) of the planar pattern of the anode region 3 , shadowing (deviation between the mask and the implanted ions) can be prevented.

[0093] The acceleration energy of ion implantation is about 300keV or more and 700keV or less, and can also be about 400keV or more and 700keV or less. Figure 5 and Figure 6 As schematically indicated by "×" in the figure, damage 4 can be generated in the surface layer of the anode region 3, destroying the crystal structure of 4H-SiC and converting it into an amorphous structure. The higher the acceleration energy of the ion implantation, the more likely the damage 4 is to be generated.

[0094] like Figure 7 As shown, considering the semiconductor substrate 100 relative to <0001> The (c-axis) direction has an off-angle θ2 with respect to the <11-20> direction. The off-angle θ2 is the angle between the (0001) plane (silicon (Si) plane) or the (000-1) plane (carbon (C) plane), i.e., the plane perpendicular to the c-axis (basal plane), and the top surface of the semiconductor substrate 100 (shown by the dotted line).

[0095] like Figure 7 As shown, when the ion implantation direction is tilted by a predetermined angle θ1 relative to the normal line L1 of the upper surface of the semiconductor substrate 100 in the direction of the deflection angle θ2 (the deflection direction), the predetermined angle θ1 is set to be smaller than the angle parallel to the deflection direction, that is, smaller than approximately (90° - θ2). This prevents the implantation direction from being parallel to the deflection angle θ2, allowing for uniform ion implantation. For example, when the deflection angle θ2 of the semiconductor substrate 100 is 4°, the implantation angle θ1 can be set to be smaller than approximately 86°.

[0096] On the other hand, Figure 8 As shown, when the ion implantation direction is tilted in a direction different from the deflection angle θ2, the ion implantation can be uniformly performed by setting the predetermined angle θ1 with respect to the normal line L1 of the upper surface of the semiconductor substrate 100 to be less than approximately 90°. Figure 8 In FIG. 5 , the case where the ion implantation direction is tilted in the direction opposite to the off-angle direction is exemplified. In this case, the implantation angle θ1 can be set to be smaller than approximately 90°.

[0097] Next, the ion-implanted p-type impurities are activated by heat treatment (activation annealing) at, for example, 1600° C. to 1900° C. At this time, the amorphous structure of the surface layer of the anode region 3 recrystallizes to form 3C-SiC.

[0098] Next, an anode electrode 5 made of aluminum (Al) or the like is formed on the upper surface side of the drift layer 2 and the anode region 3 by sputtering or vapor deposition. Figure 2 and Figure 3 The drift layer 2 forms a Schottky junction with the anode electrode 5 , and the anode region 3 makes ohmic contact with the anode electrode 5 in a low-resistance manner.

[0099] Next, the semiconductor substrate 100 is ground from the bottom surface side to adjust the thickness of the semiconductor substrate 100 to the product thickness. Next, a cathode electrode 6 made of gold (Au) or the like is formed on the entire bottom surface of the semiconductor substrate 100 by sputtering or vapor deposition (see FIG. Figure 2 and Figure 3 ). Thereafter, the semiconductor substrate 100 is cut (diced) into individual pieces, thereby completing the silicon carbide semiconductor device according to the first embodiment.

[0100] <First Comparative Example>

[0101] Here, a silicon carbide semiconductor device according to a first comparative example is described. Figure 2 The silicon carbide semiconductor device according to the first embodiment shown is different in that Figure 9 As shown in p + A silicide layer 8 made of nickel silicide (NiSi) is provided between the anode region 3 and the anode electrode 5. The depth d2 of the anode region 3 is Figure 2 The silicon carbide semiconductor devices according to the first embodiment shown have the same depth d1 of the anode region 3. The anode region 3 is made of 4H-SiC, and a silicide layer 8 is provided between the anode region 3 and the anode electrode 5 to provide ohmic contact therebetween.

[0102] In the method for manufacturing a silicon carbide semiconductor device according to the first comparative example, during the ion implantation step for forming anode region 3, p-type impurity ions are implanted from the normal direction of the upper surface of semiconductor substrate 100, without tilting relative to the normal to the upper surface of semiconductor substrate 100. The acceleration energy during ion implantation is less than 300 keV, which is lower than the acceleration energy during ion implantation in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Therefore, the surface layer of anode region 3 is not damaged, and anode region 3 remains 4H-SiC. Subsequently, a metal film such as nickel (Ni) is formed on the upper surface of anode region 3 and heat treated to form silicide layer 8.

[0103] In the silicon carbide semiconductor device and its manufacturing method according to the first comparative example, the surface of the silicide layer 8 is prone to unevenness, which may adversely affect reliability due to poor coverage of the barrier metal layer formed on the upper surface of the silicide layer 8. Furthermore, the step of forming the silicide layer 8 is required to establish ohmic contact between the anode region 3 and the anode electrode 5, which increases labor and cost.

[0104] In contrast, in the silicon carbide semiconductor device and its manufacturing method according to the first embodiment, in the ion implantation step for forming the anode region 3, p-type impurity ions are implanted into the upper surface of the drift layer 2 from an inclined direction at a predetermined angle θ1 relative to the normal line L1 to the upper surface of the semiconductor substrate 100. This allows the anode region 3 to be formed shallowly, even at high acceleration energy, and allows damage 4 to be generated in the surface layer of the anode region 3 to form 3C-SiC. This allows low-resistance ohmic contact between the anode region 3 and the anode electrode 5. Consequently, a silicide layer is not formed between the anode region 3 and the anode electrode 5, eliminating concerns about surface irregularities in the silicide layer. This improves reliability and reduces the time and cost of the silicide layer formation step.

[0105] <Second Comparative Example>

[0106] Next, a silicon carbide semiconductor device according to a second comparative example will be described. The silicon carbide semiconductor device according to the second comparative example differs from the silicon carbide semiconductor device according to the first embodiment in that Figure 10 As shown, p + The depth d3 of the anode region 3 is greater than Figure 2 The depth d1 of the anode region 3 is shown as deep. Damage 4 is generated in the surface layer of the anode region 3 due to ion implantation for forming the anode region 3, so that the surface layer of the anode region 3 contains 3C-SiC. Therefore, the anode region 3 and the anode electrode 5 are in ohmic contact with low resistance, and no silicide layer is provided between the anode region 3 and the anode electrode 5.

[0107] In the method for manufacturing a silicon carbide semiconductor device according to the second comparative example, in the ion implantation step for forming the anode region 3, p-type impurity ions are implanted from the normal direction of the upper surface of the semiconductor substrate 100 without tilting relative to the normal to the upper surface of the semiconductor substrate 100. The acceleration energy during the ion implantation is 300 keV or higher, which is comparable to the acceleration energy during the ion implantation in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Therefore, damage 4 is generated in the surface layer of the anode region 3, and 3C-SiC is formed in the surface layer of the anode region 3 after heat treatment.

[0108] However, in the silicon carbide semiconductor device according to the second comparative example, ion implantation is performed at high acceleration from the normal direction of the upper surface of the semiconductor substrate 100. Therefore, the p-type impurities are implanted deep into the surface layer of the anode region 3, and the impurity concentration in the surface layer of the anode region 3 becomes low. For example, there may be an area with an impurity concentration of less than 1×10 18 / cm 3 Therefore, in order to increase the impurity concentration of the surface layer of the anode region 3, it is necessary to perform ion implantation such as multi-stage ion implantation on the surface layer of the anode region 3, which increases the process load and takes time for implantation due to high dose.

[0109] In contrast, in the silicon carbide semiconductor device and its manufacturing method according to the first embodiment, in the ion implantation step for forming the anode region 3, p-type impurity ions are implanted into the upper surface of the drift layer 2 from an inclined direction at a predetermined angle θ1 relative to the normal line L1 to the upper surface of the semiconductor substrate 100. This creates damage 4 on the upper surface side of the anode region 3 and increases the impurity concentration in the surface layer of the anode region 3. Consequently, the process load can be reduced.

[0110] <Simulation Results>

[0111] Figure 11 The following shows the results of Monte Carlo simulation of impurity distribution when phosphorus (P) or aluminum (Al) ion implantation is performed from the normal direction of the upper surface of the wafer and the acceleration energy of the ion implantation is changed to 30keV, 100keV, 200keV, 500keV, 1000keV, 1500keV and 2000keV. Figure 11 The horizontal axis represents the depth from the top surface of the wafer. Figure 11 The vertical axis represents the impurity concentration (damage). Figure 11 As shown in the figure, it can be seen that the higher the acceleration energy, the deeper the damage occurs.

[0112] Figure 12 The ion species is fixed to Al, the wafer angle is fixed to 4°, and the dose is fixed to 1×10 13 cm -2 , Monte Carlo simulation results of impurity distribution when the injection angle relative to the normal direction of the upper surface of the wafer is fixed at 86° and the injection energy is changed to 100keV, 200keV, 300keV, 400keV, 500keV, 600keV and 700keV. Figure 12 The horizontal axis represents the depth from the top surface of the wafer. Figure 12 The vertical axis represents the impurity concentration (damage).

[0113] like Figure 12 As shown, the impurity concentration is 1×10 20 cm -3 The depth of the high-concentration damaged layer from the upper surface of the wafer needs to be at least 0.1 μm. The reason for this is that the portion about 0.1 μm deep from the upper surface of the wafer may disappear due to the subsequent oxidation process. Therefore, the acceleration energy is preferably set so that the acceleration energy becomes 1×10 20 cm -3 Around 400keV or above.

[0114] Figure 13 The ion species is fixed to Al, the wafer angle is fixed to 4°, and the dose is fixed to 1×10 13 cm -2 , Monte Carlo simulation results of impurity distribution when the injection energy is fixed at 300keV and the injection angle relative to the normal direction of the upper surface of the wafer is changed to 0°, 15°, 30°, 45°, 60°, 75°, and 86°. Figure 13 The horizontal axis represents the depth from the top surface of the wafer. Figure 13 The vertical axis represents the impurity concentration (damage).

[0115] like Figure 13 As shown in Figure 1, the peak damage amount is the same when the implantation angle is 0° and 15°. On the other hand, when the implantation angle is increased to 30° or more, the damage amount increases, and the 3C-SiC increases. Therefore, the implantation angle relative to the normal direction of the wafer top surface is preferably 30° or more.

[0116] (Second embodiment)

[0117] Figure 14 Shown from Figure 1 The cross section of the silicon carbide semiconductor device according to the second embodiment when viewed in the AA direction. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that Figure 14 As shown, in a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3, the anode region 3 has a substantially parallelogram cross-sectional shape. Figure 1 In a cross-sectional view along the extending direction of the planar pattern of the anode region 3 when viewed in the BB direction, the anode region 3 has a substantially rectangular cross-sectional shape. The remaining structure of the silicon carbide semiconductor device according to the second embodiment is the same as that of the silicon carbide semiconductor device according to the first embodiment, and therefore, repeated descriptions are omitted.

[0118] In the method for manufacturing a silicon carbide semiconductor device according to the second embodiment, Figure 15 As shown, in a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3, the photoresist film 9 is patterned. The patterned photoresist film 9 is used as an ion implantation mask to implant p-type impurities from a direction inclined at an angle θ3 relative to the normal line L1 to the upper surface of the semiconductor substrate 100, thereby forming the anode region 3. The remaining steps of the method for manufacturing a silicon carbide semiconductor device according to the second embodiment are the same as those of the method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

[0119] According to the silicon carbide semiconductor device and its manufacturing method according to the second embodiment, similar to the first embodiment, p-type impurity ions are implanted into the upper surface of the drift layer 2 from an inclined direction at a predetermined angle θ3 relative to the normal line L1 to the upper surface of the semiconductor substrate 100. This creates damage 4 in the surface layer of the anode region 3, forming 3C-SiC. This allows ohmic contact between the anode region 3 and the anode electrode 5 without requiring a silicide layer. Furthermore, the impurity concentration in the surface layer of the anode region 3 can be increased, thereby reducing the process load.

[0120] (Third embodiment)

[0121] Figure 16 Shown from Figure 1 The cross section of the silicon carbide semiconductor device according to the third embodiment when viewed in the AA direction. The silicon carbide semiconductor device according to the third embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that Figure 16 As shown, in a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3, the anode region 3 has a substantially trapezoidal cross-sectional shape. Figure 1 In a cross-sectional view along the extending direction of the planar pattern of the anode region 3 when viewed in the BB direction, the anode region 3 has a substantially rectangular cross-sectional shape. The remaining structure of the silicon carbide semiconductor device according to the third embodiment is the same as that of the silicon carbide semiconductor device according to the first embodiment, and therefore, repeated descriptions are omitted.

[0122] In the method for manufacturing a silicon carbide semiconductor device according to the third embodiment, ion implantation is performed twice to form the anode region 3. First, in the first ion implantation step, Figure 15The process of the method for manufacturing a silicon carbide semiconductor device according to the second embodiment shown in the figure is similar. In a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3, the photoresist film 9 is patterned. The patterned photoresist film 9 is used as an ion implantation mask to implant p-type impurity ions from a direction inclined at an angle θ3 relative to the normal line L1 to the upper surface of the semiconductor substrate 100. Thereafter, the photoresist film 9 is removed.

[0123] Then, in the second ion implantation process, Figure 17 As shown, in a cross-sectional view taken along a direction perpendicular to the extending direction of the planar pattern of the anode region 3, the photoresist film 10 is patterned, and the patterned photoresist film 10 is used as an ion implantation mask, and the ion implantation mask is formed from the normal line L1 relative to the upper surface of the semiconductor substrate 100 at a direction perpendicular to the extending direction of the planar pattern of the anode region 3. Figure 15 Ion implantation of p-type impurities is performed at an angle θ4, which is the same angle as angle θ3, and is tilted in a direction opposite to angle θ3 shown in FIG. Thereafter, the photoresist film 10 is removed. Furthermore, since the ion implantation for forming the anode region 3 is performed twice, the dose can be changed to a smaller value compared to a case where the ion implantation for forming the anode region 3 is performed once. The remaining steps of the method for manufacturing a silicon carbide semiconductor device according to the third embodiment are the same as those of the method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

[0124] According to the silicon carbide semiconductor device and its manufacturing method according to the third embodiment, similar to the first embodiment, p-type impurity ions are implanted into the upper surface of the drift layer 2 from an inclined direction at predetermined angles θ3 and θ4 relative to the normal line L1 to the upper surface of the semiconductor substrate 100. This creates damage 4 in the surface layer of the anode region 3, forming 3C-SiC. This allows ohmic contact between the anode region 3 and the anode electrode 5 without requiring a silicide layer. Furthermore, the impurity concentration in the surface layer of the anode region 3 can be increased, thereby reducing the process load.

[0125] Furthermore, according to the silicon carbide semiconductor device and the manufacturing method thereof according to the third embodiment, by performing ion implantation twice to form the anode region 3 , the anode region 3 can be formed with a substantially trapezoidal cross-sectional shape, thereby improving bilateral symmetry.

[0126] (Fourth embodiment)

[0127] <Structure of Silicon Carbide Semiconductor Device>

[0128] As the silicon carbide semiconductor device according to the fourth embodiment, a MOSFET is exemplified. Figure 18 As shown, the silicon carbide semiconductor device according to the fourth embodiment includes a first conductivity type (n- The drift layer 12 is a semiconductor layer of a (type) type. The drift layer 12 is composed of an epitaxial growth layer formed of SiC such as 4H-SiC.

[0129] On the upper surface side of the drift layer 12, an n-type layer having an impurity density higher than that of the drift layer 12 is provided. + The current diffusion layer 13 is a current diffusion layer (CSL) 13, which is a semiconductor layer of the n-type semiconductor layer. The current diffusion layer 13 is composed of, for example, an epitaxially grown layer formed of SiC such as 4H-SiC. The current diffusion layer 13 may also be a region formed by ion implantation of n-type impurities on the upper portion of the drift layer 12. Furthermore, the current diffusion layer 13 is not necessarily required; even without the current diffusion layer 13, the drift layer 2 may be provided in the region of the current diffusion layer 13.

[0130] Base regions 17a to 17c, which are semiconductor layers of the second conductivity type (p-type), are provided on the upper surface of current diffusion layer 13. Base regions 17a to 17c are composed of, for example, epitaxially grown layers of SiC such as 4H-SiC. Alternatively, base regions 17a to 17c may be regions formed by ion implantation of p-type impurities into current diffusion layer 13.

[0131] On the upper surface side of the base regions 17a to 17c, an impurity density higher than that of the drift layer 12 is provided as n + The first main electrode regions (source regions) 18a to 18d of the n-type semiconductor layer are formed by ion implantation of n-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As) in a direction inclined relative to the normal to the upper surface of the base regions 17a to 17c.

[0132] The depth of the source regions 18a to 18d is, for example, about 0.1 μm to about 0.5 μm, or about 0.1 μm to about 0.3 μm. The depth of the source regions 18a to 18d may also be about 0.5 μm or more. The impurity concentration in the range of 0.3 μm from the upper surface of the source regions 18a to 18d is, for example, 1×10 18 / cm 3 Above and 1×10 22 / cm 3 Below, if 1×10 19 / cm 3 Above and 1×10 22 / cm 3 The impurity concentration of the upper surface of the source regions 18a to 18d may also be 1×10 20 / cm 3 Above and 1×10 22 / cm 3In the direction perpendicular to the upper surfaces of the source regions 18 a to 18 d , that is, in the depth direction, the impurity concentration may be the same within a depth range of 0.3 μm from the upper surfaces of the source regions 18 a to 18 d .

[0133] In the direction perpendicular to the upper surfaces of the source regions 18a to 18d, that is, in the depth direction, the impurity concentration in the depth range of 0.5 μm or more from the upper surfaces of the source regions 18a to 18d is lower than the impurity concentration in the depth range of 0.3 μm from the upper surfaces of the source regions 18a to 18d. For example, the impurity concentration in the depth range of 0.5 μm or more from the upper surfaces of the source regions 18a to 18d is 1×10 17 / cm 3 Below left and right.

[0134] Source regions 18a-18d are primarily composed of 4H-SiC. During ion implantation to form source regions 18a-18d, damage occurs on at least the upper surface side (surface layer) of source regions 18a-18d, destroying the crystalline structure of 4H-SiC and forming an amorphous structure. 3C-SiC forms when the amorphous structure recrystallizes during subsequent heat treatment (activation annealing). Therefore, the surface layer of source regions 18a-18d contains 3C-SiC.

[0135] The proportion of 3C-SiC contained in the surface layer of the source regions 18a to 18d is, for example, greater than 10% and less than 100%. The surface layer of the source regions 18a to 18d may also be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layer of the source regions 18a to 18d may also contain an amorphous structure, 4H-SiC, etc. By containing 3C-SiC in the surface layer of the source regions 18a to 18d, it is possible to make ohmic contact with the source electrodes (24, 25, 26) on the upper surface side of the source regions 18a to 18d in a low-resistance manner.

[0136] On the upper surface side of the base regions 17a to 17c, a p-type region having an impurity density higher than that of the base regions 17a to 17c is provided so as to contact the source regions 18a to 18d. + Base contact regions 19a to 19c of the p-type semiconductor layer are formed. Base contact regions 19a to 19c have a substantially trapezoidal cross-sectional shape. Base contact regions 19a to 19c are formed by ion implantation of p-type impurities such as aluminum (Al) or boron (B) in a direction oblique to the normal to the upper surfaces of base regions 17a to 17c.

[0137] The depth of the base contact regions 19a to 19c is, for example, about 0.1 μm to about 0.5 μm, or about 0.1 μm to about 0.3 μm. The depth of the base contact regions 19a to 19c can also be about 0.5 μm or more. The impurity concentration in the range from the upper surface of the base contact regions 19a to 19c to a depth of 0.3 μm is, for example, 1×10 18 / cm 3 Above and 1×10 22 / cm 3 Below, if 1×10 19 / cm 3 Above and 1×10 22 / cm 3 The impurity concentration of the upper surface of the base contact regions 19a to 19c may be 1×10 20 / cm 3 Above and 1×10 22 / cm 3 In the direction perpendicular to the upper surfaces of the base contact regions 19 a to 19 c , that is, in the depth direction, the impurity concentration may be the same within a depth range of 0.3 μm from the upper surfaces of the base contact regions 19 a to 19 c .

[0138] In the direction perpendicular to the upper surfaces of the base contact regions 19a to 19c, that is, in the depth direction, the impurity concentration in the depth range of 0.5 μm or more from the upper surfaces of the base contact regions 19a to 19c is lower than the impurity concentration in the depth range of 0.3 μm from the upper surfaces of the base contact regions 19a to 19c. The impurity concentration in the depth range of 0.5 μm or more from the upper surfaces of the base contact regions 19a to 19c is, for example, 1×10 17 / cm 3 Below left and right.

[0139] Base contact regions 19a-19c are primarily composed of 4H-SiC. During ion implantation to form base contact regions 19a-19c, damage occurs in at least the upper surface (surface layer) of base contact regions 19a-19c, destroying the 4H-SiC crystal structure and forming an amorphous structure. During subsequent heat treatment (activation annealing), the amorphous structure recrystallizes to form 3C-SiC. Therefore, the surface layer of base contact regions 19a-19c consists of 3C-SiC.

[0140] The proportion of 3C-SiC contained in the surface layer of the base contact regions 19a to 19c is, for example, greater than 10% and less than 100%. The surface layer of the base contact regions 19a to 19c may also be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layer of the base contact regions 19a to 19c may also contain an amorphous structure, 4H-SiC, etc. By containing 3C-SiC in the surface layer of the base contact regions 19a to 19c, ohmic contact with the source electrodes (24, 25, 26) on the upper surface side of the base contact regions 19a to 19c can be made in a low-resistance manner.

[0141] Trenches 31a and 31b are provided which are dug from the upper surface of the source regions 18a to 18d in the depth direction. The trenches 31a and 31b penetrate the source regions 18a to 18d and the base regions 17a to 17c and reach the current diffusion layer 13. The trenches 31a and 31b may have a Figure 18 The plane pattern may be a stripe-shaped plane pattern extending in the depth direction and the front direction of the paper, or may be a dot-shaped plane pattern.

[0142] Gate insulating films 20a and 20b are provided on the lower surfaces and side surfaces of the trenches 31a and 31b. Gate electrodes 21a and 21b are embedded in the trenches 31a and 31b via the gate insulating films 20a and 20b.

[0143] The gate insulating films 20a and 20b can be made of a single layer of a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a bismuth oxide (Bi2O3) film, or a composite film obtained by laminating a plurality of these. The gate electrodes 21a and 21b can be made of, for example, a polysilicon layer (doped polysilicon layer) to which p-type or n-type impurities are added at a high impurity concentration, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni).

[0144] In order to protect the gate insulating films 20a and 20b at the bottom of the trenches 31a and 31b from being damaged by the high voltage during reverse bias, a p-type gate electrode is provided in contact with the bottom of the trenches 31a and 31b. + Type gate bottom protection areas 14a and 14b.

[0145] On the lower surface side of the base regions 17a to 17c below the base contact regions 19a to 19c, p +The base bottom buried regions (15a, 16a), (15b, 16b), and (15c, 16c) are of the type. The base bottom buried regions (15a, 16a) include a first buried region 15a and a second buried region 16a disposed on the upper surface of the first buried region 15a. The base bottom buried regions (15b, 16b) include a first buried region 15b and a second buried region 16b disposed on the upper surface of the first buried region 15b. The base bottom buried regions (15c, 16c) include a first buried region 15c and a second buried region 16c disposed on the upper surface of the first buried region 15c.

[0146] A first main electrode (source electrode) (24, 25, 26) is provided on the upper surface side of the gate electrodes 21a and 21b via interlayer insulating films 22a and 22b. As the interlayer insulating films 22a and 22b, a silicon oxide film (SiO2 film) containing no impurities, referred to as an "NSG film," a silicon oxide film doped with phosphorus (PSG film), or a silicon oxide film doped with boron (BSG film) can be used. Furthermore, as the interlayer insulating films 22a and 22b, a single layer of a silicon oxide film doped with phosphorus and boron (BPSG film) or a silicon nitride film (Si3N4 film) can be used, or a composite film obtained by combining multiple types thereof can be used.

[0147] The source electrodes (24, 25, 26) are in low-resistance ohmic contact with the source regions 18a-18d and the base contact regions 19a-19c. The source electrodes (24, 25, 26) include a first barrier metal layer 24, a second barrier metal layer 25, and a wiring layer 26. The first barrier metal layer 24 is in contact with the base contact regions 19a-19c and the source regions 18a-18d. The second barrier metal layer 25 is provided to cover the first barrier metal layer 24. The wiring layer 26 is provided to cover the second barrier metal layer 25. For example, the first barrier metal layer 24 is composed of titanium nitride (TiN), the second barrier metal layer 25 is composed of titanium (Ti) / TiN / Ti, and the wiring layer 26 is composed of aluminum (Al). The metal material of the portion of the source electrodes ( 24 , 25 , 26 ) in contact with the base contact regions 19 a - 19 c and the source regions 18 a - 18 d is, for example, aluminum (Al), Al alloy, molybdenum (Mo), titanium (Ti), or titanium nitride (TiN).

[0148] An n-type layer having an impurity concentration higher than that of the drift layer 12 is provided on the lower surface side of the drift layer 12. + The drain region 11 is formed of a substrate (SiC substrate) made of SiC such as 4H-SiC.

[0149] A second main electrode (drain electrode) 27 is disposed on the lower surface side of the drift layer 12 so as to be in contact with the drift layer 12. The drain electrode 27 can be, for example, a single-layer film formed of gold (Au) or a metal film formed by stacking Al, nickel (Ni), and Au in this order. Alternatively, a metal plate such as molybdenum (Mo) or tungsten (W) may be stacked as the bottom layer.

[0150] During operation of the silicon carbide semiconductor device according to the fourth embodiment, when a positive voltage is applied to the drain electrode 27 and a positive voltage greater than the threshold is applied to the gate electrodes 21a and 21b, an inversion layer (channel) forms on the gate electrode 21a and 21b side of the base regions 17a to 17c, thereby achieving an on-state. In the on-state, current flows from the drain electrode 27 to the source electrodes (24, 25, and 26) via the drain region 11, the drift layer 12, the inversion layer of the base regions 17a to 17c, and the source regions 18a to 18d. On the other hand, when the voltage applied to the gate electrodes 21a and 21b is less than the threshold, an inversion layer is not formed in the base regions 17a to 17c, resulting in an off-state, and no current flows from the drain electrode 27 to the source electrodes (24, 25, and 26).

[0151] <Method for Manufacturing Silicon Carbide Semiconductor Device>

[0152] Next, an example of a method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment will be described.

[0153] First, prepare an n-type SiC such as 4H-SiC to which n-type impurities such as nitrogen (N) are added. + The upper surface of the SiC substrate may also have an off-angle of about 4°. The SiC substrate is used as the drain region 11, and Figure 19 As shown in FIG, n is formed of SiC such as 4H-SiC on the upper surface of the drain region 11. - Epitaxial growth of the drift layer 12 of the type.

[0154] Next, n-type impurity ions such as nitrogen (N) are implanted from the upper surface side of the drift layer 12 to the entire surface of the drift layer 12, thereby Figure 20 As shown, n is formed by SiC such as 4H-SiC. + The current diffusion layer 13 is epitaxially grown on the upper surface of the drift layer 12. The current diffusion layer 13 does not necessarily need to be formed, and the following steps may be performed on the drift layer 12.

[0155] Then, through photolithography and ion implantation, such as Figure 21As shown, first buried regions 15a-15c and gate bottom protection regions 14a, 14b are formed inside the current diffusion layer 13. Furthermore, second buried regions 16a-16c are formed on the upper surface side of the first buried regions 15a-15c above the current diffusion layer 13 by photolithography and ion implantation.

[0156] Then, if Figure 22 As shown, epitaxial growth of a p-type base region 17 formed of SiC such as 4H-SiC is performed on the upper surface of the current diffusion layer 13 .

[0157] Then, the process is carried out twice to form n + First, in the first ion implantation step, a photoresist film 41 (see Figure 23 . ), the photoresist film 41 is patterned using a photolithography technique. The patterned photoresist film 41 is used as a mask for ion implantation, and as Figure 23 As shown in FIG. 1 , ion implantation of n-type impurities such as N is performed from a direction inclined at a predetermined angle θ11 relative to the normal line L11 of the upper surface of the base region 17. As a result, n + The source region 18 of the type is formed to have a substantially parallelogram cross-sectional shape. Thereafter, the photoresist film 41 is removed. Alternatively, an oxide film may be used as a mask instead of the photoresist film 41.

[0158] In the first ion implantation, the predetermined angle θ11 is, for example, greater than or equal to 30° and less than or equal to 90°, or may be greater than or equal to 45° and less than or equal to 90°, or may be greater than or equal to 60° and less than or equal to 90°. The acceleration energy of the ion implantation is greater than or equal to 300 keV and less than or equal to 700 keV, or may be greater than or equal to 400 keV and less than or equal to 700 keV. By setting the acceleration energy of the ion implantation to a high acceleration of greater than or equal to 300 keV, damage can be generated in the surface layer of the source region 18, thereby destroying the crystal structure of the 4H-SiC and converting it into an amorphous structure.

[0159] Next, in the second ion implantation step, a photoresist film 42 is applied on the base region 17 (see Figure 24 . ), the photoresist film 42 is patterned using photolithography technology. The patterned photoresist film 42 is used as a mask for ion implantation, such as Figure 24 As shown in FIG. 1 , ion implantation of n-type impurities such as N is performed in a direction tilted at an angle θ12, which is the same as the predetermined angle θ11, from the normal line L11 relative to the upper surface of the base region 17 on the opposite side to that in the first ion implantation step. As a result, the regions implanted with ions in the first and second implantations overlap, and n +The source region 18 of the type is formed to have a substantially trapezoidal cross-sectional shape. Thereafter, the photoresist film 42 is removed. Alternatively, an oxide film may be used as a mask instead of the photoresist film 42.

[0160] In the second ion implantation, the predetermined angle θ12 is, for example, greater than or equal to 30° and less than or equal to 90°, or may be greater than or equal to 45° and less than or equal to 90°, or may be greater than or equal to 60° and less than or equal to 90°. The acceleration energy of the ion implantation is greater than or equal to 300 keV and less than or equal to 700 keV, or may be greater than or equal to 400 keV and less than or equal to 700 keV. By setting the acceleration energy of the ion implantation to a high acceleration of greater than or equal to 300 keV, damage can be generated in the surface layer of the source region 18, thereby destroying the crystal structure of the 4H-SiC and converting it into an amorphous structure.

[0161] Then, the process for forming p + First, in the first ion implantation step, a photoresist film 43 (see FIG. 1 ) is applied on the base region 17. Figure 25 . ) The photoresist film 43 is patterned using photolithography. The patterned photoresist film 43 is used as an ion implantation mask, and ion implantation of p-type impurity ions such as Al is performed from a direction inclined at a predetermined angle θ13 relative to the normal line L11 of the upper surface of the base region 17. As a result, a p-type impurity ion having a substantially parallelogram-shaped cross section is formed on the upper surface side of the base region 17. + The base contact regions 19a to 19c of the type are formed. Thereafter, the photoresist film 43 is removed. Alternatively, an oxide film may be used as a mask instead of the photoresist film 43.

[0162] In the first ion implantation, the predetermined angle θ13 is, for example, greater than or equal to 30° and less than or equal to 90°, but may also be greater than or equal to 45° and less than or equal to 90°, or may be greater than or equal to 60° and less than or equal to 90°. The acceleration energy of the ion implantation is greater than or equal to 300 keV and less than or equal to 700 keV, but may also be greater than or equal to 400 keV and less than or equal to 700 keV. By setting the acceleration energy of the ion implantation to a high acceleration of greater than or equal to 300 keV, damage can be generated in the surface layer of the base contact regions 19 a to 19 c, thereby destroying the crystal structure of the 4H—SiC and converting it into an amorphous structure.

[0163] Next, in the second ion implantation step, a photoresist film 44 is applied on the base region 17 (see Figure 26 . ), the photoresist film 44 is patterned using photolithography technology. The patterned photoresist film 44 is used as a mask for ion implantation, such as Figure 26As shown in FIG. 1 , ion implantation of p-type impurity ions such as Al is performed from the normal line L11 to the upper surface of the base region 17 at an angle θ14 that is the same as the predetermined angle θ13 and is tilted in the opposite direction to the first ion implantation step. As a result, the regions implanted in the first and second ion implantations overlap, and a p-type impurity ion having a substantially trapezoidal cross-sectional shape is formed on the upper surface of the base region 17. + The base contact regions 19a to 19c of the type are formed. Thereafter, the photoresist film 44 is removed. Alternatively, an oxide film may be used as a mask instead of the photoresist film 44.

[0164] In the second ion implantation, the predetermined angle θ14 is, for example, greater than or equal to 30° and less than or equal to 90°, but may also be greater than or equal to 45° and less than or equal to 90°, or may be greater than or equal to 60° and less than or equal to 90°. The acceleration energy of the ion implantation is greater than or equal to 300 keV and less than or equal to 700 keV, but may also be greater than or equal to 400 keV and less than or equal to 700 keV. By setting the acceleration energy of the ion implantation to a high acceleration of greater than or equal to 300 keV, damage can be generated in the surface layer of the base contact regions 19 a to 19 c, thereby destroying the crystal structure of the 4H—SiC and converting it into an amorphous structure.

[0165] Next, the n-type impurity ions and p-type impurity ions implanted by each ion implantation are activated by heat treatment (activation annealing) at, for example, 1600° C. to 1900° C. At this time, the amorphous structure of the surface layer of the source region 18 and the base contact regions 19 a to 19 c recrystallizes to form 3C-SiC.

[0166] Next, a photoresist film 45 is applied on the source region 18 and the base contact regions 19a to 19c (see Figure 27 . ), the photoresist film 45 is patterned using a photolithography technique. The patterned photoresist film 45 is used as an etching mask, and dry etching such as reactive ion etching (RIE) is performed. Figure 27 As shown, trenches 31a and 31b are selectively formed to penetrate the source regions 18a to 18d and the base regions 17a to 17c and reach the current diffusion layer 13. Thereafter, the photoresist film 45 is removed. Alternatively, an oxide film may be used as a mask instead of the photoresist film 45.

[0167] Then, if Figure 28 As shown, by thermal oxidation or CVD, the bottom surface and side surfaces of the trenches 31a and 31b, as well as the source region 18 and the p + A gate insulating film 20 is formed on the upper surface of the base contact regions 19a to 19c. Next, a polysilicon layer (doped polysilicon layer) to which impurities such as N are added at a high concentration is deposited on the gate insulating film 20 by CVD or the like. Then, the polysilicon layer is etched, as shown in FIG. Figure 29 As shown, a polysilicon layer is buried in the trenches 31 a and 31 b via the gate insulating film 20 , thereby forming gate electrodes 21 a and 21 b .

[0168] Next, an interlayer insulating film is deposited on the gate electrodes 21a, 21b and the gate insulating film 20 by CVD or the like. Then, a photoresist film 46 (see FIG. 4 ) is applied on the interlayer insulating film. Figure 30 . ), the photoresist film 46 is patterned using a photolithography technique. The patterned photoresist film 46 is used as an etching mask, such as Figure 30 As shown, the interlayer insulating films 22a and 22b and a portion of the gate insulating film 20 are selectively removed by dry etching to form a contact hole. Thereafter, the photoresist film 46 is removed.

[0169] Then, by sputtering or vapor deposition, Figure 31 The first barrier metal layer 24 and the second barrier metal layer 25 are formed as shown. Next, a sputtering method or a vapor deposition method is used to form Figure 18 The source electrode (24, 25, 26) is formed by the first barrier metal layer 24, the second barrier metal layer 25 and the wiring layer 26. Next, a layer of a metal layer is formed on the entire surface of the lower surface of the drain region 11 by sputtering or evaporation. Figure 18 The drain electrode 27 is shown. In this way, the silicon carbide semiconductor device according to the fourth embodiment is completed.

[0170] Furthermore, in the silicon carbide semiconductor device and the manufacturing method thereof according to the fourth embodiment, ion implantation may be performed in only one of the ion implantation steps for forming the base contact regions 19a to 19c and the ion implantation step for forming the source region 18, with the implantation direction being 30° or more and less than 90° relative to the normal line L11 of the upper surface of the base region 17 and the acceleration energy being 300 keV or more. Figure 18 The base contact regions 19a to 19c and one of the source regions 18a to 18d shown include 3C-SiC to make ohmic contact with the source electrodes (24, 25, 26) in a low-resistance manner.

[0171] In addition, it is also possible to form n +In the case of performing only one of the first and second ion implantation steps, the ion implantation of n-type impurities such as N can be performed from an oblique direction on the entire upper surface of the base region 17 without using the photoresist films 41 and 42. In this case, the source region 18 is formed over the entire upper portion of the base region 17. In addition, since the surface layer of the source region 18 is formed with the p-type impurities, the source region 18 is formed in the upper portion of the base region 17. + The base contact regions 19a to 19c of the type are also damaged, so in the ion implantation process for forming the base contact regions 19a to 19c, ion implantation may be performed from the direction of the normal line L11 of the upper surface of the base region 17 with an acceleration energy less than 300 keV.

[0172] Alternatively, instead of performing the ion implantation process twice to form the base contact regions 19a to 19c, only one of the first and second ion implantation processes may be performed. In this case, the base contact regions 19a to 19c have a substantially parallelogram-shaped cross section.

[0173] According to the silicon carbide semiconductor device and the manufacturing method thereof according to the fourth embodiment, Figure 23 and Figure 24 As shown, in the ion implantation step for forming the source region 18, n-type impurity ions are implanted into the upper surface of the base region 17 from an inclination direction that is tilted at predetermined angles θ11 and θ12 relative to the normal line L11 to the upper surface of the base region 17. This allows the source region 18 to be formed shallowly despite high acceleration energy, and damage can be generated in the surface layer of the source region 18 to form 3C-SiC, thereby enabling low-resistance ohmic contact between the source region 18 and the source electrode (24, 25, 26). Consequently, a silicide layer is not formed between the source region 18 and the source electrode (24, 25, 26), eliminating concerns about surface irregularities in the silicide layer. This improves reliability and reduces the time and cost of the silicide layer formation step. Furthermore, damage can be generated on the upper surface of the source region 18, increasing the impurity concentration in the surface layer of the source region 18, thereby reducing the process load.

[0174] And, as Figure 25 and Figure 26As shown, in the ion implantation step for forming base contact regions 19a-19c, p-type impurity ions are implanted into the upper surface of base region 17 from an inclination direction that is tilted at predetermined angles θ13 and θ14 relative to the normal line L11 to the upper surface of base region 17. This allows shallow formation of base contact regions 19a-19c, even at high acceleration energy, and damage to the surface layer of base contact regions 19a-19c to form 3C-SiC. This allows low-resistance ohmic contact between base contact regions 19a-19c and source electrodes (24, 25, 26). Consequently, a silicide layer is not formed between base contact regions 19a-19c and source electrodes (24, 25, 26), eliminating concerns about surface irregularities in the silicide layer. This improves reliability and reduces the time and cost of forming the silicide layer. Furthermore, damage can be generated on the upper surface side of the base contact regions 19 a to 19 c and the impurity concentration of the surface layer of the base contact regions 19 a to 19 c can be increased, thereby reducing the process load.

[0175] (Fifth embodiment)

[0176] A silicon carbide semiconductor device according to a fifth embodiment and Figure 18 The silicon carbide semiconductor device according to the fourth embodiment shown in FIG. 1 is different in that Figure 32 As shown, the base contact regions 19a to 19c have a substantially parallelogram-shaped cross section. The remaining structure of the silicon carbide semiconductor device according to the fifth embodiment is the same as that of the silicon carbide semiconductor device according to the fourth embodiment, and therefore, repeated description will be omitted.

[0177] The method for manufacturing a silicon carbide semiconductor device according to the fifth embodiment differs from the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment in that the ion implantation for forming the base contact regions 19a to 19c is not divided into two steps, but is performed only once. Figure 25 The first ion implantation step is shown without Figure 26 The second ion implantation process is shown.

[0178] According to the silicon carbide semiconductor device and the manufacturing method thereof according to the fifth embodiment, the same effects as those of the silicon carbide semiconductor device and the manufacturing method thereof according to the fourth embodiment are achieved.

[0179] (Sixth embodiment)

[0180] A silicon carbide semiconductor device according to a sixth embodiment and Figure 18 The silicon carbide semiconductor device according to the fourth embodiment shown in FIG. 1 is different in that Figure 33As shown, the base contact regions 19a to 19c have a substantially rectangular cross-sectional shape. The remaining structure of the silicon carbide semiconductor device according to the sixth embodiment is the same as that of the silicon carbide semiconductor device according to the fourth embodiment, and therefore, repeated description will be omitted.

[0181] The method for manufacturing a silicon carbide semiconductor device according to the sixth embodiment differs from the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment in that, in the two ion implantation steps for forming the base contact regions 19a to 19c, the implantation direction is directed toward Figure 33 Ion implantation is performed in an inclined manner near the front side and the back side.

[0182] According to the silicon carbide semiconductor device and the manufacturing method thereof according to the sixth embodiment, the same effects as those of the silicon carbide semiconductor device and the manufacturing method thereof according to the fourth embodiment are achieved.

[0183] (Other embodiments)

[0184] Although the first to sixth embodiments have been described above, the descriptions and drawings constituting part of this disclosure should not be construed as limiting the present invention. Based on this disclosure, various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art.

[0185] For example, although MOSFET is illustrated in the fourth to sixth embodiments, it can also be applied to IGBT. In the case of IGBT, as long as Figure 18 The MOSFET shown in + The source regions 18a to 18d of the type are set as emitter regions, and p + Type collector region to replace n + The structure of the drain region 11 can be any type. Furthermore, in addition to being applicable to a single IGBT, the present invention can also be applied to a reverse-conducting IGBT (RC-IGBT) or a reverse-blocking insulated-gate bipolar transistor (RB-IGBT). Furthermore, while a MOSFET having a trench gate structure is exemplified, the present invention can also be applied to a MOSFET or IGBT having a planar gate structure.

[0186] Furthermore, the structures disclosed in the first to sixth embodiments can be appropriately combined within the scope of non-inconsistency. As such, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined solely by the inventive features of the claims that are appropriate based on the above description.

[0187] Description of Reference Numerals

[0188] 1: cathode region; 2: drift layer; 3: anode region; 4: damage; 5: anode electrode (top electrode); 6: cathode electrode (back electrode); 7: photoresist film; 8: silicide layer; 9, 10: photoresist film; 11: drain region; 12: drift layer; 13: current diffusion layer; 14a, 14b: gate bottom protection region; 17, 17a-17c: base region; 18, 18a-18d: source region; 1 9a~19c: base contact region; 20a, 20b: gate insulating film; 21a, 21b: gate electrode; 22a, 22b: interlayer insulating film; 24: first barrier metal layer; 25: second barrier metal layer; 26: wiring layer; 27: drain electrode; 31a, 31b: trench; 41~46: photoresist film; 100: semiconductor substrate (semiconductor base); 101: active region; 102: terminal region.

Claims

1. A silicon carbide semiconductor device comprising: a first semiconductor layer formed of 4H-SiC silicon carbide; a second semiconductor layer provided on an upper surface side of the first semiconductor layer, the second semiconductor layer being formed of silicon carbide including 3C-SiC at least on an upper surface; and a main electrode provided on the upper surface side of the second semiconductor layer, in, The impurity concentration in the range from the upper surface of the second semiconductor layer to a depth of 0.3 μm is 1×10 18 / cm 3 above, The impurity concentration within a depth range of 0.5 μm or more from the upper surface of the second semiconductor layer is 1×10 17 / cm 3 the following.

2. The silicon carbide semiconductor device according to claim 1, wherein The impurity concentration on the upper surface of the second semiconductor layer is 1×10 20 / cm 3 above.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The second semiconductor layer has a parallelogram cross-sectional shape.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein The second semiconductor layer has a trapezoidal cross-sectional shape.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein The first semiconductor layer is n-type and forms a Schottky junction together with the main electrode. The second semiconductor layer is p-type and forms a pn junction with the first semiconductor layer.

6. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The second semiconductor layer constitutes a p-type base contact region of the MOSFET.

7. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The second semiconductor layer constitutes an n-type main electrode region of the MOSFET.

8. The silicon carbide semiconductor device according to claim 1 or 2, wherein A portion of the main electrode in contact with the second semiconductor layer is made of any one of titanium, titanium nitride, aluminum, an aluminum alloy, and molybdenum.

9. A method for manufacturing a silicon carbide semiconductor device, comprising the following steps: Implanting impurity ions into an upper surface of a first semiconductor layer formed of 4H-SiC silicon carbide at an angle of not less than 30° and less than 90° with respect to a normal to the upper surface of the first semiconductor layer, thereby forming a second semiconductor layer formed of silicon carbide including 3C-SiC on at least its upper surface on the upper surface side of the first semiconductor layer; and A main electrode is formed on the upper surface side of the second semiconductor layer.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein: The acceleration energy of the ion implantation is greater than 300 keV.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The ion implantation comprises: a first ion implantation, performing ion implantation at a first angle that is tilted by 30° or more and less than 90° relative to a normal line to an upper surface of the first semiconductor layer; and The second ion implantation is performed by implanting ions at a second angle that is the same as the first angle and is tilted on the side opposite to the first angle with respect to the normal to the upper surface of the first semiconductor layer.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: In a case where the ion implantation angle is inclined toward the off-angle direction of the first semiconductor layer, the ion implantation angle is made smaller than an angle parallel to the off-angle direction.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The ion implantation angle is inclined in a direction different from an off-angle direction of the first semiconductor layer.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The second semiconductor layer has a planar shape extending in a stripe shape, The ion implantation angle is inclined toward the extending direction.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The first semiconductor layer is n-type and forms a Schottky junction together with the main electrode. The second semiconductor layer is p-type and forms a pn junction with the first semiconductor layer.

16. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The second semiconductor layer constitutes a p-type base contact region of the MOSFET.

17. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein: The second semiconductor layer constitutes an n-type main electrode region of the MOSFET.

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