Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device occupying a small area. In this semiconductor device, a first transistor is provided so as to have a region located inside a first opening of a spacer. The source electrode and the drain electrode are provided so as to face each other across the first opening in a planar view. A semiconductor layer is provided along a side surface and a bottom surface of the first opening. A gate insulating layer and a gate electrode are provided in this order on the semiconductor layer so as to have a region located inside the first opening. Further, a second transistor having a partial process common to the first transistor may be provided. The second transistor is provided so as to have a region located inside the second opening of the spacer. One of a source electrode and a drain electrode of the second transistor is arranged below the second opening, and the other one of the source electrode and the drain electrode of the second transistor is arranged on the spacer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. Another embodiment of the present invention relates to a transistor and a method for manufacturing the same. Another embodiment of the present invention relates to a display device including a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical field. Examples of technical fields encompassing one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and methods for driving or manufacturing these devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, and refers to a circuit that includes a semiconductor element (transistor, diode, photodiode, etc.), a device that includes such a circuit, etc. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, examples of semiconductor devices include integrated circuits, chips that include integrated circuits, and electronic components that contain chips in packages. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] Semiconductor devices including transistors are widely used in electronic devices. In recent years, the uses of display devices have continued to diversify. For example, display devices are used in portable information terminals, television devices (also called television receivers), digital signage (digital signage), and PIDs (public information displays). Examples of display devices include those including organic EL (electroluminescence) elements or light-emitting diodes (LEDs), those including liquid crystal elements, and electronic paper that uses electrophoretic display.

[0005] In display devices, reducing the area occupied by transistors allows for smaller pixel sizes, thereby improving resolution. Furthermore, reducing the area occupied by transistors allows for higher aperture ratios. Consequently, miniaturized transistors are becoming increasingly popular.

[0006] As devices requiring high-definition display devices, the development of devices for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR) is active.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element. [Prior technical literature] [Patent Document]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention Technical problem to be solved by the invention

[0009] When transistors are miniaturized, shortening their channel length, the saturation of the transistors decreases. For example, when a driver transistor that controls the current flowing through a light-emitting element (also referred to as a light-emitting device) of a pixel included in a display device is miniaturized, shortening its channel length and reducing its saturation, the current flowing through the light-emitting element may become unstable, thereby causing the luminance of the light-emitting element to become unstable. For example, this may cause the current flowing through the light-emitting element to become uneven over time, and when displaying a static image, this may also cause the luminance of the light-emitting element to become uneven over time.

[0010] One object of one embodiment of the present invention is to provide a micro transistor. Another object of one embodiment of the present invention is to provide a transistor with a long channel length. Another object of one embodiment of the present invention is to provide a transistor with a long channel length and a transistor with a short channel length. Another object of one embodiment of the present invention is to provide a high-saturation transistor. Another object of one embodiment of the present invention is to provide a transistor with excellent electrical characteristics. Another object of one embodiment of the present invention is to provide a small semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low wiring resistance. Another object of one embodiment of the present invention is to provide a high-speed driven semiconductor device or display device. Another object of one embodiment of the present invention is to provide an inexpensive semiconductor device or display device. Another object of one embodiment of the present invention is to provide a semiconductor device or display device with low power consumption. Another object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or display device. Another object of one embodiment of the present invention is to provide a high-definition display device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or display device with low manufacturing cost. Another object of one embodiment of the present invention is to provide a novel transistor, semiconductor device, display device, or method for manufacturing them.

[0011] Note that the inclusion of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the above objectives. Objectives other than the above objectives may be extracted from the description of the specification, drawings, and claims. Means of solving technical problems

[0012] One embodiment of the present invention is a semiconductor device comprising a first insulating layer, a second insulating layer on the first insulating layer, and a transistor, wherein the transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer, the second insulating layer comprises an opening reaching the first insulating layer, the first conductive layer and the second conductive layer are arranged on the second insulating layer in a manner opposite to each other with the opening separated therefrom when viewed from a plane, the semiconductor layer is arranged in a manner having a region in contact with the first conductive layer and a region in contact with the second conductive layer and having a region located inside the opening, the third insulating layer is arranged on the semiconductor layer in a manner having a region located inside the opening, and the third conductive layer is arranged on the third insulating layer in a manner having a region located inside the opening.

[0013] In addition, one embodiment of the present invention is a semiconductor device including a first insulating layer and a second insulating layer on the first insulating layer, a first transistor and a second transistor, wherein the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a third insulating layer, the second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer and a third insulating layer, the fourth conductive layer is provided on the first insulating layer, the second insulating layer is provided on the fourth conductive layer, the second insulating layer includes a first opening portion reaching the first insulating layer and a second opening portion reaching the fourth conductive layer, the first conductive layer and the second conductive layer are provided on the second insulating layer in a manner opposing each other with the first opening portion therebetween when viewed from a planar perspective, the fifth conductive layer is provided on the second insulating layer and includes a third opening portion having a region overlapping with the second opening portion, the first semiconductor layer The layer is arranged in a manner having an area in contact with the first conductive layer and an area in contact with the second conductive layer and having an area located inside the first opening, the second semiconductor layer is arranged in a manner having an area in contact with the fourth conductive layer and an area in contact with the fifth conductive layer and having an area located inside the first opening and an area located inside the second opening, the third insulating layer is arranged on the first semiconductor layer and the second semiconductor layer in a manner having an area located inside the first opening, an area located inside the second opening, and an area located inside the third opening, the third conductive layer is arranged on the third insulating layer in a manner having an area located inside the first opening, and the sixth conductive layer is arranged in a manner having an area located inside the second opening and an area opposite to the second semiconductor layer across the third insulating layer from the inside of the third opening.

[0014] In the above embodiment, the length of the channel length of the first transistor along the bottom surface of the first opening may be greater than the length of the channel length of the first transistor along the side surface of the first opening.

[0015] In the above method, the width of the first conductive layer and the width of the second conductive layer may also be greater than the width of the first semiconductor layer.

[0016] In the above method, the second insulating layer may include a first layer, a second layer on the first layer, and a third layer on the second layer. The first semiconductor layer and the second semiconductor layer may also contain metal oxides, and the oxygen content of the second layer may be higher than that of the first layer and the third layer.

[0017] In the above embodiment, the oxygen diffusion coefficients of the first layer and the third layer may be smaller than that of the second layer.

[0018] In the above-mentioned method, the oxygen content may be measured by secondary ion mass spectrometry, X-ray photoelectron spectroscopy, or thermal desorption spectroscopy. In addition, the oxygen diffusion coefficient may be calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

[0019] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first insulating layer; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the first conductive layer; forming a conductive film on the second insulating layer; forming a first opening portion and a second opening portion having a region overlapping with the first conductive layer in the conductive film; forming a third opening portion having a region overlapping with the first opening portion and reaching the first insulating layer and a fourth opening portion having a region overlapping with the second opening portion and reaching the first conductive layer in the second insulating layer; processing the conductive film to form the second conductive layer and the third conductive layer in a manner that they are opposite to each other with the second opening portion therebetween when viewed from a plane, and forming a conductive film including the second opening portion. a fourth conductive layer; forming a first semiconductor layer having a region in contact with the second conductive layer, a region in contact with the third conductive layer, and a region located inside the third opening, and a second semiconductor layer having a region in contact with the first conductive layer, a region in contact with the fourth conductive layer, a region located inside the second opening, and a region located inside the fourth opening, and forming a third insulating layer on the first semiconductor layer and the second semiconductor layer in a manner having a region located inside the second to fourth openings; and forming a fifth conductive layer having a region located inside the third opening, and a sixth conductive layer having a region located inside the second opening and a region located inside the fourth opening on the third insulating layer.

[0020] In the above method, a first layer, a second layer on the first layer, and a third layer on the second layer can be formed as a second insulating layer, a layer containing a metal oxide can be formed as the first semiconductor layer and the second semiconductor layer, and oxygen can be supplied to the second layer after the second layer is formed and before the third layer is formed.

[0021] In the above embodiment, the first layer and the third layer may be formed so that their oxygen diffusion coefficients are smaller than that of the second layer. Effects of the Invention

[0022] According to one embodiment of the present invention, a micro transistor can be provided. Furthermore, according to one embodiment of the present invention, a transistor with a long channel length can be provided. Furthermore, according to one embodiment of the present invention, a transistor with a long channel length and a transistor with a short channel length can be provided. Furthermore, according to one embodiment of the present invention, a transistor with high saturation can be provided. Furthermore, according to one embodiment of the present invention, a transistor with excellent electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a compact semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low wiring resistance can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device or a display device capable of high-speed operation can be provided. Furthermore, according to one embodiment of the present invention, an inexpensive semiconductor device or a display device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device or a display device with low power consumption can be provided. Furthermore, according to one embodiment of the present invention, a transistor, a semiconductor device, or a display device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a high-definition display device can be provided. Furthermore, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a display device with high productivity can be provided. Furthermore, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a display device with low manufacturing cost can be provided. Furthermore, according to one embodiment of the present invention, a novel transistor, a semiconductor device, a display device, or a method for manufacturing them can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A and Figure 1B is a plan view showing a structural example of a semiconductor device. Figure 1C and Figure 1D is a cross-sectional view showing a structural example of a semiconductor device. Figure 2A is a plan view showing a structural example of a semiconductor device. Figure 2B and Figure 2C is a cross-sectional view showing a structural example of a semiconductor device. Figures 3A to 3C is a cross-sectional view showing a structural example of a semiconductor device. Figure 4A and Figure 4B is a cross-sectional view showing a structural example of a semiconductor device. Figure 5A is a plan view showing a structural example of a semiconductor device. Figure 5B and Figure 5C is a cross-sectional view showing a structural example of a semiconductor device. Figure 6A and Figure 6B is a cross-sectional view showing a structural example of a semiconductor device. Figure 7A is a plan view showing a structural example of a semiconductor device. Figure 7B is a cross-sectional view showing a structural example of a semiconductor device. Figure 8A is a plan view showing a structural example of a semiconductor device. Figure 8B is a cross-sectional view showing a structural example of a semiconductor device. Figure 9A and Figure 9B is a plan view showing a structural example of a semiconductor device. Figure 10A and Figure 10B is a plan view showing a structural example of a semiconductor device. Figure 11A and Figure 11B is a plan view showing a structural example of a semiconductor device. Figure 12A and Figure 12B is a plan view showing a structural example of a semiconductor device. Figure 13A and Figure 13B is a plan view showing a structural example of a semiconductor device. Figure 13C is a cross-sectional view showing a structural example of a semiconductor device. Figure 14A and Figure 14B is a plan view showing a structural example of a semiconductor device. Figure 14C is a cross-sectional view showing a structural example of a semiconductor device. Figure 15A and Figure 15B is a plan view showing a structural example of a semiconductor device. Figure 15C is a cross-sectional view showing a structural example of a semiconductor device. Figure 16A and Figure 16B is a plan view showing a structural example of a semiconductor device. Figure 16C is a cross-sectional view showing a structural example of a semiconductor device. Figure 17A is a plan view showing a structural example of a semiconductor device. Figure 17B and Figure 17C is a cross-sectional view showing a structural example of a semiconductor device. Figure 18A is a plan view showing a structural example of a semiconductor device. Figure 18B is a cross-sectional view showing a structural example of a semiconductor device. Figure 19A and Figure 19B is a cross-sectional view showing a structural example of a semiconductor device. Figure 20A is a plan view showing a structural example of a semiconductor device. Figure 20B and Figure 20C is a cross-sectional view showing a structural example of a semiconductor device. Figure 21A is a plan view showing a structural example of a semiconductor device. Figure 21B is a cross-sectional view showing a structural example of a semiconductor device. Figure 22A is a block diagram showing a structural example of a display device. Figure 22B is a plan view showing a structural example of a pixel. Figure 22C and Figure 22D is a circuit diagram showing a structural example of a pixel. Figure 23A and Figure 23B It is a plan view showing a structural example of a display device. Figure 23C is a cross-sectional view showing a structural example of a display device. Figure 24A is a plan view showing a structural example of a semiconductor device. Figure 24B is a cross-sectional view showing a structural example of a semiconductor device. Figure 25A is a block diagram showing a structural example of a display device. Figure 25B is a circuit diagram showing a structural example of a pixel. Figure 26A It is a plan view showing a structural example of a display device. Figure 26B is a cross-sectional view showing a structural example of a display device. Figure 27 is a circuit diagram showing a structural example of a pixel. Figure 28 2 is a timing chart showing an example of a pixel driving method. Figure 29 This is a circuit diagram showing an example of a pixel driving method. Figure 30 This is a circuit diagram showing an example of a pixel driving method. Figure 31 This is a circuit diagram showing an example of a pixel driving method. Figure 32 This is a circuit diagram showing an example of a pixel driving method. Figure 33 This is a circuit diagram showing an example of a pixel driving method. Figure 34 This is a circuit diagram showing an example of a pixel driving method. Figure 35 This is a circuit diagram showing an example of a pixel driving method. Figure 36A and Figure 36B is a plan view showing a structural example of a pixel circuit. Figure 37A and Figure 37B is a plan view showing a structural example of a pixel circuit. Figure 38A and Figure 38B is a plan view showing a structural example of a pixel circuit. Figure 39 is a plan view showing a structural example of a pixel circuit. Figures 40A to 40E is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 41A to 41C is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 42A to 42D is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 43A to 43D is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 44A and Figure 44B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 45A and Figure 45B It is a perspective view showing a structural example of a display device. Figure 46 is a cross-sectional view showing a structural example of a display device. Figure 47 is a cross-sectional view showing a structural example of a display device. Figure 48 is a cross-sectional view showing a structural example of a display device. Figure 49A It is a plan view showing a structural example of a display device. Figure 49B and Figure 49C is a cross-sectional view showing a structural example of a display device. Figure 50A and Figure 50B is a cross-sectional view showing a structural example of a display device. Figure 51 is a cross-sectional view showing a structural example of a display device. Figures 52A to 52D is a diagram showing a configuration example of an electronic device. Figures 53A to 53F is a diagram showing a configuration example of an electronic device. Figures 54A to 54G is a diagram showing a configuration example of an electronic device. Figure 55A and Figure 55B is a cross-sectional view showing the structure of a sample according to the embodiment. Figure 56 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. Figure 57A and Figure 57B is a graph showing Id-Vg characteristics of a transistor according to an embodiment. Figure 58A and Figure 58B is a STEM image according to an embodiment. Figure 59 is a circuit diagram showing the structure of a circuit for evaluating the off-state current of a transistor according to an embodiment. Figure 60 is an Arrhenius diagram showing the evaluation results of the off-state current of the transistor according to the embodiment. Figure 61A and Figure 61B is a graph showing Id-Vg characteristics of a transistor according to an embodiment. Figure 62A and Figure 62B is a graph showing Id-Vd characteristics of a transistor according to an embodiment. Modes for Carrying Out the Invention

[0025] The embodiments will be described in detail with reference to the accompanying drawings. However, those skilled in the art will readily understand that the present invention is not limited to the above description and can be modified in various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0026] Note that in the structures of the invention described below, the same symbols are used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when parts with the same function are represented, the same hatching is sometimes used without adding a special symbol.

[0027] Furthermore, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not necessarily represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0028] Note that in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these numbers do not limit the number of components or the order of the components (for example, the order of steps or the order of stacking). In addition, the ordinal numbers assigned to components in one part of this specification may not be consistent with the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] In addition, depending on the situation or state, the terms "layer" and "film" may be interchanged. For example, a "conductive layer" may be replaced with a "conductive film." Also, an "insulating layer" may be replaced with an "insulating film." Furthermore, a "semiconductor layer" may be replaced with a "semiconductor film."

[0030] A transistor is a type of semiconductor element that can amplify current or voltage, control conduction or non-conduction, etc. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

[0031] The functions of "source" and "drain" are sometimes interchanged when using transistors with different polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as source terminal and drain terminal, source electrode and drain electrode, etc., depending on the situation.

[0032] "Gate" and "back gate" can be used interchangeably. Therefore, in this specification, "gate" and "back gate" can be used interchangeably. Note that the gate and back gate of a transistor can be appropriately referred to as a gate electrode and a back gate electrode, etc., depending on the situation.

[0033] Throughout this specification, "electrically connected" includes connection via "an element having some electrical function." This "element having some electrical function" is not particularly limited as long as it enables transmission and reception of electrical signals between the connected objects. For example, "element having some electrical function" includes switching elements such as transistors, resistors, coils, capacitors, and other components with various functions, in addition to electrodes and wiring.

[0034] In this specification, unless otherwise specified, the term "off-state current" refers to the current flowing between the source and drain when a transistor is in the off state (also called the non-conducting state or the blocked state). Unless otherwise specified, the off-state in an n-channel transistor refers to a state where the voltage between the gate and source is lower than the threshold voltage (in a p-channel transistor, the voltage between the gate and source is higher than the threshold voltage).

[0035] "Voltage" generally refers to the potential difference between a given potential and a reference potential (e.g., ground potential (GND potential) or source potential). Furthermore, "potential" is relative, and the potential supplied to wiring, etc., may vary depending on the reference potential. Therefore, the terms "voltage" and "potential" are sometimes used interchangeably.

[0036] In this specification, "approximately identical planar shapes" means that at least a portion of the edges of each layer in the stack overlap. This includes, for example, the case where the upper and lower layers are processed using the same mask pattern, or a portion of the same mask pattern. However, in practice, there are cases where the edges do not overlap, or where the upper layer is located inside or outside the lower layer. In these cases, the "approximately identical planar shapes" can also be said. When the planar shapes are identical or approximately identical, the ends can also be said to be aligned or approximately aligned.

[0037] In this specification, etc., the top surface shape of a component refers to the outline shape of the component when viewed from a plane. In addition, the plane view refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

[0038] In this specification, etc., a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to the substrate surface or the surface being formed. For example, a region in which the angle formed between the inclined side surface and the substrate surface or the surface being formed (also referred to as the taper angle) is less than 90 degrees is preferably present. Here, the side surface, substrate surface, and surface being formed of a component do not necessarily need to be completely flat; they may be approximately planar with slight curvature or have fine irregularities.

[0039] In this specification, etc., devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. In addition, in this specification, etc., devices manufactured without using a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure. Note that since devices with an MML structure can be manufactured without using a metal mask, the upper limit of the clarity caused by the alignment accuracy of the metal mask can be exceeded. In addition, devices with an MML structure can omit the equipment related to metal mask manufacturing and the metal mask washing process. In addition, devices with an MML structure can reduce manufacturing costs and are therefore suitable for mass production.

[0040] In this specification and other publications, a structure in which light-emitting layers are fabricated separately in light-emitting elements with different emission wavelengths is sometimes referred to as an SBS (Side-by-Side) structure. The SBS structure allows for optimization of materials and structures for each light-emitting element, increasing the freedom of material and structure selection and facilitating improvements in brightness and reliability.

[0041] In this specification, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes referred to as a "carrier injection layer," a hole transport layer or electron transport layer is sometimes referred to as a "carrier transport layer," and a hole blocking layer or electron blocking layer is sometimes referred to as a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not be clearly distinguished based on their cross-sectional shape or characteristics. Furthermore, a single layer may sometimes perform the functions of two or all three of these layers.

[0042] In this specification, etc., a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as layers included in the EL layer (also referred to as functional layers), a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer) and a carrier blocking layer (hole blocking layer and electron blocking layer) can be cited. In this specification, etc., a light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, etc., one of a pair of electrodes is sometimes referred to as a pixel electrode, and the other as a common electrode.

[0043] In this specification, etc., a sacrificial layer (also referred to as a mask layer) is located at least above the light-emitting layer (more specifically, a layer processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0044] In this specification, "island-shaped" refers to a state in which two or more layers formed of the same material in the same process are physically separated. For example, an island-shaped light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0045] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of a formed surface (for example, a step, etc.).

[0046] (Implementation Method 1) This embodiment describes a structural example of a semiconductor device according to one embodiment of the present invention, particularly a structure including a transistor.

[0047] In a semiconductor device according to one embodiment of the present invention, an insulating layer serving as a spacer is provided on a base insulating layer. The spacer includes a first opening that reaches the base insulating layer. A first transistor is provided so as to have a region located within the first opening. Note that in the following description, the insulating layer serving as a spacer may sometimes be simply referred to as a spacer; however, the spacer may also be referred to as an insulating layer.

[0048] A source electrode (first source electrode) and a drain electrode (first drain electrode) of the first transistor are provided on the spacer. The first source electrode and the first drain electrode are provided so as to face each other with the first opening interposed therebetween when viewed from above.

[0049] The first semiconductor layer is provided in such a manner as to have an area located inside the first opening. A channel formation area in the first transistor is provided in the first semiconductor layer. The first semiconductor layer can be provided along the bottom surface and side surfaces of the first opening. In addition, the first semiconductor layer can have, for example, an area in contact with the top surface of the first source electrode, an area in contact with the side surfaces of the first source electrode, an area in contact with the top surface of the first drain electrode, and an area in contact with the side surfaces of the first drain electrode. The gate insulating layer and the gate electrode (first gate electrode) of the first transistor are sequentially provided on the first semiconductor layer in such a manner as to have an area located inside the first opening. The first gate electrode is provided in such a manner as to have an area overlapping with the first semiconductor layer via the gate insulating layer inside the first opening. In addition, the first gate electrode is provided in such a manner as to have an area opposite to the first semiconductor layer via the gate insulating layer inside the first opening.

[0050] In this specification, when B includes an opening that reaches A, the top surface of A exposed by the opening is referred to as the "bottom surface of the opening." Furthermore, the side surfaces of B exposed by the opening are referred to as the "side surfaces of the opening."

[0051] Thus, in the first transistor, in addition to the direction along the bottom surface of the first opening, the direction along the side surface of the first opening can also be regarded as the channel length in the first semiconductor layer. Thus, compared with the case where the first opening is not provided and a planar transistor is used, for example, the channel length of the first transistor can be increased without increasing the occupied area of the first transistor, specifically, without increasing the occupied area of the first semiconductor layer. Thus, a miniature transistor with high saturation can be realized. Therefore, when, for example, a semiconductor device according to one embodiment of the present invention is used in a display device including a light-emitting element, the saturation of the driving transistor that controls the current flowing through the light-emitting element can be improved while miniaturizing the pixels. Thus, the current flowing through the light-emitting element can be stabilized and the luminance of the light-emitting element can be stabilized. For example, the temporal unevenness of the current flowing through the light-emitting element when a static image is displayed on the display device can be suppressed, and the temporal unevenness of the luminance of the light-emitting element can be suppressed. Thus, by using a semiconductor device according to one embodiment of the present invention in a display device, a high-definition and high-reliability display device can be realized.

[0052] In this specification and other documents, a case where the current change in the saturation region of the Id-Vd characteristic of a transistor is small (the gradient is small) is referred to as "high saturation".

[0053] Here, in addition to the first transistor, a second transistor having a structure different from that of the first transistor may be provided on the base insulating layer. The first transistor and the second transistor may be formed by sharing some of the steps.

[0054] When the semiconductor device of one embodiment of the present invention includes a second transistor, a first conductive layer serving as one of a source electrode (second source electrode) and a drain electrode (second drain electrode) of the second transistor is provided over the base insulating layer.

[0055] The spacer is disposed on the first conductive layer. The spacer includes a second opening that reaches the first conductive layer. The second opening can be formed using the same process as the first opening. The second transistor is disposed so as to have a region located within the second opening.

[0056] A second conductive layer, serving as the other of the second source electrode and the second drain electrode, is provided on the spacer. The second conductive layer includes a third opening having a region overlapping the second opening. The second conductive layer can be formed using the same material and the same process as the first source electrode and the first drain electrode. For example, the first source electrode, the first drain electrode, and the second conductive layer can be formed by processing the same conductive film.

[0057] A second semiconductor layer is provided so as to include a region located within the second opening and a region located within the third opening. A channel formation region for the second transistor is provided in the second semiconductor layer. The second semiconductor layer may be provided along the side surfaces of the second opening and the side surfaces of the third opening. Furthermore, the second semiconductor layer may, for example, include a region in contact with the top surface of the first conductive layer, the side surfaces of the second conductive layer, and the top surface of the second conductive layer. The second semiconductor layer may be formed using the same material as the first semiconductor layer and using the same process as the first semiconductor layer. For example, the first and second semiconductor layers may be formed by processing the same semiconductor film.

[0058] The gate insulating layer and the gate electrode (second gate electrode) of the second transistor are sequentially arranged on the second semiconductor layer in a manner having an area located inside the second opening. The second gate electrode is arranged in a manner having an area opposite to the second semiconductor layer across the gate insulating layer inside the second opening. Here, the gate insulating layer of the second transistor and the gate insulating layer of the first transistor can be shared. In addition, the second gate electrode can be formed using the same material as the first gate electrode through the same process as the first gate electrode. For example, the first gate electrode and the second gate electrode can be formed by processing the same conductive film.

[0059] In the second transistor, the direction along the side of the second opening of the spacer is the channel length, but the direction parallel to the top surface of the base insulating layer is not the channel length. Therefore, the channel length of the second transistor is shorter than the channel length of the first transistor. As a result, the on-state current of the second transistor can be larger than that of the first transistor. Therefore, by using the second transistor as a selection transistor provided in the above-mentioned pixel, for example, having the function of selecting a pixel for writing image data, a display device of one embodiment of the present invention can be driven at high speed.

[0060] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0061] Thus, in a semiconductor device according to one embodiment of the present invention, some processes can be shared, for example, to form multiple transistors with different electrical characteristics. This makes it easier to realize, for example, a circuit with desired performance while reducing manufacturing costs. This makes it possible to realize an inexpensive, high-performance semiconductor device. For example, when a semiconductor device according to one embodiment of the present invention is used in a display device, an inexpensive, high-definition, highly reliable, and high-speed display device can be realized.

[0062] <Structural Example 1 of Semiconductor Device> Figure 1A 1 is a plan view showing a structural example of a portion of a semiconductor device 10 according to one embodiment of the present invention. Figure 1A In the diagram, a portion of the components of the semiconductor device 10 is omitted, for example, a portion of the insulating layer is omitted. Figure 1A Similarly, some components are omitted in the following drawings. Figure 1B It is from Figure 1A A plan view with some components omitted.

[0063] Figure 1C It is along Figure 1A A cross-sectional view of the section taken along the dot-dash line A1-A2. Figure 1D It is along Figure 1A A cross-sectional view of the section taken along the dot-dash line B1-B2.

[0064] In the semiconductor device 10, an insulating layer 101 is provided on a substrate 102, and an insulating layer 110 and a transistor 100 are provided on the insulating layer 101. The insulating layer 101 serves as a base insulating layer. The insulating layer 110 serves as a spacer. Furthermore, at least one of an electrode, wiring, a transistor, a capacitor, and a resistor may be provided between the substrate 102 and the insulating layer 101. For example, a base insulating layer may be provided on the substrate 102, a layer provided with wiring (also referred to as a wiring layer) may be provided on the base insulating layer, and the insulating layer 101 may be provided on the wiring layer.

[0065] The transistor 100 includes a conductive layer 104, a conductive layer 112a, a conductive layer 112b, an insulating layer 106, and a semiconductor layer 108. In the transistor 100, the conductive layer 104 serves as a gate electrode, and a portion of the insulating layer 106 serves as a gate insulating layer. The conductive layer 112a serves as one of a source electrode and a drain electrode, and the conductive layer 112b serves as the other of the source electrode and the drain electrode. The layers constituting the transistor 100 may have a single-layer structure or a stacked-layer structure.

[0066] The insulating layer 110 includes an opening 141 that reaches the insulating layer 101. The transistor 100 is provided so as to have a region located inside the opening 141.

[0067] Conductive layer 112a and conductive layer 112b are provided on insulating layer 110. In other words, each transistor 100 has two conductive layers 112 provided on insulating layer 110. In the following description, conductive layers with alphabetical letters appended to symbol "112" are collectively referred to as conductive layers 112.

[0068] Partial ends of the conductive layers 112a and 112b are preferably aligned with the end of the insulating layer 110 on the side of the opening 141. The conductive layers 112a and 112b can be made of the same material. Furthermore, the conductive layers 112a and 112b can be formed using the same process. For example, the conductive layers 112a and 112b can be formed by forming a conductive film to be the conductive layers 112a and 112b and processing the conductive film.

[0069] Figure 1B It is from Figure 1A The conductive layer 104 is omitted. Figure 1B As shown, the conductive layer 112 a and the conductive layer 112 b are provided so as to face each other with the opening 141 therebetween when viewed from a plan view.

[0070] The semiconductor layer 108 includes a region located within the opening 141. The semiconductor layer 108 may be provided along the bottom and side surfaces of the opening 141. Furthermore, the semiconductor layer 108 may include, for example, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surfaces of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surfaces of the conductive layer 112b. Furthermore, the semiconductor layer 108 may include a region in contact with the top surface of the insulating layer 101 and a region in contact with the side surfaces of the insulating layer 110.

[0071] The region of the semiconductor layer 108 in contact with the conductive layer 112a serves as one of the source region and the drain region, and the region in contact with the conductive layer 112b serves as the other. In the semiconductor layer 108, a channel formation region is provided between the source region and the drain region.

[0072] The insulating layer 106 is provided so as to have a region located inside the opening 141, specifically, so as to cover the opening 141. The insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the insulating layer 101. The insulating layer 106 has a shape along the top surface and side surfaces of the semiconductor layer 108, the top surfaces of the conductive layers 112a and 112b, the top surface and side surfaces of the insulating layer 110, and the top surface of the insulating layer 101. The insulating layer 106 may have a region in contact with the top surface of the semiconductor layer 108, a region in contact with the side surfaces of the semiconductor layer 108, a region in contact with the top surface of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, a region in contact with the top surface of the insulating layer 110, a region in contact with the side surfaces of the insulating layer 110, and a region in contact with the top surface of the insulating layer 101. In addition, although Figure 1C and Figure 1D Although not shown in the drawings, the insulating layer 106 may have a shape along the side surfaces of the conductive layer 112a and the conductive layer 112b and may have a region in contact with the side surfaces of the conductive layer 112a and a region in contact with the side surfaces of the conductive layer 112b.

[0073] Conductive layer 104 is provided on insulating layer 106 so as to have a region located inside opening 141. Conductive layer 104 is provided so as to have a region overlapping with semiconductor layer 108 via insulating layer 106 inside opening 141. Furthermore, conductive layer 104 is provided so as to have a region facing semiconductor layer 108 via insulating layer 106 inside opening 141. Conductive layer 104 can have a shape that follows insulating layer 106, specifically, a shape that follows the top surface of insulating layer 106 and the side surfaces of insulating layer 106 inside opening 141. Furthermore, conductive layer 104 can have a region in contact with the top surface of insulating layer 106 and a region in contact with the side surfaces of insulating layer 106 inside opening 141.

[0074] An insulating layer 109 is provided so as to cover the transistor 100. The insulating layer 109 is provided over the conductive layer 104 and the insulating layer 106. The insulating layer 109 serves as a protective layer for the transistor 100. Note that although Figure 1C and Figure 1D Although the insulating layer 109 is not planarized in the example shown, the insulating layer 109 may be planarized. Alternatively, the insulating layer 109 may have a stacked-layer structure of an insulating layer that is not planarized and an insulating layer that is planarized over the insulating layer.

[0075] Figure 2A 、 Figure 2B and Figure 2C They are Figure 1B 、 Figure 1C and Figure 1D See the enlarged view of Figure 2A 、 Figure 2B and Figure 2C The channel length, channel width, etc. of the transistor 100 will be described.

[0076] exist Figure 2A 、 Figure 2B and Figure 2C , the channel length of the transistor 100 is set to length L100, the channel width is set to width W100, the width of the opening 141 is set to width D141, the thickness of the insulating layer 110 is set to thickness T110_1, the angle formed by the side surface of the insulating layer 110 in the opening 141 and the top surface of the insulating layer 101 is set to angle θ110, the width of the conductive layer 112a is set to width W112a, and the width of the conductive layer 112b is set to width W112b. In addition, Figure 2A 、 Figure 2B and Figure 2C In FIG. 1 , the length L100, the width W100, the width D141, the thickness T110_1, the width W112a and the width W112b are indicated by double arrows. The same is also indicated in the following figures. Figure 2B As shown, thickness T110_1 may be the shortest distance between the formed surface of insulating layer 110 (here, the top surface of insulating layer 101 ) and the bottom surface of conductive layer 112 a or conductive layer 112 b in cross-sectional view.

[0077] In this specification, the width of a conductive layer used as a source electrode or a drain electrode is the length of the conductive layer in a direction parallel to the channel width. Therefore, width W112a and width W112b are in a direction parallel to width W100.

[0078] exist Figure 2B , a region 108i, a region 108na, and a region 108nb are shown as regions of the semiconductor layer 108. The region 108i is provided between the region 108na and the region 108nb.

[0079] At least a portion of the region 108i is used as a channel formation region of the transistor 100. The region 108na is a region in the semiconductor layer 108 that is in contact with the conductive layer 112a and a region in the vicinity thereof. At least a portion of the region 108na is used as one of the source region and the drain region of the transistor 100. The region 108nb is a region in the semiconductor layer 108 that is in contact with the conductive layer 112b and a region in the vicinity thereof. At least a portion of the region 108nb is used as the other of the source region and the drain region of the transistor 100. At least a portion of the region 108na and the region 108nb may be a region whose resistance is lower than that of at least a portion of the region 108i (hereinafter also referred to as a low resistance region). For example, at least a portion of the region 108na and the region 108nb may be a region whose carrier concentration or oxygen vacancy density is higher than that of at least a portion of the region 108i. Although Figure 2B An example is shown in which the height of the boundary between region 108i and region 108na is consistent or approximately consistent with the height of the boundary between the insulating layer 110 and the conductive layer 112a, and the height of the boundary between region 108i and region 108nb is consistent or approximately consistent with the height of the boundary between the insulating layer 110 and the conductive layer 112b, but the above heights may also be inconsistent or approximately consistent.

[0080] In this specification, etc., "high consistency or approximately consistency" means that the height from a reference plane (for example, a flat surface such as a substrate surface) is equal when viewed in section. For example, in the manufacturing process of a semiconductor device, a flattening process is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface after the flattening process from the reference plane is equal. However, depending on the processing device, processing method or material of the processed surface used during the flattening process, the heights of the multiple layers of the processed surface are sometimes not completely equal. In this specification, etc., this situation is also regarded as "high consistency or approximately consistency". For example, the following situation is also referred to as "high consistency or approximately consistency": comprising two layers (here, the first layer and the second layer) with different heights from the reference plane, wherein the difference between the top surface height of the first layer and the top surface height of the second layer is 20nm or less.

[0081] The channel length L100 of transistor 100 corresponds to the sum of twice the length of the side surface of insulating layer 110 in opening 141 when viewed in cross section and the width D141 of opening 141. The length of the side surface of insulating layer 110 in opening 141 when viewed in cross section can be determined using thickness T110_1 and angle θ110. Here, the height of opening 141 can be thickness T110_1. Alternatively, width D141 can be the length of the bottom surface of opening 141 in a direction parallel to the channel length of transistor 100 along the bottom surface of opening 141, and can be, for example, the maximum value of this length.

[0082] Thus, in transistor 100, in addition to the direction along the bottom surface of opening 141 (also called the lateral direction) in semiconductor layer 108, the channel length can also be considered along the side surfaces of opening 141 (also called the longitudinal direction). This allows the channel length of transistor 100 to be increased without increasing the area occupied by transistor 100, specifically, the area occupied by semiconductor layer 108, compared to a planar transistor without opening 141. This allows for a miniaturized transistor with high saturation performance. Therefore, when semiconductor device 10 is used in a display device including a light-emitting element, for example, the saturation performance of the driver transistor that controls the current flowing through the light-emitting element can be improved while miniaturizing the pixels. This stabilizes the current flowing through the light-emitting element and the luminance of the light-emitting element. For example, temporal variations in the current flowing through the light-emitting element when displaying a static image on the display device can be suppressed, and temporal variations in the luminance of the light-emitting element can be suppressed. Thus, using semiconductor device 10 in a display device can achieve a high-definition, high-reliability display device. Note that the transistor 100 has a structure in which current flows both vertically and laterally, and therefore can be called a VLFET (Vertical Lateral Field Effect Transistor).

[0083] As described above, the channel length L100 of transistor 100 has a component along the bottom surface of opening 141 and a component along the side surfaces of opening 141. Here, when the component along the bottom surface of opening 141 is longer than the component along the side surfaces of opening 141, the contribution of the component along the bottom surface of opening 141 to length L100 can be greater than the contribution of the component along the side surfaces of opening 141 to length L100. When multiple transistors 100 are provided in semiconductor device 10, for example, the width D141 of opening 141 can vary from transistor to transistor 100. On the other hand, the thickness T110_1, which can be the height of opening 141, can be equal or substantially equal among multiple transistors 100. Therefore, by increasing the contribution of the component along the bottom surface of opening 141 to length L100, it is easier to control length L100 among multiple transistors 100, specifically, to make length L100 more variable. This makes it easy to manufacture, for example, multiple transistors 100 each having different electrical characteristics in a circuit included in the semiconductor device 10. This makes it easy to implement a circuit having desired performance, for example. This makes it possible to implement a high-performance semiconductor device.

[0084] For example, the length of the component of the channel length of the transistor 100 along the bottom surface of the opening 141 is preferably greater than the length of the component of the channel length of the transistor 100 along the side surface of the opening 141. Alternatively, the length L108 of the semiconductor layer 108 in a direction parallel to the component of the channel length of the transistor 100 along the bottom surface of the opening 141, when viewed from a planar perspective, is preferably greater than or equal to the thickness T110_1. Alternatively, the width D141 is preferably greater than or equal to the thickness T110_1.

[0085] The thickness T110_1 can be, for example, greater than 0.1 nm and less than 3 μm, greater than 0.1 nm and less than 2.5 μm, greater than 1 nm and less than 2 μm, greater than 1 nm and less than 1.5 μm, greater than 5 nm and less than 1.2 μm, greater than 5 nm and less than 1 μm, greater than 7 nm and less than 500 nm, greater than 7 nm and less than 300 nm, greater than 10 nm and less than 200 nm, greater than 10 nm and less than 100 nm, or greater than 10 nm and less than 50 nm.

[0086] When the opening 141 is formed by photolithography, the width D141 of the opening 141 is greater than or equal to the limiting resolution of the exposure apparatus. For example, the width D141 may be 200 nm or greater and less than 5 μm, 200 nm or greater and 4.5 μm or less, 200 nm or greater and 4 μm or less, 300 nm or greater and 3.5 μm or less, 300 nm or greater and 3 μm or less, 400 nm or greater and 2.5 μm or less, 400 nm or greater and 2 μm or less, 500 nm or greater and 1.5 μm or less, or 500 nm or greater and 1 μm or less.

[0087] Figure 1A 、 Figure 1B and Figure 2A The example in which the planar shape of the opening 141 is circular is shown. In this case, the width D141 may be equivalent to the diameter of the circle. In this specification, etc., the circular shape is not limited to a perfect circle.

[0088] The planar shape of the opening 141 is not limited and may be, for example, a polygon such as a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, or any of these polygons with rounded corners. The polygon may also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0089] In this specification, etc., the planar shape of an opening in an insulating layer refers to the shape of the top or bottom end of the insulating layer on the side of the opening. For example, the planar shape of opening 141 refers to the shape of the top or bottom end of insulating layer 110 on the side of opening 141.

[0090] The side surface of the insulating layer 110 in the opening 141 preferably has a vertical shape, for example, preferably perpendicular to the insulating layer 101. That is, the angle θ110 is preferably greater than 80° and less than 100°, more preferably greater than 85° and less than 95°. Thus, a micro transistor can be realized as the transistor 100. Therefore, the occupied area of the circuit provided in the semiconductor device 10 can be reduced, so that the semiconductor device 10 can be a small semiconductor device. Note that the side surface of the insulating layer 110 in the opening 141 can also have a tapered shape. For example, the angle θ110 can also be less than 90° or less than 80°. In this case, the coverage of the layer (for example, the semiconductor layer 108) formed on the insulating layer 110 can be improved. In addition, the smaller the angle θ110, the larger the length L100 can be, and the larger the angle θ110, the smaller the length L100 can be.

[0091] Note that in Figure 2B and Figure 2C In the embodiment of the present invention, the side surface of the insulating layer 110 in the opening 141 is a straight line when viewed in cross section. However, one embodiment of the present invention is not limited to this. When viewed in cross section, the side surface of the insulating layer 110 in the opening 141 may be curved, or may have both straight and curved areas.

[0092] The width W100 of the channel width of the transistor 100 corresponds to the length of the semiconductor layer 108 in a direction perpendicular to the component of the length L100 along the bottom surface of the opening 141. Note that in this specification and other documents, the length of the semiconductor layer 108 in a direction perpendicular to the component of the length L100 along the bottom surface of the opening 141 is referred to as the width of the semiconductor layer 108. In other words, the width W100 may be the width of the semiconductor layer 108.

[0093] Here, widths W112a and W112b of conductive layer 112a and 112b are preferably larger than width W100. This reduces wiring resistance of conductive layers 112a and 112b, allowing for high-speed operation of semiconductor device 10. Note that widths W112a and W112b may be smaller than width W100.

[0094] Furthermore, the width D141 of the opening 141 is preferably greater than the width W112a and the width W112b , thereby preventing the conductive layer 112a and the conductive layer 112b from contacting and causing an electrical short circuit.

[0095] Next, the detailed structure of the transistor 100 will be described.

[0096] There are no particular limitations on the semiconductor material used for the semiconductor layer 108. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. In addition, examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). Note that these semiconductor materials may also contain impurities as dopants.

[0097] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108. An amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a partially crystalline region) can be used. Using a single crystal semiconductor or a crystalline semiconductor is preferred because it suppresses degradation of the characteristics of the transistor 100.

[0098] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS). Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field-effect mobility and can operate at high speed. In addition, transistors using microcrystalline silicon in the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0099] In this specification and the like, a transistor using silicon in a channel formation region is referred to as a Si transistor.

[0100] The semiconductor layer 108 preferably includes a metal oxide exhibiting semiconductor characteristics (also referred to as an oxide semiconductor).

[0101] The band gap of the metal oxide used for the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0102] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have significantly higher field-effect mobility. Furthermore, OS transistors have extremely low off-state current, allowing them to retain charge stored in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of OS transistors can reduce power consumption in semiconductor devices.

[0103] The insulating layer 110 preferably includes one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and oxynitrides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of oxynitrides include silicon oxynitride and aluminum oxynitride. In particular, using silicon nitride for the insulating layer 110 allows the insulating layer 110 to be a layer that is less susceptible to impurities, thereby suppressing the incorporation of impurities into the channel formation region of the transistor 100. Consequently, the transistor 100 can exhibit excellent electrical characteristics and high reliability. Similarly, when silicon nitride is also used for the insulating layer 101 , incorporation of impurities into the channel formation region of the transistor 100 can be more effectively suppressed.

[0104] In this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, while "oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0105] In the transistor 100, regions of the semiconductor layer 108 in contact with the insulating layer 101 and regions in contact with the insulating layer 110 serve as channel formation regions. When a metal oxide is used for the semiconductor layer 108, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 101 and between the semiconductor layer 108 and the insulating layer 110, at least a portion of the region of the insulating layer 101 in contact with the semiconductor layer 108 and at least a portion of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contain oxygen. Specifically, the region of the insulating layer 101 in contact with the channel formation region of the semiconductor layer 108 and the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contain oxygen. The region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 can be made of one or more of an oxide and an oxynitride, as appropriate.

[0106] Furthermore, at least a portion of the region of the insulating layer 101 in contact with the semiconductor layer 108 preferably has a function of capturing or fixing (also referred to as gettering) hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 108. As a result, the oxygen vacancies (V O ) and V OH can realize i-type or substantially i-type formation of the channel formation region. As a result, the transistor 100 can exhibit good electrical characteristics and high reliability.

[0107] Examples of insulating layers capable of capturing or fixing hydrogen include metal oxides with an amorphous structure. For example, magnesium oxide or metal oxides containing one or both of aluminum and hafnium are preferably used. These amorphous metal oxides sometimes have the property of having dangling bonds in their oxygen atoms, which can capture or fix hydrogen. In other words, metal oxides with an amorphous structure have a high ability to capture or fix hydrogen.

[0108] Figure 3A and Figure 3B yes Figure 2B and Figure 2C The structure of the modified example shown in FIG, wherein the insulating layer 110 has a two-layer stacked structure of an insulating layer 110b and an insulating layer 110c on the insulating layer 110b. Note that the planar structure example can be referred to Figure 1A and Figure 2A .exist Figure 3A In the illustrated structural example, the insulating layer 110b may have a region in contact with the side surface of the semiconductor layer 108 and a region in contact with the top surface of the insulating layer 101. In addition, the insulating layer 110c may have a region in contact with the side surface of the semiconductor layer 108, a region in contact with the bottom surface of the conductive layer 112a, a region in contact with the bottom surface of the conductive layer 112b, and a region in contact with the bottom surface of the insulating layer 106.

[0109] The insulating layer 110b preferably contains oxygen. For example, the oxygen content of the insulating layer 110b is preferably greater than the oxygen content of the insulating layer 110c. For example, the oxygen content per unit volume of the insulating layer 110b is preferably greater than the oxygen content per unit volume of the insulating layer 110c. Furthermore, the insulating layer 110b preferably uses one or more of the aforementioned oxides and oxynitrides. Specifically, the insulating layer 110b can be made of either or both silicon oxide and silicon oxynitride, as appropriate. Thus, at least the region of the semiconductor layer 108 in contact with the insulating layer 110b can be used as a channel formation region for the transistor 100.

[0110] For example, the content of elements such as oxygen can be measured using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When the content of the target element is high (for example, 0.5 atomic% or more or 1 atomic% or more), it is preferred to use XPS for analysis. On the other hand, when the content of the target element is low (for example, 0.5 atomic% or less or 1 atomic% or less), it is preferred to use SIMS for analysis. When comparing the content of elements, it is more preferred to use a composite analysis using both SIMS and XPS analysis techniques. In addition, by measuring the amount of desorption of the above elements using thermal desorption spectroscopy (TDS), the content of the above elements in two layers can be compared, for example. Note that SIMS, XPS, TDS, etc. can also be used to measure the content of elements other than oxygen.

[0111] The insulating layer 110b is preferably a film that releases oxygen by heating. Oxygen is released from the insulating layer 110b by heat applied during the manufacturing process of the transistor 100, and thus oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V O ), which can reduce oxygen vacancies (V O ). Therefore, the transistor 100 can be a transistor having good electrical characteristics and high reliability.

[0112] For example, oxygen can be supplied to the insulating layer 110 b by performing heat treatment or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming an oxide film on the top surface of the insulating layer 110 b by sputtering in an oxygen-containing atmosphere. This oxide film can then be removed.

[0113] The insulating layer 110b is preferably formed using a deposition method such as sputtering or plasma-enhanced chemical vapor deposition (PECVD). In particular, by using sputtering without using hydrogen as the deposition gas, a film containing an extremely low amount of hydrogen can be achieved. This prevents hydrogen from entering the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0114] It is preferable that substances diffuse easily in the insulating layer 110 b. Alternatively, the diffusion coefficient of substances in the insulating layer 110 b is preferably large. It is particularly preferable that oxygen diffuse easily in the insulating layer 110 b. In other words, the oxygen diffusion coefficient in the insulating layer 110 b is preferably large. Oxygen in the insulating layer 110 b diffuses within the insulating layer 110 b and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110 b and the semiconductor layer 108.

[0115] The oxygen diffusion coefficient can be calculated using TDS or SIMS. Note that the diffusion coefficients of substances other than oxygen can also be calculated using TDS or SIMS.

[0116] Here, by using a material with high conductivity for the semiconductor layer 108, a transistor with a large on-state current can be realized. However, when a material with high conductivity is used, oxygen vacancies (V O ), oxygen vacancies in the channel formation region (V O ) increases, the threshold voltage of the transistor may drift, and the drain current (hereinafter also referred to as off-state current) that flows when the gate voltage is 0V may increase. For example, in an n-channel transistor, when the threshold voltage drifts negatively, the off-state current may increase. By providing the insulating layer 110b, oxygen is supplied to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, that is, the channel formation region of the transistor 100, thereby reducing oxygen vacancies (V O ). As a result, the threshold voltage drift can be suppressed, so a transistor with a small off-state current and a large on-state current can be realized. As a result, the semiconductor device 10 can be a low-power and high-performance semiconductor device.

[0117] Preferably, the insulating layer 110c releases a small amount of impurities (e.g., hydrogen and water) and is not easily permeable to impurities. This prevents impurities in the insulating layer 110c from diffusing into the channel formation region of the transistor 100. Consequently, the transistor 100 can exhibit excellent electrical characteristics and high reliability.

[0118] The insulating layer 110c is preferably made of a film that is not easily permeable to oxygen, for example, a film that is not easily permeable to oxygen compared to the insulating layer 110b. In addition, the insulating layer 110c is preferably made of a film with a small oxygen diffusion coefficient, for example, a film with a smaller oxygen diffusion coefficient than the insulating layer 110b. As a result, the oxygen in the insulating layer 110b can be suppressed from diffusing through the insulating layer 110c to the conductive layer 112a and the conductive layer 112b. As a result, the resistance of the conductive layer 112a and the conductive layer 112b can be suppressed from increasing. At the same time, the diffusion of oxygen in the insulating layer 110b to the insulating layer 110c side can be suppressed, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor 100 increases, and the oxygen vacancies (VO ) and V O H. Thus, the channel formation region of the transistor 100 can be made i-type or substantially i-type. Therefore, the transistor 100 can exhibit good electrical characteristics and high reliability.

[0119] The insulating layer 110c preferably contains nitrogen, and preferably uses one or more of the aforementioned nitrides and oxynitrides. Silicon nitride or silicon oxynitride can be used as the insulating layer 110c, for example. Furthermore, one or more oxides and oxynitrides can be used as the insulating layer 110c. Aluminum oxide can be used as the insulating layer 110c, for example.

[0120] exist Figure 3A In the embodiment, the thickness of the insulating layer 110 b is set to thickness T110 b_1 , and the thickness of the insulating layer 110 c is set to thickness T110 c_1 .

[0121] The thickness T110b_1 of the insulating layer 110b can be, for example, 5 nm or more and less than 3 μm, 5 nm or more and less than 2.5 μm, 5 nm or more and less than 2 μm, 5 nm or more and less than 1.5 μm, 7 nm or more and less than 1.2 μm, 7 nm or more and less than 1 μm, 7 nm or more and less than 500 nm, 7 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, or 10 nm or more and less than 30 nm. The thickness T110c_1 of the insulating layer 110c can be equal to or less than the thickness T110b_1. Thickness T110c_1 may be, for example, 3 nm to 1 μm, 3 nm to 500 nm, 3 nm to 300 nm, 3 nm to 200 nm, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 5 nm to 20 nm.

[0122] like Figure 3A As shown, thickness T110b_1 can be the shortest distance between the formed surface of insulating layer 110b (here, the top surface of insulating layer 101) and the bottom surface of insulating layer 110c when viewed in cross section. Furthermore, thickness T110c_1 can be the shortest distance between the formed surface of insulating layer 110c (here, the top surface of insulating layer 110b) and the bottom surface of conductive layer 112a or conductive layer 112b when viewed in cross section.

[0123] When the thickness T110c_1 of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c may increase, thereby increasing the amount of impurities diffused into the channel formation region of the transistor 100. On the other hand, when the thickness T110c_1 is thin, oxygen in the insulating layer 110b may diffuse through the insulating layer 110c to the conductive layer 112a and the conductive layer 112b, thereby reducing the amount of oxygen supplied to the channel formation region of the transistor 100. By setting the thickness T110c_1 within the above range, the oxygen vacancies (V O ) and V O H. Thus, the channel formation region of the transistor 100 can be made i-type or substantially i-type. Furthermore, oxidation of the conductive layers 112 a and 112 b by oxygen in the insulating layer 110 b, which would otherwise increase the resistance of the conductive layers 112 a and 112 b, can be suppressed. As a result, the transistor 100 can exhibit excellent electrical characteristics and high reliability.

[0124] Figure 3C It shows Figure 3A An enlarged view of region 108na and its vicinity. Figure 3C In the example shown, in the semiconductor layer 108, in addition to the region in contact with the conductive layer 112a and the region in the vicinity thereof, the region in contact with the insulating layer 110c and the region in the vicinity thereof, that is, the region 107 is included in the region 108na having a low resistance region. Figure 3C Although not shown in the figure, in addition to the region in contact with the conductive layer 112b and the region in the vicinity thereof, the region in contact with the insulating layer 110c and the region in the vicinity thereof may also be included in the region 108nb. Figure 3C In the example shown, the height of the boundary between the regions 108i and 108na is identical or substantially identical to the height of the boundary between the insulating layers 110b and 110c. However, these heights may be inconsistent or substantially identical. Similarly, the height of the boundary between the regions 108i and 108nb may be identical or substantially identical to the height of the boundary between the insulating layers 110b and 110c, or may be inconsistent or substantially identical.

[0125] By using a material that releases impurities for the insulating layer 110c, the region 107 can be made into a low resistance region. The semiconductor layer 108 can have a low resistance region between the source region and the drain region and the channel formation region in the transistor 100. The low resistance region can be used as a buffer region for mitigating the drain electric field (the electric field generated in the drain region and its vicinity). In addition, these low resistance regions can also be used as source regions or drain regions. By providing a low resistance region between the drain region and the channel formation region, a high electric field is not easily generated near the drain region. Thus, the generation of hot carriers can be suppressed and the degradation of the transistor can be suppressed.

[0126] As described above, if the amount of impurities released from the insulating layer 110c is too large, the impurities may diffuse into the channel formation region of the transistor 100. Even if a material that releases impurities is used for the insulating layer 110c, the amount of impurities released is preferably small.

[0127] exist Figure 3A In the example shown, the channel length L100 of the transistor 100 corresponds to the sum of twice the length of the side surface of the insulating layer 110b in the opening 141 when viewed in cross section and the width D141 of the opening 141. The length of the side surface of the insulating layer 110b in the opening 141 when viewed in cross section can be determined using the thickness T110b_1 and the angle θ110.

[0128] Figure 4A and Figure 4B They are Figure 2B and Figure 3A A modified example of the structure shown. Figure 4A and Figure 4B An example is shown in which the insulating layer 106 is processed into an island shape, for example.

[0129] Figure 4A and Figure 4B In the example shown, the top end of the insulating layer 106 is aligned or approximately aligned with the bottom end of the conductive layer 104. For example, by processing the insulating layer 106 using the same pattern as that of the conductive layer 104, the top end of the insulating layer 106 can be aligned or approximately aligned with the bottom end of the conductive layer 104. Note that the top end of the insulating layer 106 does not need to be aligned or approximately aligned with the bottom end of the conductive layer 104. For example, the top end of the insulating layer 106 may be located outside the bottom end of the conductive layer 104.

[0130] Figure 5A 、 Figure 5B and Figure 5C They are Figure 1A 、 Figure 3A and Figure 3B In the illustrated modification of the semiconductor device 10, a transistor 100 includes a conductive layer 103 and an insulating layer 105. Herein, the transistor 100 including the conductive layer 103 and the insulating layer 105 is referred to as a transistor 100A, and the semiconductor device 10 including the transistor 100A is referred to as a semiconductor device 10A.

[0131] In the transistor 100A, a conductive layer 103 is provided over an insulating layer 101, and an insulating layer 105 is provided over the conductive layer 103 and the insulating layer 101. The insulating layer 105 has a shape that follows the top surface and side surfaces of the conductive layer 103 and the top surface of the insulating layer 101. The insulating layer 105 may have a region in contact with the top surface of the conductive layer 103, a region in contact with the side surfaces of the conductive layer 103, and a region in contact with the top surface of the insulating layer 101.

[0132] An insulating layer 110 and a semiconductor layer 108 are provided over the insulating layer 105. The insulating layer 110 includes an opening 141 that reaches the insulating layer 105. The bottom surface of the semiconductor layer 108 may have a region in contact with the top surface of the insulating layer 105. In addition, the insulating layer 106 may have a region in contact with the top surface of the insulating layer 105.

[0133] The conductive layer 103 may have a region that overlaps with the semiconductor layer 108, the insulating layer 106, and the region of the conductive layer 104 located within the opening 141, with the insulating layer 105 interposed therebetween. Consequently, the conductive layer 103 can be used as a gate electrode in addition to the conductive layer 104, and the insulating layer 105 can be used as a gate insulating layer in addition to the insulating layer 106. Therefore, the transistor 100A can be said to be a dual-gate transistor having gate electrodes on both sides with the channel formation region interposed therebetween.

[0134] In transistor 100A, for example, the conductive layer 104 may be referred to as a first gate electrode, a front gate electrode, or simply a gate electrode. Furthermore, the conductive layer 103 may be referred to as a second gate electrode or a back gate electrode. Note that the names of the conductive layer 104 and the conductive layer 103 may be interchanged. Furthermore, the insulating layer 106 and the insulating layer 105 may be referred to as a first gate insulating layer and a second gate insulating layer, respectively. Note that the insulating layer 105 and the insulating layer 106 may also be referred to as a first gate insulating layer and a second gate insulating layer, respectively.

[0135] By including the conductive layer 103 in the transistor 100, the potential on the back channel side of the semiconductor layer 108 can be fixed, thereby suppressing the drift of the threshold voltage. Here, when the threshold voltage of the transistor 100 drifts negatively, the off-state current may increase. By suppressing the negative drift of the threshold voltage of the transistor 100, a transistor with low off-state current can be realized. Note that a state with low off-state current is sometimes referred to as normally-off.

[0136] Note that although Figure 5B Although the example in which the insulating layer 110 b is planarized is shown, the insulating layer 110 b may not be planarized. In this case, the insulating layer 110 c may or may not be planarized.

[0137] Figure 6A and Figure 6B They are Figure 3A and Figure 3B In the modified example of the structure shown, an insulating layer 147 and an insulating layer 149 are provided. Figure 6A An example is shown in which the insulating layer 147 and the insulating layer 149 are provided between the insulating layer 110 and the semiconductor layer 108 , between the conductive layer 112 a and the semiconductor layer 108 , and between the conductive layer 112 b and the semiconductor layer 108 . Figure 6B An example is shown in which the insulating layer 147 and the insulating layer 149 are provided between the insulating layer 110 and the insulating layer 106 .

[0138] The insulating layer 147 may have a region in contact with the side surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112b, a region in contact with the top surface of the insulating layer 101, a region in contact with the side surface of the semiconductor layer 108, and a region in contact with the insulating layer 106. Figure 6A and Figure 6B As shown in FIG. 1 , in a cross-sectional view, a portion of insulating layer 147 that contacts the top surface of insulating layer 101 forms a protrusion. Insulating layer 147 may contact semiconductor layer 108 at the end of the protrusion. The protrusion of insulating layer 147 protrudes toward the center of opening 141 more than the other portions.

[0139] The insulating layer 147 preferably has hydrogen barrier properties, and particularly preferably has a high ability to inhibit hydrogen diffusion. For example, the insulating layer 147 can be made of one or more of aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. For example, silicon nitride can be used for the insulating layer 147. Providing the insulating layer 147 can inhibit hydrogen from diffusing from outside the transistor 100 through the insulating layer 147 into the semiconductor layer 108.

[0140] The insulating layer 149 may be provided on the insulating layer 147. The insulating layer 149 may have a region in contact with the side surface of the insulating layer 147, a region in contact with the top surface of the protrusion of the insulating layer 147, a region in contact with the semiconductor layer 108, and a region in contact with the insulating layer 106. Figure 6A and Figure 6B As shown, in a cross-sectional view, the side surfaces of the insulating layer 149 may be flush with the side ends of the protruding portions of the insulating layer 147 .

[0141] The insulating layer 149 preferably has a hydrogen barrier property, and it is particularly preferred that it has a high ability to capture or fix hydrogen. For example, the insulating layer 149 can use one or more of an oxide containing magnesium, an oxide containing one of aluminum and hafnium, and an oxide containing both aluminum and hafnium. In addition, these oxides more preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and sometimes have the property of capturing or fixing hydrogen by the dangling bonds. In addition, these oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region. In addition, as materials with a high ability to inhibit hydrogen diffusion, silicon nitride and silicon oxynitride can be cited. For example, hafnium oxide can be appropriately used for the insulating layer 149. By providing the insulating layer 149, hydrogen in the insulating layer 110 can be captured or fixed by the insulating layer 149. For example, when a metal oxide is used for the semiconductor layer 108, hydrogen and water that may be mixed into the semiconductor layer 108 can be removed by providing the insulating layer 147 and the insulating layer 149 in the semiconductor device. Therefore, the transistor 100 can be a transistor having good electrical characteristics and high reliability.

[0142] In manufacturing Figure 6A and Figure 6B In the semiconductor device shown, an insulating layer 101, an insulating layer 110, and conductive layers 112a and 112b are formed on a substrate 102. An opening 141 is formed in the insulating layer 110. Then, an insulating film to become an insulating layer 147 and an insulating film to become an insulating layer 149 are sequentially formed to cover the opening 141. Next, the insulating films to become the insulating layers 149 and 147 are processed to form the insulating layers 149 and 147. For example, the top surfaces of the insulating films to become the insulating layers 149 and 147 can be etched substantially uniformly to form the insulating layers 149 and 147. This process of planarizing by uniform etching is also called anisotropic etching. Alternatively, the insulating layers 149 and 147 can be formed using photolithography.

[0143] Then, the semiconductor layer 108, the insulating layer 106, the conductive layer 104, and the insulating layer 109 are sequentially formed. Figure 6A and Figure 6B The semiconductor device shown.

[0144] Figure 7A and Figure 7B They are Figure 2A and Figure 3A In the modified example of the semiconductor device 10 shown in FIG. 1 , the conductive layer 112 b is provided between the insulating layer 101 and the insulating layer 110 . Figure 7A and Figure 7B 1 shows an example in which the conductive layer 112b is provided under the insulating layer 110. Figure 7A The semiconductor device 10 shown is referred to as a semiconductor device 10B. Figure 7B The transistor 100 shown is referred to as transistor 100B. In semiconductor device 10B, opening 141 has a region that reaches conductive layer 112b. Furthermore, in semiconductor device 10B, conductive layer 112a may be provided below insulating layer 110, and conductive layer 112b may be provided above insulating layer 110. In this case, the following description of semiconductor device 10B and transistor 100B can be referred to by appropriately replacing conductive layer 112b and region 108nb with conductive layer 112a and region 108na, respectively.

[0145] In the transistor 100B, for example, the boundary between the region 108i and the region 108nb is located lower than the top surface of the insulating layer 110b. Figure 7B An example is shown in which the height of the boundary between the region 108 i and the region 108 nb is lower than the height of the boundary between the insulating layer 110 b and the insulating layer 110 c .

[0146] Regarding the transistor 100B, the vertical channel length can be set to 1 or approximately 1 times the length of the side surface in the opening 141. In addition, the lateral channel length can be set to be shorter than the width D141 of the opening 141. Thus, the channel length of the transistor 100B can be set to be shorter than, for example, Figure 3A Transistor 100 is shown short. Note that although Figure 7A and Figure 7B Although the bottom edge of the semiconductor layer 108 overlapping the conductive layer 112 b is shown as being provided on the insulating layer 110 , the bottom edge may be in contact with the conductive layer 112 b . In this case, the region 108 nb may not be in contact with the insulating layer 110 .

[0147] Figure 8A and Figure 8B They are Figure 7A and Figure 7B In the modified example of the semiconductor device 10B shown in FIG, a conductive layer 112a is provided between the insulating layer 101 and the insulating layer 110 in addition to the conductive layer 112b. Figure 8A and Figure 8B 1 shows an example in which a conductive layer 112a is provided under the insulating layer 110 in addition to the conductive layer 112b. Figure 8A The semiconductor device 10 shown is referred to as a semiconductor device 10C. Figure 8B The transistor 100 shown is referred to as a transistor 100C. In the semiconductor device 10C, the opening 141 has a region reaching the conductive layer 112a and a region reaching the conductive layer 112b.

[0148] The transistor 100C may not have a longitudinal channel length, that is, its longitudinal channel length may be 0. In addition, the lateral channel length may be shorter than that of the transistor 100B. Thus, the channel length of the transistor 100C may be shorter than that of the transistor 100B. Note that although Figure 8A and Figure 8B In the example shown, the bottom end portions of semiconductor layer 108 overlapping conductive layer 112a and the bottom end portions overlapping conductive layer 112b are provided on insulating layer 110. However, the bottom end portions overlapping conductive layer 112a may be in contact with conductive layer 112a, and the bottom end portions overlapping conductive layer 112b may be in contact with conductive layer 112b. In this case, region 108na and region 108nb do not need to be in contact with insulating layer 110.

[0149] Figure 9A yes Figure 2A A modified example of the structure shown in FIG. 1 is shown in FIG. 1 , wherein the width W100 of the semiconductor layer 108 is greater than the width W112a of the conductive layer 112a and the width W112b of the conductive layer 112b. Figure 9A Although an example is shown in which the width W100 is smaller than the width D141 , the width W100 may be greater than the width D141 .

[0150] By increasing the width W100, it is possible to increase the on-state current of the transistor 100 included in the semiconductor device 10. On the other hand, by decreasing the width W100, a micro transistor can be realized as the transistor 100.

[0151] Figure 9B yes Figure 2A In the modified example of the structure shown, two semiconductor layers 108 are provided in one opening 141 .

[0152] In this specification, when the same symbol is used to represent multiple components, especially when it is necessary to distinguish between them, the symbol may be supplemented with an identification symbol such as "[1]", "[2]", "_1", or "_2". For example, the two semiconductor layers 108 are respectively referred to as semiconductor layer 108[1] and semiconductor layer 108[2] to distinguish them.

[0153] exist Figure 9B In the example shown, the semiconductor layer 108[1] and the semiconductor layer 108[2] both have regions in contact with the same conductive layer 112a and the same conductive layer 112b. Note that three or more semiconductor layers 108 may be provided in one opening 141.

[0154] When a plurality of semiconductor layers 108 are provided in one opening 141, the area of each semiconductor layer 108 can be reduced compared to when only one semiconductor layer 108 is provided in one opening 141. This makes it easier to supply oxygen to the semiconductor layer 108 during the manufacturing process of the semiconductor device 10. This can reduce oxygen vacancies (V O ) and V O H. As a result, the transistor 100 included in the semiconductor device 10 may exhibit good electrical characteristics and high reliability. On the other hand, when one semiconductor layer 108 is provided in one opening 141, compared with the case where multiple semiconductor layers 108 are provided in one opening 141, the transistor 100 included in the semiconductor device 10 can be miniaturized and the channel width can be increased.

[0155] Figure 10A and Figure 10B yes Figure 2A The modified example of the structure shown in FIG. 1 is a planar shape of the opening 141. Figure 2A The semiconductor device 10 shown is different. Figure 10A An example is shown in which the planar shape of the opening 141 is a rectangle. Figure 10B An example is shown in which the planar shape of the opening 141 is a rectangle with rounded corners.

[0156] For example, by adopting the planar shape of the opening 141 Figure 2A The circular shape shown can improve the processing accuracy when forming the opening 141. On the other hand, by adopting a rectangular or rectangular shape with rounded corners as the planar shape of the opening 141, the side surface of the opening 141 has a flat or substantially flat area, which can sometimes improve the coverage of layers disposed within the opening 141, such as the semiconductor layer 108, the insulating layer 106, and the conductive layer 104. Furthermore, when the planar shape of the opening 141 is rectangular, by making the corners angular, the area of the opening 141 when viewed from a plan view can be increased while miniaturizing the transistor 100 included in the semiconductor device 10, compared to a case where the corners are rounded. On the other hand, when the corners of the opening 141 are rounded, the coverage of the corners of the opening 141 by layers disposed within the opening 141 can be improved compared to a case where the corners of the opening 141 are angular.

[0157] Figure 11A and Figure 11B They are Figure 10A and Figure 10B A modified example of the structure shown in FIG. Figure 9BIn the illustrated structure, two semiconductor layers 108 are provided in one opening 141. Note that three or more semiconductor layers 108 may be provided in one opening 141 as described above.

[0158] Figure 12A and Figure 12B They are Figure 11A and Figure 11B A modified example of the structure shown in FIG. 1 is a configuration in which the opening 141 provided with the semiconductor layer 108[1] is different from the opening 141 provided with the semiconductor layer 108[2]. Figure 12A and Figure 12B In the figure, the opening 141 in which the semiconductor layer 108[1] is provided is referred to as the opening 141[1], and the opening 141 in which the semiconductor layer 108[2] is provided is referred to as the opening 141[2], thereby distinguishing the two openings 141. The same description is also made in the following figures. Note that when three or more semiconductor layers 108 having regions in contact with the same conductive layer 112a and the same conductive layer 112b are provided, three or more openings 141 may be provided.

[0159] and Figure 11A and Figure 11B Compared to the example shown, according to Figure 12A and Figure 12B The example shown makes it easy to supply oxygen from the insulating layer 110 to the semiconductor layer 108. Figure 12A and Figure 12B Compared to the example shown, according to Figure 11A and Figure 11B In the example shown, the total area occupied by the openings 141 provided in one transistor 100 can be reduced, so that a micro transistor can be realized as the transistor 100 .

[0160] Figure 13A yes Figure 1A A modified example of the structure shown. Figure 13B It is from Figure 13A A plan view of the conductive layer 104 is omitted. Figure 13C It is along Figure 13A The cross-sectional view of the section along the dot-dash line A1-A2 in FIG. 13A to 13C In the example shown, a transistor 100 is provided across the inside of the opening 141[1] and the inside of the opening 141[2], and a conductive layer 112c is provided between the opening 141[1] and the opening 141[2] when viewed from a plane. In other words, 13A to 13CIn the semiconductor device 10 shown, the conductive layer 112a and the conductive layer 112c are arranged so as to face each other with the opening 141[1] interposed therebetween when viewed from a planar perspective. Furthermore, the conductive layer 112b and the conductive layer 112c are arranged so as to face each other with the opening 141[2] interposed therebetween when viewed from a planar perspective. Here, the transistor 100 in which a single semiconductor layer 108 is arranged across the interior of a plurality of openings 141 and a conductive layer is arranged between the plurality of openings 141 when viewed from a planar perspective is referred to as a transistor 100D, and the semiconductor device 10 including the transistor 100D is referred to as a semiconductor device 10D.

[0161] exist 13A to 13C In the illustrated example, one transistor 100 includes three conductive layers 112. Alternatively, one transistor 100 may be provided across three or more openings 141. In this case, four or more conductive layers 112 may be provided in one transistor 100.

[0162] By providing one transistor 100 across the interiors of multiple openings 141, the vertical channel length of transistor 100 can be increased, thereby improving the saturation performance of transistor 100, compared to a case where one transistor 100 is provided within one opening 141. Furthermore, by providing one transistor 100 within one opening 141, a more micro-transistor can be realized as transistor 100, compared to a case where one transistor 100 is provided across the interiors of multiple openings 141.

[0163] Figure 14A 、 Figure 14B and Figure 14C They are Figure 13A 、 Figure 13B and Figure 13C A modified example of the structure shown in FIG. 1 is a semiconductor layer 108 having a region located inside the opening 141[1] and a semiconductor layer 108 having a region located inside the opening 141[2]. Figure 14A 、 Figure 14B and Figure 14C, the semiconductor layer 108 having a region located inside the opening 141[1] is referred to as the semiconductor layer 108[1]. Furthermore, the semiconductor layer 108 having a region located inside the opening 141[2] is referred to as the semiconductor layer 108[2]. Note that, in the case where one transistor 100 is provided across the interiors of three or more openings 141, for example, a different semiconductor layer 108 may be provided in each opening 141. Here, the transistor 100 provided across the interiors of a plurality of openings 141, each of the plurality of openings 141 having a different semiconductor layer 108, and having a conductive layer provided between the plurality of openings 141 when viewed from a plane, is referred to as the transistor 100E, and the semiconductor device 10 including the transistor 100E is referred to as the semiconductor device 10E.

[0164] Compared to the transistor 100D, the area of each semiconductor layer 108 can be reduced in the transistor 100E. Therefore, compared to the semiconductor device 10D, the semiconductor device 10E can be more easily supplied with oxygen to the semiconductor layer 108 during the manufacturing process. As a result, oxygen vacancies (V O ) and V O H. Therefore, the transistor 100E may have better electrical characteristics and higher reliability than the transistor 100D. On the other hand, the distance between the openings 141 of the transistor 100D can be shorter than that of the transistor 100E, so the transistor 100D can be a micro transistor.

[0165] Figure 15A 、 Figure 15B and Figure 15C They are Figure 13A 、 Figure 13B and Figure 13C The modified example of the structure shown in FIG. 1 is a transistor 100 including a conductive layer 103 and an insulating layer 105. In other words, Figure 15A 、 Figure 15B and Figure 15C It is a combination Figure 5A 、 Figure 5B and Figure 5C The structure shown and Figure 13A 、 Figure 13B and Figure 13C The transistor 100 is referred to as a transistor 100F. The semiconductor device 10 including the transistor 100F is referred to as a semiconductor device 10F.

[0166] The transistor 100F can achieve higher saturation than the transistor 100A while suppressing threshold voltage drift. On the other hand, the transistor 100A can be further miniaturized than the transistor 100F.

[0167] Figure 16A 、 Figure 16B and Figure 16C They are Figure 15A 、 Figure 15B and Figure 15C A modified example of the structure shown is provided in which the semiconductor layer 108[1] is provided so as to have a region located inside the opening 141[1], and the semiconductor layer 108[2] is provided so as to have a region located inside the opening 141[2]. Figure 16A 、 Figure 16B and Figure 16C It can be said to be a combination Figure 14A 、 Figure 14B and Figure 14C The structure shown and Figure 15A 、 Figure 15B and Figure 15C The transistor 100 is referred to as a transistor 100G. The semiconductor device 10 including the transistor 100G is referred to as a semiconductor device 10G.

[0168] The transistor 100G may have better electrical characteristics and higher reliability than the transistor 100F. Furthermore, the distance between the openings 141 of the transistor 100F may be shorter than that of the transistor 100G, so the transistor 100F may be a micro transistor.

[0169] <Structural Example 2 of Semiconductor Device> Figure 17A 1 is a plan view showing a structural example of a semiconductor device 20 that is one embodiment of the present invention. Figure 17B It is along Figure 17A A cross-sectional view of the section taken along the dot-dash line A3-A4 in FIG. Figure 17C It is along Figure 17A A cross-sectional view of the section taken along the dot-dash line B3-B4.

[0170] The semiconductor device 20 has Figure 1A 、 Figure 1C and Figure 1D In addition to the transistor 100 shown, a transistor 200 having a structure different from that of the transistor 100 is included. The transistor 200 is provided on the insulating layer 101.

[0171] Transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, and a semiconductor layer 208. In transistor 200, conductive layer 204 serves as a gate electrode, and a portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 212a serves as one of a source electrode and a drain electrode, and conductive layer 212b serves as the other of the source electrode and the drain electrode. Each layer constituting transistor 200 may have a single-layer structure or a stacked-layer structure.

[0172] Conductive layer 212a is provided on insulating layer 101. Insulating layer 110 is provided on conductive layer 212a. Insulating layer 110 is provided so as to cover the top surface and side surfaces of conductive layer 212a. Insulating layer 110 includes opening 241 that reaches conductive layer 212a. Transistor 200 is provided so as to have a region located inside opening 241. Note that although Figure 17B and Figure 17C Although an example in which the insulating layer 110 is planarized is shown, the insulating layer 110 may not be planarized.

[0173] A conductive layer 212b is provided on the insulating layer 110. The conductive layer 212b includes an opening 243 having an area overlapping with the opening 241. The planar shapes of the openings 241 and 243 may be the same as the planar shape that the opening 141 may have. Here, the planar shape of the opening 241 and the planar shape of the opening 243 may be identical or substantially identical. In this case, the bottom end of the conductive layer 212b on the side of the opening 243 is preferably aligned or substantially aligned with the top end of the insulating layer 110 on the side of the opening 241. The bottom surface of the conductive layer 212b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 212b.

[0174] Furthermore, the planar shape of the opening 241 may not be consistent with the planar shape of the opening 243. Furthermore, when the planar shapes of the openings 241 and 243 are circular, the openings 241 and 243 may or may not be concentric circles.

[0175] The conductive layer 212b can be formed using the same material as the conductive layers 112a and 112b. Furthermore, the conductive layer 212b can be formed using the same process as the conductive layers 112a and 112b. For example, the conductive layers 112a, 112b, and 212b can be formed by forming a conductive film to be the conductive layers 112a, 112b, and 212b and processing the conductive film.

[0176] Semiconductor layer 208 includes a region located within opening 241 and a region located within opening 243. Semiconductor layer 208 may be provided along the bottom and side surfaces of opening 241 and the side surfaces of opening 243. For example, semiconductor layer 208 may include a region in contact with the top surface of conductive layer 212a, a region in contact with the side surfaces of conductive layer 212b, and a region in contact with the top surface of conductive layer 212b. Furthermore, semiconductor layer 208 may include a region in contact with the side surfaces of insulating layer 110.

[0177] The region of the semiconductor layer 208 in contact with the conductive layer 212a serves as one of the source region and the drain region, and the region in contact with the conductive layer 212b serves as the other. In the semiconductor layer 208, a channel formation region is provided between the source region and the drain region.

[0178] The semiconductor layer 208 can be formed using the same material as the semiconductor layer 108. The semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming films to be the semiconductor layer 108 and the semiconductor layer 208 and processing the semiconductor films.

[0179] The insulating layer 106 is provided to include a region located within the opening 241 and a region located within the opening 243. Specifically, it is provided to cover the opening 241 and the opening 243. The insulating layer 106 is provided on the semiconductor layer 208 and the conductive layer 212b. The insulating layer 106 has a shape that follows the top surface and side surfaces of the semiconductor layer 208 and the top surface and side surfaces of the conductive layer 212b. The insulating layer 106 may include a region in contact with the top surface of the semiconductor layer 208, a region in contact with the side surfaces of the semiconductor layer 208, a region in contact with the top surface of the conductive layer 212b, and a region in contact with the side surfaces of the conductive layer 212b.

[0180] Conductive layer 204 is provided on insulating layer 106 so as to include a region located inside opening 241 and a region located inside opening 243. Conductive layer 204 is provided so as to include a region located inside opening 241 and facing semiconductor layer 208 with insulating layer 106 interposed therebetween. Conductive layer 204 can have a shape that conforms to insulating layer 106, specifically, a shape that conforms to the top surface of insulating layer 106 and the side surfaces of insulating layer 106 within openings 241 and 243. Furthermore, conductive layer 204 can include a region in contact with the top surface of insulating layer 106 and a region in contact with the side surfaces of insulating layer 106 within openings 241 and 243.

[0181] The conductive layer 204 can use the same material as the conductive layer 104. The conductive layer 204 can be formed by the same process as the conductive layer 104. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming films to become the conductive layer 104 and the conductive layer 204 and processing the conductive films.

[0182] The insulating layer 109 is provided so as to cover the transistor 200. The insulating layer 109 is provided over the conductive layer 204. The insulating layer 109 serves as a protective layer for the transistor 200.

[0183] Transistor 200 is a so-called top-gate transistor that includes a gate electrode above semiconductor layer 208. Furthermore, since the bottom surface of semiconductor layer 208 is in contact with conductive layer 212a and conductive layer 212b, which serve as the source electrode and drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor. In addition, in transistor 200, the source electrode and the drain electrode have different heights relative to the surface of insulating layer 101 on which they are formed, and the drain current flows in a direction perpendicular to or approximately perpendicular to the surface of insulating layer 101. It can also be said that in transistor 200, the drain current flows in the vertical direction or the approximately vertical direction. Therefore, transistor 200 can be said to be a vertical channel transistor or VFET (Vertical Field Effect Transistor).

[0184] The channel length of transistor 200 can be controlled by the thickness of insulating layer 110 provided between conductive layer 212a and conductive layer 212b. Therefore, a transistor having a channel length smaller than the limiting resolution of the exposure device used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between multiple transistors 200 can be reduced. Therefore, the operation of the semiconductor device including transistor 200 is stable and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the circuit design freedom is improved, and the operating voltage of the semiconductor device can also be reduced. As a result, the power consumption of the semiconductor device can be reduced.

[0185] Since the source electrode, the layer having the channel formation region, and the drain electrode can be overlapped, the occupied area of the transistor 200 can be made much smaller than that of a so-called planar transistor in which the layer having the channel formation region is arranged in a planar shape.

[0186] Conductive layer 212a, conductive layer 212b, and conductive layer 204 can all be used as wiring, and transistor 200 can be provided in a region where these wirings overlap. In other words, in a circuit including transistor 200 and wirings, the area occupied by transistor 200 and wirings can be reduced. Consequently, the area occupied by the circuit can be reduced, thereby achieving a compact semiconductor device.

[0187] The transistor 200 with a short channel length and the transistor 100 with a long channel length can be formed on the insulating layer 101 by sharing some of the same processes. For example, by using the transistor 200 as a transistor requiring a large on-state current and the transistor 100 as a transistor requiring high saturation, a high-performance semiconductor device can be realized. Thus, the semiconductor device of one embodiment of the present invention has the following excellent effect: transistors with different channel lengths can be freely designed on the same substrate according to the thickness and pattern formation of the insulating layer.

[0188] exist Figure 17A In the embodiment, the width of the opening 241 is set to width D241. Figure 17A In FIG, the width D241 is indicated by a double arrow. The same is also indicated in the following figures.

[0189] Width D241 is preferably small, for example, preferably less than width D141 of opening 141 of transistor 100, which preferably has a large channel length. Thus, transistor 200 can be a miniaturized transistor. Furthermore, since the channel length of transistor 100 depends on width D141, by making width D141 larger than width D241, transistor 200 can be a miniaturized transistor while ensuring the channel length of transistor 100.

[0190] Conductive layer 212a, which serves as one of the source and drain electrodes of transistor 200, and conductive layer 212b, which serves as the other of the source and drain electrodes of transistor 200, are provided on different surfaces. Specifically, conductive layer 212a is provided on insulating layer 101, and conductive layer 212b is provided on insulating layer 110, with insulating layer 110 sandwiched between conductive layer 212a and conductive layer 212b. On the other hand, conductive layer 112a, which serves as one of the source and drain electrodes of transistor 100, and conductive layer 112b, which serves as the other of the source and drain electrodes of transistor 100, are provided on the same surface. Specifically, conductive layer 112a and conductive layer 112b are provided on insulating layer 110. In other words, one of the source and drain electrodes of transistor 200 is provided on a different surface from the source and drain electrodes of transistor 100, while the other of the source and drain electrodes of transistor 200 is provided on the same surface as the source and drain electrodes of transistor 100.

[0191] For example, when a semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, thereby realizing a high-definition display device. Furthermore, when a semiconductor device according to one embodiment of the present invention is used in a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, thereby realizing a display device with a narrow frame.

[0192] Figure 18A and Figure 18B They are Figure 17A and Figure 17B FIG. 2 is an enlarged view of transistor 200. Figure 18A and Figure 18B The channel length, channel width, etc. of the transistor 200 will be described.

[0193] exist Figure 18A and Figure 18B In the embodiment, the channel length of the transistor 200 is set to length L200, the channel width is set to width W200, the thickness of the insulating layer 110 is set to thickness T110_2, and the angle formed by the side surface of the insulating layer 110 in the opening 241 and the top surface of the insulating layer 101 is set to angle θ110. Figure 18A and Figure 18B In FIG. 1 , the length L200, the width W200 and the thickness T110_2 are indicated by double arrows. The same is also indicated in the following figures. Figure 18B As shown, the thickness T110_2 may be the shortest distance between the formed surface of the conductive layer 212a (here, the top surface of the conductive layer 212a) and the bottom surface of the conductive layer 212b in a cross-sectional view.

[0194] exist Figure 18B , a region 208i, a region 208na, and a region 208nb are shown as regions of the semiconductor layer 208. The region 208i is provided between the region 208na and the region 208nb.

[0195] At least a portion of the region 208i is used as a channel formation region of the transistor 200. The region 208na is a region in the semiconductor layer 208 that is in contact with the conductive layer 212a and a region in the vicinity thereof. At least a portion of the region 208na is used as one of the source region and the drain region of the transistor 200. The region 208nb is a region in the semiconductor layer 208 that is in contact with the conductive layer 212b and a region in the vicinity thereof. At least a portion of the region 208nb is used as the other of the source region and the drain region of the transistor 200. At least a portion of the region 208na and the region 208nb may be a region having a lower resistance than at least a portion of the region 208i (hereinafter also referred to as a low resistance region). For example, at least a portion of the region 208na and the region 208nb may be a region having a higher carrier concentration or a higher oxygen vacancy density than at least a portion of the region 208i. Although Figure 18B In the example shown, the height of the boundary between the region 208i and the region 208nb coincides with or substantially coincides with the height of the boundary between the insulating layer 110 and the conductive layer 212b. However, these heights may not coincide with or substantially coincide with each other.

[0196] The length L200 of the channel length of the transistor 200 is equivalent to the length of the side surface of the insulating layer 110 in the opening portion 241 when viewed in section. That is, the length L200 is determined by the thickness T110_2 of the insulating layer 110 and the angle θ110 formed by the side surface of the insulating layer 110 in the opening portion 241 and the formed surface of the insulating layer 110 (here, the top surface of the conductive layer 212a). Therefore, the length L200 can be set to a value smaller than the limiting resolution of the exposure device, and a micro transistor can be realized. Specifically, a transistor with an extremely small channel length that cannot be realized in the exposure device used in the mass production of existing flat-panel displays (for example, a minimum line width of about 2μm or 1.5μm) can be realized. In addition, a transistor with a channel length of less than 10nm can be realized without using the very expensive exposure device used in the most advanced LSI technology.

[0197] The length L200 can be, for example, greater than 0.1 nm and less than 3 μm, greater than 0.1 nm and less than 2.5 μm, greater than 1 nm and less than 2 μm, greater than 1 nm and less than 1.5 μm, greater than 5 nm and less than 1.2 μm, greater than 5 nm and less than 1 μm, greater than 7 nm and less than 500 nm, greater than 7 nm and less than 300 nm, greater than 10 nm and less than 200 nm, greater than 10 nm and less than 100 nm, or greater than 10 nm and less than 50 nm.

[0198] By shortening the length L200, the on-state current of transistor 200 can be increased. By using transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when a semiconductor device according to one embodiment of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced when the number of wirings increases, thereby suppressing display unevenness. In addition, since the area occupied by the circuit can be reduced, the frame of the display device can be reduced.

[0199] By adjusting the thickness T110_2 and the angle θ110 of the insulating layer 110 , the length L200 can be controlled.

[0200] The side surfaces of the insulating layer 110 in the opening 241 preferably have a vertical shape similar to the side surfaces in the opening 141, and are preferably perpendicular to the insulating layer 101, for example. Note that the side surfaces of the insulating layer 110 in the opening 241 may also have a tapered shape. Furthermore, the side surfaces of the insulating layer 110 in the opening 241 may be straight or curved similar to the side surfaces in the opening 141, and may have both straight and curved regions.

[0201] Here, the conductive layer 212b is preferably not provided within the opening 241. Specifically, the conductive layer 212b preferably does not have a region in contact with the side surface of the insulating layer 110 within the opening 241. If the conductive layer 212b is also provided inside the opening 241, the length L200 of the transistor 200 becomes shorter than the length of the side surface of the insulating layer 110, making it difficult to control the length L200. Therefore, it is preferable that the planar shape of the opening 243 matches the planar shape of the opening 241, or that the opening 243 overlaps the opening 241 in a plan view.

[0202] Figure 18A An example is shown in which the planar shape of opening 241 is circular. In this case, width D241 corresponds to the diameter of the circle, and width W200 of the channel width of transistor 200 corresponds to the circumference of the circle. In other words, width W200 is π × D141. Thus, when the planar shape of opening 241 is circular, a transistor with a smaller width W200 can be realized compared to other shapes.

[0203] The width D241 of the opening 241 may vary in the depth direction. The width D241 of the opening 241 may be, for example, the average of the diameters of the insulating layer 110 at its highest point, lowest point, and midway between them when viewed in cross section. Alternatively, the diameter of the opening 241 may be any of the diameters of the insulating layer 110 at its highest point, lowest point, and midway between them when viewed in cross section.

[0204] When the opening 241 is formed by photolithography, the width D241 of the opening 241 is greater than or equal to the limiting resolution of the exposure apparatus. For example, the width D241 may be 200 nm or greater and less than 5 μm, 200 nm or greater and 4.5 μm or less, 300 nm or greater and 4 μm or less, 300 nm or greater and 3.5 μm or less, 400 nm or greater and 3 μm or less, 400 nm or greater and 2.5 μm or less, 500 nm or greater and 2 μm or less, 500 nm or greater and 1.5 μm or less, or 500 nm or greater and 1 μm or less.

[0205] For example Figure 18B In the transistor 200, the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are shown as covering the openings 241 and 243. However, one embodiment of the present invention is not limited to this. Alternatively, a structure may be employed in which the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are provided along a step formed by the insulating layer 110 and the conductive layer 212a.

[0206] Figure 19A yes Figure 17BA modified example of the structure shown in FIG. 1 is a three-layer stacked structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. Note that a planar structure example can be referred to. Figure 17A .

[0207] exist Figure 19A In the example shown, the insulating layer 110a may have a region in contact with the side surface of the semiconductor layer 108, a region in contact with the side surface of the semiconductor layer 208, a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surface of the conductive layer 212a, and a region in contact with the top surface of the insulating layer 101. The insulating layer 110b may have a region in contact with the side surface of the semiconductor layer 108 and a region in contact with the side surface of the semiconductor layer 208. The insulating layer 110c may have a region in contact with the side surface of the semiconductor layer 108, a region in contact with the side surface of the semiconductor layer 208, a region in contact with the bottom surface of the conductive layer 112a, a region in contact with the bottom surface of the conductive layer 112b, a region in contact with the bottom surface of the conductive layer 212b, and a region in contact with the bottom surface of the insulating layer 106. Note that although Figure 19A In the example shown, the insulating layer 110a is not planarized and the insulating layer 110b is planarized, but the insulating layer 110a may be planarized and the insulating layer 110b may not be planarized. If the insulating layer 110b is not planarized, the insulating layer 110c may or may not be planarized.

[0208] Insulating layer 110a can use the same material as insulating layer 110c and can have the same function as insulating layer 110c. For example, insulating layer 110a preferably has a lower oxygen content than insulating layer 110b. In other words, insulating layer 110b preferably has a higher oxygen content than insulating layer 110a. Furthermore, insulating layer 110b preferably has a higher oxygen content than both insulating layer 110a and insulating layer 110c. For example, the oxygen content per unit volume of insulating layer 110b is preferably higher than both the oxygen content per unit volume of insulating layer 110a and the oxygen content per unit volume of insulating layer 110c.

[0209] In addition, the insulating layer 110a and the insulating layer 110c are preferably made of a film that is not easily permeable to oxygen, for example, a film that is not easily permeable to oxygen compared to the insulating layer 110b. In addition, the insulating layer 110a and the insulating layer 110c are preferably made of a film with a small oxygen diffusion coefficient, for example, a film with a smaller oxygen diffusion coefficient than the insulating layer 110b. As a result, it is possible to suppress the oxygen in the insulating layer 110b from diffusing through the insulating layer 110a to the conductive layer 212a and from diffusing through the insulating layer 110c to the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b. As a result, it is possible to suppress the resistance of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b from increasing. At the same time, the diffusion of oxygen in the insulating layer 110b to the insulating layer 110a side and the insulating layer 110c side is suppressed, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor 200 increases, and the oxygen vacancies (V O ) and V O H. Thus, the transistor 200 can exhibit good electrical characteristics and be highly reliable.

[0210] Figure 19B It shows Figure 19A An enlarged view of the semiconductor layer 208 and its vicinity in FIG. Figure 19B The following example is shown: in the semiconductor layer 208, in addition to the region in contact with the conductive layer 212a and the region in the vicinity thereof, the region 107a in contact with the insulating layer 110a and the region in the vicinity thereof is included in the region 208na having a low resistance region. Figure 19B In addition to the region in contact with the conductive layer 212b and the region in the vicinity thereof in the semiconductor layer 208, the region in contact with the insulating layer 110c and the region in the vicinity thereof, that is, the region 107b is included in the region 208nb having the low resistance region. Figure 19B In the example shown, the height of the boundary between the region 208i and the region 208nb coincides with or substantially coincides with the height of the boundary between the insulating layer 110b and the insulating layer 110c. However, these heights may not coincide with or substantially coincide with each other.

[0211] By using a material that releases impurities for the insulating layer 110a, the region 107a can be made into a low-resistance region. By using a material that releases impurities for the insulating layer 110c, the region 107b can be made into a low-resistance region. The semiconductor layer 208 can include a low-resistance region between the source and drain regions and the channel formation region in the transistor 100. As described above, the low-resistance region can be used as a buffer region to mitigate the drain electric field. Alternatively, these low-resistance regions can be used as source or drain regions.

[0212] As described above, by providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region. This can suppress the generation of hot carriers and thus the degradation of the transistor. For example, when the conductive layer 212a is used as a drain electrode and the conductive layer 212b is used as a source electrode, by using the region of the semiconductor layer 208 in contact with the insulating layer 110a as a low-resistance region, a high electric field is less likely to be generated near the drain region. When the conductive layer 212a is used as a source electrode and the conductive layer 212b is used as a drain electrode, by using the region of the semiconductor layer 208 in contact with the insulating layer 110c as a low-resistance region, a high electric field is less likely to be generated near the drain region.

[0213] As with the insulating layer 110c, if the amount of impurities released from the insulating layer 110a is too high, the impurities may diffuse into the channel formation region. Even if a material that releases impurities is used for the insulating layers 110a and 110c, the amount of impurities released is preferably small.

[0214] exist Figure 19B In the embodiment, the thickness of the insulating layer 110a is set to thickness T110a, the thickness of the insulating layer 110b is set to thickness T110b_2, and the thickness of the insulating layer 110c is set to thickness T110c_2.

[0215] The thickness T110a of the insulating layer 110a may be, for example, 0.5 nm or more and less than 1 μm, 0.5 nm or more and 500 nm or less, 0.5 nm or more and 400 nm or less, 1 nm or more and 300 nm or less, 1 nm or more and 200 nm or less, 1 nm or more and 150 nm or less, 2 nm or more and 100 nm or less, 2 nm or more and 50 nm or less, 2 nm or more and 30 nm or less, 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, or 3 nm or more and 10 nm or less. Figure 19B As shown, thickness T110a may be the shortest distance between the formed surface of insulating layer 110a (here, the top surface of conductive layer 212a) and the bottom surface of insulating layer 110b in cross-sectional view.

[0216] When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a may increase, thereby increasing the amount of impurities diffused into the channel formation region. On the other hand, when the thickness T110a is small, oxygen in the insulating layer 110b may diffuse through the insulating layer 110a to the conductive layer 212a side, thereby reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T110a within the above range, the oxygen vacancies (V O ) and V OH. In addition, oxidation of the conductive layer 212a due to oxygen in the insulating layer 110b, which would otherwise increase the resistance of the conductive layer 212a, can be suppressed.

[0217] exist Figure 19B In the example shown, the channel length L200 of the transistor 200 corresponds to the length of the side surface of the insulating layer 110b in the opening 241 when viewed in cross section. Figure 19B In the example shown, the length L200 can be determined based on the thickness T110b_2 and the angle θ110 .

[0218] Figure 20A and Figure 20B They are Figure 17A and Figure 19A In the illustrated modification of the semiconductor device 20, a transistor 100A including a conductive layer 103 and an insulating layer 105 is provided as the transistor 100. Here, the semiconductor device 20 including the transistor 100A is referred to as a semiconductor device 20A. Figure 20B An example is shown in which the conductive layer 212 a is provided over the insulating layer 105 .

[0219] Figure 20C yes Figure 20B A modified example of the structure shown in FIG. 1 is a configuration in which the conductive layer 212a is provided between the insulating layer 101 and the insulating layer 105. Figure 20C In the example shown, the opening 241 is provided not only in the insulating layer 110 but also in the insulating layer 105. Figure 20C In the illustrated example, the conductive layer 212a can be formed using the same material and process as the conductive layer 103. For example, the conductive layer 103 and the conductive layer 212a can be formed by forming a conductive film to be the conductive layer 103 and the conductive layer 212a and processing the conductive film.

[0220] Figure 21A and Figure 21B They are Figure 17A and Figure 19A In the modified example of the semiconductor device 20 shown in FIG, the gate electrode of the transistor 100 is electrically connected to the other of the source electrode and the drain electrode of the transistor 200. Specifically, Figure 21A and Figure 21B An example is shown in which the gate electrode of the transistor 100 and the other of the source electrode and the drain electrode of the transistor 200 are both the conductive layer 104. Figure 21A and Figure 21B 2 shows an example in which the transistor 200 does not include the conductive layer 212b. Figure 21A and Figure 21B The semiconductor device 20 shown is referred to as a semiconductor device 20B.

[0221] exist Figure 21A and Figure 21B In the semiconductor device 20B shown, the insulating layer 110 and the insulating layer 106 include an opening 245 that reaches the conductive layer 212a. The transistor 200 is provided so as to have a region located inside the opening 245.

[0222] Conductive layer 104 includes opening 247 having an area overlapping with opening 245. The planar shape of opening 245 can be the same as the planar shape of opening 241, and the planar shape of opening 247 can be the same as the planar shape of opening 243. The planar shapes of opening 245 and opening 247 can be identical or substantially identical. In this case, the bottom end of conductive layer 104 on the side of opening 247 is preferably aligned or substantially aligned with the top end of insulating layer 106 on the side of opening 245.

[0223] Furthermore, the planar shape of the opening 245 may not be consistent with the planar shape of the opening 247. Furthermore, when the planar shapes of the openings 245 and 247 are circular, the openings 245 and 247 may or may not be concentric.

[0224] exist Figure 21A and Figure 21B In the illustrated semiconductor device 20B, the semiconductor layer 208 includes a region located within the opening 245 and a region located within the opening 247. The semiconductor layer 208 may be provided along the bottom and side surfaces of the opening 245 and the side surfaces of the opening 247. For example, the semiconductor layer 208 may include a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surfaces of the conductive layer 104, and a region in contact with the top surface of the conductive layer 104. Furthermore, the semiconductor layer 208 may include a region in contact with the side surfaces of the insulating layer 110 and a region in contact with the side surfaces of the insulating layer 106.

[0225] An insulating layer 206 serving as a gate insulating layer for transistor 200 is provided over semiconductor layer 208. Insulating layer 206 is provided to include a region located inside opening 245 and a region located inside opening 247. Specifically, it is provided to cover opening 245 and opening 247. Insulating layer 206 is provided over semiconductor layer 208, conductive layer 104, and insulating layer 106. Insulating layer 206 has a shape that extends along the top and side surfaces of semiconductor layer 208, the top and side surfaces of conductive layer 104, and insulating layer 106. Insulating layer 206 may include a region in contact with the top surface of semiconductor layer 208, a region in contact with the side surfaces of semiconductor layer 208, a region in contact with the top surface of conductive layer 104, a region in contact with the side surfaces of conductive layer 104, and a region in contact with insulating layer 106.

[0226] Conductive layer 204 is provided on insulating layer 206 so as to include a region located inside opening 245 and a region located inside opening 247. Conductive layer 204 is provided so as to include a region within opening 245 that faces semiconductor layer 208 with insulating layer 206 interposed therebetween. Conductive layer 204 can have a shape that follows insulating layer 206, specifically, a shape that follows the top surface of insulating layer 206 and the side surfaces of insulating layer 206 within openings 245 and 247. Furthermore, conductive layer 204 can include a region in contact with the top surface of insulating layer 206 and a region in contact with the side surfaces of insulating layer 206 within openings 245 and 247.

[0227] The semiconductor device 20 and the like can be used as a display device, for example, can be used as a pixel circuit included in the display device. Figure 22A This is a block diagram illustrating an example configuration of a display device 30, which is one embodiment of the present invention. The display device 30 includes a display unit 25, a scan line driver circuit 31, a signal line driver circuit 33, and a power supply circuit 35. The display unit 25 includes a plurality of pixels 21 arranged in a matrix. Alternatively, the power supply circuit 35 may be provided externally to the display device 30.

[0228] The scanning line driving circuit 31 is electrically connected to the pixels 21 via wirings 41. The wirings 41 extend in the row direction of the matrix, for example.

[0229] The signal line driving circuit 33 is electrically connected to the pixel 21 via the wiring 43. The wiring 43 extends in the column direction of the above-mentioned matrix, for example.

[0230] The power supply circuit 35 is electrically connected to the pixels 21 via the wiring 45. For example, all the pixels 21 may be electrically connected to the power supply circuit 35 via the same wiring 45.

[0231] exist Figure 22AIn the figure, wiring 41 and wiring 43 are represented by straight lines. However, a straight line is not limited to a single wiring line; multiple wiring lines may be represented by a single line. In the following block diagrams and circuit diagrams, multiple wiring lines may also be represented by a single line. Furthermore, wiring lines other than wiring 41 and wiring 43 may also be represented by a single line.

[0232] The pixel 21 includes a display element, and the display element can display an image on the display unit 25. As the display element, for example, a light-emitting element can be used, specifically, an organic EL element can be used. Alternatively, a liquid crystal element (also called a liquid crystal device) can be used as the display element.

[0233] The scan line driver circuit 31 has, for example, a function of selecting pixels 21 for which image data is to be written, row by row. Specifically, the scan line driver circuit 31 can select pixels 21 for which image data is to be written by outputting a signal to the wiring 41. Here, for example, the scan line driver circuit 31 can output the signal to the wiring 41 of the first row, then to the wiring 41 of the second row, and then to the wiring 41 of the last row, thereby selecting all pixels 21. Therefore, the signal output by the scan line driver circuit 31 to the wiring 41 is a scan signal, and the wiring 41 can be said to be a scan line.

[0234] The signal line driver circuit 33 has the function of generating image data. The image data is supplied to the pixels 21 via the wiring 43. For example, the image data can be written to all pixels 21 included in the row selected by the scan line driver circuit 31. Here, the image data can be expressed as a signal (image signal). Therefore, the wiring 43 can be said to be a signal line.

[0235] The power supply circuit 35 has the function of generating a power supply potential and supplying it to the wiring 45. For example, the power supply circuit 35 has the function of generating a high power supply potential (hereinafter referred to as "high potential" or "VDD") and supplying it to the wiring 45. Alternatively, the power supply circuit 35 may have the function of generating a low power supply potential (hereinafter referred to as "low potential" or "VSS"). Since the power supply potential is supplied to the wiring 45, the wiring 45 can be said to be a power supply line.

[0236] Figure 22B 2 is a plan view showing a structural example of a pixel 21. The pixel 21 may include a plurality of sub-pixels 23. Figure 22B The example in which the pixel 21 includes the sub-pixel 23R, the sub-pixel 23G, and the sub-pixel 23B is shown. Here, in the case where the pixel 21 includes a light-emitting element as a display element, for example Figure 22B The planar shape of the sub-pixel shown corresponds to the planar shape of the light-emitting region of the light-emitting element. Figure 22BThe aperture ratios (also known as the size or the size of the light-emitting area) of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B are equal or approximately equal, but one embodiment of the present invention is not limited to this. The aperture ratios of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B can be appropriately determined. The aperture ratios of sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B can be different from each other, or two or more of them can be equal or approximately equal.

[0237] In this specification and other documents, for example, when describing common features among sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B, the letters distinguishing these features may be omitted and the sub-pixel 23 may be referred to as sub-pixel 23. When describing common features among other components distinguished by letters, the symbols may be omitted and the letters may be used for the description.

[0238] exist Figure 22B In the illustrated pixel 21, a stripe arrangement is adopted as an arrangement method of the sub-pixels 23. Alternatively, the sub-pixels 23 may be arranged in an S-stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, or a Pentile arrangement.

[0239] Sub-pixels 23R, sub-pixels 23G, and sub-pixels 23B emit light of different colors. As sub-pixels 23R, sub-pixels 23G, and sub-pixels 23B, there can be cited sub-pixels of three colors of red (R), green (G), and blue (B), sub-pixels of three colors of yellow (Y), cyan (C), and magenta (M), etc. In addition, more than four sub-pixels 23 may be provided in the pixel 21. For example, sub-pixels of four colors of R, G, B, and white (W) may be provided in the pixel 21. Thus, by including a plurality of sub-pixels 23 that emit light of different colors in the pixel 21 in the display device 30, a full-color image can be displayed on the display unit 25. In addition, in the pixel 21, for example, sub-pixels of R, G, B, and infrared light (IR) may be provided.

[0240] Furthermore, the display unit 25 may be provided with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 25 may also function as a fingerprint sensor. For example, the display unit 25 may also function as an optical or ultrasonic fingerprint sensor.

[0241] Figure 22C is a circuit diagram showing a structural example of the sub-pixel 23 . Figure 22CThe sub-pixel 23 shown includes a pixel circuit 40A and a light-emitting element 60. As the light-emitting element 60, for example, an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used. Examples of the light-emitting substance contained in the light-emitting element 60 include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (such as quantum dot materials). In addition, as the light-emitting element 60, an LED such as a micro-LED (Light Emitting Diode) can also be used.

[0242] The pixel circuit 40A includes a transistor 200, a transistor 100, and a capacitor 57. That is, the pixel circuit 40A is a 2Tr (transistor) 1C (capacitor) type pixel circuit.

[0243] In the pixel circuit 40A, one of the source and drain of the transistor 200 is electrically connected to the wiring 43. The other of the source and drain of the transistor 200 is electrically connected to the gate of the transistor 100. The gate of the transistor 100 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 200 is electrically connected to the wiring 41.

[0244] One of the source and drain of transistor 100 is electrically connected to wiring 45. The other of the source and drain of transistor 100 is electrically connected to the other electrode of capacitor 57. The other electrode of capacitor 57 is electrically connected to one electrode of light-emitting element 60. The other electrode of light-emitting element 60 is electrically connected to wiring 47. Here, one electrode of light-emitting element 60 is referred to as a pixel electrode. Alternatively, for example, wiring 47 may be shared by all sub-pixels 23. Thus, the other electrode of light-emitting element 60 may be referred to as a common electrode.

[0245] As described above, wiring 41 functions as a scan line, wiring 43 functions as a signal line, and wiring 45 functions as a power supply line. Furthermore, wiring 47 functions as a power supply line. For example, when wiring 45 is supplied with a high power supply potential, wiring 47 is supplied with a low power supply potential. Wiring 47 can be electrically connected to power supply circuit 35, for example.

[0246] Transistor 200 functions as a switch and is also referred to as a select transistor. Transistor 200 controls the conductive state and non-conductive state between wiring 43 and the gate of transistor 100 based on the potential of wiring 41. When transistor 200 is turned on, image data is written to pixel circuit 40A. When transistor 200 is turned off, the written image data is retained. A high on-state current of transistor 200 is preferred because it allows for high-speed writing of image data to pixel circuit 40A.

[0247] Transistor 100 controls the amount of current flowing through light-emitting element 60 and is also referred to as a driver transistor. Capacitor 57 maintains the gate potential of transistor 100. The brightness of light-emitting element 60 is controlled based on the potential corresponding to image data supplied to the gate of transistor 100. Specifically, when wiring 45 is supplied with a high power supply potential and wiring 47 is supplied with a low power supply potential, the magnitude of the current flowing from wiring 45 to wiring 47 is controlled based on the gate potential of transistor 100. This controls the brightness of light-emitting element 60. High saturation of transistor 100 is preferred because it stabilizes the current flowing through light-emitting element 60 and the brightness of light-emitting element 60. For example, this can suppress temporal variations in the current flowing through light-emitting element 60 when a static image is displayed on display unit 25, thereby suppressing temporal variations in the brightness of light-emitting element 60.

[0248] As Figure 22C The transistor 100 and the transistor 200 shown can be used Figure 21A and Figure 21B 1 and 2. As shown in FIG. 1 , transistor 100 and transistor 200 are shown. As described above, transistor 100 has a longer channel length and higher saturation than transistor 200. In addition, transistor 100 can be a miniature transistor. Thus, by using transistor 100 as a drive transistor, the saturation of the drive transistor can be improved while miniaturizing the pixel 21 provided with the sub-pixel 23. As a result, the current flowing through the light-emitting element 60 can be stabilized, thereby stabilizing the luminance of the light-emitting element 60.

[0249] In addition, the channel length of transistor 200 is shorter than that of transistor 100. Therefore, compared with transistor 100, transistor 200 can increase the on-state current. In addition, transistor 200 can be a miniature transistor. Thus, by using transistor 200 as a selection transistor, the on-state current of the selection transistor can be increased while miniaturizing the pixel 21 provided with the sub-pixel 23. Therefore, image data can be written to the pixel 21 at high speed while miniaturizing the pixel 21.

[0250] Thus, by using the semiconductor device 20 in a display device, a display device with high definition, high reliability, and high-speed driving can be realized.

[0251] Here, for example Figure 3A and Figure 17A The width D141 shown is larger than Figure 19B When the thickness T110b_2 shown is large, the difference between the channel lengths of transistor 100 and transistor 200 can be increased. This can further increase the saturation of transistor 100 and the on-state current of transistor 200, which is preferable.

[0252] Figure 22D is a circuit diagram showing a structural example of the sub-pixel 23 . Figure 22D The sub-pixel 23 shown includes a pixel circuit 40B and a liquid crystal element 69 .

[0253] The pixel circuit 40B includes a transistor 50 and a capacitor 57. That is, the pixel circuit 40B is a 1Tr1C type pixel circuit.

[0254] In pixel circuit 40B, one of the source and drain of transistor 50 is electrically connected to wiring 43. The other of the source and drain of transistor 50 is electrically connected to one electrode of capacitor 57. One electrode of capacitor 57 is electrically connected to one electrode of liquid crystal element 69. The gate of transistor 50 is electrically connected to wiring 41. The other electrode of capacitor 57 and the other electrode of liquid crystal element 69 are electrically connected to wiring 45. Here, one electrode of liquid crystal element 69 is also referred to as a pixel electrode. In addition, the other electrode of liquid crystal element 69 is sometimes referred to as a common electrode. In pixel circuit 40B, for example, wiring 45 is supplied with a ground potential.

[0255] In the pixel circuit 40B, the transistor 50 functions as a switch, and has a function of controlling the conductive state or non-conductive state between the wiring 43 and one electrode of the liquid crystal element 69 according to the potential of the wiring 41. When the transistor 50 is turned on, image data is written to the pixel circuit 40B, and when the transistor 50 is turned off, the written image data is retained.

[0256] The capacitor 57 has a function of holding the potential of one electrode of the liquid crystal element 69. The alignment state of the liquid crystal element 69 is controlled by the potential corresponding to the image data supplied to the one electrode of the liquid crystal element 69.

[0257] As the mode of the liquid crystal element 69, for example, the following modes can be used: TN (Twisted Nematic) mode; STN (Super-Twisted Nematic) mode; VA (Vertical Alignment) mode; ASM (Axially Symmetric Aligned Micro-cell) mode; OCB (Optically Compensated Birefringence) mode; FLC (Ferroelectric Liquid Crystal) mode; AFLC (AntiFerroelectric Liquid Crystal) mode; MVA (Multidomain Vertical Alignment) mode; PVA (Patterned Vertical Alignment) mode; IPS (In Plane Switching) mode; FFS (Fringe Field Switching) mode; or TBA (Transverse Bend Alignment) mode, etc. Other examples include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode. Note that the present invention is not limited to these, and various modes can be used.

[0258] Transistor 50 can have the same structure as transistor 100 or transistor 200 described in this specification and other documents. By making transistor 50 have the same structure as transistor 100, for example, the channel length of transistor 50 can be increased compared to a case where transistor 50 has the same structure as transistor 200, thereby reducing the off-state current of transistor 50. As a result, image data can be retained in sub-pixel 23 for a long time. On the other hand, by making transistor 50 have the same structure as transistor 200, for example, the channel length of transistor 50 can be shortened compared to a case where transistor 50 has the same structure as transistor 100, thereby increasing the on-state current of transistor 50. As a result, image data can be written to sub-pixel 23 at a high speed.

[0259] Figure 23AIt shows Figure 22C FIG. 4 is a plan view of a structural example of a pixel circuit 40A shown in FIG. Figure 23B is omitted Figure 23A The conductive layer 104 is shown shaded and represented as a plan view with dashed lines. Figure 23A and Figure 23B The insulating layer 110 is not shown. Figure 23C It is along Figure 23A A cross-sectional view of the section taken along the dot-dash line C1-C2. Figure 23C An example of the structure of the capacitor 57 is shown.

[0260] exist Figure 23A In the example shown, transistor 100 and transistor 200 have the same Figure 21A The same structure as shown in Figure 23C As shown, capacitor 57 includes conductive layer 112 b on insulating layer 110 , insulating layer 106 on conductive layer 112 b , and conductive layer 104 on insulating layer 106 .

[0261] At least a portion of the conductive layer 212a is used as a wiring 43 having a function as a signal line, and is connected to the conductive layer 212a. Figure 22A At least a portion of the conductive layer 112a is used as a wiring 45 having a function as a power supply line and is electrically connected to the signal line driver circuit 33 shown. Figure 22A At least a portion of the conductive layer 204 is used as a wiring 41 having a scanning line function and is electrically connected to the power supply circuit 35 shown. Figure 22A The scan line driving circuit 31 shown is electrically connected.

[0262] Figure 24A and Figure 24B They are Figure 17A and Figure 19A In the modified example of the semiconductor device 20 shown in FIG, the other of the source electrode and the drain electrode of the transistor 100 is electrically connected to the other of the source electrode and the drain electrode of the transistor 200. Specifically, Figure 24A and Figure 24B An example is shown in which the other of the source electrode and the drain electrode of the transistor 100 and the other of the source electrode and the drain electrode of the transistor 200 are both the conductive layer 112b. Figure 24A and Figure 24B 2 shows an example in which the transistor 200 does not include the conductive layer 212b. Figure 24A and Figure 24B The semiconductor device 20 shown is referred to as a semiconductor device 20C. In the transistor 200 included in the semiconductor device 20C, the semiconductor layer 208 may have a region in contact with a side surface of the conductive layer 112b and a region in contact with a top surface of the conductive layer 112b.

[0263] Figure 25A is a block diagram showing an example of the structure of the display device 30, and Figure 22A A modified example of the display device 30 is shown. Figure 25A The display device 30 shown is Figure 22A The display device 30 shown differs in that: Figure 25A The display device 30 shown includes a wiring 41 a and a wiring 41 b as the wiring 41 , and is provided with a reference potential generating circuit 37 .

[0264] The reference potential generating circuit 37 is electrically connected to the pixel 21 via the wiring 48. For example, all pixels 21 can be electrically connected to the reference potential generating circuit 37 via the same wiring 48. For example, the reference potential generating circuit 37 has a function of generating a reference potential for correcting the uneven gate-source voltage (the potential difference between the source and the drain) of each driving transistor and supplying it to the wiring 48. The potential of the wiring 48 becomes the reference potential, so the wiring 48 can be called a reference potential line. In addition, the reference potential generating circuit 37 can also be called a power supply circuit. In addition, the power supply circuit 35 and the reference potential generating circuit 37 can also be combined to form a single circuit. For example, the power supply circuit 35 can also include the reference potential generating circuit 37.

[0265] Figure 25B It shows Figure 25A 1 is a circuit diagram showing a structural example of a sub-pixel 23 included in a pixel 21 shown. Figure 25B The sub-pixel 23 shown includes a pixel circuit 40C and a light-emitting element 60 .

[0266] The pixel circuit 40C includes a transistor 51, a transistor 100, a transistor 200, and a capacitor 57. That is, the pixel circuit 40C is a 3Tr (transistor) 1C (capacitor) type pixel circuit.

[0267] In the pixel circuit 40C, one of the source and drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and drain of the transistor 51 is electrically connected to the gate of the transistor 100. The gate of the transistor 100 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41a.

[0268] One of the source and drain of transistor 100 is electrically connected to wiring 45. One of the source and drain of transistor 200 is electrically connected to wiring 48. The other of the source and drain of transistor 100 is electrically connected to the other of the source and drain of transistor 200. The other of the source and drain of transistor 200 is electrically connected to the other electrode of capacitor 57. The other electrode of capacitor 57 is electrically connected to one electrode of light-emitting element 60. The gate of transistor 200 is electrically connected to wiring 41 b. The other electrode of light-emitting element 60 is electrically connected to wiring 47.

[0269] In pixel circuit 40C, transistor 51 serves as a select transistor. Transistor 100 serves as a drive transistor. Transistor 200 serves as a switch, controlling the conductive state and non-conductive state between wiring 48 and one electrode of light-emitting element 60 based on the potential of wiring 41b. Wiring 48 is supplied with, for example, a reference potential. The reference potential of wiring 48 supplied by transistor 200 suppresses variations in gate-source voltage of each transistor 100 provided in each of the plurality of sub-pixels 23.

[0270] Furthermore, wiring 48 can be used as a monitoring line for outputting the current flowing through transistor 100 or the current flowing through light-emitting element 60 to the outside of sub-pixel 23. The current output to wiring 48 can be converted into a potential by, for example, a source follower circuit. Alternatively, it can be converted into a digital signal by, for example, an AD converter.

[0271] As Figure 25B The transistor 100 and the transistor 200 shown can be used Figure 24A and Figure 24B The transistor 100 and the transistor 200 are shown. By using the transistor 100 as a driving transistor, the saturation of the driving transistor can be improved while miniaturizing the sub-pixel 23. In addition, by using the transistor 200 as a transistor electrically connected to the wiring 48 serving as a reference potential line, the reference potential can be supplied to the pixel circuit 40C at high speed while miniaturizing the sub-pixel 23. Note that the transistor 51 can be, for example, a transistor having the same structure as the transistor 200.

[0272] Figure 26A It shows Figure 25B FIG. 4 is a plan view of a structural example of a pixel circuit 40C shown in FIG. Figure 26A The insulating layer 110 is not shown. Figure 26B It is along Figure 26A A cross-sectional view of the section taken along the dot-dash line C3-C4. Figure 26B An example of the structure of the transistor 51 and the capacitor 57 is shown.

[0273] exist Figure 26A In the example shown, transistor 100 and transistor 200 have the same Figure 24AThe transistor 51 has the same structure as that shown in FIG. The transistor 51 includes a conductive layer 72a serving as one of a source electrode and a drain electrode, a conductive layer 112b serving as the other of the source electrode and the drain electrode, a semiconductor layer 78 having a channel formation region, an insulating layer 106 serving as a gate insulating layer, and a conductive layer 74 serving as a gate electrode. The insulating layer 110 has an opening 71 extending to the conductive layer 72a, and the conductive layer 112b has an opening 73 having a region overlapping with the opening 71. The semiconductor layer 78, the insulating layer 106, and the conductive layer 74 are arranged so as to have a region located within the opening 71 and a region located within the opening 73.

[0274] As described above, the transistor 51 may be a transistor having the same structure as the transistor 200. Figure 26A and Figure 26B In the illustrated example, the conductive layer 72 a , the semiconductor layer 78 , the conductive layer 74 , the opening 71 , and the opening 73 correspond to the conductive layer 212 a , the semiconductor layer 208 , the conductive layer 204 , the opening 241 , and the opening 243 , respectively.

[0275] For details about capacitor 57, please refer to Figure 23C Description.

[0276] like Figure 26B As shown, insulating layer 106 includes opening 75 that reaches conductive layer 112b, and conductive layer 112b is electrically connected to conductive layer 104 inside opening 75. Specifically, for example, inside opening 75 there is a region where conductive layer 112b and conductive layer 104 are in contact.

[0277] Although Figure 26A The planar shape of the middle opening portion 75 is circular, but one embodiment of the present invention is not limited thereto and may be the same shape as that of the opening portion 141 , the same shape as that of the opening portion 241 , or the same shape as that of the opening portion 243 .

[0278] At least a portion of the conductive layer 72a is used as a wiring 43 having a function as a signal line, and is connected to the conductive layer 72a. Figure 25A At least a portion of the conductive layer 112a is used as a wiring 45 having a function as a power supply line and is electrically connected to the signal line driver circuit 33 shown. Figure 25A At least a portion of the conductive layer 212a is used as a wiring 48 having a function as a reference potential line and is electrically connected to the power supply circuit 35 shown. Figure 25A At least a portion of the conductive layer 74 is used as a wiring 41a having a function as a scanning line and is electrically connected to the reference potential generating circuit 37 shown. Figure 25AAt least a portion of the conductive layer 204 is used as a wiring 41b having a scanning line function and is electrically connected to the scanning line driving circuit 31 shown. Figure 25A The scan line driving circuit 31 shown is electrically connected.

[0279] Although examples in which the insulating layer 110 has a single-layer structure, a two-layer stacked structure, or a three-layer stacked structure are described in this embodiment, the insulating layer 110 may have a stacked structure of four or more layers.

[0280] Similar to the semiconductor device 10, the semiconductor device 20 described in this embodiment can be provided with the insulating layer 147 and the insulating layer 149. In this case, the insulating layer 147 and the insulating layer 149 can also be provided between the insulating layer 110 and the semiconductor layer 208, and between the conductive layer 212b and the semiconductor layer 208. For example, the insulating layer 147 can have a region in contact with the top surface of the conductive layer 212a and a region in contact with the side surface of the conductive layer 212b in the opening 243. In addition, the insulating layer 149 can have a region in contact with the semiconductor layer 208.

[0281] Figure 27 It shows Figure 25A 1 is a circuit diagram showing a structural example of a sub-pixel 23 included in a pixel 21 shown. Figure 27 The sub-pixel 23 shown includes a pixel circuit 40D and a light-emitting element 60 .

[0282] Pixel circuit 40D includes transistor Tr1, transistor Tr2, transistor Tr3, transistor Tr4, transistor Tr5, transistor Tr6, transistor Tr7, capacitor C1, capacitor C2, and capacitor C3. In other words, pixel circuit 40D is a 7Tr (transistor) 3C (capacitor) type pixel circuit. Here, transistor Tr2 is a dual-gate transistor consisting of a first gate and a second gate. Hereinafter, the first gate of transistor Tr2 is simply referred to as the gate, and the second gate is referred to as the back gate.

[0283] In pixel circuit 40D, one of the source and drain of transistor Tr1 is electrically connected to the gate of transistor Tr2, one of the source and drain of transistor Tr3, and one electrode of capacitor C1. One of the source and drain of transistor Tr2 is electrically connected to the other of the source and drain of transistor Tr3, one of the source and drain of transistor Tr5, one of the source and drain of transistor Tr6, the other electrode of capacitor C1, and one electrode of capacitor C2. The back gate of transistor Tr2 is electrically connected to one of the source and drain of transistor Tr4 and the other electrode of capacitor C2. The other of the source and drain of transistor Tr5 is electrically connected to one electrode of capacitor C3 and one electrode of light-emitting element 60. The gate of transistor Tr5 is electrically connected to one of the source and drain of transistor Tr7 and the other electrode of capacitor C3.

[0284] In the pixel circuit 40D, a node electrically connected to one of the source and drain of the transistor Tr2, the other of the source and drain of the transistor Tr3, one of the source and drain of the transistor Tr5, one of the source and drain of the transistor Tr6, the other electrode of the capacitor C1, and one electrode of the capacitor C2 is referred to as node N1. Furthermore, a node electrically connected to the back gate of the transistor Tr2, one of the source and drain of the transistor Tr4, and the other electrode of the capacitor C2 is referred to as node N2. Furthermore, a node electrically connected to one of the source and drain of the transistor Tr1, the gate of the transistor Tr2, one of the source and drain of the transistor Tr3, and one electrode of the capacitor C1 is referred to as node N3. Furthermore, a node electrically connected to the gate of the transistor Tr5, one of the source and drain of the transistor Tr7, and the other electrode of the capacitor C3 is referred to as node N4.

[0285] The pixel circuit 40D is electrically connected to wiring 41a, wiring 41b, and wiring 41c, which are wirings 41. Wiring 41a is electrically connected to the gates of transistors Tr1, Tr6, and Tr7. Wiring 41b is electrically connected to the gates of transistors Tr3 and Tr4. Wiring 41c is electrically connected to the other of the source and drain of transistor Tr7.

[0286] Wiring 43 is electrically connected to the other of the source and drain of transistor Tr1. Wiring 45 is electrically connected to the other of the source and drain of transistor Tr2. Wiring 48 is electrically connected to the other of the source and drain of transistor Tr6. Wiring 49 is electrically connected to the other of the source and drain of transistor Tr4.

[0287] Transistor Tr1 and transistors Tr3 to Tr7 function as switches. Transistors Tr1, Tr6, and Tr7 are turned on or off based on the potential of wiring 41a. Transistors Tr3 and Tr4 are turned on or off based on the potential of wiring 41b. Transistor Tr5 is turned on or off based on the potential of wiring 41c when transistor Tr7 is on.

[0288] When the on-state currents of transistors Tr1, Tr6, and Tr7 are large, the pixel circuit 40D can be driven at high speed, which is preferable. As described above, the on-state current of transistor 200 can be larger than the on-state current of transistor 100. Therefore, transistor 200 is preferably used as transistor Tr1 and transistors Tr3 to Tr7.

[0289] By turning on transistor Tr1, the gate potential of transistor Tr2 becomes a potential corresponding to the potential of wiring 43. Furthermore, wiring 43 is electrically connected to a signal line driver circuit 33 that generates image data. Thus, by turning on transistor Tr1, image data can be written to pixel circuit 40D, and by turning off transistor Tr1, the written image data can be retained. Transistor Tr1 is also called a select transistor.

[0290] Transistor Tr2 controls the amount of current flowing through light-emitting element 60 and is also called a drive transistor. Capacitor C1 maintains the gate potential of transistor Tr2. The brightness of light-emitting element 60 is controlled based on the potential supplied to the gate of transistor Tr2 according to image data. Specifically, when a high power supply potential is supplied to wiring 45 and a low power supply potential is supplied to wiring 47, the amount of current flowing from wiring 45 to wiring 47 is controlled based on the gate potential of transistor Tr2. This controls the brightness of light-emitting element 60.

[0291] When the saturation of transistor Tr2 is high, it is preferable because it stabilizes the current flowing through light-emitting element 60 and stabilizes the luminance of light-emitting element 60. As described above, the saturation of transistor 100 can be higher than that of transistor 200, for example. Furthermore, transistor 100A is a dual-gate transistor 100. Therefore, transistor 100A or transistor 100F, for example, can be used as transistor Tr2.

[0292] Transistor Tr5 has the function of controlling the emission and quenching of light-emitting element 60. When transistors Tr3 and Tr6 are off, turning transistor Tr5 on causes a current corresponding to the gate potential of transistor Tr2 to flow through light-emitting element 60, thereby causing light-emitting element 60 to emit light. On the other hand, turning transistor Tr5 off prevents current from flowing through light-emitting element 60 regardless of the gate potential of transistor Tr2, thereby preventing light-emitting element 60 from emitting light, i.e., quenching the light-emitting element 60.

[0293] In pixel circuit 40D, wiring 48 may function as a monitoring line that outputs the current flowing through transistor Tr2, which functions as a drive transistor, or the current flowing through light-emitting element 60, to the outside of subpixel 23. In this case, the threshold voltage of transistor Tr2 can be corrected. Specifically, the threshold voltage of transistor Tr2 can be corrected by controlling the backgate potential of transistor Tr2. The backgate potential of transistor Tr2 can be held in capacitor C2.

[0294] <Example of a method for driving a display device> The following describes with reference to the accompanying drawings Figure 27 An example of a driving method of the sub-pixel 23 is shown. Figure 28 40D is a timing chart showing an example of a driving method of the pixel circuit 40D. Figures 29 to 35 This circuit diagram shows the states of pixel circuit 40D during each period in the timing chart. Here, potentials Va, Vc, V0, and V1 are supplied to wiring 45, wiring 47, wiring 48, and wiring 49, respectively. Furthermore, a high potential or a low potential is supplied to wiring 41a, wiring 41b, and wiring 41c, respectively.

[0295] A high potential is a potential that turns an n-channel transistor on when supplied to its gate, and a low potential is a potential that turns an n-channel transistor off when supplied to its gate. The following description assumes that transistors Tr1 through Tr7 are all n-channel transistors. However, by appropriately reversing the potential magnitude relationship, for example, the following description can be applied even if at least some of transistors Tr1 through Tr7 are p-channel transistors.

[0296] Potential Va is the anode potential, and potential Vc is the cathode potential. Potential Va is higher than potential Vc and potential V0. In addition, potential V1 is higher than potential V0. Figures 28 to 35 In the description, the potential V0 is set to 0 V.

[0297] The pixel circuit 40D has a function of controlling the magnitude of the current flowing through the light emitting element 60 according to the image signal supplied from the wiring 43. The light emission brightness of the light emitting element 60 is controlled according to the magnitude of the current.

[0298] Note that, for example, in timing diagrams and circuit diagrams showing pixel driving methods, symbols indicating potentials such as "H", "L", "V0" or "V1" (also referred to as "potential symbols") are sometimes attached adjacent to terminals or wirings. Here, "H" represents a high potential, and "L" represents a low potential. In addition, for example, in circuit diagrams showing pixel driving methods, in order to facilitate understanding of potential changes in terminals and wirings, the potential symbols attached to terminals and wirings that have undergone potential changes are sometimes represented in the form of frames. In addition, an "×" symbol is sometimes attached to overlap with a transistor in an off state. Furthermore, current is sometimes represented by a dotted arrow. When current is represented by a dotted arrow, the direction in which the current flows is sometimes opposite to the direction indicated by the arrow.

[0299] The current flowing through the light-emitting element 60 is primarily determined by the aforementioned image signal and the threshold voltage of the transistor Tr2. Therefore, even when the same image signal is supplied to a plurality of pixel circuits 40D arranged in a matrix, if the threshold voltages of the transistors Tr2 included in each pixel circuit 40D differ, the current flowing through the light-emitting element 60 will differ. Therefore, variations in the threshold voltage of the transistor Tr2 contribute to degradation in display quality.

[0300] In view of this, the unevenness of the current flowing through the light emitting element 60 is reduced by obtaining the threshold voltage of the transistor Tr2 in each sub-pixel 23. Note that the operation of obtaining the threshold voltage of the transistor Tr2 is sometimes referred to as "threshold voltage correction operation."

[0301] [Threshold voltage correction operation] Before the period T1, the potentials of the wirings 41a and 41b are low, and the potential of the wiring 41c is high. During the period T1, a reset operation is performed. Specifically, a high potential is supplied to the wirings 41a, 41b, and 41c (see Figure 29 ). A high potential is supplied to the wiring 41a, thereby turning on the transistors Tr1, Tr6, and Tr7. A high potential is supplied to the wiring 41b, thereby turning on the transistors Tr3 and Tr4.

[0302] Node N1 is supplied with potential V0 via transistor Tr6. Node N2 is supplied with potential V1 via transistor Tr4. Node N3 is supplied with potential V0 via transistors Tr6 and Tr3. A high potential is supplied from wiring 41c to node N4 via transistor Tr7, turning on transistor Tr5.

[0303] In the period T1, the wiring 43 and the wiring 48 are turned on by the transistors Tr1, Tr3, and Tr6. Therefore, in the period T1, it is preferable to make the wiring 43 and the wiring 48 have the same potential or to make the wiring 43 floating. Figure 29 An example is shown in which the potential of the wiring 43 is the same potential V0 as the potential of the wiring 48 .

[0304] During period T1, the potential of node N1 is lower than the potential of wiring 45. Therefore, current can flow between the source of transistor Tr2 and node N1. Because the potentials of node N3 and node N1 are both at potential V0, the gate-source voltage of transistor Tr2 is 0 V. Furthermore, because the potential of node N2 is at potential V1 and the potential of node N1 is at potential V0, the backgate-source voltage of transistor Tr2 (the potential difference between the backgate and source) is "V1-V0".

[0305] During the period T2, a low potential is supplied to the wiring 41c (see Figure 30 ). As a result, a low potential is supplied from the wiring 41c to the node N4 via the transistor Tr7, and the transistor Tr5 is turned off.

[0306] During the period T3, a low potential is supplied to the wiring 41a (see Figure 31 ). As a result, transistors Tr1, Tr6, and Tr7 are turned off. In this state, the potential of the back gate of transistor Tr2 is V1, and current flows from wiring 45 to node N1. As a result, the potential of node N1 rises. In addition, because transistor Tr3 is in the on state, the potential of node N3 also rises. Specifically, the potential of nodes N1 and N3 rises to a value "V1-Vth" obtained by subtracting the threshold voltage Vth of transistor Tr2 from the potential V1 of the back gate of transistor Tr2. Therefore, the back gate-source voltage of transistor Tr2 reaches the threshold voltage Vth.

[0307] During the period T4, a low potential is supplied to the wiring 41b (see Figure 32 ). As a result, transistors Tr3 and Tr4 are turned off. Nodes N1, N2, and N3 are then floating. Consequently, the threshold voltage of transistor Tr2 is corrected.

[0308] Note that a small current may sometimes flow between wiring 45 and wiring 47. Consequently, during period T4, the potential of node N1 may sometimes decrease. Furthermore, as the potential of node N1 decreases, the potentials of node N2 and node N3 may also decrease. In this case, the back gate-source voltage of transistor Tr2 remains at the threshold voltage Vth.

[0309] [Data writing work] During the period T5, the potential Vdata corresponding to the image signal is supplied to the wiring 43. In this state, a high potential is supplied to the wiring 41a and the wiring 41c (see Figure 33 ). A high potential is supplied to wiring 41a, turning on transistors Tr1, Tr6, and Tr7. Transistor Tr1 is turned on, causing potential Vdata to be supplied to node N3, and image data to be written to subpixel 23. Transistor Tr6 is turned on, causing potential V0 to be supplied to node N1. Consequently, the gate-source voltage of transistor Tr2 becomes "Vdata - V0," which is Vdata when potential V0 is 0V.

[0310] Nodes N1 and N2 are capacitively coupled via capacitor C2. Therefore, when the potential of node N1 changes from "V1-Vth" to "V0," the potential of node N2 also changes. The potential of node N2 is represented by "V1-(V1-Vth-V0)." That is, the potential of node N2 becomes "Vth+V0," and when potential V0 is 0V, it reaches the threshold voltage Vth.

[0311] A high potential is supplied from the wiring 41c to the node N4 via the transistor Tr7, thereby turning on the transistor Tr5. As a result, the potential V0 is supplied to the anode of the light emitting element 60 via the transistors Tr6 and Tr5.

[0312] 〔Luminous Work〕 During the period T6, a low potential is supplied to the wiring 41a (see Figure 34 ). Consequently, transistors Tr1, Tr6, and Tr7 are turned off. Turning transistor Tr6 off causes current to flow from wiring 45 to wiring 47. Consequently, current Ie flows through light-emitting element 60, causing light-emitting element 60 to emit light at a brightness corresponding to current Ie. Furthermore, as current flows from wiring 45 to wiring 47, the potential of node N1 and the potential of the anode of light-emitting element 60 rise.

[0313] Nodes N2 and N3 are now floating. Nodes N1 and N3 are capacitively coupled via capacitor C1. During period T6, when the potential of node N1 changes from V0 to Va1, the potential of node N3 also changes. Here, the potential of node N3 becomes "Vdata + Va1." That is, even if the source potential of transistor Tr2 changes, the gate-source voltage of transistor Tr2 remains at Vdata.

[0314] Likewise, as the potential of the node N1 changes, the potential of the node N2 becomes “Vth+Va1.” Therefore, the back gate-source voltage of the transistor Tr2 is maintained at Vth.

[0315] Furthermore, the anode of light-emitting element 60 is capacitively coupled to node N4 via capacitor C3. Consequently, when the potential of the anode of light-emitting element 60 changes from potential V0 to potential Va2, the potential of node N4 also changes. Here, the potential of node N4 becomes "H + Va2." This means that even if the potential of the anode of light-emitting element 60, which corresponds to the source of transistor Tr5, changes, the gate-source voltage of transistor Tr5 can be maintained at a high potential.

[0316] For example, when the gate of transistor Tr5 has a fixed potential, when the source potential of transistor Tr5 rises, the gate-source voltage decreases. When the gate-source voltage is less than the threshold voltage of transistor Tr5, transistor Tr5 is in the off state. Therefore, when the anode potential of light-emitting element 60 is increased, it is also necessary to supply a high potential to the gate of transistor Tr5, and a power supply or power supply circuit needs to be provided. In view of this, capacitor C3 is provided between the gate and source of transistor Tr5 to form a bootstrap circuit, thereby maintaining the on state of transistor Tr5 even if the anode potential of light-emitting element 60 is increased, without providing a power supply circuit. Therefore, current Ie can be stably supplied to light-emitting element 60. Note that capacitor C3 is sometimes referred to as a "bootstrap capacitor". In addition, capacitor C1 and capacitor C2 are each used as a bootstrap capacitor.

[0317] As described above, the amount of current Ie flowing through the light-emitting element 60 is determined by the potential Vdata corresponding to the image signal and the threshold voltage Vth of the transistor Tr2. In the pixel circuit 40D, the amount of current Ie flowing through the light-emitting element 60 can be controlled by the potential Vdata by performing a threshold correction operation.

[0318] The brightness of the light-emitting element 60 is controlled by the potential Vdata. Therefore, during the light-emitting operation, transistor Tr5 must be reliably turned on. In the pixel circuit 40D, transistor Tr5 can be reliably turned on during the light-emitting operation. This allows for accurate control of the current Ie, thereby improving the color reproducibility of halftones. This improves the display quality of the display device according to one embodiment of the present invention.

[0319] 〔Quenching work〕 During the period T7, a high potential is supplied to the wiring 41a, and a low potential is supplied to the wiring 41c (see Figure 35A high potential is supplied to wiring 41a, turning on transistors Tr1, Tr6, and Tr7. Transistor Tr6 is turned on, applying potential V0 to node N1. Transistor Tr4 is turned off, and nodes N1 and N2 are capacitively coupled via capacitor C2. Therefore, as the potential of node N1 changes, the potential of node N2 becomes "Vth + V0."

[0320] The low potential is supplied from the wiring 41c to the node N4 via the transistor Tr7, thereby turning off the transistor Tr5. As a result, no current flows through the light emitting element 60, and the light emitting element 60 stops emitting light.

[0321] Note that during the period T7 , the potential VdataX corresponding to the image data written to the other sub-pixels 23 electrically connected to the wiring 43 may be supplied to the node N3 via the transistor Tr1 . However, since the transistor M5 is in the off state, the quenching operation is not affected.

[0322] A display device using a light-emitting element such as an EL element as a display element can continuously emit light from the light-emitting element during a frame period. This driving method is also called "hold type" or "hold type drive." By adopting hold type drive as the driving method for a display device, flickering of the display screen can be reduced. On the other hand, hold type drive is prone to afterimages and image blur when displaying dynamic images. The resolution perceived by humans when displaying dynamic images is also called "dynamic image resolution." In other words, the dynamic image resolution of hold type drive is easily reduced.

[0323] Furthermore, "black insertion drive" is known as a method for improving afterimages and image blur when displaying moving images. This method, also known as "pseudo-pulse drive" or "pseudo-impulse drive," displays black every other frame or for a specified period within a frame.

[0324] The display device including the pixel circuit 40D can easily realize black insertion driving by the quenching operation. Therefore, the display device is unlikely to reduce the resolution of moving images and can realize moving image display with high display quality.

[0325] After the period T7, the potential of the wiring 41a is lowered to a low potential, and then the potential of the wiring 41c is raised to a high potential. The above is an example of a driving method of the pixel circuit 40D.

[0326] Figure 36A 、 Figure 36B 、 Figure 37A 、 Figure 37B 、 Figure 38A 、 Figure 38B and Figure 3940D is a plan view showing a structural example of a pixel circuit 40D. Figure 36A 、 Figure 36B and Figure 37A , the components of transistors Tr1 to Tr7 are shown. Figure 37B 、 Figure 38A 、 Figure 38B and Figure 39 , in addition to the components of transistors Tr1 to Tr7, components of capacitors C1, C2, and C3 are also shown. Figures 36A to 39 In the example shown, transistor Tr2 is used Figure 16A The transistor 100G shown in FIG. 1 is a transistor 100G. In addition, as the transistor Tr1 and the transistors Tr3 to Tr7, for example, Figure 20A Transistor 200 is shown.

[0327] exist Figure 36A , conductive layer 901A, conductive layer 901B, conductive layer 901C, conductive layer 901D, conductive layer 901E, conductive layer 901F, conductive layer 901G, conductive layer 903A, conductive layer 903B, conductive layer 903C, conductive layer 903D, and conductive layer 903E are shown. Figures 36A to 39 In the figures, conductive layers denoted by the same reference numerals (with letters omitted) can all be formed using the same material and through the same process. For example, conductive layers 901A to 901G can all be formed using the same material and through the same process. Furthermore, conductive layers 903A to 903E can all be formed using the same material and through the same process.

[0328] Conductive layer 901A corresponds to conductive layer 103 included in transistor 100G and is used as a back gate electrode of transistor Tr2. Conductive layers 903A to 903E all correspond to conductive layer 212a included in transistor 200. Conductive layer 903A is used as one of the source electrode and drain electrode of transistors Tr1 and Tr3. Conductive layer 903B is used as one of the source electrode and drain electrode of transistor Tr4. Conductive layer 903C is used as one of the source electrode and drain electrode of transistor Tr5. Conductive layer 903D is used as one of the source electrode and drain electrode of transistor Tr6. Conductive layer 903E is used as one of the source electrode and drain electrode of transistor Tr7. Here, conductive layer 903D is used as Figure 27 Wiring 48 is shown.

[0329] exist Figure 36B In addition to Figure 36AIn addition to the components shown, conductive layer 905A, conductive layer 905B, conductive layer 905C, conductive layer 905D, conductive layer 905E, conductive layer 905F, conductive layer 905G, conductive layer 905H, semiconductor layer 909A, semiconductor layer 909B, semiconductor layer 909C, semiconductor layer 909D, semiconductor layer 909E, semiconductor layer 909F, semiconductor layer 909G and semiconductor layer 909H are also shown.

[0330] The conductive layer 905A corresponds to the conductive layer 212b included in the transistor 200 and serves as the other of the source electrode and the drain electrode of the transistor Tr1. The conductive layer 905B corresponds to the conductive layer 112a included in the transistor 100G and serves as one of the source electrode and the drain electrode of the transistor Tr2. The conductive layer 905C corresponds to the conductive layer 112b included in the transistor 100G and serves as the other of the source electrode and the drain electrode of the transistor Tr2. The conductive layer 905D corresponds to the conductive layer 112c included in the transistor 100G.

[0331] Conductive layers 905E to 905H all correspond to the conductive layer 212b included in the transistor 200. The conductive layer 905E serves as the other of the source and drain electrodes of the transistors Tr3 and Tr6. The conductive layer 905F serves as the other of the source and drain electrodes of the transistor Tr4. The conductive layer 905G serves as the other of the source and drain electrodes of the transistor Tr5. The conductive layer 905H serves as the other of the source and drain electrodes of the transistor Tr7.

[0332] Insulation layer 110 (not shown) is provided with openings 907A, 907B, 907C, 907D, 907E, 907F, 907G, and 907H. Opening 907A corresponds to, for example, Figure 20A The opening 241 shown in FIG. 1 reaches the conductive layer 903A. The opening 907B corresponds to Figure 16A The opening 141[1] shown in FIG. 1 reaches the conductive layer 901A. The opening 907C corresponds to Figure 16A The opening 141[2] shown reaches the conductive layer 901A.

[0333] Openings 907D to 907H are equivalent to Figure 20A Opening 907D reaches conductive layer 903A. Opening 907E reaches conductive layer 903B. Opening 907F reaches conductive layer 903C. Opening 907G reaches conductive layer 903D. Opening 907H reaches conductive layer 903E.

[0334] Conductive layer 905A has opening 908A formed so as to overlap with opening 907A. Conductive layer 905E has opening 908B formed so as to overlap with opening 907D, and opening 908E formed so as to overlap with opening 907G. Conductive layer 905F has opening 908C formed so as to overlap with opening 907E. Conductive layer 905G has opening 908D formed so as to overlap with opening 907F. Conductive layer 905H has opening 908F formed so as to overlap with opening 907H.

[0335] Semiconductor layer 909A corresponds to semiconductor layer 208 in transistor 200 and is provided to include a region located within opening 907A and a region located within opening 907B. Semiconductor layer 909B corresponds to semiconductor layer 108[1] in transistor 100G and is provided to include a region located within opening 907B. Semiconductor layer 909C corresponds to semiconductor layer 108[2] in transistor 100G and is provided to include a region located within opening 907C.

[0336] Semiconductor layers 909D to 909H correspond to semiconductor layer 208 in transistor 200. Semiconductor layer 909D is provided so as to include a region located within opening 907D and a region located within opening 908B. Semiconductor layer 909E is provided so as to include a region located within opening 907E and a region located within opening 908C. Semiconductor layer 909F is provided so as to include a region located within opening 907F and a region located within opening 908D. Semiconductor layer 909G is provided so as to include a region located within opening 907G and a region located within opening 908E. Semiconductor layer 909H is provided so as to include a region located within opening 907H and a region located within opening 908F.

[0337] exist Figure 37A In addition to Figure 36B In addition to the components shown, conductive layers 911A, 911B, 911C, and 911D are also shown. The conductive layer 911A corresponds to the conductive layer 204 included in the transistor 200 and serves as the gate electrode of the transistors Tr1, Tr6, and Tr7. The conductive layer 911B corresponds to the conductive layer 104 included in the transistor 100G and serves as the gate electrode of the transistor Tr2.

[0338] The conductive layer 911C and the conductive layer 911D correspond to the conductive layer 204 included in the transistor 200. The conductive layer 911C serves as a gate electrode of the transistor Tr3 and the transistor Tr4, and the conductive layer 911D serves as a gate electrode of the transistor Tr5.

[0339] exist Figure 37B In addition to Figure 37A In addition to the components shown, conductive layers 913A, 913B, 913C, 913D, 913E, 913F, 913G, 913H, 913I, 913J, and 913K are shown. Figure 37B In the following plan views showing an example of the structure of the pixel circuit 40D, reference numerals of some components are omitted.

[0340] Conductive layer 913A serves as one electrode of capacitor C1. Conductive layer 913B serves as one electrode of capacitor C2. Conductive layer 913G serves as one electrode of capacitor C3.

[0341] Conductive layer 913A is electrically connected to conductive layer 903A via contact hole 917A and to conductive layer 911B via contact hole 921B. Conductive layer 913B is electrically connected to conductive layer 901A via contact hole 915A and to conductive layer 903B via contact hole 917B. Conductive layer 913C is electrically connected to conductive layer 901B via contact hole 915B and to conductive layer 911C via contact hole 921C. Conductive layer 913D is electrically connected to conductive layer 901C via contact hole 915C and to conductive layer 911A via contact hole 921A. Conductive layer 913E is electrically connected to conductive layer 901G via contact hole 915D and to conductive layer 905H via contact hole 919G. Conductive layer 913F is electrically connected to conductive layer 905C via contact hole 919C. Conductive layer 913G is electrically connected to conductive layer 903E via contact hole 917D, and is electrically connected to conductive layer 911D via contact hole 921D. Conductive layer 913H is electrically connected to conductive layer 905A via contact hole 919A. Conductive layer 913I is electrically connected to conductive layer 905B via contact hole 919B. Conductive layer 913J is electrically connected to conductive layer 903C via contact hole 917C, to conductive layer 905E via contact hole 919D, and to conductive layer 905G via contact hole 919F. Conductive layer 913K is electrically connected to conductive layer 905F via contact hole 919E.

[0342] In this specification and other documents, a contact hole refers to an opening that electrically connects two conductive layers. In other words, a contact hole is one form of opening. "A and B are electrically connected through a contact hole" includes cases where a plug is provided in the contact hole, electrically connecting A and B through the plug. Furthermore, it also includes cases where at least one of A and B has a region located within the contact hole, and A and B make contact within the contact hole, thereby electrically connecting A and B. The contact hole can be provided, for example, in an insulating layer.

[0343] exist Figure 38A In addition to Figure 37B In addition to the components shown, conductive layer 923A and conductive layer 923B are shown. Conductive layer 923A serves as the other electrode of capacitor C1 and the other electrode of capacitor C2. Conductive layer 923B serves as the other electrode of capacitor C3.

[0344] Insulating layers serving as dielectrics are provided between conductive layers 913A and 923A, between conductive layers 913B and 923A, and between conductive layers 913G and 923B. The overlapping region of conductive layers 913A and 923A functions as capacitor C1, the overlapping region of conductive layers 913B and 923A functions as capacitor C2, and the overlapping region of conductive layers 913G and 923B functions as capacitor C3.

[0345] exist Figure 38B In addition to Figure 38A In addition to the illustrated components, a conductive layer 925A, a conductive layer 925B, a conductive layer 925C, a conductive layer 925D, a conductive layer 925E, a conductive layer 925F, a conductive layer 925G, and a conductive layer 925H functioning as leads are also illustrated.

[0346] Conductive layer 925A is electrically connected to conductive layer 913C via contact hole 927A. Conductive layer 925B is electrically connected to conductive layer 913D via contact hole 927B. Conductive layer 925C is electrically connected to conductive layer 913E via contact hole 927C. Conductive layer 925D is electrically connected to conductive layer 913J via contact hole 927D and to conductive layer 923B via contact hole 929B. Conductive layer 925E is electrically connected to conductive layer 913H via contact hole 927E. Conductive layer 925F is electrically connected to conductive layer 913I via contact hole 927F. Conductive layer 925G is electrically connected to conductive layer 913J via contact hole 927G and to conductive layer 923A via contact hole 929A. Conductive layer 925H is electrically connected to conductive layer 913K via contact hole 927H.

[0347] The conductive layer 925A is used as Figure 27 The conductive layer 925B is used as the wiring 41b shown. Figure 27The conductive layer 925C is used as the wiring 41a shown. Figure 27 The conductive layer 925F is used as the wiring 41c shown. Figure 27 Wiring 45 is shown.

[0348] exist Figure 39 In addition to Figure 38B In addition to the components shown, conductive layers 931A, 931B, and 931C serving as leads are also shown. Conductive layer 931A is electrically connected to conductive layer 925D via contact hole 933A. Conductive layer 931B is electrically connected to conductive layer 925E via contact hole 933B. Conductive layer 931C is electrically connected to conductive layer 925H via contact holes 933C and 933D.

[0349] The conductive layer 931B is used as Figure 27 The conductive layer 931C is used as the wiring 49.

[0350] [Semiconductor Layer 108 and Semiconductor Layer 208] The metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 are described in detail. Examples of the metal oxide include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is a metal element or semimetal element with a high bond energy with oxygen, for example, a metal element or semimetal element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and “metal elements” described in this specification and the like may include semi-metal elements.

[0351] The semiconductor layer 108 and the semiconductor layer 208 can be made of, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (A Indium-zinc oxide (also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc. Alternatively, indium tin oxide (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. containing silicon may be used.

[0352] By increasing the ratio of the number of indium atoms contained in the metal oxide to the total number of atoms of all metal elements, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0353] Note that the metal oxide may also replace indium or contain one or more metal elements with a large period number in the periodic table in addition to indium. There is a trend that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As such metal elements, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0354] Metal oxides may also contain one or more non-metallic elements. When a metal oxide contains non-metallic elements, the carrier concentration may increase or the band gap may narrow, thereby improving the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0355] Increasing the ratio of zinc atoms to the total number of atoms of all metal elements in a metal oxide increases the metal oxide's crystallinity, suppressing the diffusion of impurities within the metal oxide. This reduces fluctuations in transistor electrical characteristics and improves reliability.

[0356] When the ratio of the number of atoms of the element M to the total number of atoms of all metal elements in the metal oxide is increased, the formation of oxygen vacancies (V O ). Therefore, it is caused by oxygen vacancies (V O ) is suppressed, making it possible to form a transistor with a low off-state current. In addition, the variation in the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0357] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be achieved.

[0358] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of the atomic ratio of the metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these ratios. Note that these near-range compositions fall within a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can improve the on-state current and field-effect mobility of the transistor.

[0359] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of the atomic ratio of metal elements in such an In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions near these. By increasing the ratio of the number of atoms of M in the metal oxide, oxygen vacancies (V O ) is generated.

[0360] Note that when a plurality of metal elements are included as the element M, the total ratio of the number of atoms of the metal elements may be the ratio of the number of atoms of the element M.

[0361] In this specification, etc., the ratio of the number of indium atoms to the total number of atoms of all metal elements contained may be described as the indium content. The same applies to other metal elements.

[0362] By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current and field effect mobility of the transistor can be improved. In addition, by including the element M, the generation of oxygen vacancies (V O ). The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements) is preferably not less than 0.1% and not more than 3%, more preferably not less than 0.1% and not more than 2%. Thus, a transistor with good electrical characteristics can be realized. For example, it is preferred to use metal oxides of In:M:Zn=40:1:10 and the like. The element M is preferably any one or more of the above-mentioned elements, more preferably one or more selected from aluminum, gallium, tin and yttrium. Specifically, metal oxides of In:Sn:Zn=40:1:10 and the like can be appropriately used. Alternatively, metal oxides of In:Al:Zn=40:1:10 and the like can be appropriately used.

[0363] Here, by using a polycrystalline metal oxide for semiconductor layers 108 and 208, grain boundaries become recombination centers, trapping carriers, which may reduce the on-state current of the transistor. When using a metal oxide with a composition that easily forms a polycrystalline structure, it is preferable to include an element that hinders crystallization. For example, compared to indium tin oxide (ITO), indium tin oxide (ITSO) containing silicon is less likely to form a polycrystalline structure, so it can be suitably used for semiconductor layers 108 and 208. When using ITSO, the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, more preferably 3% to 15%, and more preferably 5% to 15%. Specifically, metal oxides with a ratio of In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8, and their approximate ratios can be suitably used.

[0364] For example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the semiconductor layer 108 and the semiconductor layer 208. Alternatively, a combination of multiple methods can be used for analysis. Note that the actual content of an element with a low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0365] The metal oxide can be formed using sputtering or atomic layer deposition (ALD) as appropriate. Note that when forming the metal oxide using sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content of the formed metal oxide may be reduced to approximately 50% of that of the sputtering target.

[0366] Semiconductor layer 108 and semiconductor layer 208 may also have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in semiconductor layer 108 and semiconductor layer 208 may also have the same or substantially the same composition. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0367] The two or more metal oxide layers included in semiconductor layer 108 and semiconductor layer 208 may also have different compositions. For example, a stacked structure may be suitably constructed of a first metal oxide layer having an atomic ratio of In:M:Zn = 1:3:4 or approximately thereabouts, and a second metal oxide layer having an atomic ratio of In:M:Zn = 1:1:1 or approximately thereabouts disposed on the first metal oxide layer. Gallium, aluminum, or tin is particularly preferred as the element M. The element M in the first and second metal oxide layers may be the same or different. For example, the first and second metal oxide layers may be IGZO layers having different compositions.

[0368] For example, a stacked structure of a first metal oxide layer having a composition of In:Zn=4:1 [atomic ratio] or thereabouts and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts provided on the first metal oxide layer can be appropriately used.

[0369] For example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0370] Note that when there is a stacked structure having a first metal oxide layer containing a first metal oxide and a second metal oxide layer containing a second metal oxide, and the composition of the first metal oxide is the same as or approximately the same as the composition of the second metal oxide, the boundary (interface) between the first metal oxide layer and the second metal oxide layer may not be clearly confirmed.

[0371] Semiconductor layers 108 and 208 preferably include a crystalline metal oxide. Examples of crystalline metal oxide structures include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. Using a crystalline metal oxide reduces the defect state density in semiconductor layers 108 and 208, thereby achieving a highly reliable semiconductor device.

[0372] It is preferable that CAAC-OS or nc-OS be used for each of the semiconductor layer 108 and the semiconductor layer 208 .

[0373] CAAC-OS has a plurality of layered crystals. The c-axis of the crystal is oriented in the normal direction of the formed surface. Both the semiconductor layer 108 and the semiconductor layer 208 preferably have layered crystals parallel or approximately parallel to the formed surface. For example, it is preferred that the semiconductor layer 208 has layered crystals parallel or approximately parallel to the top surface in the region in contact with the top surface of the conductive layer 212b, and layered crystals parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 212b. In particular, the semiconductor layer 208 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110 as the formed surface in the opening portion 241. By adopting this structure, the layered crystals of the semiconductor layer 208 are formed in a manner parallel or approximately parallel to the channel length direction of the transistor 200, so that a transistor with a large on-state current can be realized. Similarly, the semiconductor layer 108 preferably has layered crystals that are parallel or substantially parallel to the surface on which it is formed (here, the side surfaces of the insulating layer 110, the side surfaces of the conductive layer 112a, and the side surfaces of the conductive layer 112b). In particular, the semiconductor layer 108 preferably has layered crystals that are parallel or substantially parallel to the side surfaces of the insulating layer 110, which is the surface on which it is formed, in the region overlapping with the conductive layer 104.

[0374] By using a metal oxide with high crystallinity in the channel formation region, the defect state density in the channel formation region can be reduced. On the other hand, by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0375] When forming a metal oxide using a sputtering method, the higher the substrate temperature during formation, the more likely a metal oxide with high crystallinity will be formed. The substrate temperature during formation can be adjusted, for example, based on the temperature of the stage on which the substrate is placed during formation. In addition, the higher the flow rate ratio of the oxygen gas relative to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the more likely a metal oxide with high crystallinity will be formed.

[0376] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD) patterns, transmission electron microscope (TEM) images, or electron diffraction (ED) patterns, or by combining a plurality of these methods.

[0377] When metal oxide is used as the semiconductor layer 108 and the semiconductor layer 208, it is preferable to minimize the V OH to make it high purity intrinsic or substantially high purity intrinsic. In order to obtain this V O The metal oxide with sufficiently reduced H is mainly characterized by: removing impurities such as water and hydrogen from the metal oxide (sometimes described as dehydration or dehydrogenation treatment); and supplying oxygen to the metal oxide to repair oxygen vacancies (V O ). By setting V O Metal oxides with sufficiently reduced impurities such as H are used in the channel formation region of transistors to provide stable electrical characteristics. Note that oxygen is sometimes supplied to the metal oxide to repair oxygen vacancies (V O ) is recorded as oxidation treatment.

[0378] When metal oxide is used as the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration in the channel formation region is preferably 1×10 18 cm -3 less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , more preferably less than 1×10 12 cm -3 Note that there is no lower limit on the carrier concentration in the channel formation region, and it can be, for example, 1×10 -9 cm -3 .

[0379] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits for flat-panel detectors of X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0380] Semiconductor layer 108 and semiconductor layer 208 may also include a layered material that functions as a semiconductor. Layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity per unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0381] As the above-mentioned layered substances, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (belonging to Group 16 elements). In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used in the channel formation region of the transistor, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0382] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 103, conductive layer 212a, conductive layer 212b, and conductive layer 204] The conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204 may have a single-layer structure or a stacked structure of two or more layers. Examples of materials that can be used for the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204 include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the foregoing metals. A low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be suitably used for the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204. Among these, copper and aluminum are particularly preferred due to their advantages in mass production.

[0383] Conductive metal oxides (oxide conductors) can be used for the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (ITO containing silicon, also known as ITSO), zinc oxide doped with gallium, and In-Ga-Zn oxide. In particular, conductive oxides containing indium are preferably used because they have high conductivity.

[0384] For example, oxygen vacancies form in a metal oxide that exhibits semiconductor properties. Hydrogen addition to these oxygen vacancies creates donor levels near the conduction band. As a result, the metal oxide's conductivity increases, making it a conductor. Metal oxides that can function as conductors are called oxide conductors.

[0385] A stacked-layer structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy may be employed as the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204. The use of a conductive film containing a metal or alloy can reduce wiring resistance.

[0386] A Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204. The use of a Cu-X alloy film allows processing by wet etching, thereby reducing manufacturing costs.

[0387] Note that materials used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may be the same or different.

[0388] Conductive layer 112a and conductive layer 112b have regions in contact with semiconductor layer 108. Conductive layer 212a and conductive layer 212b have regions in contact with semiconductor layer 208. When a metal oxide is used as semiconductor layer 108, there is a concern that when a metal that is easily oxidized (e.g., aluminum) is used as conductive layer 112a and conductive layer 112b, insulating oxide (e.g., aluminum oxide) may form between conductive layer 112a and semiconductor layer 108, and between conductive layer 112b and semiconductor layer 108, thereby hindering electrical conduction therebetween. Similarly, when a metal oxide is used as semiconductor layer 208, there is a concern that when a metal that is easily oxidized is used as conductive layer 212a and conductive layer 212b, insulating oxide may form between conductive layer 212a and semiconductor layer 208, and between conductive layer 212b and semiconductor layer 208, thereby hindering electrical conduction therebetween. Therefore, the conductive layers 112a, 112b, 212a, and 212b preferably use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even when oxidized, or an oxide conductive material.

[0389] Conductive layers 112a, 112b, 212a, and 212b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These materials are preferred because they are conductive materials that are not easily oxidized or maintain low resistance even when oxidized.

[0390] The conductive layers 112a, 112b, 212a, and 212b can use the aforementioned oxide conductors. Specifically, conductive oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide doped with gallium can be used.

[0391] A nitride conductor may be used for the conductive layers 112a, 112b, 212a, and 212b. Examples of the nitride conductor include tantalum nitride and titanium nitride.

[0392] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 104 may all have a stacked-layer structure. In this case, it is preferred that a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material be used for at least the region in contact with the semiconductor layer 108 or the semiconductor layer 208. In addition, a material having a low resistivity is preferably used for the region not in contact with the semiconductor layer 108 or the semiconductor layer 208. Thus, the resistance of the conductive layer can be reduced. For example, In-Sn-Si oxide (ITSO) can be appropriately used for the region in contact with the semiconductor layer 108 or the semiconductor layer 208, and copper or tungsten can be appropriately used for the region not in contact with the semiconductor layer 108 or the semiconductor layer 208.

[0393] [Insulating layer 106, insulating layer 105, and insulating layer 206] The insulating layer 106, the insulating layer 105, and the insulating layer 206 can have a single-layer structure or a stacked-layer structure of two or more layers. The insulating layer 106, the insulating layer 105, and the insulating layer 206 preferably include one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating films include oxides, nitrides, oxynitrides, and oxynitrides. The insulating layer 106, the insulating layer 105, and the insulating layer 206 can use the same material that can be used for the insulating layer 110.

[0394] The insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the insulating layer 105 has a region in contact with the semiconductor layer 108, and the insulating layer 206 has a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, at least the portion of the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108 and the semiconductor layer 208 is preferably made of any of the aforementioned oxides and oxynitrides. Furthermore, at least the portion of the film constituting the insulating layer 105 that is in contact with the semiconductor layer 108 is preferably made of any of the aforementioned oxides and oxynitrides. Furthermore, at least the portion of the film constituting the insulating layer 206 that is in contact with the semiconductor layer 208 is preferably made of any of the aforementioned oxides and oxynitrides. Furthermore, a film that releases oxygen upon heating is preferably used for the insulating layers 106, 105, and 206.

[0395] Specifically, when the insulating layer 106, the insulating layer 105, and the insulating layer 206 have a single-layer structure, oxide or oxynitride is preferably used for the insulating layer 106, the insulating layer 105, and the insulating layer 206. Specifically, silicon oxide or silicon oxynitride can be appropriately used for the insulating layer 106, the insulating layer 105, and the insulating layer 206.

[0396] When the insulating layer 106 has a stacked-layer structure, the insulating film on the side in contact with the semiconductor layer 108 and the semiconductor layer 208 preferably includes an oxide or an oxynitride, and the insulating film on the side in contact with the conductive layer 204 and the conductive layer 104 preferably includes a nitride or an oxynitride. Furthermore, when the insulating layer 105 has a stacked-layer structure, the insulating film on the side in contact with the semiconductor layer 108 preferably includes an oxide or an oxynitride, and the insulating film on the side in contact with the conductive layer 103 preferably includes a nitride or an oxynitride. Furthermore, when the insulating layer 206 has a stacked-layer structure, the insulating film on the side in contact with the semiconductor layer 208 preferably includes an oxide or an oxynitride, and the insulating film on the side in contact with the conductive layer 204 preferably includes a nitride or an oxynitride. Silicon oxide or silicon oxynitride can be suitably used as the oxide or oxynitride, for example. Silicon nitride or silicon oxynitride can be suitably used as the nitride or oxynitride, for example.

[0397] Silicon nitride and silicon oxynitride have the characteristics of releasing very little impurities (for example, water and hydrogen) and not easily permeating oxygen and hydrogen. Therefore, they can be suitably used as the insulating layers 106, 105, and 206. Since diffusion of impurities from the insulating layers 106, 105, and 206 into the semiconductor layers 108 and 208 is suppressed, favorable electrical characteristics of the transistor can be achieved, and reliability can be improved.

[0398] Note that in micro transistors, when the thickness of the gate insulating layer is small, the leakage current sometimes increases. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. As high-k materials that can be used for the insulating layer 106, the insulating layer 105, and the insulating layer 206, for example, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium can be cited.

[0399] [Insulation layer 109] The insulating layer 109, which serves as a protective layer for transistors 100 and 200, is preferably made of a material that is less susceptible to impurity diffusion. The insulating layer 109 effectively suppresses the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0400] The insulating layer 109 may be an insulating layer composed of an inorganic material or an insulating layer composed of an organic material. For example, an inorganic material such as an oxide, an oxynitride, an oxynitride, or a nitride may be used as appropriate for the insulating layer 109. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate may be used. As an organic material, for example, one or more of an acrylic resin and a polyimide resin may be used. A photosensitive material may also be used as the organic material. Furthermore, two or more of the above insulating films may be stacked. The insulating layer 109 may have a stacked structure of an insulating layer composed of an inorganic material and an insulating layer composed of an organic material.

[0401] [Substrate 102] While the material of the substrate 102 is not particularly limited, it must at least have heat resistance sufficient to withstand subsequent heat treatment. For example, the substrate 102 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. Furthermore, a semiconductor element may be provided on the substrate 102. Note that the semiconductor substrate and the insulating substrate may have a circular or angular shape.

[0402] A flexible substrate may be used as substrate 102, and transistors 100 and 200 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between substrate 102 and transistors 100 and 200. Providing a release layer allows for fabrication of part or all of a semiconductor device on the release layer, followed by separation from substrate 102 and transfer to another substrate. In this case, transistors 100 and 200 may also be transferred to a substrate with low heat resistance or a flexible substrate.

[0403] As the substrate 102 , an insulating layer may be stacked over the above substrate.

[0404] <Example 1 of Method for Manufacturing Semiconductor Device> Hereinafter, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. Note that regarding the materials and formation methods of each component, descriptions of the same components as those already described may be omitted.

[0405] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), ALD, and molecular beam epitaxy (MBE). CVD methods include PECVD and thermal CVD. Furthermore, one thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0406] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or doctor blade coating.

[0407] When processing thin films that constitute semiconductor devices, photolithography can be used, for example. Alternatively, thin films can be processed using nanoimprinting, sandblasting, lift-off, and other methods. Furthermore, island-shaped thin films can be directly formed using a deposition method using a shadow mask such as a metal mask.

[0408] Photolithography typically involves two methods. One involves forming a resist mask on the film to be processed, processing the film by, for example, etching, and then removing the resist mask. The other involves depositing a photosensitive film, exposing it to light, and developing it to shape the film into the desired shape.

[0409] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used. In addition, an electron beam can also be used instead of the light used for exposure. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0410] In etching the thin film, one or more of a dry etching method, a wet etching method, and a sandblasting method may be used.

[0411] Reference Figures 40A to 41C illustrate Figure 17A and Figure 17B An example of a method for manufacturing the semiconductor device 20 is shown. Figures 40A to 41C It is along Figure 17A A cross-sectional view along the dot-dash line A3-A4 in FIG.

[0412] First, an insulating layer 101 ( Figure 40A The insulating layer 101 can be formed, for example, by sputtering, CVD, or ALD. When the insulating layer 101 has a multi-layer structure, at least one of the layers may be formed using a different method than the other layers. The above description also applies to the other insulating layers, conductive layers, and semiconductor layers described below.

[0413] Next, a conductive film to be the conductive layer 212a is formed over the insulating layer 101, and the conductive film is processed to form the conductive layer 212a ( Figure 40A ) The conductive film can be formed by appropriately utilizing a sputtering method.

[0414] Next, insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b are formed on insulating layer 101 and conductive layer 212a. Figure 40A ).

[0415] The insulating layers 110a, 110b, and 110c can be formed by, for example, ALD, sputtering, or CVD. For example, the insulating layer 110a can be formed by ALD, and the insulating layers 110b and 110c can be formed by sputtering.

[0416] Here, by depositing the insulating layer 110b in an oxygen-containing atmosphere, the insulating layer 110b can be made to contain a large amount of oxygen. For example, by depositing the insulating layer 110b in an oxygen-containing atmosphere using a sputtering method, the insulating layer 110b can be made to contain a large amount of oxygen. Furthermore, by depositing the insulating layer 110b using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 110b can be reduced. By depositing the insulating layer 110b in this manner, oxygen can be supplied from the insulating layer 110b to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 to be formed in subsequent steps, thereby reducing oxygen vacancies.

[0417] Alternatively, an oxide film may be formed on the insulating layer 110 b by sputtering in an oxygen-containing atmosphere to supply oxygen.

[0418] There are no restrictions on the conductivity of the oxide film. The oxide film can be at least one of an insulating film, a semiconductor film, and a conductive film. Examples of the oxide film include aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide, or silicon-containing indium tin oxide.

[0419] As the oxide film, an oxide material containing one or more elements common to those of the semiconductor layer 108 is preferably used. In particular, an oxide semiconductor material that can be used for the semiconductor layer 108 is preferably used.

[0420] When forming an oxide film, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the processing chamber of the deposition apparatus (oxygen flow ratio) or the oxygen partial pressure within the processing chamber, the greater the amount of oxygen supplied to the insulating layer 110 b. The oxygen flow ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, and more preferably 80% to 100%.

[0421] In this way, by forming the oxide film by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating layer 110b while preventing oxygen from being released from the insulating layer 110b during the oxide film formation. As a result, a large amount of oxygen can be enclosed in the insulating layer 110b. Furthermore, a large amount of oxygen can be supplied to the semiconductor layer 108 during the subsequent heat treatment. As a result, oxygen vacancies in the semiconductor layer 108 and V O H, and a transistor with good electrical characteristics and high reliability can be realized.

[0422] Alternatively, heat treatment may be performed after the oxide film is formed. By performing heat treatment after the oxide film is formed, oxygen can be appropriately supplied from the oxide film to the insulating layer 110 b.

[0423] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 150°C or higher and 450°C or lower, further preferably 150°C or higher and 350°C or lower, and even more preferably 200°C or higher and 300°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Dry air (CDA: Clean Dry Air) can also be used as a nitrogen-containing atmosphere or an oxygen-containing atmosphere. Note that the content of hydrogen, oxygen, etc. in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferably used. By using an atmosphere with as low a content of hydrogen, water, etc. as possible, absorption of hydrogen, water, etc. by the insulating layer 110b, etc. can be prevented as much as possible. This heat treatment can be performed in an oven or a rapid thermal annealing (RTA: Rapid Thermal Annealing) apparatus. By using an RTA apparatus, the heat treatment time can be shortened.

[0424] After the oxide film is formed or after the above-mentioned heat treatment, oxygen may also be supplied to the insulating layer 110b through the oxide film. Examples of oxygen supply methods include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. In the plasma treatment of the semiconductor device manufacturing method according to one embodiment of the present invention, for example, an apparatus for converting oxygen gas into plasma using high-frequency power can be appropriately used. Examples of apparatus for converting gas into plasma using high-frequency power include plasma etching equipment and plasma ashing equipment.

[0425] Alternatively, heat treatment may be performed after forming the insulating layer 101, the conductive layer 212a, the insulating layer 110a, and the insulating layer 110b and before forming the oxide film. Heat treatment can remove water and hydrogen from the surface and film of the insulating layer 110b.

[0426] Next, the oxide film is removed.

[0427] The method for removing the oxide film is not particularly limited, and chemical mechanical polishing (CMP) or etching can be used. When removing the oxide film by etching, wet etching can suppress etching of the insulating layer 110b during the removal of the oxide film.

[0428] Note that the oxygen supply treatment for the insulating layer 110b is not limited to the above-mentioned method. For example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment may be performed without forming the above-mentioned oxide film on the insulating layer 110b. Alternatively, a film that inhibits oxygen detachment may be formed on the insulating layer 110b, and then oxygen may be supplied to the insulating layer 110b through the film. Preferably, the film is removed after the oxygen is supplied. As the above-mentioned film that inhibits oxygen detachment, a conductive film or semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten may be used.

[0429] Here, it is preferable to form insulating layers 110a and 110c in a manner that does not easily allow oxygen to pass through. For example, it is preferable to form insulating layers 110a and 110c in a manner that does not easily allow oxygen to pass through compared to insulating layer 110b. Furthermore, insulating layers 110a and 110c are preferably formed in a manner that has a small oxygen diffusion coefficient. For example, it is preferable to form insulating layers 110a and 110c in a manner that has a smaller oxygen diffusion coefficient than insulating layer 110b. This can prevent oxygen in insulating layer 110b from diffusing through insulating layer 110a into conductive layer 212a and then through insulating layer 110c into conductive layers 112a, 112b, and 212b to be formed in subsequent steps. This can prevent the resistance of conductive layers 112a, 112b, 212a, and 212b from increasing. At the same time, diffusion of oxygen in the insulating layer 110b to the insulating layer 110a and the insulating layer 110c can be suppressed, thereby increasing the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor and reducing oxygen vacancies (V O ) and V O H. Thus, a transistor having good electrical characteristics and high reliability can be manufactured.

[0430] Figure 40A The figure shows an example in which the insulating layer 110 is planarized, specifically, the insulating layer 110b is planarized. Planarization can be performed, for example, using a CMP method. Note that, as described above, the insulating layer 110a may be planarized, while the insulating layer 110b may not be planarized. If the insulating layer 110b is not planarized, the insulating layer 110c may or may not be planarized.

[0431] Next, a conductive film 112f (which will become the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b in the subsequent steps) is formed on the insulating layer 110c. Figure 40B ) The conductive film 112f can be formed by, for example, sputtering as appropriate.

[0432] Next, a portion of the conductive film 112f is removed to form openings 143 and 243 in the conductive film 112f ( Figure 40C The conductive film 112f can be processed by etching, and is preferably processed by dry etching from the viewpoint of microfabrication.

[0433] Next, a portion of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c is removed to form the opening 141 and the opening 241 in the insulating layer 110 ( Figure 40D ). Opening 141 is formed so as to have a region overlapping with opening 143 and reach insulating layer 101. Opening 241 is formed so as to have a region overlapping with opening 243 and reach conductive layer 212a. Parts of insulating layers 110a, 110b, and 110c can be removed by etching, preferably by dry etching from the perspective of microfabrication.

[0434] Alternatively, a portion of the conductive layer 212a in a region overlapping with the opening 241 may be removed during or after the formation of the opening 241. When the thickness of the conductive layer 212a in a region in contact with the bottom surface of the semiconductor layer 208 to be formed in a later step is thinner than the thickness of a region not in contact with the semiconductor layer 208, the electric field applied to the gate electrode in the channel formation region near the conductive layer 212a can be enhanced, thereby increasing the on-state current of the transistor 200.

[0435] Next, the conductive film 112f is processed to form the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b ( Figure 40E ). The conductive layer 112a and the conductive layer 112b are formed so as to face each other with the opening 141 therebetween when viewed from a planar perspective. In addition, the conductive layer 212b is formed so as to have an opening 243. As described above, the conductive film 112f can be processed by etching, and from the viewpoint of microfabrication, processing by dry etching is preferred.

[0436] Next, a heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed, for example, under a nitrogen or inert gas atmosphere. The heat treatment may also be performed under reduced pressure. By performing the heat treatment, impurities such as water in the insulating layers 101 and 110 may be reduced prior to the deposition of the metal oxide films that will become the semiconductor layers 108 and 208, which will be described later.

[0437] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment contains a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using highly purified gas for the heat treatment, for example, it is possible to minimize moisture absorption by the insulating layers 101 and 110. Alternatively, the heat treatment may be performed after forming the openings 143 and 243 in the conductive film 112 f and before forming the conductive layers 112 a, 112 b, and 212 b.

[0438] Next, a semiconductor film 108f ( 108f ) to be the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141 , the opening 241 , and the opening 243 . Figure 41A The semiconductor film 108f can be formed so as to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, a region in contact with the side surface of the conductive layer 112b, a region in contact with the top surface of the conductive layer 212a, a region in contact with the top surface of the conductive layer 212b, a region in contact with the side surface of the conductive layer 212b, a region in contact with the top surface of the insulating layer 110, a region in contact with the side surface of the insulating layer 110 in the opening 141, a region in contact with the side surface of the insulating layer 110 in the opening 241, and a region in contact with the top surface of the insulating layer 101.

[0439] A metal oxide film, specifically an oxide semiconductor film, can be used as the semiconductor film 108f. The semiconductor film 108f can be formed, for example, by sputtering, CVD, or ALD. The semiconductor film 108f is preferably deposited using a deposition method with good coverage, more preferably CVD or ALD. For example, an In-Ga-Zn oxide can be deposited using ALD as the oxide semiconductor film. Note that when the side surfaces of the openings 141, 241, and 243 have a tapered shape, the semiconductor film 108f can be deposited using sputtering.

[0440] Furthermore, it is preferable to perform microwave treatment in, for example, an oxygen-containing atmosphere during or after deposition of the semiconductor film 108f to reduce the impurity concentration in the semiconductor film 108f. Examples of impurities include hydrogen and carbon. Microwave treatment can also improve the crystallinity of the semiconductor film 108f. Microwave treatment, for example, refers to treatment using an apparatus that includes a power source for generating high-density plasma using microwaves.

[0441] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmatized using microwaves or high frequencies such as RF (Radio Frequency) to allow the oxygen plasma to act. In addition, as oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O radicals, which are atoms, molecules, or ions with unpaired electrons). In addition, the oxygen acting on the oxide semiconductor can be any one or more of the above forms, and oxygen free radicals are particularly preferred.

[0442] Furthermore, heating the substrate during the microwave treatment in the oxygen-containing atmosphere is preferred because it can further reduce the impurity concentration in the semiconductor film 108f. The substrate can be heated at a temperature of 100°C to 650°C, preferably 200°C to 600°C, and more preferably 300°C to 450°C.

[0443] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere as described above, the carbon concentration in the oxide semiconductor film measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0444] The semiconductor film 108f may have a stacked structure of more than two layers. In this case, the deposition methods of the layers may be the same or different. For example, when the semiconductor film 108f has a two-layer stacked structure, the lower semiconductor film 108f may be deposited by sputtering and the upper semiconductor film 108f may be deposited by ALD. The oxide semiconductor film deposited by sputtering may easily have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower semiconductor film 108f, the crystallinity of the upper semiconductor film 108f may be improved. In addition, even if pinholes or breaks are formed in the lower oxide semiconductor film deposited by sputtering, the portion overlapping with the pinholes or breaks may be blocked by the upper semiconductor film 108f deposited by ALD with good coverage.

[0445] After forming the semiconductor film 108f, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the oxide semiconductor film does not undergo polycrystallization, and can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, and then in order to compensate for the detached oxygen, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0446] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes moisture absorption by, for example, the oxide semiconductor film.

[0447] Here, the heat treatment is preferably performed while the semiconductor film 108f is in contact with the insulating layer 110b containing a large amount of oxygen. This allows oxygen to be supplied from the insulating layer 110b to the portion of the semiconductor film that will form the channel formation region of the semiconductor film 108f, thereby reducing oxygen vacancies.

[0448] Note that although the heat treatment is performed after the semiconductor film 108f is deposited, the present invention is not limited to this and the heat treatment may be performed in a later step.

[0449] Next, the semiconductor film 108f is processed to form the semiconductor layer 108 and the semiconductor layer 208 ( Figure 41B When a metal oxide film is used as the semiconductor film 108f, the semiconductor layer 108 and the semiconductor layer 208 may be layers containing metal oxide. The semiconductor film 108f can be processed by etching, and from the perspective of microfabrication, dry etching is preferably used.

[0450] The semiconductor layer 108 is formed to include a region located within the opening 141. The semiconductor layer 108 can be formed along the bottom surface and side surfaces of the opening 141. Furthermore, the semiconductor layer 108 can be formed to include, for example, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surfaces of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surfaces of the conductive layer 112b. Furthermore, the semiconductor layer 108 can be formed to include a region in contact with the top surface of the insulating layer 101 and a region in contact with the side surfaces of the insulating layer 110.

[0451] Semiconductor layer 208 is formed to include a region located within opening 241 and a region located within opening 243. Semiconductor layer 208 can be formed along the bottom and side surfaces of opening 241 and the side surfaces of opening 243. For example, semiconductor layer 208 can be formed to include a region in contact with the top surface of conductive layer 212a, a region in contact with the side surfaces of conductive layer 212b, and a region in contact with the top surface of conductive layer 212b. Furthermore, semiconductor layer 208 can be formed to include a region in contact with the side surfaces of insulating layer 110.

[0452] Next, the insulating layer 106 is formed so as to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112a, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110. Figure 41C The insulating layer 106 is formed over the semiconductor layer 108 and the semiconductor layer 208 so as to include a region located inside the opening 141, a region located inside the opening 241, and a region located inside the opening 243. The insulating layer 106 can be formed by, for example, ALD, CVD, or sputtering.

[0453] When metal oxide is used for the semiconductor layers 108 and 208, the insulating layer 106 is preferably used as a barrier layer to inhibit oxygen diffusion. By providing the insulating layer 106 with the function of inhibiting oxygen diffusion, diffusion of oxygen in the semiconductor layers 108 and 208 to the upper side of the insulating layer 106 is suppressed, thereby suppressing the increase of oxygen vacancies (V O ). As a result, a transistor having good electrical characteristics and high reliability can be manufactured.

[0454] In this specification, etc., a barrier layer refers to a layer having barrier properties. For example, an insulating layer having barrier properties may be referred to as a barrier insulating layer. In this specification, etc., barrier properties refer to either or both the function of inhibiting the diffusion of the corresponding substance (also referred to as low permeability) and the function of capturing or immobilizing the corresponding substance.

[0455] By increasing the temperature during the formation of the insulating layer 106 serving as a gate insulating layer, an insulating layer with fewer defects can be formed. However, when the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V O ) and V O H increases. The substrate temperature during formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, and more preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced while oxygen desorption from the semiconductor layers 108 and 208 can be suppressed. Consequently, a transistor exhibiting excellent electrical characteristics and high reliability can be manufactured.

[0456] Before forming the insulating layer 106, the surfaces of the semiconductor layer 108 and the semiconductor layer 208 may be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities in the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. In particular, it is preferable to perform plasma treatment when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. The plasma treatment and the deposition of the insulating layer 106 are preferably performed continuously without being exposed to the atmosphere.

[0457] Next, a conductive film to be the conductive layer 104 and the conductive layer 204 is formed over the insulating layer 106 and processed, thereby forming the conductive layer 104 and the conductive layer 204. In this way, the transistor 100 and the transistor 200 ( Figure 41C ).

[0458] The conductive layer 104 is formed to include a region located inside the opening 141. The conductive layer 204 is formed to include a region located inside the opening 241 and a region located inside the opening 243. The conductive films to be used as the conductive layers 104 and 204 can be formed by, for example, sputtering, CVD, or ALD.

[0459] Next, the insulating layer 109 is formed to cover the transistor 100 and the transistor 200. Specifically, the insulating layer 109 is formed to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106. Figure 17B The insulating layer 109 can be formed by, for example, sputtering, CVD, or ALD.

[0460] Heat treatment may be performed after forming the insulating layer 109. Note that this heat treatment does not necessarily have to be performed. Furthermore, heat treatment may not be performed in this step, and heat treatment performed in a later step may be used as the heat treatment in this step. In some cases, high-temperature treatment in a later step (e.g., a deposition step) may be used as the heat treatment in this step.

[0461] Through the above process, it can be manufactured Figure 17A and Figure 17B The semiconductor device 20 is shown.

[0462] As described above, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, some processes can be made common, for example, to form a plurality of transistors with different electrical characteristics. For example, the conductive layer 112a and the conductive layer 112b included in the transistor 100 and the conductive layer 212b included in the transistor 200 can be formed by the same process. In addition, the semiconductor layer 108 included in the transistor 100 and the semiconductor layer 208 included in the transistor 200 can be formed by the same process. Furthermore, the conductive layer 104 included in the transistor 100 and the conductive layer 204 included in the transistor 200 can be formed by the same process. Therefore, it is possible to easily realize, for example, a circuit having desired performance while reducing manufacturing costs. Therefore, it is possible to manufacture a semiconductor device that is inexpensive and has high performance. For example, when the semiconductor device according to one embodiment of the present invention is used in a display device, a display device that is inexpensive, high-definition, highly reliable, and can be driven at high speed can be realized.

[0463] <Example 2 of Method for Manufacturing Semiconductor Device> Reference Figures 42A to 42D illustrate Figure 20A and Figure 20B An example of a method for manufacturing the semiconductor device 20A is shown. Figures 42A to 42D It is along Figure 20A Note that descriptions of portions overlapping with those in the above-described <Example 1 of the method for manufacturing a semiconductor device> are omitted as appropriate, and descriptions will focus on the different portions.

[0464] First, an insulating layer 101 is formed on a substrate 102, and a conductive film to be a conductive layer 103 is formed on the insulating layer 101. Next, the conductive film is processed to form the conductive layer 103 ( Figure 42A ). The conductive film can be formed by, for example, sputtering, CVD, or ALD.

[0465] Next, the insulating layer 105 is formed over the insulating layer 101 and the conductive layer 103. The insulating layer 105 can be formed by, for example, ALD, CVD, or sputtering.

[0466] When a metal oxide is used for the semiconductor layer 108 to be formed in a later step, the insulating layer 105 is preferably used as a barrier layer to inhibit oxygen diffusion. By providing the insulating layer 105 with the function of inhibiting oxygen diffusion, diffusion of oxygen in the semiconductor layer 108 to the lower side of the insulating layer 105 is suppressed, thereby suppressing the increase of oxygen vacancies (V O ). As a result, a transistor having good electrical characteristics and high reliability can be manufactured.

[0467] Next, a conductive layer 212a is formed on the insulating layer 105. Then, an insulating layer 110 is formed on the insulating layer 105 and the conductive layer 212a, and a conductive film 112f is formed on the insulating layer 110. Figure 42B ).

[0468] Next, the conductive film 112f is processed to form the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b including the opening 243. In addition, a portion of the insulating layer 110 is removed to form the opening 141 and the opening 241 ( Figure 42C ). The opening 141 has a region overlapping with the conductive layer 103 and reaches the insulating layer 105. The opening 241 reaches the conductive layer 212a. The formation of the opening 141, the opening 241, the opening 243, the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b can refer to Figures 40C to 40E .

[0469] Note that in manufacturing Figure 20C In the case of the semiconductor device 20A shown in FIG. 1 , after the openings 141 and 241 are formed in the insulating layer 110, an opening that reaches the conductive layer 212a is formed in the insulating layer 105. Thus, the opening 241 is also formed in the insulating layer 105. For example, the insulating layer 110 is patterned using a resist mask to form the openings 141 and 241, the resist mask is removed, and then the insulating layer 105 is patterned again using a resist mask to form the opening 241, and the resist mask is removed. Thus, the semiconductor device 20A can be manufactured. Figure 20C The semiconductor device 20A is shown.

[0470] Then, the semiconductor layer 108, the semiconductor layer 208, the insulating layer 106, the conductive layer 104 and the conductive layer 204 are formed ( Figure 42D Then, an insulating layer 109 is formed ( Figure 20B ). Through the above process, it is possible to produce Figure 20A and Figure 20BThe semiconductor device 20A is shown.

[0471] <Example 3 of Method for Manufacturing Semiconductor Device> Reference Figures 43A to 44B illustrate Figure 21A and Figure 21B An example of a method for manufacturing the semiconductor device 20B is shown. Figures 43A to 44B It is along Figure 21A Note that descriptions of portions overlapping with those in the above-described <Example 1 of the method for manufacturing a semiconductor device> are omitted as appropriate, and descriptions will focus on the different portions.

[0472] First, the insulating layer 101, the conductive layer 212a, the insulating layer 110, and the conductive film 112f are sequentially formed on the substrate 102. Next, a portion of the conductive film 112f is removed to form an opening. Then, a portion of the insulating layer 110 is removed to form an opening 141 (a region overlapping with the opening) in the insulating layer 110. Figure 43A ).

[0473] Next, the conductive film 112f is processed to form the conductive layer 112a and the conductive layer 112b ( Figure 43B The conductive film 112f can be processed by etching, and preferably by dry etching from the viewpoint of microfabrication. Here, heat treatment may be performed after the conductive layer 112a and the conductive layer 112b are formed.

[0474] Next, the semiconductor layer 108 is formed so as to have a region located inside the opening 141. Next, the insulating layer 106 is formed so as to cover the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. Then, a conductive film 104f ( Figure 43C The conductive film 104f can be formed by, for example, sputtering, CVD, or ALD.

[0475] Next, a portion of the conductive film 104f is removed to form an opening 247, and a portion of the insulating layer 110 is removed to form an opening 245 ( Figure 43D The opening 245 has a region overlapping with the opening 247 and reaches the conductive layer 212a. A portion of the conductive film 104f and a portion of the insulating layer 110 can be removed by etching. From the perspective of microfabrication, dry etching is preferably used for removal.

[0476] Next, the conductive film 104f is processed to form the conductive layer 104. Thus, the transistor 100 ( Figure 44AThe conductive layer 104 is formed to have the opening 247. Note that after the conductive film 104f is processed to form the conductive layer 104, a portion of the conductive layer 104 may be removed to form the opening 247, and thereafter a portion of the insulating layer 110 may be removed to form the opening 245.

[0477] Next, an insulating layer 206 is formed to cover the semiconductor layer 208, the conductive layer 104, and the insulating layer 106. Figure 44B Insulating layer 206 is formed on semiconductor layer 208 so as to have a region located within opening 245 and a region located within opening 247. Insulating layer 206 can be formed, for example, by ALD, CVD, or sputtering. The formation of insulating layer 206 can be referred to the above description regarding the formation of insulating layer 106.

[0478] Next, a conductive film to be the conductive layer 204 is formed over the insulating layer 206 and processed, thereby forming the conductive layer 204. In this way, the transistor 200 ( Figure 44B The conductive layer 204 is formed to have a region located inside the opening 245 and a region located inside the opening 247. The conductive film to be the conductive layer 204 can be formed by, for example, a sputtering method, a CVD method, or an ALD method.

[0479] Next, an insulating layer 109 is formed so as to cover the conductive layer 204 and the insulating layer 206 ( Figure 21B ). Through the above process, it is possible to produce Figure 21A and Figure 21B The semiconductor device 20B is shown.

[0480] The multiple structural examples shown in this specification and the like can be combined appropriately for implementation. For example, Figure 10A and Figure 10B The planar shape of the opening 141 shown in FIG. 1 and FIG. 2 can be applied to the opening 141 shown in other drawings.

[0481] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to these examples can be combined with other structural examples, drawings, etc. as appropriate.

[0482] (Implementation Method 2) In this embodiment, a structural example of a display device that can be used in the semiconductor device of one embodiment of the present invention is described.

[0483] Because the transistors included in the semiconductor device according to one embodiment of the present invention can be micro-transistors, a display device using the semiconductor device according to one embodiment of the present invention can be a high-definition display device. For example, the display device according to one embodiment of the present invention can be used in the display portion of information terminal devices (wearable devices) such as watches and bracelets, and in the display portion of head-mounted devices (HMDs) such as VR devices and glasses-type AR devices.

[0484] [Display module] Figure 45A 3D is a perspective view of a display module 380 . The display module 380 includes a display device 30 and an FPC 390 .

[0485] The display module 380 includes the substrate 102 and the substrate 170. The display module 380 includes a display portion 25. The display portion 25 is a region where an image is displayed.

[0486] Figure 45B This is a perspective schematic diagram of the structure on one side of the substrate 102. A circuit portion 382, a pixel circuit portion 383 on the circuit portion 382, and a pixel portion 384 on the pixel circuit portion 383 are stacked on the substrate 102. Furthermore, a terminal portion 385 for connecting to an FPC 390 is provided on the portion of the substrate 102 that does not overlap with the pixel portion 384. The terminal portion 385 is electrically connected to the circuit portion 382 via a wiring portion 386 composed of a plurality of wiring lines.

[0487] The pixel portion 384 includes a plurality of pixels 21 arranged periodically. Figure 45B The right side of FIG2 shows an enlarged view of one pixel 21. The pixel 21 includes a light-emitting element 60R that emits red light, a light-emitting element 60G that emits green light, and a light-emitting element 60B that emits blue light.

[0488] The pixel circuit portion 383 includes a plurality of pixel circuits 40 arranged periodically. One pixel circuit 40 controls the light emission of three light-emitting elements included in one pixel 21. One pixel circuit 40 can be composed of three circuits that control the light emission of one light-emitting element. For example, the pixel circuit 40 can adopt a structure having at least one selection transistor, one current control transistor (driving transistor) and a capacitor for one light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. Thus, an active matrix display device can be realized. Note that the pixel circuit 40 can also be included in the pixel 21.

[0489] The circuit portion 382 includes circuits for driving each pixel circuit 40 of the pixel circuit portion 383. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit. Furthermore, the transistors provided in the circuit portion 382 may also constitute part of the pixel circuit 40. In other words, the pixel circuit 40 may also be constituted by the transistors included in the pixel circuit portion 383 and the transistors included in the circuit portion 382.

[0490] The FPC 390 is used as wiring for supplying image signals, power supply potential, etc. from the outside to the circuit portion 382. In addition, an IC may be mounted on the FPC 390.

[0491] The display module 380 can adopt a structure in which one or both of the pixel circuit unit 383 and the circuit unit 382 are overlapped on the lower side of the pixel unit 384, so that the display unit 25 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display unit 25 can be greater than 40% and less than 100%, preferably greater than 50% and less than 95%, and more preferably greater than 60% and less than 95%. In addition, the pixels 21 can be arranged at an extremely high density, thereby making the display unit 25 have an extremely high definition. For example, the display unit 25 preferably configures the pixels 21 with a definition of greater than 2000ppi, more preferably greater than 3000ppi, further preferably greater than 5000ppi, and even more preferably greater than 6000ppi and less than 20,000ppi or less than 30,000ppi.

[0492] This extremely high-definition display module 380 is suitable for use in VR devices such as head-mounted displays or glasses-type AR devices. For example, because the display module 380 has an extremely high-definition display portion 25, in a structure where the display portion of the display module 380 is viewed through a lens, even if the display portion is magnified using the lens, the user cannot see the pixels, thereby achieving a highly immersive display. Moreover, without limitation, the display module 380 can also be applied to electronic devices with relatively small display portions. For example, it is suitable for use in the display portion of wearable electronic devices such as watch-type devices.

[0493] Hereinafter, a display device 30A, a display device 30B, and a display device 30C are described as display devices that can be used in the display device 30 .

[0494] [Display device 30A] Figure 46 The display device 30A shown includes a substrate 102 , an insulating layer 101 , an insulating layer 110 , an insulating layer 109 , a transistor 100 , a capacitor 340 , a light-emitting element 60R, a light-emitting element 60G, a light-emitting element 60B, and the like. Figure 46An example is shown in which the insulating layer 110 has a three-layer stacked structure of an insulating layer 110 a , an insulating layer 110 b on the insulating layer 110 a , and an insulating layer 110 c on the insulating layer 110 b .

[0495] The transistor 100 includes a conductive layer 112 a , a conductive layer 112 b , a semiconductor layer 108 , an insulating layer 106 , a conductive layer 104 , and the like. The transistor 100 can use any of the various transistors described in Embodiment 1. Furthermore, the substrate 102 , the insulating layer 101 , the insulating layer 110 a , the insulating layer 110 b , the insulating layer 110 c , and the insulating layer 109 can use the materials described in Embodiment 1 and can have the functions described in Embodiment 1.

[0496] An insulating layer 119 is provided over the insulating layer 109. The insulating layer 119 serves as an interlayer insulating layer and may be a planarized layer. Furthermore, a barrier layer may be provided between the insulating layer 119 and the insulating layer 354 provided over the insulating layer 119 to prevent impurities such as water or hydrogen from diffusing from the insulating layer 119 into the transistor 100.

[0497] Conductive layer 112a is electrically connected to plug 374 embedded in insulating layer 119. Plug 374 preferably includes conductive layer 374a covering the side surfaces of the opening in insulating layer 119, the side surfaces of the opening in insulating layer 109, and a portion of the top surface of conductive layer 112a, and conductive layer 374b having a region in contact with conductive layer 374a. Conductive layer 374a is preferably made of a conductive material that does not readily diffuse hydrogen and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. Furthermore, a conductive material that inhibits the permeation of impurities such as water and hydrogen can be used, either as a single layer or in a stacked layer. This structure prevents impurities such as water and hydrogen from entering semiconductor layer 108 and semiconductor layer 208 through plug 374. Furthermore, since conductive layer 374b also serves as wiring, it is preferably made of a highly conductive conductor. For example, a conductive material primarily composed of tungsten, copper, or aluminum can be used for conductive layer 374b.

[0498] Capacitor 340 is provided on insulating layer 119. Capacitor 340 includes conductive layer 341, conductive layer 345, and insulating layer 343 located therebetween. Conductive layer 341 serves as one electrode of capacitor 340, conductive layer 345 serves as the other electrode of capacitor 340, and insulating layer 343 serves as a dielectric of capacitor 340.

[0499] Conductive layer 341 is provided on insulating layer 119 and embedded in insulating layer 354. Conductive layer 341 is electrically connected to conductive layer 112a of transistor 100 via plug 374. Insulating layer 343 is provided to cover conductive layer 341. Conductive layer 345 is provided in a region overlapping conductive layer 341 with insulating layer 343 interposed therebetween.

[0500] An insulating layer 355 a is provided to cover the capacitor 340 , an insulating layer 355 b is provided on the insulating layer 355 a , and an insulating layer 355 c is provided on the insulating layer 355 b .

[0501] Inorganic insulating films can be used as appropriate for the insulating layers 119, 354, 343, 355a, 355b, and 355c. As described above, examples of materials that can be used for the inorganic insulating films include oxides, nitrides, oxynitrides, and nitride oxides.

[0502] For example, it is preferable to use a silicon oxide film as the insulating layer 355a and the insulating layer 355c, and to use a silicon nitride film as the insulating layer 355b. Thus, the insulating layer 355b can function as an etching protection film. Although this embodiment shows an example in which a recess is formed by etching a portion of the insulating layer 355c, the recess need not be formed in the insulating layer 355c.

[0503] The light emitting element 60R, the light emitting element 60G, and the light emitting element 60B are provided on the insulating layer 355c.

[0504] Light-emitting element 60R includes a pixel electrode 411R, an organic layer 412R, a common layer 414, and a common electrode 413. Light-emitting element 60G includes a pixel electrode 411G, an organic layer 412G, a common layer 414, and a common electrode 413. Light-emitting element 60B includes a pixel electrode 411B, an organic layer 412B, a common layer 414, and a common electrode 413. Light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B share common layer 414 and common electrode 413.

[0505] Hereinafter, when describing the common features among light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B, they may be referred to as light-emitting element 60. Similarly, when describing the common features among components identified by letters, such as organic layer 412R, organic layer 412G, and organic layer 412B, the letters may be omitted.

[0506] Organic layer 412R included in light-emitting element 60R contains a light-emitting organic compound that emits at least red light. Organic layer 412G included in light-emitting element 60G contains a light-emitting organic compound that emits at least green light. Organic layer 412B included in light-emitting element 60B contains a light-emitting organic compound that emits at least blue light. Organic layer 412R, organic layer 412G, and organic layer 412B may each be referred to as an EL layer and include at least a layer containing a light-emitting organic compound (light-emitting layer).

[0507] Display device 30A has separate light-emitting elements for each color, resulting in minimal chromaticity variation between low-brightness and high-brightness light. Furthermore, organic layers 412R, 412G, and 412B are separated from each other, minimizing crosstalk between adjacent sub-pixels even when using a high-definition display panel. This enables a high-definition, high-quality display panel.

[0508] An insulating layer 425 , a resin layer 426 , and a layer 428 are provided in a region between adjacent light-emitting elements.

[0509] The pixel electrodes 411R, 411G, and 411B of the light-emitting element are electrically connected to the conductive layer 112a of the transistor 100 via a plug 356 embedded in the insulating layers 355a, 355b, and 355c, a conductive layer 341 embedded in the insulating layer 354, and a plug 374. The height of the top surface of the insulating layer 355c is equal to or substantially equal to the height of the top surface of the plug 356. Various conductive materials can be used as the plug. For example, the same material as that used for the plug 374 can be used for the plug 356.

[0510] Furthermore, a protective layer 421 is provided on the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B. The substrate 170 is bonded to the protective layer 421 via an adhesive layer 471 .

[0511] No insulating layer covering the top end of the pixel electrodes 411 is provided between two adjacent pixel electrodes 411. Therefore, the interval between adjacent light-emitting elements can be made very small, thereby realizing a high-definition or high-resolution display device.

[0512] [Display device 30B] Hereinafter, a display device having a partially different structure from the above example will be described. Note that the same parts as above will be referred to the above description, and the description may be omitted.

[0513] Figure 47 The display device 30B shown shows an example in which a transistor 150 , which is a planar transistor in which a semiconductor layer is formed on a plane, and a transistor 100 in which current flows both vertically and horizontally are stacked.

[0514] The transistor 150 includes a semiconductor layer 151 , an insulating layer 153 , a conductive layer 154 , a pair of conductive layers 155 , an insulating layer 156 , and a conductive layer 157 .

[0515] An insulating layer 152 is provided over the substrate 102. The insulating layer 152 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the substrate 102 to the transistor 150 and prevents oxygen from escaping from the semiconductor layer 151 toward the insulating layer 152. For example, a film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, into which one or both of hydrogen and oxygen are less likely to diffuse than a silicon oxide film, can be used as the insulating layer 152.

[0516] A conductive layer 157 is provided over the insulating layer 152, and an insulating layer 156 is provided so as to cover the conductive layer 157. The conductive layer 157 serves as a first gate electrode of the transistor 150, and a portion of the insulating layer 156 serves as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least the portion of the insulating layer 156 that contacts the semiconductor layer 151. The top surface of the insulating layer 156 is preferably planarized.

[0517] The semiconductor layer 151 is provided on the insulating layer 156. The semiconductor layer 151 preferably contains a metal oxide. A pair of conductive layers 155 are in contact with the semiconductor layer 151 and serve as a source electrode and a drain electrode.

[0518] Insulating layers 158 and 161 are provided to cover the top and side surfaces of the pair of conductive layers 155 and the side surfaces of the semiconductor layer 151. The insulating layer 158 serves as a barrier layer that prevents impurities such as water and hydrogen from diffusing into the semiconductor layer 151 and oxygen from escaping from the semiconductor layer 151. As the insulating layer 158, an insulating film similar to that of the insulating layer 152 described above can be used.

[0519] In a planar view, an opening is provided between one of the pair of conductive layers 155 in the insulating layers 158 and 161, reaching the semiconductor layer 151. The insulating layer 153 and the conductive layer 154 are embedded in the opening, contacting the top surface of the semiconductor layer 151. The conductive layer 154 serves as a second gate electrode, and the insulating layer 153 serves as a second gate insulating layer.

[0520] The top surfaces of the conductive layer 154, the insulating layer 153, and the insulating layer 161 are planarized so that their heights are uniform or substantially uniform, and an insulating layer 159 is provided to cover them. The insulating layer 159 functions as a barrier layer to prevent impurities such as water and hydrogen from diffusing into the transistors 100 and 150. The insulating layer 159 can be an insulating film similar to that used for the insulating layer 152.

[0521] Transistor 150 employs a structure in which two gates sandwich a semiconductor layer forming a channel. Alternatively, the two gates may be connected and the transistor may be driven by supplying the same signal to both gates. Alternatively, the threshold voltage of transistor 150 may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving the other.

[0522] [Display device 30C] Figure 48 The display device 30C shown includes a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 100 through which current flows both vertically and horizontally.

[0523] Transistor 310 is a transistor having a channel formation region in substrate 102. As substrate 102 included in display device 30C, a semiconductor substrate such as a single crystal silicon substrate can be used. Transistor 310 includes a portion of substrate 102, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. Conductive layer 311 serves as a gate electrode. Insulating layer 313 is located between substrate 102 and conductive layer 311 and serves as a gate insulating layer. Low-resistance region 312 is a region doped with impurities in substrate 102 and serves as either a source or a drain. Insulating layer 314 covers the side surfaces of conductive layer 311.

[0524] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 102 .

[0525] Next, the light emitting element 60R, the light emitting element 60G, and the light emitting element 60B will be described. Figures 46 to 48 Examples of different structures.

[0526] As described above, one embodiment of the present invention is a display device including a light-emitting element. The display device includes two or more pixels that emit light of different colors. Each pixel includes a light-emitting element. For example, by including three light-emitting elements that emit red (R), green (G), or blue (B) light, a full-color display device can be achieved.

[0527] When manufacturing a display device that includes multiple light-emitting elements emitting different colors, it is necessary to form at least the layer containing the light-emitting material (the light-emitting layer) into an island shape. A known method is to form island-shaped organic films using a metal mask or other shadow mask when forming a portion or all of the EL layer. However, this method suffers from various factors, such as the accuracy of the metal mask, misalignment between the metal mask and the substrate, metal mask deflection, and vapor scattering that causes the deposited film to expand. This can cause the shape and position of the island-shaped organic films to deviate from the designed shape and position, making it difficult to achieve high-definition and high-aperture display devices. Furthermore, during vapor deposition, the layer outline may be blurred, resulting in a reduced film thickness at the ends. In other words, the film thickness of the island-shaped light-emitting layer may vary depending on the location. Furthermore, when manufacturing large, high-resolution or high-definition display devices, there is a concern that the manufacturing yield may decrease due to low dimensional accuracy of the metal mask and deformation caused by heat, etc. Therefore, efforts have been made to artificially improve resolution (also known as pixel density) by adopting special pixel arrangements, such as the Pentile arrangement.

[0528] Note that in this specification, "island-shaped" refers to a state in which two or more layers formed of the same material in the same process are physically se...

Claims

1. A semiconductor device comprising: a first insulating layer; as well as a second insulating layer and a transistor on the first insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a third insulating layer. The second insulating layer includes an opening that reaches the first insulating layer, The first conductive layer and the second conductive layer are provided on the second insulating layer so as to face each other with the opening interposed therebetween when viewed from a planar perspective. The semiconductor layer is provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and to have a region located inside the opening. The third insulating layer is provided on the semiconductor layer so as to have a region located inside the opening. Furthermore, the third conductive layer is provided on the third insulating layer so as to have a region located inside the opening.

2. The semiconductor device according to claim 1, The length of a component of the channel length of the transistor along the bottom surface of the opening is greater than or equal to the length of a component of the channel length of the transistor along the side surface of the opening.

3. The semiconductor device according to claim 1, The width of the first conductive layer and the width of the second conductive layer are both greater than the width of the semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, The second insulating layer includes a first layer and a second layer on the first layer, The semiconductor layer comprises a metal oxide, And the first layer has a higher oxygen content than the second layer.

5. The semiconductor device according to claim 4, The oxygen content is measured by secondary ion mass spectrometry, X-ray photoelectron spectroscopy or thermal desorption spectroscopy.

6. The semiconductor device according to claim 4, The oxygen diffusion coefficient of the second layer is smaller than that of the first layer.

7. The semiconductor device according to claim 6, The oxygen diffusion coefficient is calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

8. A semiconductor device comprising: a first insulating layer; as well as a second insulating layer, a first transistor, and a second transistor on the first insulating layer; The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a third insulating layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer and the third insulating layer, The fourth conductive layer is provided on the first insulating layer, The second insulating layer is provided on the fourth conductive layer, The second insulating layer includes a first opening portion reaching the first insulating layer and a second opening portion reaching the fourth conductive layer. The first conductive layer and the second conductive layer are provided on the second insulating layer so as to face each other with the first opening interposed therebetween when viewed from a planar perspective. The fifth conductive layer is provided on the second insulating layer and includes a third opening having an area overlapping with the second opening. The first semiconductor layer is provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and to have a region located inside the first opening. The second semiconductor layer is provided so as to have a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer and to have a region located inside the first opening and a region located inside the second opening. The third insulating layer is provided on the first semiconductor layer and the second semiconductor layer so as to have a region located inside the first opening, a region located inside the second opening, and a region located inside the third opening. The third conductive layer is provided on the third insulating layer so as to have a region located inside the first opening. Furthermore, the sixth conductive layer is provided so as to include a region located inside the second opening and a region inside the third opening facing the second semiconductor layer via the third insulating layer.

9. The semiconductor device according to claim 8, The length of a component of the channel length of the first transistor along the bottom surface of the first opening is greater than or equal to the length of a component of the channel length of the first transistor along the side surface of the first opening.

10. The semiconductor device according to claim 8, The width of the first conductive layer and the width of the second conductive layer are both greater than the width of the first semiconductor layer.

11. The semiconductor device according to any one of claims 8 to 10, The second insulating layer includes a first layer, a second layer on the first layer, and a third layer on the second layer, The first semiconductor layer and the second semiconductor layer include metal oxide, Furthermore, the oxygen content of the second layer is higher than that of the first layer and the third layer.

12. The semiconductor device according to claim 11, The oxygen content is measured by secondary ion mass spectrometry, X-ray photoelectron spectroscopy or thermal desorption spectroscopy.

13. The semiconductor device according to claim 11, The oxygen diffusion coefficients of the first layer and the third layer are smaller than that of the second layer.

14. The semiconductor device according to claim 13, The oxygen diffusion coefficient is calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

15. A method for manufacturing a semiconductor device, comprising: forming a first insulating layer; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the first conductive layer; forming a conductive film on the second insulating layer; forming a first opening and a second opening having a region overlapping with the first conductive layer in the conductive film; forming, in the second insulating layer, a third opening having a region overlapping with the first opening and reaching the first insulating layer, and a fourth opening having a region overlapping with the second opening and reaching the first conductive layer; processing the conductive film to form a second conductive layer and a third conductive layer so as to face each other with the second opening interposed therebetween when viewed from a planar perspective, and forming a fourth conductive layer including the second opening; forming a first semiconductor layer having a region in contact with the second conductive layer, a region in contact with the third conductive layer, and a region located inside the third opening, and forming a second semiconductor layer having a region in contact with the first conductive layer, a region in contact with the fourth conductive layer, a region located inside the second opening, and a region located inside the fourth opening, forming a third insulating layer on the first semiconductor layer and the second semiconductor layer so as to have a region located inside the second to fourth openings; as well as A fifth conductive layer having a region located inside the third opening and a sixth conductive layer having a region located inside the second opening and inside the fourth opening are formed on the third insulating layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein a first layer, a second layer on the first layer, and a third layer on the second layer are formed as the second insulating layer, forming a layer containing a metal oxide as the first semiconductor layer and the second semiconductor layer, And oxygen is supplied to the second layer after forming the second layer and before forming the third layer.

17. The method for manufacturing a semiconductor device according to claim 16, The first layer and the third layer are formed so that their oxygen diffusion coefficients are smaller than that of the second layer.

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