Contact resistance reduction by integration of molybdenum with titanium

Abstract

Methods for forming semiconductor structures and semiconductor structures are described. The method includes patterning a substrate to form a first opening and a second opening, the substrate including an n-type transistor and a p-type transistor, the first opening over the n-type transistor, and the second opening over the p-type transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p-type transistor and the n-type transistor. A titanium silicide (TiSi) layer is formed on the n-type transistor and the p-type transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in the processing chamber without disrupting the vacuum.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the fields of semiconductor devices and semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a method for reducing contact resistance of NMOS and PMOS by integrating molybdenum processes with titanium. Background Art

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. Over the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003] Transistors are key components of most integrated circuits. Because the drive current, and therefore the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Consequently, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting transistor goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the transistor's footprint, and finFETs are now used in many integrated circuits. However, finFETs also have their own disadvantages.

[0004] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures and reduce contact resistance. Examples of transistor device structures include planar structures, fin field-effect transistor (finFET) structures, and gate-all-around (GAA) structures. The performance of logic gates is related to the properties of the materials used and the thickness and area of the structural layers. However, as some gate characteristics are adjusted to accommodate device scaling, challenges arise.

[0005] As we move into advanced modes below the 2nm node, it is desirable to increase device speed and drive current by reducing contact resistance. Therefore, improved methods for reducing contact resistance are needed. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method for forming a semiconductor structure. The method includes: depositing a molybdenum silicide (MoSi) layer on one or more of a p-type transistor and an n-type transistor on a substrate, the substrate including the n-type transistor and the p-type transistor and having a first opening above the n-type transistor and a second opening above the p-type transistor; optionally, in-situ annealing the substrate in a hydrogen (H2) atmosphere; forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor; and forming a capping layer on the titanium silicide (TiSi) layer.

[0007] Another embodiment of the present disclosure is directed to a method for forming a semiconductor structure. In one or more embodiments, the method includes: pre-cleaning a substrate comprising an n-type transistor and a p-type transistor, a first opening above the n-type transistor, and a second opening above the p-type transistor; depositing a molybdenum silicide (MoSi) layer on the p-type transistor and the n-type transistor; optionally, in-situ annealing the substrate in a hydrogen (H2) atmosphere; forming a titanium silicide (TiSi) layer on the molybdenum silicide (MoSi) layer; forming a capping layer on the titanium silicide (TiSi) layer; and depositing a gap-fill material in the first opening and the second opening.

[0008] Other embodiments of the present disclosure are directed to a semiconductor structure comprising: an n-type transistor and a p-type transistor; a molybdenum silicide (MoSi) layer on one or more of the p-type transistor and the n-type transistor; a titanium silicide (TiSi) layer on the p-type transistor and the n-type transistor; a capping layer on the titanium silicide (TiSi) layer; and a gapfill material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To facilitate a detailed understanding of the above-described features of the present disclosure, the present disclosure, briefly summarized above, will be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0010] Figure 1 A process flow diagram illustrating a method according to one or more embodiments of the present disclosure is shown;

[0011] Figure 2A shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0012] Figure 2B shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0013] Figure 2Cshows a semiconductor structure according to one or more embodiments of the present disclosure;

[0014] Figure 2D shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0015] Figure 2E shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0016] Figure 3 A process flow diagram illustrating a method according to one or more alternative embodiments of the present disclosure;

[0017] Figure 4A shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0018] Figure 4B shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0019] Figure 4C shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0020] Figure 4D shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0021] Figure 4E shows a semiconductor structure according to one or more embodiments of the present disclosure;

[0022] Figure 5 shows a schematic top view of an example multi-chamber processing system according to one or more embodiments; and

[0023] Figure 6 is a bar graph of contact resistance results according to an embodiment.

[0024] In the drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished by following the reference numeral with a dash and a second reference numeral, the second reference numeral used to distinguish similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral. DETAILED DESCRIPTION

[0025] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0026] As used herein, the term "about" means approximately or close to, and in the context of a numerical value or range, "about" means a variation of ±15% or less of that numerical value. For example, values that differ by ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of "about."

[0027] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may refer to only a portion of a substrate. Furthermore, reference to depositing on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0028] Furthermore, the term "substrate" as used herein refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, dielectric materials, other conductive materials, or combinations thereof. In some embodiments, the substrate includes silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminide (TiAl), silicon germanium (SiGe), silicon germanium boride (SiGeB), hafnium oxide (HfO2), aluminum oxide (Al2O3), or combinations thereof. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film treatment directly on the surface of the substrate itself, in the present disclosure, any film treatment steps disclosed may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as referred to in the context.

[0029] As used in this specification and the appended claims, the term "selectively" refers to a process that acts on a first surface with a greater effect than on a second surface. Such a process will be described as acting "selectively" on the first surface relative to the second surface. The term "relative to" used in this sense does not imply a physical orientation of one surface over another, but rather the relationship of the thermodynamic or kinetic properties of a chemical reaction on one surface relative to the other.

[0030] According to one or more embodiments, the term "on..." with respect to a film or film layer includes both the film or layer directly on a surface, such as a substrate surface, and the film or layer as one or more underlying layers between the film or layer and a surface, such as a substrate surface. Thus, in one or more embodiments, the phrase "on a substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on..." refers to a layer or film in contact with a surface (e.g., a substrate surface) without intervening layers. Thus, the phrase "a layer directly on a substrate surface" refers to a layer in direct contact with the substrate surface without intervening layers.

[0031] As used herein, the term "substrate surface" refers to any substrate surface on which a layer can be formed. A substrate surface can have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of the feature can be any suitable shape, including but not limited to peaks, grooves, and cylindrical through-holes. In this sense, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, a groove having a top, two sidewalls, and a bottom, a peak having a top and two sidewalls extending upward from the surface, and a through-hole having sidewalls extending downward from the surface and having an open bottom.

[0032] As used herein, the term "processing chamber" includes a portion of the processing chamber adjacent to the substrate surface, but does not encompass the entire interior volume of the processing chamber. For example, in a spatially separated section of the processing chamber, the portion of the processing chamber adjacent to the substrate surface may be purged of one or more reactive compounds by any suitable technique, including but not limited to moving the substrate through a gas curtain to a portion or section of the processing chamber that is free or substantially free of the reactive compound.

[0033] As used herein, the term "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. A substrate or a portion of a substrate surface is sequentially exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. The sequential exposure of the reactive gases prevents or minimizes gas phase reactions between the reactive gases. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to attach to and / or react on the substrate surface. In a spatial ALD process, different portions of a substrate surface or material on a substrate surface are exposed to two or more reactive compounds simultaneously, such that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, those skilled in the art will understand that the term "substantially" used in this sense means that due to diffusion, a small portion of the substrate may be exposed to multiple reactive gases at the same time, and that the simultaneous exposure is not intentional.

[0034] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into a reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction zone or remove any residual reactive compounds or byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the gas flow is purged during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with compound A or compound B and continue with the respective cycle sequence until a film having a desired thickness is obtained. In one or more embodiments, a time-domain ALD process may be performed with two or more reactive compounds in a predetermined order.

[0035] In one aspect of a spatial ALD process, a first reactive gas and a second reactive gas are delivered simultaneously to a reaction zone, but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus such that any given point on the substrate is exposed to both the first and second reactive gases. In one or more embodiments, a spatial ALD process can be performed using two or more reactive compounds in a predetermined sequence.

[0036] In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially sequentially. As used throughout this specification, "substantially sequentially" means that the majority of the duration of exposure to the first reactive compound does not overlap with exposure to the second reactive compound, but there may be some overlap.

[0037] As used herein, the term "chemical vapor deposition" refers to exposing at least one reactive compound to deposit a layer of material on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive compounds in a processing chamber to allow vapor phase reaction and deposition of the reactive compounds. In some embodiments, the CVD process includes exposing the substrate surface to two or more reactive compounds simultaneously. In some embodiments, the CVD process includes continuously exposing the substrate surface to a first reactive compound while intermittently exposing it to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film having a predetermined thickness. In a CVD process, a film may be deposited in a single exposure to the mixed reactive compounds, or may be deposited in multiple exposures to the mixed reactive compounds with purging in between. In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially simultaneously.

[0038] As used throughout the specification, "substantially simultaneously" means that a majority of the duration of the exposure of the first reactive compound overlaps with the exposure of the second reactive compound.

[0039] As used herein, the term "cleaning" includes any suitable cleaning process for removing unreacted precursors, reaction products, and by-products from a process area. Suitable cleaning processes include moving the substrate through a gas curtain to a portion or section of the processing area that is free of or substantially free of reactants. In one or more embodiments, cleaning the processing chamber includes applying a vacuum. In some embodiments, cleaning the processing area includes flowing a purge gas over the substrate. In some embodiments, the cleaning process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, the first reactive compound is purged from the reaction chamber for a duration in a range from 0.1 to 30 seconds, 0.1 to 10 seconds, 0.1 to 5 seconds, 0.5 to 30 seconds, 0.5 to 10 seconds, 0.5 to 5 seconds, 1 to 30 seconds, 1 to 10 seconds, 1 to 5 seconds, 5 to 30 seconds, 5 to 10 seconds, or 10 to 30 seconds prior to exposing the substrate to the second reactive compound.

[0040] Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to its cost effectiveness and the variety of film properties it produces. For example, in a PECVD process, a hydrocarbon source, such as a gaseous hydrocarbon or liquid hydrocarbon vapor that has been entrained in a carrier gas, is introduced into a PECVD chamber. A plasma initiating gas, typically helium, is also introduced into the chamber. Subsequently, a plasma is initiated in the chamber to generate excited CH- radicals. The excited CH- radicals chemically bond to the surface of a substrate located within the chamber, forming the desired film thereon. The embodiments described herein with reference to the PECVD process may be implemented using any suitable thin film deposition system. Any apparatus descriptions described herein are intended to be and should not be understood or construed as limiting the scope of the embodiments described herein.

[0041] As used herein, the term "liner" or "barrier layer" refers to a layer that is conformally formed along at least a portion of the sidewalls and / or lower surface of an opening, such that a majority of the opening remains unfilled after the layer is deposited, prior to layer deposition. The liner may be formed along the entire sidewalls and lower surface of the opening. The liner may be formed by any process known to those skilled in the art. In some embodiments, the liner comprises a metal nitride, a PVD metal, or a combination thereof. In one or more embodiments, the "liner" or "barrier layer" may also be optionally formed at the bottom of the structure.

[0042] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a semiconductor device may contain many transistors, in addition to capacitors, inductors, resistors, diodes, wires, or other components. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate whose voltage determines the device's conductivity. This ability to vary conductivity with the amount of applied voltage is used to amplify or convert electronic signals.

[0043] Generally, a transistor includes a gate formed between source and drain regions. The source and drain regions may comprise doped regions of the substrate and may exhibit a doping profile suitable for a particular application. The gate is located above a channel region and may include a gate dielectric interposed between a gate electrode in the substrate and the channel region.

[0044] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which charge carriers enter the channel; the drain (D), through which charge carriers leave the channel; and the gate (G), which is the terminal that modulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is called I S , and the current entering the channel at the drain (D) is called I D The drain-to-source voltage is called V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0045] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate whose voltage determines the device's conductivity. This ability to vary conductivity with the amount of applied voltage is used to amplify or convert electronic signals. MOSFETs are based on the modulation of charge concentration by the metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body, insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a single highly doped region separated by a body region. These regions can be p-type or n-type, but are all of the same type and opposite to the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the doping type.

[0046] If the MOSFET is an n-channel, or nMOS FET, the source and drain are n+ regions, while the bulk is a p-region. If the MOSFET is a p-channel, or pMOS FET, the source and drain are p+ regions, while the bulk is an n-region. The source is so named because it is the source of charge carriers flowing through the channel (electrons for the n-channel, holes for the p-channel); similarly, the drain is where the charge carriers leave the channel.

[0047] Embodiments of the present disclosure provide semiconductor structures and methods for forming semiconductor structures. In order to improve the speed and drive current of devices with advanced modes below the 2 nanometer node, it is necessary to reduce the contact resistance. In one or more embodiments, the integration of molybdenum and titanium exhibits a large contact resistance (R c ) reduction. Surprisingly, this reduction is observed in NMOS contacts, even though molybdenum (Mo) is considered a p-type metal, and if only Mo is used in NMOS contacts, the contact resistance is very high. Therefore, in one or more embodiments, the performance of NMOS is particularly surprising.

[0048] Embodiments of the present disclosure are described through figures showing processes for forming NMOS and PMOS. Figure 1 A process flow diagram of a method 10 of forming a semiconductor structure is shown. Figure 1 Shows the formation Figures 2A to 2E Methods for any semiconductor structure according to one or more embodiments are shown. Figure 3 A process flow diagram of a method 50 of forming a semiconductor structure is shown. Figure 3 Shows the formation Figures 4A to 4E Methods for any semiconductor structure according to one or more embodiments are shown.

[0049] refer to Figure 1 In one or more embodiments, the method 10 of forming a semiconductor structure includes pre-cleaning the substrate in operation 12. The substrate may be pre-cleaned by any suitable method known to a skilled person. In operation 14, a molybdenum silicide (MoSi) layer is deposited over the p-type transistor. In operation 16, the method 10 optionally includes in-situ annealing the transistor in a hydrogen (H2) atmosphere. In operation 18, the method 10 includes forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor. In operation 20, the method 10 includes forming a capping layer on the n-type transistor and the p-type transistor. In operation 22, the method 10 optionally includes annealing the semiconductor structure. In operation 24, the method 10 optionally includes gap filling.

[0050] In one or more embodiments not shown, the substrate may be patterned to form at least one of the first opening 106 and the second opening 108. In one or more embodiments, patterning the substrate includes using one or more patterning techniques known to one of ordinary skill in the art of microelectronic device fabrication. In some embodiments, a semiconductor structure 100 is provided, and patterning is not required to form the semiconductor structure 100.

[0051] refer to Figure 1 and Figures 2A to 2E, in operation 12, method 10 includes pre-cleaning the substrate. In one or more embodiments, maintaining the pre-cleaning process under vacuum ensures that no oxide is introduced / formed on the substrate surface during the method. In some embodiments, pre-cleaning the substrate (or substrate surface) can remove oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, the cleaned surface forms a surface that is substantially free of oxide. The term "substantially free of oxide" used in this manner means that there are less than or equal to 5%, 2%, 1% or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxide from the surface. In one or more embodiments, anisotropic etching removes more oxide from the surface of the source / drain material compared to the dielectric material. In one or more embodiments, the pre-cleaned surface forms a source / drain material that is substantially free of oxide.

[0052] refer to Figures 2A to 2E , a semiconductor structure 100 is shown. The semiconductor structure 100 includes an n-type transistor 102 and a p-type transistor 104. In one or more embodiments, each of the n-type transistor 102 and the p-type transistor 104 includes a dielectric material 110, source / drain materials 120, 122, and a substrate 130.

[0053] In one or more embodiments, the dielectric material 110 may include any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material 110 includes one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and a low-k dielectric. As used herein, terms such as "silicon oxide" and "silicon nitride" refer to materials containing silicon and oxygen or silicon and nitrogen. "Silicon oxide" and "silicon nitride" should not be understood to imply any stoichiometric ratio. In other words, the dielectric material containing silicon oxide or silicon nitride can be stoichiometric or non-stoichiometric, silicon-rich or silicon-poor. In some embodiments, the dielectric material 110 includes silicon oxide (SiO2). In some embodiments, the dielectric material 110 includes silicon nitride (SiN).

[0054] In some embodiments, the n-type transistor 102 and the p-type transistor 104 include source and drain contacts. In one or more embodiments, the source / drain material 120, 122 may have more than one layer.

[0055] In one or more specific embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si). The source / drain material 120 of the n-type transistor 102 can be doped or undoped. In one or more embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si) doped with phosphorus (P).

[0056] In one or more embodiments, the source / drain material 122 of the p-type transistor 104 includes silicon germanium (SiGe). In one or more embodiments, the silicon germanium (Ge) may have any suitable germanium concentration. In some embodiments, the germanium concentration of the silicon germanium (SiGe) is in a range from 10% to 100%, or in a range from 20% to 60%. The source / drain 122 material of the p-type transistor 104 may be doped or undoped. In one or more embodiments, the source / drain material 122 of the p-type transistor 104 includes silicon germanium (SiGe) doped with boron (B).

[0057] refer to Figures 2A to 2E In one or more embodiments, a first opening 106 is provided on the n-type transistor 102, and a second opening 108 is provided on the p-type transistor 104. The first opening 106 and the second opening 108 can have any suitable aspect ratio (the ratio of the depth of the opening to the width of the opening). In one or more embodiments, the first opening 106 and the second opening 108 can independently have an aspect ratio in the range of 3:1 to 15:1, or in the range of 6:1 to 15:1, or in the range of 9:1 to 15:1, or in the range of 12:1 to 15:1. In one or more embodiments, the first opening 106 and the second opening 108 can independently have an aspect ratio greater than 10:1.

[0058] refer to Figure 1 and Figure 2B In operation 14, a molybdenum silicide (MoSi) layer 140 is deposited on one or more of the source / drain 122 of the p-type transistor 104 and the source / drain 122 of the n-type transistor 102. Figures 2A to 2E In the illustrated embodiment, the molybdenum silicide (MoSi) layer 140 is deposited only on the source / drain 122 of the p-type transistor 104. However, those skilled in the art will recognize that the deposition of the MoSi layer 104 need not be selective for the p-type transistor. In one or more embodiments, the MoSi layer 140 can be formed by any suitable means. In one or more embodiments, the MoSi layer 140 is deposited on the p-type transistor by a chemical vapor deposition (CVD) process.

[0059] In some embodiments, the molybdenum silicide layer 140 is selectively deposited on the source / drain material 122 of the p-type transistor, but not on the source / drain material 120 of the n-type transistor. As used in this specification and the appended claims, the term "selectively depositing a film on one surface relative to another surface" and the like means that a first amount of film is deposited on the first surface, and a second amount of film is deposited on the second surface, wherein the second amount of film is less than the first amount of film, or no film is deposited on the second surface.

[0060] The selectivity of a deposition process is generally expressed as a multiple of the growth rate. For example, if the growth (or deposition) rate on one surface is 25 times faster than on another surface, the process would be described as having a selectivity of 25:1. In this sense, a higher ratio indicates a more selective process.

[0061] In one or more embodiments, the substrate 100 is optionally exposed to a barrier compound.This process step can be used to control the selectivity of a deposition process on a substrate comprising a metal surface and a dielectric surface.

[0062] In one or more embodiments, the molybdenum silicide (MoSi) layer 140 is deposited by CVD. The substrate 100 is exposed to a process gas for a period of time. The process gas includes a molybdenum precursor that reacts with the substrate surface to deposit a molybdenum film. The reactive gas may also be referred to as a metal precursor gas.

[0063] The platinum precursor can be any suitable precursor that reacts with the substrate. In some embodiments, the platinum precursor comprises a metal center and one or more ligands. In some embodiments, the metal center comprises one or more metal atoms. In other words, in some embodiments, the metal precursor is one or more of a dimer, trimer, or tetramer.

[0064] The molybdenum precursor can be any suitable precursor having a decomposition temperature higher than the deposition temperature. The molybdenum precursor of one or more embodiments is volatile and thermally stable, and thus suitable for vapor deposition.

[0065] In some embodiments, the platinum precursor includes a platinum halide. As used herein, the term "halide" refers to a binary phase, a portion of which is a halogen atom, and the other portion is an element or group with an electronegativity less than that of the halogen, to form a compound of fluoride, chloride, bromide, iodide or astatide. A halogen ion is a negatively charged halogen atom. As known to those skilled in the art, halogen anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-) and astatine (At-). Therefore, as used herein, the term "platinum halide" refers to any coordination complex of platinum with one or more halogen or halide ligands. The term platinum halide includes a platinum mixed halide with at least two different halide atoms.

[0066] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodine chloride.

[0067] In other embodiments, the platinum precursor is substantially free of oxygen or nitrogen atoms. Therefore, in these embodiments, the metal precursor does not include carbonyl, oxygen, amine or imine ligands. Within these parameters, the number of ligands on the platinum precursor and the type of ligand can be different based on, for example, the oxidation state of the platinum atom. The platinum precursor can be iso- or iso-. In certain embodiments, the platinum precursor includes at least one ligand that includes an optional alkyl-substituted cyclopentadiene (Cp) ring. In certain embodiments, the platinum precursor includes at least one ligand that includes an optional alkyl-substituted benzene ring. In certain embodiments, the platinum precursor includes at least one p-isopropyltoluene ligand. In certain embodiments, the platinum precursor includes at least one ligand that includes an open-chain or closed-chain diene.

[0068] In one or more embodiments, the molybdenum precursor is delivered to the processing chamber as a molybdenum precursor gas or via a carrier gas (e.g., argon (Ar), nitrogen (N2), hydrogen (H2), etc.). The molybdenum precursor gas or carrier gas may be provided in one or more pulses, or continuously. The flow rate of the molybdenum precursor gas or carrier gas may be any suitable flow rate, including but not limited to a flow rate in the range of about 1 to about 5000 sccm, or in the range of about 2 to about 4000 sccm, or in the range of about 3 to about 3000 sccm, or in the range of about 5 to about 2000 sccm.

[0069] The molybdenum precursor gas may be provided at any suitable pressure, including but not limited to a pressure of about 5 mTorr to about 500 Torr, or about 10 mTorr to about 500 Torr, or about 100 mTorr to about 500 Torr, or about 5 Torr to about 500 Torr.

[0070] The substrate may be exposed to the platinum precursor gas for any suitable time required to allow the metal precursor to react with the substrate surface. For example, the process gas may flow into the processing chamber for a period of time greater than or equal to about 60 seconds. In some embodiments, the exposure time to the platinum precursor is about 0.5 seconds. In some embodiments, the exposure time to the platinum precursor is about 100 seconds, about 200 seconds, about 300 seconds, about 400 seconds, or about 500 seconds.

[0071] In one or more embodiments, the deposition process is cyclic; the exposure time of the molybdenum precursor for each cycle is about 500 milliseconds. The flow is then turned off for about 3.5 seconds. In one or more embodiments, the deposition process is cyclic, and each cycle can be represented as follows: H2 gas is always on; the precursor is exposed for 0.5 seconds, simultaneously with H2; only H2 is on for 3.5 seconds during the purge; the total cycle duration is 4 seconds; the cycle is repeated until the target molybdenum thickness is achieved.

[0072] During exposure to the molybdenum precursor, the temperature of the substrate can be controlled, for example, by setting the temperature of the substrate support or susceptor. This temperature is also referred to as the deposition temperature. In some embodiments, the substrate is maintained at a temperature in the range of about 0°C to about 600°C, or in the range of about 25°C to about 500°C, or in the range of about 50°C to about 450°C, or in the range of about 100°C to about 400°C, or in the range of about 200°C to about 400°C, or in the range of about 250°C to about 350°C. In some embodiments, the substrate is maintained at a temperature below the decomposition temperature of the metal precursor.

[0073] In one or more embodiments, the substrate is maintained at a temperature of less than or equal to about 350° C., or less than or equal to about 310° C., or less than or equal to about 300° C., or less than or equal to about 250° C., or less than or equal to about 200° C. In one or more embodiments, the substrate is maintained at a temperature of greater than or equal to about 200° C., or greater than or equal to about 300° C., or greater than about 350° C. In some embodiments, the substrate is maintained at a temperature in the range of about 200° C. to about 310° C.

[0074] In some embodiments, a carrier gas may be provided to the processing chamber simultaneously with the platinum precursor gas. The carrier gas may be mixed with the platinum precursor gas (e.g., as a diluent gas) or provided separately and may be a pulsed flow or a constant flow. In some embodiments, the carrier gas flows into the processing chamber at a constant flow in the range of about 1 to about 10,000 sccm. The carrier gas may be any carrier gas, such as argon, helium, neon, hydrogen, nitrogen, or combinations thereof.

[0075] The deposition process is performed as a thermal process without the use of plasma reactants. In other words, the method is performed in the absence of plasma.

[0076] In one or more embodiments, a determination is made as to whether the molybdenum film has reached a predetermined thickness. If the predetermined thickness has not been reached, the method returns to continue exposing the substrate to the molybdenum precursor until the predetermined thickness is reached. In some embodiments, the molybdenum film may be deposited to form a total layer thickness of about 10 angstroms to about 10,000 angstroms, or in some embodiments, about 20 angstroms to about 1,000 angstroms, or in some embodiments, about 50 angstroms to about 200 angstroms.

[0077] In one or more embodiments, the molybdenum halide precursor directly reacts with silicon or silicon germanium of the source / drain materials 120 , 122 to form the molybdenum silicide layer 140 .

[0078] In other embodiments, once the molybdenum film reaches its predetermined thickness, the molybdenum film may be exposed to reactants to form a molybdenum silicide layer 140. In one or more embodiments, the reactants include an oxidant, a reducing agent, or a combination thereof. In some embodiments, the reactants include hydrogen (H2), ammonia (NH3), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher-order silanes, and substituted silanes. In a specific embodiment, the reactants include silane to form a molybdenum silicide (MoSi) layer 140. In one or more embodiments, a carrier gas is used to flow the reactants over the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas includes one or more of N2, Ar, and He. In other embodiments, the reactive gas may flow continuously, and the flow of the molybdenum precursor to the chamber may be opened and closed.

[0079] In other embodiments, in operation 16, the molybdenum silicide layer 140 may be annealed as appropriate. The annealing may be performed in any suitable atmosphere at any suitable temperature. In some embodiments, the molybdenum silicide layer 140 is annealed in a hydrogen (H2) atmosphere at a temperature in the range of 200°C to 600°C or in the range of 400°C to 500°C. In one or more embodiments, the molybdenum silicide layer 140 is annealed at a pressure in the range of 10 mTorr to 20 Torr, or in the range of 100 mTorr to 20 Torr, or in the range of 500 mTorr to 10 Torr.

[0080] In one or more embodiments, the molybdenum silicide layer 140 may have any suitable thickness. In some embodiments, the thickness of the molybdenum silicide layer 140 is in a range from 20 angstroms to about 100 angstroms, or in a range from about 30 angstroms to about 90 angstroms, or in a range from about 40 angstroms to about 80 angstroms, or in a range from about 50 angstroms to about 70 angstroms. In one or more embodiments, the molybdenum silicide (MoSi) layer 140 has a thickness of about 40 angstroms. The molybdenum silicide (MoSi) layer 140 on the p-type transistor 102 has a Schottky barrier height in a range from about 0.65 eV to about 0.95 eV.

[0081] refer to Figure 1 and Figure 2CIn operation 18, a titanium silicide (TiSi) layer 160 is deposited on the source / drain 120 of the n-type transistor 102 and the source / drain 122 of the p-type transistor. In one or more embodiments, the titanium silicide (TiSi) layer 160 may have any suitable thickness. In some embodiments, the titanium silicide (TiSi) layer 160 has a thickness in a range from 20 angstroms to about 100 angstroms, or in a range from about 30 angstroms to about 90 angstroms, or in a range from about 40 angstroms to about 80 angstroms, or in a range from about 50 angstroms to about 70 angstroms. In one or more embodiments, the titanium silicide (TiSi) layer 160 has a thickness of about 40 angstroms.

[0082] The titanium silicide (TiSi) layer 160 can be formed according to any suitable process known to those skilled in the art. In one or more embodiments, the structure 100 is first cleaned to remove oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, the cleaned surface forms a surface that is substantially free of oxide. As used in this manner, the term "substantially free of oxide" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, an anisotropic etch is used to remove oxide from the surface.

[0083] In one or more embodiments, to form the titanium silicide (TiSi) layer 160, a metal film is selectively formed on the source / drain 120 of the n-type transistor 102 and the source / drain 122 of the p-type transistor, for example, on the molybdenum silicide layer 140. In some embodiments, the structure 100 is exposed to a metal precursor and a reactant. The metal film can be deposited by an ALD deposition process, a CVD deposition process, a plasma-enhanced CVD process, or a combination thereof. In some embodiments, the metal film includes a titanium silicide (TiSi) film.

[0084] In one or more embodiments, the metal precursor comprises a titanium precursor. In some embodiments, the titanium precursor comprises a titanium halide. In some embodiments, the titanium halide comprises titanium fluoride, titanium chloride, or a combination thereof. In specific embodiments, the titanium precursor comprises titanium fluoride. In other specific embodiments, the titanium precursor comprises titanium chloride. In one or more embodiments, the precursor is flowed over the surface using a carrier gas. In some embodiments, the carrier gas is flowed through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N2, Ar, and He.

[0085] In one or more embodiments, the reactant includes an oxidant, a reducing agent, or a combination thereof. In some embodiments, the reactant includes hydrogen (H2), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher-order silanes, and substituted silanes. In a specific embodiment, the reactant includes silane to form a titanium silicide (TiSi) layer 160. In one or more embodiments, a carrier gas is used to flow the reactant over the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas includes one or more of Ar and He. In other embodiments, the reactive gas can flow continuously, and the flow of the titanium precursor to the chamber can be turned on and off.

[0086] In other embodiments, the titanium silicide film is formed by reacting titanium tetrachloride (TiCl4), hydrogen (H2) and plasma with an underlying silicon substrate. In one or more embodiments, no additional silicon source is provided.

[0087] In one or more embodiments, by combining Mo with Ti in an integrated manner, the contact resistance is reduced more than when a single metal silicide is present. In other words, the combination of Mo and Ti produces a contact resistance that is lower than the contact resistance when only Mo is present, and lower than the contact resistance when only Ti is present.

[0088] refer to Figure 1 In one or more embodiments, operations 12 and 14 are performed in an integrated system without vacuum breaks between operations. In other embodiments, operations 12, 14, 16, and 18 are performed in an integrated system without vacuum breaks between operations.

[0089] refer to Figure 1 and Figure 2D In operation 20, a capping layer 170 may be formed on each of the n-type transistor 102 and the p-type transistor 104. The capping layer 170 may include any suitable material known to those skilled in the art. In one or more embodiments, the capping layer 170 includes a PVD metal film. In one or more embodiments, the capping layer 170 is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), PVD tungsten (W), PVD molybdenum (Mo), and PVD ruthenium (Ru). In one or more embodiments, the capping layer 170 prevents oxide formation on the titanium silicide (TiSi) layer 160.

[0090] In additional embodiments, the capping layer 170 is selectively formed on the top surface of the titanium silicide (TiSi) layer 160 by nitriding the titanium silicide (TiSi) layer 160 using one or more of ammonia (NH 3 ) plasma, N 2 / H 2 plasma, and the like.

[0091] refer to Figure 1 In some embodiments, in operation 22, the semiconductor structure 100 may be optionally annealed to further reduce the contact resistance of the structure 100. In one or more embodiments, annealing the semiconductor structure 100 may produce a smooth surface.

[0092] The semiconductor structure 100 may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by a rapid thermal process (RTP). In one or more embodiments, the RTP includes annealing the semiconductor structure 100 to a temperature in a range from about 400° C. to about 700° C. In one or more embodiments, the RTP includes annealing the semiconductor structure 100 to a temperature in a range from about 600° C.

[0093] refer to Figure 1 and Figure 2E In operation 24, the first opening 106 on the n-type transistor 102 and the second opening 108 on the p-type transistor 104 are independently filled with a gap-filling material 180 and a gap-filling material 182, respectively. In one or more embodiments, the gap-filling material 180 and the gap-filling material 182 are substantially free of voids or seams. The gap-filling material 180 and the gap-filling material 182 may independently comprise any suitable gap-filling material known to those skilled in the art. In one or more embodiments, the gap-filling material 180 and the gap-filling material 182 independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the gap-filling material 180 in the first opening 106 on the n-type transistor 102 is the same as the gap-filling material 182 in the second opening 108 on the p-type transistor 104. In one or more embodiments, the gap-filling material 180 in the first opening 106 on the n-type transistor 102 is different from the gap-filling material 182 in the second opening 108 on the p-type transistor 104. In one or more embodiments, the gap-fill material 180 and the gap-fill material 182 are the same and include tungsten (W).

[0094] The gapfill process may include any suitable gapfill process known to those skilled in the art. In one or more embodiments, the gapfill process includes exposing the semiconductor structure 100 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0095] In some embodiments, the gap-fill process is a bottom-up gap-fill process. In other embodiments, the gap-fill process includes a conformal gap-fill process.

[0096] refer to Figure 3 In one or more embodiments, the method 50 of forming a semiconductor structure includes: in operation 52, pre-cleaning the substrate. The substrate can be pre-cleaned by any suitable method known to a person skilled in the art. In operation 54, a molybdenum silicide (MoSi) layer is deposited on the p-type transistor and the n-type transistor. In operation 56, the method 50 optionally includes in-situ annealing the transistor in a hydrogen (H2) atmosphere. In operation 58, the method 50 includes forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor. In operation 60, the method 50 includes forming a capping layer on the n-type transistor and the p-type transistor. In operation 62, the method 50 optionally includes annealing the semiconductor structure. In operation 64, the method 50 optionally includes gap filling.

[0097] refer to Figure 3 and Figures 4A to 4E , in operation 52, method 50 includes pre-cleaning the substrate. In one or more embodiments, maintaining the pre-cleaning process under vacuum ensures that no oxide is introduced / formed on the substrate surface during the method. In some embodiments, pre-cleaning the substrate (or substrate surface) removes oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, the cleaned surface forms a surface that is substantially free of oxide. As used in this manner, the term "substantially free of oxide" means that there are less than or equal to 5%, 2%, 1% or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxide from the surface. In one or more embodiments, anisotropic etching removes more oxide from the surface of the source / drain material compared to the dielectric material. In one or more embodiments, the pre-cleaned surface forms a source / drain material that is substantially free of oxide.

[0098] refer to Figures 4A to 4E , a semiconductor structure 300 is shown. The semiconductor structure 300 includes an n-type transistor 302 and a p-type transistor 304. In one or more embodiments, each of the n-type transistor 302 and the p-type transistor 304 includes a dielectric material 310, source / drain materials 320, 322, and a substrate 330.

[0099] In one or more embodiments, dielectric material 310 may include any suitable dielectric material known to those skilled in the art and as described above for dielectric material 110. In some embodiments, dielectric material 310 includes silicon oxide (SiO2). In some embodiments, dielectric material 310 includes silicon nitride (SiN).

[0100] In some embodiments, the n-type transistor 302 and the p-type transistor 304 include source and drain contacts. In one or more embodiments, the source / drain material 320, 322 may have more than one layer.

[0101] In one or more specific embodiments, the source / drain material 320 of the n-type transistor 302 includes silicon (Si). The source / drain 320 material of the n-type transistor 302 can be doped or undoped. In one or more embodiments, the source / drain material 320 of the n-type transistor 302 includes silicon (Si) doped with phosphorus (P).

[0102] In one or more embodiments, the source / drain material 322 of the p-type transistor 304 includes silicon germanium (SiGe). In one or more embodiments, the silicon germanium (Ge) can have any suitable germanium concentration. In some embodiments, the silicon germanium (SiGe) has a germanium concentration in the range of from 10% to 100%, or in the range of from 20% to 60%. The source / drain 322 material of the p-type transistor 304 can be doped or undoped. In one or more embodiments, the source / drain material 322 of the p-type transistor 304 includes silicon germanium (SiGe) doped with boron (B).

[0103] refer to Figures 4A to 4E In one or more embodiments, a first opening 306 is provided on the n-type transistor 302, and a second opening 308 is provided on the p-type transistor 304. The first opening 306 and the second opening 308 can have any suitable aspect ratio (the ratio of the depth of the opening to the width of the opening). In one or more embodiments, the first opening 306 and the second opening 308 can independently have an aspect ratio in the range of 3:1 to 15:1, or in the range of 6:1 to 15:1, or in the range of 9:1 to 15:1, or in the range of 12:1 to 15:1. In one or more embodiments, the first opening 306 and the second opening 308 can independently have an aspect ratio greater than 10:1.

[0104] refer to Figure 3 and Figure 4B In operation 54, a molybdenum silicide (MoSi) layer 340 is deposited on the source / drain 322 of the p-type transistor 304 and the source / drain 320 of the n-type transistor. In one or more embodiments, the molybdenum silicide layer 340 can be formed by any suitable means, as described above with respect to the molybdenum silicide (MoSi) layer 140. In one or more embodiments, the molybdenum silicide layer 340 is deposited on the p-type transistor and the n-type transistor by a chemical vapor deposition (CVD) process, as described above with respect to the molybdenum silicide layer 140.

[0105] In one or more embodiments, a determination is made as to whether the molybdenum film has reached a predetermined thickness. If the predetermined thickness has not been reached, the method returns to continue exposing the substrate to the molybdenum precursor until the predetermined thickness is reached. In some embodiments, the molybdenum film may be deposited to form a total layer thickness of about 10 angstroms to about 10,000 angstroms, or in some embodiments, a total layer thickness of about 20 angstroms to about 1,000 angstroms, or in some embodiments, a total layer thickness of about 50 angstroms to about 200 angstroms.

[0106] In one or more embodiments, once the molybdenum film reaches its predetermined thickness, the molybdenum film may be exposed to reactants to form the molybdenum silicide layer 340 , as described above with respect to the molybdenum silicide layer 140 .

[0107] In other embodiments, in operation 56, the molybdenum silicide layer 340 may be annealed as appropriate. The annealing may be performed in any suitable atmosphere at any suitable temperature. In some embodiments, the molybdenum silicide layer 340 is annealed in a hydrogen (H2) atmosphere at a temperature in the range of 200°C to 600°C or in the range of 400°C to 500°C. In one or more embodiments, the molybdenum silicide layer 340 is annealed at a pressure in the range of 10 mTorr to 20 Torr, or in the range of 100 mTorr to 20 Torr, or in the range of 500 mTorr to 10 Torr.

[0108] In one or more embodiments, the molybdenum silicide layer 340 can have any suitable thickness. In some embodiments, the thickness of the molybdenum silicide layer 340 is in a range from 20 angstroms to about 100 angstroms, or in a range from about 30 angstroms to about 90 angstroms, or in a range from about 40 angstroms to about 80 angstroms, or in a range from about 50 angstroms to about 70 angstroms. In one or more embodiments, the molybdenum silicide (MoSi) layer 340 has a thickness of about 40 angstroms.

[0109] See Figure 3 and Figure 4C In operation 58, a titanium silicide (TiSi) layer 360 is deposited on the source / drain 320 of the n-type transistor 302 and the source / drain 322 of the p-type transistor. In one or more embodiments, the titanium silicide (TiSi) layer 360 may have any suitable thickness. In some embodiments, the thickness of the titanium silicide (TiSi) layer 360 is in a range from 20 angstroms to about 100 angstroms, or in a range from about 30 angstroms to about 90 angstroms, or in a range from about 40 angstroms to about 80 angstroms, or in a range from about 50 angstroms to about 70 angstroms. In one or more embodiments, the titanium silicide (TiSi) layer 360 has a thickness of about 40 angstroms.

[0110] The titanium silicide (TiSi) layer 360 can be formed according to any suitable process known to those skilled in the art, as described above with respect to the titanium silicide (TiSi) layer 160. In one or more embodiments, the structure 100 is first cleaned to remove oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, the cleaned surface forms a surface that is substantially free of oxide. As used in this manner, the term "substantially free of oxide" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, an anisotropic etch is used to remove the oxide from the surface.

[0111] In one or more embodiments, by combining Mo with Ti in an integrated manner, contact resistance is reduced further than when a single metal silicide is present. In other words, the combination of Mo and titanium Ti produces a contact resistance on both n-type and p-type transistors that is lower than the contact resistance when using only Mo, and lower than the contact resistance when using only Ti.

[0112] refer to Figure 3 In one or more embodiments, operations 52 and 54 are performed in an integrated system without vacuum breaks between operations. In other embodiments, operations 52, 54, 56, and 58 are performed in an integrated system without vacuum breaks between operations.

[0113] refer to Figure 3 and Figure 4D In operation 60, a capping layer 370 may be formed on each of the n-type transistor 302 and the p-type transistor 304. The capping layer 370 may include any suitable material known to those skilled in the art. In one or more embodiments, the capping layer 370 includes a PVD metal film. In one or more embodiments, the capping layer 370 is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), PVD tungsten (W), PVD molybdenum (Mo), and PVD ruthenium (Ru). In one or more embodiments, the capping layer 370 prevents oxide formation on the titanium silicide (TiSi) layer 360.

[0114] In additional embodiments, the capping layer 370 is selectively formed on the top surface of the titanium silicide (TiSi) layer 360 by nitriding the titanium silicide (TiSi) layer 360 using one or more of ammonia (NH 3 ) plasma, N 2 / H 2 plasma, and the like.

[0115] refer to Figure 3 In some embodiments, in operation 62, the semiconductor structure 300 may be optionally annealed to further reduce the contact resistance of the structure 300. In one or more embodiments, annealing the semiconductor structure 300 may produce a smooth surface.

[0116] The semiconductor structure 300 may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, the RTP includes annealing the semiconductor structure 300 to a temperature in the range of about 500° C. to about 700° C. In one or more embodiments, the RTP includes annealing the semiconductor structure 300 to a temperature in the range of about 600° C.

[0117] In some embodiments, the root mean square (RMS) roughness of the semiconductor structure after annealing is in a range of 4% to less than 30%, 4% to less than 20%, 4% to less than 10%, 10% to less than 30%, 10% to less than 20%, or 20% to less than 30%.

[0118] refer to Figure 3 and Figure 4E In operation 64, the first opening 306 over the n-type transistor 302 and the second opening 308 over the p-type transistor 304 are independently filled with a gap-filling material 380 and a gap-filling material 382, respectively. In one or more embodiments, the gap-filling material 380 and the gap-filling material 382 are substantially free of voids or seams. The gap-filling material 380 and the gap-filling material 382 may independently comprise any suitable gap-filling material known to those skilled in the art. In one or more embodiments, the gap-filling material 380 and the gap-filling material 382 independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the gap-filling material 380 in the first opening 306 over the n-type transistor 302 is the same as the gap-filling material 382 in the second opening 308 over the p-type transistor 304. In one or more embodiments, the gap-filling material 380 in the first opening 306 over the n-type transistor 302 is different from the gap-filling material 382 in the second opening 308 over the p-type transistor 304. In one or more embodiments, the gap-fill material 380 and the gap-fill material 382 are the same and include tungsten (W).

[0119] The gapfill process may include any suitable gapfill process known to those skilled in the art. In one or more embodiments, the gapfill process includes exposing the semiconductor structure 300 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0120] In some embodiments, the gap-fill process is a bottom-up gap-fill process. In other embodiments, the gap-fill process includes a conformal gap-fill process.

[0121] Figure 5 A schematic top view of an example of a multi-chamber processing system 400, or cluster tool, according to an embodiment of the present disclosure is shown. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with corresponding transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment external to the processing system 400 (e.g., such as the atmospheric ambient environment that may be present during manufacturing). For example, wafers can be processed in and transferred between the various chambers under a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 400. Thus, the processing system 400 can provide an integrated solution for certain processing of wafers.

[0122] Examples of processing systems that may be appropriately modified according to the teachings provided herein include or An integrated processing system or other suitable processing system is commercially available from Applied Materials, Inc., located in Santa Clara, Calif. It is contemplated that other processing systems, including systems from other manufacturers, may also be adapted to benefit from the aspects described herein.

[0123] exist Figure 5 In the illustrated example, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 positioned at one end of the respective factory interface robot 442. The blade 448 is configured to transfer wafers from the factory interface 402 to the load lock chambers 404 and 406.

[0124] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 may be, for example, slit valve openings having slit valves to facilitate wafer passage by transfer robots 412, 414 and to provide a seal between chambers to prevent gas from being transferred between chambers. Generally, any port is open for wafer transfer through the port. Otherwise, the port is closed.

[0125] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits that fluidly couple to the various chambers. In operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system then evacuates the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and holding chambers 416, 418 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 404 or 406 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0126] After the wafers in the load lock chamber 404 or 406 have been evacuated, the transfer robot 412 transfers the wafers from the load lock chamber 404 or 406 to the transfer chamber 408 via the port 454 or 456. The transfer robot 412 can then transfer the wafers to and / or between any of the processing chambers 420, 422 via the corresponding ports 462, 464 for processing, and transfer the wafers to the holding chambers 416, 418 via the corresponding ports 458, 460 to be held pending further transfer. Similarly, the transfer robot 414 can access wafers in the holding chamber 416 or 418 through the port 466 or 468 and can transfer the wafers to any of the processing chambers 424, 426, 428, 430 and / or between any of the processing chambers 424, 426, 428, 430 through the corresponding ports 470, 472, 474, 476 for processing and transfer the wafers to the holding chamber 416, 418 through the corresponding ports 466, 468 for holding pending further transfer. The transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0127] Processing chambers 420, 422, 424, 426, 428, 430 may be any suitable chamber for processing wafers. In some embodiments, processing chamber 420 may be capable of performing a pre-clean process, processing chamber 422 may be capable of performing a chemical vapor deposition (CVD) process, and processing chambers 424, 426, 428, 430 may be capable of performing a plasma enhanced chemical vapor deposition (PECVD) process. Processing chamber 420 may be a SiCoNi® chamber available from Applied Materials, Inc., Santa Clara, California. TM Pre-clean the chamber.

[0128] A system controller 490 is coupled to the processing system 400 for controlling the processing system 400 or components thereof. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 430. In operation, the system controller 490 enables data and feedback to be collected from the various chambers to coordinate the performance of the processing system 400.

[0129] System controller 490 typically includes a central processing unit (CPU) 492, memory 494, and support circuits 496. CPU 492 can be any form of general-purpose processor useful in an industrial environment. Memory 494, or non-transitory computer-readable medium, is accessible by CPU 492 and can be one or more of a memory device, such as random-access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. Support circuits 496 are coupled to CPU 492 and may include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of CPU 492 by CPU 492 executing computer scripts stored, for example, as software routines in memory 494 (or memory of a particular processing chamber). When the computer scripts are executed by CPU 492, CPU 492 controls the chamber to perform processes according to the various methods.

[0130] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the example shown, the transfer apparatus includes transfer chambers 408 and 410 and holding chambers 416 and 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as a transfer apparatus in a processing system.

[0131] The present disclosure is now described with reference to the following examples. Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or executed in various ways.

[0132] Example

[0133] Example 1: Comparison

[0134] The substrate including the n-type and p-type transistors is pre-cleaned, and a titanium silicide layer is deposited on the junction. A PVD tungsten capping layer is deposited on the titanium silicide layer, and the contact structure is filled with tungsten.

[0135] Example 2: Comparison

[0136] The substrate including the n-type and p-type transistors is pre-cleaned, and a molybdenum silicide layer is deposited on the junction. A PVD tungsten capping layer is deposited on the molybdenum silicide layer, and the contact structure is filled with tungsten.

[0137] Example 3

[0138] The substrate containing the n-type and p-type transistors is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on the p-type and n-type transistors. A titanium silicide (TiSi) layer is formed on the MoSi layer. A PVD tungsten capping layer is deposited on the TiSi layer, and the contacts are filled with tungsten.

[0139] Figure 6 FIG4 shows an example of an n-type transistor contact resistance. Figure 6 As shown, using a combination of MoSi and TiSi (Example 3) can produce devices with reduced contact resistance compared to devices with only titanium silicide (Example 1) or molybdenum silicide (Example 2).

[0140] In the context of describing the materials and methods discussed herein (especially in the context of the appended claims), the use of the terms "a," "an," and "the," and similar indicators should be understood to encompass both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of numerical ranges herein is intended merely to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods and does not limit the scope unless otherwise stated. No language in the specification should be construed to indicate that any unclaimed element is essential to the implementation of the disclosed materials and methods.

[0141] References in this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0142] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor structure, the method comprising: depositing a molybdenum silicide (MoSi) layer on one or more of a p-type transistor and an n-type transistor of a substrate, the substrate including the n-type transistor and the p-type transistor and having a first opening over the n-type transistor and a second opening over the p-type transistor; Optionally, performing in-situ annealing on the substrate in a hydrogen (H2) atmosphere; forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor; as well as A capping layer is formed on the titanium silicide (TiSi) layer.

2. The method of claim 1, further comprising: A gap-fill material is independently deposited in the first opening and the second opening.

3. The method of claim 1, further comprising: The substrate is pre-cleaned. The method of claim 3 , wherein the method is an integrated method performed in a cluster tool. 5 . The method of claim 1 , wherein the capping layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). 6 . The method of claim 1 , wherein the n-type transistor comprises silicon (Si) doped with phosphorus (P), and the p-type transistor comprises silicon germanium (SiGe) doped with boron (B). The method of claim 2 , wherein the gap-filling material is substantially free of voids or seams. 8 . The method of claim 2 , wherein the gap-fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

9. The method of claim 4, wherein the method produces a contact resistance that is lower than the contact resistance of a p-type transistor or an n-type transistor comprising only molybdenum silicide.

10. The method of claim 4, wherein the method produces a contact resistance that is lower than the contact resistance of a p-type transistor or an n-type transistor comprising only titanium silicide.

11. The method of claim 1, wherein the molybdenum suicide (MoSi) layer is on both the n-type transistor and the p-type transistor.

12. A method of forming a semiconductor structure, the method comprising: pre-cleaning a substrate comprising an n-type transistor and a p-type transistor, a first opening above the n-type transistor, and a second opening above the p-type transistor; depositing a molybdenum silicide (MoSi) layer on the p-type transistor and the n-type transistor; Optionally, performing in-situ annealing on the substrate in a hydrogen (H2) atmosphere; forming a titanium silicide (TiSi) layer on the molybdenum silicide (MoSi) layer; forming a capping layer on the titanium silicide (TiSi) layer; as well as A gap-fill material is deposited in the first opening and the second opening. 13 . The method of claim 12 , wherein the capping layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

14. The method of claim 12, wherein the gap-fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

15. The method of claim 12, wherein the n-type transistor comprises silicon (Si) doped with phosphorus (P), and the p-type transistor comprises silicon germanium (SiGe) doped with boron (B).

16. The method of claim 12, wherein the gap-filling material is substantially free of voids or seams.

17. The method of claim 12, wherein the method produces a contact resistance that is lower than a contact resistance of the p-type transistor or n-type transistor comprising only molybdenum silicide.

18. The method of claim 12, wherein the method produces a contact resistance that is lower than a contact resistance of the p-type transistor or n-type transistor comprising only titanium silicide.

19. A semiconductor structure, comprising: n-type transistors and p-type transistors; a molybdenum silicide (MoSi) layer on one or more of the p-type transistor and the n-type transistor; a titanium silicide (TiSi) layer over the p-type transistor and the n-type transistor; a capping layer on the titanium silicide (TiSi) layer; as well as Gap filling material.

20. The semiconductor structure of claim 19, wherein the molybdenum suicide (MoSi) layer is on both the n-type transistor and the p-type transistor.

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