Analog IC test anomaly location method and system based on parallel asynchronous testing

Abstract

The present invention discloses a method and system for locating anomalies in analog IC tests based on parallel asynchronous testing, aiming to improve the efficiency and accuracy of locating abnormal channels during complex analog IC testing. This method first obtains data throughput information for the multi-channel analog-to-digital converter (ADC) of the analog IC during testing and, based on this information, formulates a parallel asynchronous testing plan. Subsequently, the transmission data of each ADC channel during testing is collected to construct a channel response characteristic matrix, and the timing drift parameters of each channel are calculated. A spectral clustering algorithm is used to cluster the timing drift parameters and identify clusters of abnormal drift channels. Finally, the clustering results are used to accurately locate the abnormal channels during testing. This method, with its high parallelism and adaptability, is suitable for rapid testing and anomaly analysis of large-scale analog ICs, offering significant advantages in improving test efficiency and reducing testing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of analog IC testing, and in particular to a method and system for locating anomalies in analog IC testing based on parallel asynchronous testing. Background Art

[0002] With the increasing complexity and high performance of integrated circuit design, analog integrated circuits (AICs) are increasingly being used in fields such as communications, automotive electronics, industrial control, and consumer electronics. To improve analog IC testing efficiency, parallel asynchronous testing technology has been gradually introduced in recent years. This involves asynchronously testing multiple analog ICs simultaneously on the same test platform. This approach effectively shortens test cycles by improving equipment utilization and data acquisition efficiency. However, during parallel asynchronous testing, due to the sharing of test resources, the parallel operation of multi-channel analog-to-digital converters (ADCs), and asynchronous sampling between channels, channel accuracy drift, data mismatch, and signal interference are highly likely to occur. These issues can lead to test data anomalies in some analog ICs, and can even make it difficult to accurately locate the source of the anomaly.

[0003] In particular, when an ADC channel experiences timing drift, crosstalk coupling, or decreased data sampling integrity, the test results of the underlying analog IC may deviate from actual performance, affecting test accuracy and subsequent quality assessment. Furthermore, in an asynchronous environment, the lack of a unified reference timing between channels makes traditional anomaly detection methods based on a single channel or synchronous sampling difficult to apply. Existing methods, which mostly rely on manual intervention or offline analysis, are not only inefficient but also lack support for large-scale automated testing, making them difficult to meet the demands of fast, high-reliability testing for industrial-grade analog ICs.

[0004] Therefore, there is an urgent need for an analog IC test anomaly detection and channel anomaly identification method and system that combines the characteristics of multi-channel ADCs, adapts to parallel asynchronous test modes, and has high-precision automatic positioning capabilities, so as to achieve accurate identification of test abnormal channels and rapid calibration of abnormal analog ICs, and improve the automation and intelligence level of test quality control. Summary of the Invention

[0005] In order to solve at least one of the above technical problems, the present invention proposes a method and system for locating anomalies in analog IC testing based on parallel asynchronous testing.

[0006] A first aspect of the present invention provides a method for locating anomalies in analog IC testing based on parallel asynchronous testing, comprising:

[0007] Acquiring data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information;

[0008] Acquire transmission data of each ADC channel of the analog IC during a parallel asynchronous test, construct a channel response characteristic matrix based on the transmission data, and calculate a timing drift parameter of each channel based on the channel response characteristic matrix;

[0009] Performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters;

[0010] The abnormal test channels in the parallel asynchronous test process of the analog IC are located according to the abnormal drift channel clustering cluster.

[0011] In this solution, the data throughput information of the multi-channel analog-to-digital converter is obtained during the analog IC test process, and the parallel asynchronous test solution of the analog IC is determined based on the data throughput information. Specifically,

[0012] Obtaining a preset number of standard analog ICs as input to a target test platform for pre-testing operations, and obtaining test output data of a multi-channel analog-to-digital converter during the pre-testing process, wherein the test output data includes data processing delay information, cache backlog rate, and analog IC current and voltage output signal change data;

[0013] Performing a smoothness analysis on the output signal change data to determine the signal sampling integrity and signal jump degree of the output signal;

[0014] Determine the abnormal sampling frequency of the data interface of each ADC channel according to the signal sampling integrity and the signal sampling jump degree, and perform data sampling quality evaluation on each ADC channel according to the abnormal sampling frequency to obtain data sampling quality data;

[0015] Performing correlation analysis on the data sampling quality data, the data processing delay information, and the cache backlog rate to determine data throughput capacity information of the multi-channel analog-to-digital converter;

[0016] The data processing volume information of a single analog IC test is obtained, the number of analog ICs for parallel asynchronous testing is determined according to the data processing volume information and data throughput capacity information, and a parallel asynchronous testing solution is constructed.

[0017] In this solution, the transmission data of each ADC channel of the analog IC during the parallel asynchronous test is obtained, a channel response characteristic matrix is ​​constructed based on the transmission data, and the timing drift parameter of each channel is calculated based on the channel response characteristic matrix, specifically:

[0018] Acquire the transmission data of each ADC channel of the analog IC during the parallel asynchronous test process. The transmission data includes the amplitude sequence of the channel output, the sampling timestamp, the edge mutation mark, and the corresponding temperature, voltage, and current operating condition information;

[0019] Extracting response characteristic information of each ADC channel according to the transmission data, and performing structured representation of the response characteristic information according to a time window to construct a channel response characteristic matrix, wherein the channel response characteristic matrix includes channel response amplitude variation, sampling stability, and signal edge morphology characteristics;

[0020] Dynamic time warping is performed based on the response change trend of each channel in different time windows in the channel response feature matrix, and the timing drift component of each channel is extracted by calculating the alignment error of the response curves between the channels;

[0021] The timing drift component is combined with the signal edge morphology characteristics of the corresponding channel to perform weighted analysis to obtain the timing drift parameter of each channel.

[0022] In this solution, the step of obtaining the transmission data of each ADC channel of the analog IC during the parallel asynchronous test process further includes:

[0023] Obtain the amplitude sequence signals of all ADC channels, perform Hanning window processing on each channel signal, and then perform fast Fourier transform to generate amplitude spectrum data;

[0024] Locate the first N frequency components with the largest energy in the amplitude spectrum data as reference frequency points, and expand the predetermined bandwidth to both sides with each reference frequency point as the center to form a detection frequency band;

[0025] Scan the spectrum line whose amplitude value exceeds the noise floor level in each detection frequency band. When the difference between the spectrum line frequency and the reference frequency point is an integer multiple and the spectrum line amplitude value is greater than the predetermined multiple of the amplitude values ​​of the two adjacent frequency points on its left and right, mark the spectrum line as an abnormal spectrum peak.

[0026] If the ratio of the abnormal spectrum peak energy to the total channel energy is within a predefined ratio range, the corresponding period of the channel is recorded as the crosstalk verification interval;

[0027] Calculate the normalized cross-correlation coefficient matrix between all channel amplitude sequence signals, and extract the channel pairs whose physical distance is less than a predetermined distance threshold as the channel pairs to be analyzed;

[0028] For each channel pair to be analyzed, fix the time offset of the first channel signal and slide the time offset of the second channel signal to determine the time offset when the cross-correlation coefficient reaches a maximum value;

[0029] Counting the actual time offset at each time point within the interval to be verified. When the deviation of the actual time offset from the maximum time offset obtained by the sliding calculation exceeds a predetermined tolerance and the number of times the deviation direction changes reaches a predetermined frequency, it is determined that the ADC channel pair has crosstalk coupling in the interval to be crosstalk verified, and the crosstalk interval of the data transmitted by each ADC channel is output;

[0030] The acquisition section of the transmission data is optimized according to the crosstalk interval.

[0031] In this solution, the spectral clustering algorithm is used to cluster the timing drift parameters and extract abnormal drift channel clusters, specifically:

[0032] Calculating the similarity of timing drift parameters between ADC channels based on radial basis functions, constructing a similarity matrix, and calculating a degree matrix based on the similarity matrix;

[0033] Constructing a normalized Laplace matrix based on the similarity matrix and the degree matrix, performing eigendecomposition on the normalized Laplace matrix, and extracting eigenvectors corresponding to the first k smallest eigenvalues;

[0034] Combining the eigenvectors to form an eigenvector matrix, randomly selecting k vectors from the row vectors of the eigenvector matrix as initial cluster centers, calculating the Euclidean distances from all row vectors to each cluster center, and assigning each row vector to the category corresponding to the cluster center closest to it;

[0035] Take the arithmetic mean of the row vector coordinates in each category to obtain the new cluster center point position, and repeat the distance calculation, vector allocation and center point update process until the cluster center point position no longer changes, and obtain k clusters;

[0036] The average value of the timing drift parameters within each cluster is calculated, and the cluster with the highest average value is identified as the abnormal drift channel cluster.

[0037] In this solution, the abnormal test channels in the analog IC parallel asynchronous test process are located according to the abnormal drift channel clustering, specifically:

[0038] According to the abnormal drift channel cluster, extract all ADC channel identification information contained in the cluster, and locate the test abnormal channel according to the ADC channel identification information;

[0039] An analog IC to be tested corresponding to the test abnormal channel is obtained, marked as a test data abnormal analog IC, and an ADC channel is reallocated for the test data abnormal analog IC.

[0040] A second aspect of the present invention further provides a system for locating anomalies in a simulated IC test based on parallel asynchronous testing. The system comprises: a memory and a processor. The memory includes a program for locating anomalies in a simulated IC test based on parallel asynchronous testing. When the program is executed by the processor, the following steps are implemented:

[0041] Acquiring data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information;

[0042] Acquire transmission data of each ADC channel of the analog IC during a parallel asynchronous test, construct a channel response characteristic matrix based on the transmission data, and calculate a timing drift parameter of each channel based on the channel response characteristic matrix;

[0043] Performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters;

[0044] The abnormal test channels in the parallel asynchronous test process of the analog IC are located according to the abnormal drift channel clustering cluster.

[0045] The present invention discloses a method and system for locating anomalies in analog IC tests based on parallel asynchronous testing, aiming to improve the efficiency and accuracy of locating abnormal channels during complex analog IC testing. This method first obtains data throughput information for the multi-channel analog-to-digital converter (ADC) of the analog IC during testing and, based on this information, formulates a parallel asynchronous testing plan. Subsequently, the transmission data of each ADC channel during testing is collected to construct a channel response characteristic matrix, and the timing drift parameters of each channel are calculated. A spectral clustering algorithm is used to cluster the timing drift parameters and identify clusters of abnormal drift channels. Finally, the clustering results are used to accurately locate the abnormal channels during testing. This method, with its high parallelism and adaptability, is suitable for rapid testing and anomaly analysis of large-scale analog ICs, offering significant advantages in improving test efficiency and reducing testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A flowchart of a method for locating anomalies in analog IC testing based on parallel asynchronous testing according to the present invention is shown;

[0047] Figure 2 A flow chart of the present invention for determining a parallel asynchronous test scheme for an analog IC is shown;

[0048] Figure 3 A flow chart of calculating the timing drift parameters of each channel according to the present invention is shown;

[0049] Figure 4A block diagram of a parallel asynchronous test-based analog IC test anomaly locating system according to the present invention is shown. DETAILED DESCRIPTION

[0050] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0052] Figure 1 The flowchart of the present invention shows a method for locating anomalies in analog IC testing based on parallel asynchronous testing.

[0053] like Figure 1 As shown, the first aspect of the present invention provides a method for locating anomalies in analog IC testing based on parallel asynchronous testing, comprising:

[0054] S102, obtaining data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information;

[0055] S104, acquiring transmission data of each ADC channel of the analog IC during the parallel asynchronous test, constructing a channel response characteristic matrix based on the transmission data, and calculating a timing drift parameter of each channel based on the channel response characteristic matrix;

[0056] S106, performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters;

[0057] S108 , locating abnormal test channels during the parallel asynchronous test of analog ICs according to the abnormal drift channel clusters.

[0058] It is important to note that by acquiring data throughput information for multi-channel analog-to-digital converters during testing, the comprehensive capabilities of each test platform channel in terms of processing speed, buffer response, and signal stability can be comprehensively assessed. This allows for the scientific and rational development of parallel asynchronous testing plans, optimal allocation of test resources, and the avoidance of channel congestion or test bottlenecks caused by uneven resource allocation. Secondly, by acquiring transmission data for each ADC channel and constructing a channel response characteristic matrix, key response characteristics of the channel signals, including amplitude variation, sampling stability, and edge characteristics, are extracted to achieve multi-dimensional modeling of each channel's data behavior, providing a foundation for subsequent refined analysis. By calculating the timing drift parameters for each channel based on this matrix, the channel's stability variation characteristics along the time dimension are further revealed, helping to identify potential timing offset issues caused by asynchronous parallel operation or signal interference. Using a spectral clustering algorithm to cluster the timing drift parameters effectively uncovers correlations between abnormal behaviors across channels, automatically grouping channels with similar drift trends, and forming structured groupings of abnormal channels. Finally, based on the clustering results, the abnormal drift channel clusters extracted can accurately locate the ADC channels that exhibit abnormal characteristics during the parallel asynchronous test process.

[0059] Figure 2 A flow chart of determining a parallel asynchronous test solution for an analog IC according to the present invention is shown.

[0060] According to an embodiment of the present invention, the data throughput information of the multi-channel analog-to-digital converter is obtained during the analog IC test process, and the parallel asynchronous test scheme of the analog IC is determined based on the data throughput information, specifically:

[0061] S202, obtaining a preset number of standard analog ICs for input into a target test platform for pre-testing, and obtaining test output data of a multi-channel analog-to-digital converter during the pre-testing process, wherein the test output data includes data processing delay information, a cache backlog rate, and analog IC current and voltage output signal change data;

[0062] S204, performing a smoothness analysis on the output signal change data to determine the signal sampling integrity and signal jump degree of the output signal;

[0063] S206, determining an abnormal sampling frequency of a data interface of each ADC channel based on the signal sampling integrity and the signal sampling transition degree, and performing a data sampling quality assessment on each ADC channel based on the abnormal sampling frequency to obtain data sampling quality data;

[0064] S208, performing correlation analysis on the data sampling quality data, the data processing delay information, and the cache backlog rate to determine data throughput capacity information of the multi-channel analog-to-digital converter;

[0065] S210 , obtaining data processing volume information of a single analog IC test, determining the number of analog ICs for parallel asynchronous testing based on the data processing volume information and data throughput capacity information, and constructing a parallel asynchronous testing solution.

[0066] It should be noted that limited test platform resources and performance variations among ADC channels can easily lead to data processing bottlenecks, cache congestion, or test delays, impacting overall system test efficiency and test result accuracy. This is particularly true when faced with large-scale parallel asynchronous testing, where performance inconsistencies between channels become more prominent, further impacting test task scheduling and allocation. By introducing a pre-test mechanism, standard analog ICs are used to probe the test platform's performance, capturing test output data across multiple dimensions, including data processing latency, cache backlog rate, and signal output stability. Signal smoothness and transition analysis are used to assess the data sampling quality and frequency of abnormal sampling for each ADC channel, objectively quantifying each channel's sampling stability and responsiveness. Correlation analysis is then performed, combining data processing latency information with cache status, to accurately extract data throughput information for multi-channel analog-to-digital converters. Based on the average data processing capacity of individual analog ICs, the number of analog ICs that can be tested simultaneously is dynamically determined, enabling the adaptive construction of parallel asynchronous test solutions. This significantly improves test resource allocation while maximizing test efficiency while ensuring data integrity and channel stability, minimizing test errors and resource waste caused by channel performance variations. The standard analog IC is an analog IC that meets quality requirements.

[0067] Figure 3 The flowchart of the present invention for calculating the timing drift parameter of each channel is shown.

[0068] According to an embodiment of the present invention, the transmission data of each ADC channel of the analog IC during the parallel asynchronous test is obtained, a channel response characteristic matrix is ​​constructed based on the transmission data, and the timing drift parameter of each channel is calculated based on the channel response characteristic matrix. Specifically,

[0069] S302, acquiring transmission data of each ADC channel of the analog IC during the parallel asynchronous test process, wherein the transmission data includes an amplitude sequence of the channel output, a sampling timestamp, an edge mutation mark, and corresponding temperature, voltage, and current operating condition information;

[0070] S304: extracting response characteristic information of each ADC channel according to the transmitted data, and performing structured representation of the response characteristic information according to a time window to construct a channel response characteristic matrix, wherein the channel response characteristic matrix includes channel response amplitude variation, sampling stability, and signal edge morphology characteristics;

[0071] S306, performing dynamic time warping according to the response change trend of each channel in the channel response feature matrix within different time windows, and extracting the timing drift component of each channel by calculating the alignment error of the response curves between the channels;

[0072] S308 , performing weighted analysis on the timing drift component in combination with the signal edge morphology characteristics of the corresponding channel to obtain a timing drift parameter for each channel.

[0073] It should be noted that the timing drift parameter is a quantitative indicator that reflects the degree of time offset of each ADC channel's response curve relative to other channels during parallel asynchronous testing. It comprehensively measures the temporal consistency of channel sampling, response delay, and the impact of signal edge variations on timing synchronization. By extracting features from channel output amplitude sequences, sampling timestamps, and edge mutation markers, a dynamic time warping algorithm is used to align and analyze the response trends of each channel within different time windows. Weighted processing is then performed based on channel signal edge morphology to accurately reflect the channel's timing response deviation under real-world operating conditions. The resulting timing drift parameter not only reveals sampling differences between channels caused by asynchronous testing but also provides key feature input for the subsequent spectral clustering algorithm, effectively identifying channel clusters exhibiting abnormal timing drift through cluster analysis. This enables early identification and quantitative assessment of channel timing stability issues, improves sensitivity to subtle drift issues, and avoids test misjudgments caused by timing inconsistencies between channels.

[0074] According to an embodiment of the present invention, the step of obtaining transmission data of each ADC channel of the analog IC during the parallel asynchronous test further includes:

[0075] Obtain the amplitude sequence signals of all ADC channels, perform Hanning window processing on each channel signal, and then perform fast Fourier transform to generate amplitude spectrum data;

[0076] Locate the first N frequency components with the largest energy in the amplitude spectrum data as reference frequency points, and expand the predetermined bandwidth to both sides with each reference frequency point as the center to form a detection frequency band;

[0077] Scan the spectrum line whose amplitude value exceeds the noise floor level in each detection frequency band. When the difference between the spectrum line frequency and the reference frequency point is an integer multiple and the spectrum line amplitude value is greater than the predetermined multiple of the amplitude values ​​of the two adjacent frequency points on its left and right, mark the spectrum line as an abnormal spectrum peak.

[0078] If the ratio of the abnormal spectrum peak energy to the total channel energy is within a predefined ratio range, the corresponding period of the channel is recorded as the crosstalk verification interval;

[0079] Calculate the normalized cross-correlation coefficient matrix between all channel amplitude sequence signals, and extract the channel pairs whose physical distance is less than a predetermined distance threshold as the channel pairs to be analyzed;

[0080] For each channel pair to be analyzed, fix the time offset of the first channel signal and slide the time offset of the second channel signal to determine the time offset when the cross-correlation coefficient reaches a maximum value;

[0081] Counting the actual time offset at each time point within the interval to be verified. When the deviation of the actual time offset from the maximum time offset obtained by the sliding calculation exceeds a predetermined tolerance and the number of times the deviation direction changes reaches a predetermined frequency, it is determined that the ADC channel pair has crosstalk coupling in the interval to be crosstalk verified, and the crosstalk interval of the data transmitted by each ADC channel is output;

[0082] The acquisition section of the transmission data is optimized according to the crosstalk interval.

[0083] It should be noted that during the parallel asynchronous testing of analog ICs, as test channel density increases and physical distances between channels decrease, signals from different ADC channels are prone to frequency domain crosstalk coupling. This is particularly true in certain high-frequency components or regions with sudden edge changes. Interference signals may be superimposed on adjacent channels in the form of harmonics, causing non-native signal components to be mixed into the test results, thus affecting the accuracy of channel response feature extraction and timing drift parameters. By applying a Hanning window to the amplitude sequence signal of each ADC channel and then performing a fast Fourier transform, detailed amplitude spectrum data is obtained. The frequency components with the highest energy contribution are then extracted to construct a detection band. This effectively locates abnormal spectral peaks with prominent amplitudes that are octaves of the reference frequency, thereby identifying potential crosstalk risk areas. Furthermore, by combining the physical layout information between the channels with the normalized cross-correlation matrix, channel pairs with close physical distance and high cross-correlation are selected. The time offset dynamics of their signals within the abnormal region are calculated using a sliding window, and the presence of actual crosstalk coupling is determined by statistical deviation and transition characteristics. Finally, the crosstalk interval of each channel is output and the test data acquisition section is optimized to eliminate signal segments affected by crosstalk or perform weighted correction processing. This effectively improves the purity and independence of the sampled data and avoids feature contamination caused by frequency domain coupling.

[0084] According to an embodiment of the present invention, the clustering operation on the timing drift parameters based on the spectral clustering algorithm to extract abnormal drift channel clusters is specifically as follows:

[0085] Calculating the similarity of timing drift parameters between ADC channels based on radial basis functions, constructing a similarity matrix, and calculating a degree matrix based on the similarity matrix;

[0086] Constructing a normalized Laplace matrix based on the similarity matrix and the degree matrix, performing eigendecomposition on the normalized Laplace matrix, and extracting eigenvectors corresponding to the first k smallest eigenvalues;

[0087] Combining the eigenvectors to form an eigenvector matrix, randomly selecting k vectors from the row vectors of the eigenvector matrix as initial cluster centers, calculating the Euclidean distances from all row vectors to each cluster center, and assigning each row vector to the category corresponding to the cluster center closest to it;

[0088] Take the arithmetic mean of the row vector coordinates in each category to obtain the new cluster center point position, and repeat the distance calculation, vector allocation and center point update process until the cluster center point position no longer changes, and obtain k clusters;

[0089] The average value of the timing drift parameters within each cluster is calculated, and the cluster with the highest average value is identified as the abnormal drift channel cluster.

[0090] It should be noted that during the parallel asynchronous testing of analog ICs, significant timing drift may occur in some channels due to factors such as the physical environment, workload, power supply interference, and device aging. These anomalous channels often affect the timing consistency and accuracy of test results. Traditional threshold-based methods struggle to accurately identify these potentially anomalous channels, especially in complex test environments with continuously varying drift levels or a large number of channels. Therefore, a spectral clustering algorithm is employed to perform nonlinear similarity modeling and cluster identification on the timing drift parameters of all channels. Radial basis functions are used to calculate the drift parameter similarity between channels, construct a similarity matrix, and combine this similarity matrix to generate a normalized Laplacian matrix. While preserving the local neighborhood structure between channels, eigendecomposition is performed to obtain a separable low-dimensional subspace representation. These eigenvectors are then clustered using the K-means algorithm. Spectral clustering algorithms excel at handling datasets with non-convex distributions or fuzzy sample boundaries, effectively identifying anomalous clusters that are difficult to separate in the original feature space. Finally, by comparing the average timing drift parameters of the channels within each cluster, the category with a significantly higher drift degree than other clusters is marked as an abnormal drift channel cluster. The diagonal elements of the degree matrix are the sum of the similarities between the corresponding channel and other channels; k is the preset number of clusters.

[0091] According to an embodiment of the present invention, locating abnormal test channels during the parallel asynchronous test of analog ICs based on the abnormal drift channel clustering is specifically as follows:

[0092] According to the abnormal drift channel cluster, extract all ADC channel identification information contained in the cluster, and locate the test abnormal channel according to the ADC channel identification information;

[0093] An analog IC to be tested corresponding to the test abnormal channel is obtained, marked as a test data abnormal analog IC, and an ADC channel is reallocated for the test data abnormal analog IC.

[0094] It should be noted that by extracting the unique identification information of all channels in the cluster, channels with significant timing drift issues can be accurately identified, thereby determining these channels as potential test abnormality channels. Further tracing the specific analog IC units to which these channels are connected during the test process can identify analog IC chip samples that have test data distortion or failure due to channel anomalies and mark them as analog ICs with test data anomalies. This enables the source tracking of abnormal test results and the reallocation of ADC channels to these abnormal analog ICs in subsequent test processes, avoiding the continued use of test paths with existing performance drift, effectively improving the accuracy and repeatability of test data, and reducing the test misjudgment rate due to ADC channel issues.

[0095] According to an embodiment of the present invention, the further embodiment includes:

[0096] Obtaining real-time scheduling logs and resource occupancy status of multiple ADC channels during the parallel asynchronous test process, wherein the scheduling logs include channel bandwidth allocation time slots, buffer call queues, and corresponding test IC identifiers, and the resource occupancy status includes channel occupancy rate and buffer overflow flag;

[0097] Align the resource occupancy status with the bandwidth allocation time slots in the scheduling log in the time domain to construct a resource competition feature matrix, which includes the channel load intensity, preemption conflict frequency and buffer call delay in each time slot;

[0098] Synchronously collecting the timing drift parameters of the multiple ADC channels, performing joint encoding in combination with the resource contention feature matrix of the corresponding time slot, and generating a drift feature vector with a resource contention marker;

[0099] Establishing a contention interference analysis model for drift feature vectors, training the model to identify correlation coefficients between resource load intensity, preemption conflict frequency, and timing drift parameters, dynamically compensating the timing drift parameters based on the correlation coefficients, and generating timing drift compensation parameters;

[0100] Perform cluster analysis on the timing drift compensation parameters of all channels within the same test period. Compare the variance fluctuation of the drift compensation parameters between clusters with the residual distribution of the competitive interference analysis model to calculate the timing confidence of each channel.

[0101] When the channel timing confidence is lower than the preset confidence threshold and belongs to the abnormal drift cluster, the channel abnormality is determined to be a real hardware fault. When the channel timing confidence is higher than the preset confidence threshold, the drift is determined to be caused by resource scheduling conflicts, and a channel rescheduling instruction is generated to the test platform.

[0102] According to the channel rescheduling instruction, the ADC channel is reallocated to the test IC of the conflicting marked channel and the test timing is updated.

[0103] According to an embodiment of the present invention, establishing a competitive interference analysis model of a drift characteristic vector specifically includes:

[0104] Extracting the load intensity and preemption conflict frequency from the drift feature vector with resource contention marker as input features and the timing drift parameter as output label to construct a multivariate regression model;

[0105] The benchmark timing drift parameters collected during the test platform's idle state are used as the intercept constraint of the regression model. The model parameters are iteratively optimized using the gradient descent algorithm until the residual converges.

[0106] The correlation coefficient output by the model is verified for significance. When the absolute value of the correlation coefficient between the load intensity and the timing drift parameter is greater than the correlation coefficient of the preemption conflict frequency and passes the significance test, the load intensity is marked as a strong interference factor.

[0107] A resource conflict intensity weight function is constructed based on the strong interference factor, and the real-time load intensity is input to calculate the contention interference compensation amount. The timing drift compensation parameter is obtained by subtracting the contention interference compensation amount from the original timing drift parameter.

[0108] It's important to note that in highly parallel analog IC testing scenarios, the test platform must simultaneously process massive amounts of ADC channel data from multiple chips. Dynamic resource conflicts, such as channel bandwidth preemption and buffer queue backlogs, can cause scheduling delays in some channels, generating pseudo-anomalies due to timing drift that isn't caused by hardware defects. Traditional testing methods, unable to effectively distinguish between true hardware failures and resource scheduling interference, can not only mistakenly classify normal channels as abnormal, leading to false test stoppages, but can also mask subtle drift characteristics of truly faulty channels due to strong resource competition noise, leading to missed defects. Furthermore, inability to locate the root cause of the conflict can lead to the reallocation of invalid channels. Therefore, by integrating the test system scheduling information with electrical characteristic analysis, a resource competition characteristic matrix is ​​constructed to capture key indicators such as channel load intensity, preemption conflict frequency and buffer delay in real time, and the interference weight of resource conflict on drift signal is quantified through the competition interference analysis model; the platform idle benchmark drift parameter is used to calibrate the model intercept to eliminate inherent noise, and the competition interference compensation amount is dynamically generated based on the strong interference factor marker to output the denoised timing drift compensation parameter; the clustering results and the model residual distribution are further combined to calculate the timing confidence. When the low-confidence channel belongs to the abnormal drift cluster cluster, it is confirmed as a real hardware fault, while the high-confidence abnormal channel triggers the intelligent rescheduling instruction to migrate to the low-conflict resource node; the deep coordination of the test system resource status and chip-level abnormal diagnosis is achieved, which significantly improves the fault location accuracy and reduces the frequency of invalid retests, while extending the life of the test equipment.

[0109] Figure 4 A block diagram of a parallel asynchronous test-based analog IC test anomaly locating system according to the present invention is shown.

[0110] A second aspect of the present invention further provides a system 4 for locating an anomaly in a simulated IC test based on parallel asynchronous testing. The system comprises: a memory 41 and a processor 42. The memory comprises a program for locating an anomaly in a simulated IC test based on parallel asynchronous testing. When the program is executed by the processor, the following steps are implemented:

[0111] Acquiring data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information;

[0112] Acquire transmission data of each ADC channel of the analog IC during a parallel asynchronous test, construct a channel response characteristic matrix based on the transmission data, and calculate a timing drift parameter of each channel based on the channel response characteristic matrix;

[0113] Performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters;

[0114] The abnormal test channels in the parallel asynchronous test process of the analog IC are located according to the abnormal drift channel clustering cluster.

[0115] The present invention discloses a method and system for locating anomalies in analog IC tests based on parallel asynchronous testing, aiming to improve the efficiency and accuracy of locating abnormal channels during complex analog IC testing. This method first obtains data throughput information for the multi-channel analog-to-digital converter (ADC) of the analog IC during testing and, based on this information, formulates a parallel asynchronous testing plan. Subsequently, the transmission data of each ADC channel during testing is collected to construct a channel response characteristic matrix, and the timing drift parameters of each channel are calculated. A spectral clustering algorithm is used to cluster the timing drift parameters and identify clusters of abnormal drift channels. Finally, the clustering results are used to accurately locate the abnormal channels during testing. This method, with its high parallelism and adaptability, is suitable for rapid testing and anomaly analysis of large-scale analog ICs, offering significant advantages in improving test efficiency and reducing testing costs.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0117] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0118] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0119] Those skilled in the art will appreciate that all or part of the steps of the above-mentioned method embodiments may be implemented by hardware associated with program instructions, and the aforementioned program may be stored in a computer-readable storage medium. When the program is executed, the program executes the steps of the above-mentioned method embodiments. The aforementioned storage medium includes various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0120] Alternatively, if the integrated units described above are implemented as software modules and sold or used as standalone products, they can also be stored on a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product, stored on a storage medium, includes instructions for enabling a computer device (such as a personal computer, server, or network device) to execute all or part of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as removable storage devices, ROM, RAM, magnetic disks, or optical disks.

[0121] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for locating anomalies in analog IC testing based on parallel asynchronous testing, characterized in that: The following steps are involved: Obtaining data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information, specifically: Obtaining a preset number of standard analog ICs as input to a target test platform for pre-testing operations, and obtaining test output data of a multi-channel analog-to-digital converter during the pre-testing process, wherein the test output data includes data processing delay information, cache backlog rate, and analog IC current and voltage output signal change data; Performing a smoothness analysis on the output signal change data to determine the signal sampling integrity and signal jump degree of the output signal; Determine the abnormal sampling frequency of the data interface of each ADC channel according to the signal sampling integrity and the signal sampling jump degree, and perform data sampling quality evaluation on each ADC channel according to the abnormal sampling frequency to obtain data sampling quality data; Performing correlation analysis on the data sampling quality data, the data processing delay information, and the cache backlog rate to determine data throughput capacity information of the multi-channel analog-to-digital converter; Acquire data processing volume information of a single analog IC test, determine the number of analog ICs to be tested in parallel asynchronously based on the data processing volume information and data throughput information, and construct a parallel asynchronous testing solution; Acquire transmission data of each ADC channel of the analog IC during a parallel asynchronous test, construct a channel response characteristic matrix based on the transmission data, and calculate a timing drift parameter of each channel based on the channel response characteristic matrix; Performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters; The abnormal test channels in the parallel asynchronous test process of the analog IC are located according to the abnormal drift channel clustering cluster.

2. The method for locating anomalies in analog IC testing based on parallel asynchronous testing according to claim 1, characterized in that: The method of acquiring transmission data of each ADC channel of the analog IC during the parallel asynchronous test process, constructing a channel response characteristic matrix based on the transmission data, and calculating the timing drift parameter of each channel based on the channel response characteristic matrix is ​​specifically as follows: Acquire the transmission data of each ADC channel of the analog IC during the parallel asynchronous test process. The transmission data includes the amplitude sequence of the channel output, the sampling timestamp, the edge mutation mark, and the corresponding temperature, voltage, and current operating condition information; Extracting response characteristic information of each ADC channel according to the transmission data, and performing structured representation of the response characteristic information according to a time window to construct a channel response characteristic matrix, wherein the channel response characteristic matrix includes channel response amplitude variation, sampling stability, and signal edge morphology characteristics; Dynamic time warping is performed based on the response change trend of each channel in different time windows in the channel response feature matrix, and the timing drift component of each channel is extracted by calculating the alignment error of the response curves between the channels; The timing drift component is combined with the signal edge morphology characteristics of the corresponding channel to perform weighted analysis to obtain the timing drift parameter of each channel.

3. The method for locating anomalies in analog IC testing based on parallel asynchronous testing according to claim 2, characterized in that: The step of acquiring transmission data of each ADC channel of the analog IC during the parallel asynchronous test process further includes: Obtain the amplitude sequence signals of all ADC channels, perform Hanning window processing on each channel signal, and then perform fast Fourier transform to generate amplitude spectrum data; Locate the first N frequency components with the largest energy in the amplitude spectrum data as reference frequency points, and expand the predetermined bandwidth to both sides with each reference frequency point as the center to form a detection frequency band; Scan the spectrum line whose amplitude value exceeds the noise floor level in each detection frequency band. When the difference between the spectrum line frequency and the reference frequency point is an integer multiple and the spectrum line amplitude value is greater than the predetermined multiple of the amplitude values ​​of the two adjacent frequency points on its left and right, mark the spectrum line as an abnormal spectrum peak. If the ratio of the abnormal spectrum peak energy to the total channel energy is within a predefined ratio range, the corresponding period of the channel is recorded as the crosstalk verification interval; Calculate the normalized cross-correlation coefficient matrix between all channel amplitude sequence signals, and extract the channel pairs whose physical distance is less than a predetermined distance threshold as the channel pairs to be analyzed; For each channel pair to be analyzed, fix the time offset of the first channel signal and slide the time offset of the second channel signal to determine the time offset when the cross-correlation coefficient reaches a maximum value; Counting the actual time offset at each time point within the interval to be verified. When the deviation of the actual time offset from the maximum time offset obtained by the sliding calculation exceeds a predetermined tolerance and the number of times the deviation direction changes reaches a predetermined frequency, it is determined that the ADC channel pair has crosstalk coupling in the interval to be crosstalk verified, and the crosstalk interval of the data transmitted by each ADC channel is output; The acquisition section of the transmission data is optimized according to the crosstalk interval.

4. The method for locating anomalies in analog IC testing based on parallel asynchronous testing according to claim 1, wherein: The clustering operation is performed on the timing drift parameters based on the spectral clustering algorithm to extract abnormal drift channel clusters, specifically: Calculating the similarity of timing drift parameters between ADC channels based on radial basis functions, constructing a similarity matrix, and calculating a degree matrix based on the similarity matrix; Constructing a normalized Laplace matrix based on the similarity matrix and the degree matrix, performing eigendecomposition on the normalized Laplace matrix, and extracting eigenvectors corresponding to the first k minimum eigenvalues, where k is a preset number of clusters; Combining the eigenvectors to form an eigenvector matrix, randomly selecting k vectors from the row vectors of the eigenvector matrix as initial cluster centers, calculating the Euclidean distances from all row vectors to each cluster center, and assigning each row vector to the category corresponding to the cluster center closest to it; Take the arithmetic mean of the row vector coordinates in each category to obtain the new cluster center point position, and repeat the distance calculation, vector allocation and center point update process until the cluster center point position no longer changes, and obtain k clusters; The average value of the timing drift parameters within each cluster is calculated, and the cluster with the highest average value is identified as the abnormal drift channel cluster.

5. The method for locating anomalies in analog IC testing based on parallel asynchronous testing according to claim 1, characterized in that: The positioning of abnormal test channels in the analog IC parallel asynchronous test process according to the abnormal drift channel cluster is specifically as follows: According to the abnormal drift channel cluster, extract all ADC channel identification information contained in the cluster, and locate the test abnormal channel according to the ADC channel identification information; An analog IC to be tested corresponding to the test abnormal channel is obtained, marked as a test data abnormal analog IC, and an ADC channel is reallocated for the test data abnormal analog IC.

6. A parallel asynchronous test-based analog IC test anomaly location system, characterized in that: The analog IC test anomaly locating system based on parallel asynchronous testing includes a memory and a processor. The memory includes a program for locating anomaly of an analog IC test based on parallel asynchronous testing. When the program for locating anomaly of an analog IC test based on parallel asynchronous testing is executed by the processor, the following steps are implemented: Obtaining data throughput information of a multi-channel analog-to-digital converter during an analog IC test process, and determining a parallel asynchronous test scheme for the analog IC based on the data throughput information, specifically: Obtaining a preset number of standard analog ICs as input to a target test platform for pre-testing operations, and obtaining test output data of a multi-channel analog-to-digital converter during the pre-testing process, wherein the test output data includes data processing delay information, cache backlog rate, and analog IC current and voltage output signal change data; Performing a smoothness analysis on the output signal change data to determine the signal sampling integrity and signal jump degree of the output signal; Determine the abnormal sampling frequency of the data interface of each ADC channel according to the signal sampling integrity and the signal sampling jump degree, and perform data sampling quality evaluation on each ADC channel according to the abnormal sampling frequency to obtain data sampling quality data; Performing correlation analysis on the data sampling quality data, the data processing delay information, and the cache backlog rate to determine data throughput capacity information of the multi-channel analog-to-digital converter; Acquire data processing volume information of a single analog IC test, determine the number of analog ICs to be tested in parallel asynchronously based on the data processing volume information and data throughput information, and construct a parallel asynchronous testing solution; Acquire transmission data of each ADC channel of the analog IC during a parallel asynchronous test, construct a channel response characteristic matrix based on the transmission data, and calculate a timing drift parameter of each channel based on the channel response characteristic matrix; Performing a clustering operation on the time series drift parameters based on a spectral clustering algorithm to extract abnormal drift channel clusters; The abnormal test channels in the parallel asynchronous test process of the analog IC are located according to the abnormal drift channel clustering cluster.

Images