Simulation data generation method and device for chip testing and electronic equipment

Abstract

The invention provides a simulation data generation method and device for chip testing, electronic equipment, a computer storage medium and a chip module, and the method comprises the steps: obtaining a source data template which comprises a fixed code and a plurality of configuration filling bits; according to the parameter type of the configuration filling bit, performing random number configuration on the configuration filling bit to obtain a test parameter group; filling all the test parameter groups into the corresponding configuration filling positions to obtain a source data packet; and selecting a test parameter for configuring filling position filling in the source data packet to generate simulation source data. By automatically and randomly configuring the parameter value for each configuration filling bit in the source data template, each configuration filling bit can obtain a plurality of different test parameters, so that a plurality of pieces of simulation source data can be automatically generated after selection according to the preset configuration condition, different parameters are configured for the simulation data in single simulation verification, and the simulation verification efficiency is improved. And the number of simulation data is effectively increased, and the problem that the existing IP core simulation verification efficiency is low is solved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a method and device for generating simulation data for chip testing, electronic equipment, computer storage medium, and chip module. Background Art

[0002] With the advancement of integrated circuit technology, chips are becoming increasingly popular as self-contained, ready-to-use components. These chips integrate numerous circuit modules (IP cores, or intellectual property components) to implement their respective functions. Common IP cores include processor cores, memory controllers, interface protocols, and graphics processing units. To ensure that all IP cores not only correctly implement their own functions but also seamlessly collaborate with other modules on the chip, chip testing, including simulation verification of the IP cores, is often required.

[0003] Currently, simulation verification of IP cores (especially software algorithm IP cores) requires the use of simulation data with different configurations to ensure the IP core functions in various scenarios. However, existing simulation data cannot be configured with different parameters. Therefore, after each simulation verification, the simulation data must be replaced and re-verified until all available simulation data is used, resulting in low verification efficiency. Furthermore, the amount of simulation data suitable for IP cores is limited, making it impossible to guarantee that the IP core simulation verification can traverse all scenarios, resulting in poor reliability of simulation verification results. Summary of the Invention

[0004] The purpose of the present invention is to provide a method and device for generating simulation data for chip testing, an electronic device, a computer storage medium and a chip module, so as to at least solve the problem of low efficiency of existing IP core simulation verification.

[0005] To solve the above technical problems, the present invention provides a method for generating simulation data for chip testing, comprising: Obtaining a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; Under preset constraints, according to the parameter type corresponding to the configuration fill bit, each configuration fill bit is configured with a random number to obtain a test parameter group corresponding to each configuration fill bit; Fill all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain the source data packet; According to the preset configuration conditions, the test parameters for filling each configuration filling bit in the source data packet are selected to generate simulation source data.

[0006] Optionally, in the simulation data generation method for chip testing, the method for obtaining the source data template includes: Setting a test requirement information table, wherein the test requirement information table includes a plurality of test requirement information; Extract test configuration information from the test requirement information table; Use the script data platform to parse the test configuration information and generate multiple test source codes; Multiple test source codes are integrated and analyzed to separate fixed codes and configuration fill bits to obtain source data templates.

[0007] Optionally, in the simulation data generation method for chip testing, the method of performing random number configuration on each configuration padding bit according to the parameter type corresponding to the configuration padding bit under preset constraints to obtain a test parameter group corresponding to each configuration padding bit includes: Determine whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter; For protocol parameters, the value range of the test parameter for the configuration padding bit is determined according to the protocol specification; For configuration parameters, the value range of the test parameter of the configuration fill bit is determined according to the configuration requirements; Randomly generate at least one test parameter within the value range of the test parameter configured with the padding bit; All test parameters randomly generated for each configuration fill bit are used as the test parameter group for the configuration fill bit.

[0008] Optionally, in the simulation data generation method for chip testing, after generating the simulation source data, the simulation data generation method for chip testing further includes: generating a target test vector based on at least one simulation source data using a script algorithm platform; The target test vector is packaged to obtain simulation data.

[0009] Optionally, in the simulation data generation method for chip testing, the method of generating a target test vector based on at least one simulation source data using a script algorithm platform includes: Writing at least one simulation source data into the script algorithm platform; Using the script algorithm platform, simulate the simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data; According to register parameters, protocol parameters, input data and output data, protocol conversion is performed on the simulation source data to obtain the target test vector.

[0010] Optionally, in the simulation data generation method for chip testing, the method of encapsulating the target test vector to obtain simulation data includes: Fill the input data and output data that meet the algorithm protocol into the target test vector to obtain simulation data.

[0011] To solve the above technical problems, the present invention further provides a simulation data generation device for chip testing, which is used to implement the simulation data generation method for chip testing as described in any one of the above items. The simulation data generation device for chip testing includes: A template acquisition module is used to acquire a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; A parameter configuration module is used to configure each configuration filling bit with a random number according to the parameter type corresponding to the configuration filling bit under preset constraints to obtain a test parameter group corresponding to each configuration filling bit; The source data generation module is used to fill all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain the source data packet, and select the test parameters to be filled in each configuration filling bit in the source data packet according to the preset configuration conditions to generate simulation source data.

[0012] Optionally, in the simulation data generation device for chip testing, the template acquisition module is provided with a test requirement information table, a configuration extraction unit and a script data platform; the test requirement information table is used to fill in the test requirement information; the configuration extraction unit is used to extract the test configuration information from the test requirement information table; the script data platform is used to parse the test configuration information, generate multiple test source codes, and integrate and analyze the multiple test source codes to separate the fixed code and the configuration fill bits to obtain the source data template.

[0013] Optionally, in the simulation data generating device for chip testing, the parameter configuration module includes a parameter confirmation unit, a parameter generation unit and a parameter integration unit; the parameter confirmation unit is used to determine whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter; the parameter generation unit is used to determine the value range of the test parameter of the configuration fill bit according to the confirmation result of the parameter confirmation unit, for the protocol parameters according to the protocol specification, and for the configuration parameters according to the configuration requirements, and randomly generate at least one test parameter within the value range of the test parameter of the configuration fill bit; the parameter integration unit is used to use all the test parameters randomly generated for each configuration fill bit as the test parameter group of the configuration fill bit.

[0014] Optionally, in the simulation data generating device for chip testing, the simulation data generating device for chip testing also includes a simulation data generating module; the simulation data generating module is used to use a script algorithm platform to generate a target test vector based on at least one simulation source data, and encapsulate the target test vector to obtain simulation data.

[0015] Optionally, in the simulation data generation device for chip testing, the simulation data generation module includes a script algorithm platform and a vector encapsulation unit; the script algorithm platform is used to simulate the input simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data, and perform protocol conversion on the simulation source data according to the register parameters, protocol parameters, input data and output data to obtain a target test vector; the vector encapsulation unit is used to fill the input data and output data that meet the algorithm protocol into the target test vector to encapsulate the target test vector to obtain simulation data.

[0016] In order to solve the above technical problems, the present invention also provides an electronic device, including a memory, a processor and an executable program stored in the memory and capable of being run by the processor; when the processor runs the executable program, it executes the simulation data generation method for chip testing as described in any one of the above items.

[0017] In order to solve the above technical problems, the present invention also provides a computer storage medium, which stores an executable program; when the executable program is executed, it implements the simulation data generation method for chip testing as described in any of the above items.

[0018] To solve the above technical problems, the present invention also provides a chip or chip module, which is coupled to a memory and is used to execute a computer program stored in the memory to execute the simulation data generation method for chip testing as described in any one of the above items.

[0019] The present invention provides a simulation data generation method and device for chip testing, an electronic device, a computer storage medium, and a chip module, comprising: obtaining a source data template, wherein the source data template includes a fixed code and a plurality of configuration fill bits; under preset constraints, performing random number configuration on each configuration fill bit according to the parameter type corresponding to the configuration fill bit to obtain a test parameter group corresponding to each configuration fill bit; filling all test parameter groups into the source data template according to the corresponding configuration fill bits to obtain a source data packet; selecting the test parameters filled in each configuration fill bit in the source data packet according to the preset configuration conditions to generate simulation source data. By automatically and randomly configuring parameter values for each configuration fill bit in the source data template, each configuration fill bit can obtain a plurality of different test parameters, so that after selecting according to the preset configuration conditions, a plurality of simulation source data can be automatically generated, which not only realizes the configuration of different parameters for simulation data in a single simulation verification, but also effectively expands the amount of simulation data, solving the problem of low efficiency of existing IP core simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flowchart of a method for generating simulation data for chip testing provided in this embodiment; Figure 2 A schematic diagram of the process of generating test source code from the script data platform provided in this embodiment; Figure 3 A schematic diagram of the process of generating simulation source data provided in this embodiment; Figure 4 A schematic diagram of the process of generating target test vectors provided in this embodiment; Figure 5 A schematic diagram of the structure of a simulation data generating device for chip testing provided in this embodiment; Figure 6 A schematic diagram of the structure of the template acquisition module provided in this embodiment; Figure 7 A schematic diagram of the structure of the parameter configuration module provided in this embodiment; Figure 8 A schematic structural diagram of a simulation data generating device for chip testing provided by this embodiment and having a simulation data generating module. DETAILED DESCRIPTION

[0021] The following is a further detailed description of the simulation data generation method and device for chip testing, electronic device, computer storage medium and chip module proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often part of the actual structure. In particular, each drawing needs to show different focuses, and sometimes different proportions are used.

[0022] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0023] This embodiment provides a method for generating simulation data for chip testing, such as Figure 1 Shown, including: S1, obtaining a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; S2, under preset constraints, performing random number configuration on each configuration padding bit according to the parameter type corresponding to the configuration padding bit, so as to obtain a test parameter group corresponding to each configuration padding bit; S3, filling all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain a source data packet; S4, according to the preset configuration conditions, selecting the test parameters for filling each configuration filling bit in the source data packet to generate simulation source data.

[0024] The simulation data generation method for chip testing provided in this embodiment automatically and randomly configures parameter values for each configuration fill bit in the source data template, so that each configuration fill bit can obtain multiple different test parameters. Therefore, after selecting according to preset configuration conditions, multiple simulation source data can be automatically generated. This not only realizes the configuration of different parameters for simulation data in a single simulation verification, but also effectively expands the amount of simulation data, solving the problem of low efficiency of existing IP core simulation verification.

[0025] Specifically, in this embodiment, step S1, the method of obtaining the source data template includes: S11, setting a test requirement information table, wherein the test requirement information table includes a plurality of test requirement information.

[0026] In actual applications, the test requirement information table may be an editable Excel form, in which relevant test requirement information may be filled in column by column according to the actual simulation verification requirements of the IP core.

[0027] S12, extracting test configuration information from the test requirement information table.

[0028] In actual applications, the script data platform can be used to input the test requirement information table into the script data platform, and the script data platform extracts the test configuration information from the test requirement information table according to a preset program. Of course, the test configuration information can also be extracted from the test requirement information table using additional programs or manual extraction methods, and this application does not limit this.

[0029] Test configuration information usually includes test keywords and parameters, such as protocol name, configuration name, protocol parameters, and configuration parameters.

[0030] S13, using the script data platform, parsing the test configuration information and generating multiple test source codes.

[0031] like Figure 2 As shown, the test configuration information extracted from the test requirement information table is entered into the script data platform, and the script data platform generates the test source code by parsing the test configuration information.

[0032] In this embodiment, the script data platform generates a test source code for each test requirement information, which facilitates the subsequent integration and analysis of sufficient test source code, making the separation of fixed code and configuration filler more accurate. Of course, in other embodiments, multiple test requirement information can also be used to generate a test source code. For example, multiple test requirement information in the test requirement information table can be randomly combined to obtain multiple combined test requirement information, and a test source code is generated using the test configuration information corresponding to the combined test requirement information.

[0033] The implementation of the script data platform can be designed and developed by those skilled in the art based on the functional settings of this application, and this application will not go into details about it.

[0034] S14, integrating and analyzing the plurality of test source codes to separate the fixed codes and the configuration fill bits, and obtaining a source data template.

[0035] In practical applications, multiple test source codes can be integrated and analyzed using pre-set programs or manual methods. Common portions and logic code across multiple test source codes can be treated as fixed code, while adjustable portions such as protocol names, configuration names, protocol parameters, and configuration parameters can be used as configuration padding. Subsequently, multiple test source codes can be concatenated and redundant code removed to create a source data template.

[0036] Furthermore, in this embodiment, in step S2, under preset constraints, according to the parameter type corresponding to the configuration fill bit, a method of performing a random number configuration on each configuration fill bit to obtain a test parameter group corresponding to each configuration fill bit includes: S21, determining whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter.

[0037] Specifically, protocol parameters are parameters specified by the protocol specification; configuration parameters include register configuration parameters, which are used to configure certain hardware parameters. In actual applications, the parameter type that should be filled in the configuration fill bit can be determined based on the context of the configuration fill bit in the source data template.

[0038] S22-1: For protocol parameters, determine the value range of the test parameter for the configuration padding bit according to the protocol specification.

[0039] For example, the 802.11ax protocol followed by Wi-Fi 7 stipulates that the modulation level (Modulation and Coding Strategy, MCS) ranges from 0 to 11. Therefore, if the configuration padding bit corresponds to the MCS, the value range of its test parameter is 0 to 11.

[0040] S22-2: For configuration parameters, determine the value range of the test parameter of the configuration fill bit according to the configuration requirements.

[0041] In practical applications, there are threshold requirements for registers. For example, the threshold of a register is 0 to 10. Therefore, if the configuration padding bit corresponds to the register, the value range of its test parameter is 0 to 10.

[0042] S23: Randomly generate at least one test parameter within the value range of the test parameter configured with the padding bit.

[0043] Specifically, in practical applications, a random value generator can be used to randomly generate test parameters within a range for each configuration padding bit. Compared to traditional solutions, this eliminates the need to configure parameter values based on test scenarios. Instead, random generation is performed based on constraints such as protocol specifications and register thresholds. The final test parameters are then determined by reverse verification of the scenario parameters. This allows for traversal of all parameter values without requiring specialized analysis of test requirements, saving both the time and labor required to analyze and verify scenario parameters.

[0044] Of course, other constraints may also be considered when generating test parameters, such as integers, odd numbers, etc. The setting of the constraints may be based on the specific parameters corresponding to each configuration padding bit, and this application does not impose any restrictions on this.

[0045] S24, taking all the test parameters randomly generated for each configuration filling bit as the test parameter group for the configuration filling bit.

[0046] Specifically, each configuration fill position can randomly generate at least one test parameter, package all the test parameters into a test parameter group, and name the test parameter group with the name corresponding to the configuration fill position, and store it as a candidate parameter to be filled in the configuration fill position for later call.

[0047] Furthermore, in this embodiment, in step S3, all test parameter groups are filled into the source data template according to the corresponding configuration filling bits to obtain a source data packet. In other words, the source data packet is filled with its corresponding test parameter groups according to the configuration filling bits.

[0048] And, in this embodiment, step S4 selects the test parameters for filling each configuration filling bit in the source data packet according to the preset configuration conditions to generate simulation source data.

[0049] Specifically, such as Figure 3As shown, a test parameter is extracted from the test parameter group filled with each configuration padding bit in the source data packet according to a preset method and filled into the configuration padding bit to obtain a simulation source data. In this way, each configuration padding bit in the source data packet is filled with a test parameter, and at least one configuration padding bit in different simulation source data is filled with a different test parameter, thereby obtaining multiple simulation source data.

[0050] In actual applications, the test parameters can be extracted in an ascending order of values, that is, each configuration fill bit is filled with the minimum value in its test parameter group to obtain the first simulation source data; each configuration fill bit is filled with the second minimum value in its test parameter group to obtain the second simulation source data; ... each configuration fill bit is filled with the maximum value in its test parameter group to obtain the last simulation source data. Of course, it can also be done in a permutation and combination manner, that is, controlling one configuration fill bit to traverse all test parameters in its test parameter group, while controlling the test parameters filled by other configuration fill bits to remain unchanged, thereby obtaining multiple simulation source data; then controlling another configuration fill bit to traverse all test parameters in its test parameter group, while controlling the test parameters filled by other configuration fill bits to remain unchanged, thereby obtaining multiple simulation source data; until all configuration fill bits traverse all test parameters in their test parameter groups. Specific configuration conditions can be set according to actual needs, and this application does not impose any restrictions.

[0051] Furthermore, after generating the simulation source data in step S4, the simulation data generation method for chip testing further includes: S5, using the script algorithm platform to generate a target test vector according to at least one simulation source data.

[0052] Specifically, in this embodiment, Figure 4 As shown, step S5 includes: first, writing at least one simulation source data into the script algorithm platform; then, using the script algorithm platform, simulating the simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data; finally, performing protocol conversion on the simulation source data according to the register parameters, protocol parameters, input data and output data to obtain the target test vector.

[0053] In this embodiment, one target test vector is generated for each simulation source data, which facilitates the subsequent generation of sufficient simulation data. Of course, in other embodiments, a target test vector can also be generated using multiple simulation source data, for example, by randomly combining multiple simulation source data and generating a target test vector using the combined simulation source data.

[0054] S6, encapsulate the target test vector to obtain simulation data.

[0055] Specifically, in this embodiment, input data and output data that meet the algorithm protocol are filled into the target test vector to obtain simulation data, wherein the simulation data includes the driving vector data and the inspection output vector data of the device under test.

[0056] The simulation data generation method for chip testing provided in this embodiment uses a script data platform to generate a source data template based on test requirement information, and configures random numbers for the configuration fill bits in the source data template, so as to quickly obtain simulation source data that traverses all scenarios; then uses a script algorithm platform to obtain simulation data based on the simulation source data, which is used to simulate and verify the IP core. This not only realizes the configuration of different parameters for the simulation data in a single simulation verification, but also effectively expands the amount of simulation data, solving the problem of low efficiency of existing IP core simulation verification.

[0057] This embodiment also provides a simulation data generation device for chip testing, which is used to implement the simulation data generation method for chip testing as described above. Figure 5 As shown, the simulation data generating device for chip testing includes: A template acquisition module is used to acquire a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; A parameter configuration module is used to configure each configuration filling bit with a random number according to the parameter type corresponding to the configuration filling bit under preset constraints to obtain a test parameter group corresponding to each configuration filling bit; The source data generation module is used to fill all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain the source data packet, and select the test parameters to be filled in each configuration filling bit in the source data packet according to the preset configuration conditions to generate simulation source data.

[0058] The simulation data generation device for chip testing provided in this embodiment automatically and randomly configures parameter values for each configuration fill bit in the source data template, so that each configuration fill bit can obtain multiple different test parameters. Therefore, after selecting according to preset configuration conditions, multiple simulation source data can be automatically generated. This not only realizes the configuration of different parameters for simulation data in a single simulation verification, but also effectively expands the amount of simulation data, solving the problem of low efficiency of existing IP core simulation verification.

[0059] Specifically, in this embodiment, Figure 6As shown, the template acquisition module is provided with a test requirement information table, a configuration extraction unit and a script data platform; the test requirement information table is used to fill in the test requirement information; the configuration extraction unit is used to extract the test configuration information from the test requirement information table; the script data platform is used to parse the test configuration information, generate multiple test source codes, and integrate and analyze the multiple test source codes to separate the fixed code and the configuration filling bits to obtain the source data template.

[0060] And, in this embodiment, if Figure 7 As shown, the parameter configuration module includes a parameter confirmation unit, a parameter generation unit and a parameter integration unit; the parameter confirmation unit is used to determine whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter; the parameter generation unit is used to determine the value range of the test parameter of the configuration fill bit according to the confirmation result of the parameter confirmation unit, the protocol parameter according to the protocol specification, and the configuration parameter according to the configuration requirements, and randomly generate at least one test parameter within the value range of the test parameter of the configuration fill bit; the parameter integration unit is used to use all the test parameters randomly generated for each configuration fill bit as the test parameter group of the configuration fill bit.

[0061] Furthermore, in this embodiment, the simulation data generation device for chip testing also includes a simulation data generation module; the simulation data generation module is used to use a script algorithm platform to generate a target test vector based on at least one simulation source data, and encapsulate the target test vector to obtain simulation data.

[0062] Specifically, in this embodiment, Figure 8 As shown, the simulation data generation module includes a script algorithm platform and a vector encapsulation unit; the script algorithm platform is used to simulate the input simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data, and perform protocol conversion on the simulation source data according to the register parameters, protocol parameters, input data and output data to obtain the target test vector; the vector encapsulation unit is used to fill the input data and output data that meet the algorithm protocol into the target test vector to encapsulate the target test vector and obtain simulation data.

[0063] In addition, this embodiment also provides an electronic device, including a memory, a processor, and an executable program stored in the memory and capable of being run by the processor; when the processor runs the executable program, it executes the simulation data generation method for chip testing as described above.

[0064] Furthermore, this embodiment further provides a computer storage medium storing an executable program. When the executable program is executed, the simulation data generation method for chip testing as described above is implemented.

[0065] Furthermore, this embodiment further provides a chip or a chip module, wherein the chip or the chip module is coupled to a memory and is used to execute a computer program stored in the memory to execute the simulation data generation method for chip testing as described above.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0067] The simulation data generation method and device, electronic device, computer storage medium and chip module provided in this embodiment for chip testing include: obtaining a source data template, wherein the source data template includes a fixed code and multiple configuration fill bits; under preset constraints, performing random number configuration on each configuration fill bit according to the parameter type corresponding to the configuration fill bit to obtain a test parameter group corresponding to each configuration fill bit; filling all test parameter groups into the source data template according to the corresponding configuration fill bits to obtain a source data packet; according to preset configuration conditions, selecting the test parameters filled in each configuration fill bit in the source data packet to generate simulation source data. By automatically and randomly configuring parameter values for each configuration fill bit in the source data template, each configuration fill bit can obtain multiple different test parameters, so that after selecting according to the preset configuration conditions, multiple simulation source data can be automatically generated, which not only realizes the configuration of different parameters for simulation data in a single simulation verification, but also effectively expands the amount of simulation data, solving the problem of low efficiency of existing IP core simulation verification.

[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for generating simulation data for chip testing, characterized in that: include: Obtaining a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; Under preset constraints, according to the parameter type corresponding to the configuration fill bit, each configuration fill bit is configured with a random number to obtain a test parameter group corresponding to each configuration fill bit; Fill all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain the source data packet; According to the preset configuration conditions, the test parameters for filling each configuration filling bit in the source data packet are selected to generate simulation source data.

2. The method for generating simulation data for chip testing according to claim 1, wherein: The method for obtaining the source data template includes: Setting a test requirement information table, wherein the test requirement information table includes a plurality of test requirement information; Extract test configuration information from the test requirement information table; Use the script data platform to parse the test configuration information and generate multiple test source codes; Multiple test source codes are integrated and analyzed to separate fixed codes and configuration fill bits to obtain source data templates.

3. The method for generating simulation data for chip testing according to claim 1, wherein: The method of performing random number configuration on each configuration padding bit according to the parameter type corresponding to the configuration padding bit under preset constraints to obtain a test parameter group corresponding to each configuration padding bit includes: Determine whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter; For protocol parameters, the value range of the test parameter for the configuration padding bit is determined according to the protocol specification; For configuration parameters, the value range of the test parameter of the configuration fill bit is determined according to the configuration requirements; Randomly generate at least one test parameter within the value range of the test parameter configured with the padding bit; All test parameters randomly generated for each configuration fill bit are used as the test parameter group for the configuration fill bit.

4. The method for generating simulation data for chip testing according to claim 1, wherein: After generating the simulation source data, the simulation data generation method for chip testing further includes: generating a target test vector based on at least one simulation source data using a script algorithm platform; The target test vector is packaged to obtain simulation data.

5. The method for generating simulation data for chip testing according to claim 4, wherein: The method of generating a target test vector according to at least one simulation source data using a script algorithm platform includes: Writing at least one simulation source data into the script algorithm platform; Using the script algorithm platform, simulate the simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data; According to register parameters, protocol parameters, input data and output data, protocol conversion is performed on the simulation source data to obtain the target test vector.

6. The method for generating simulation data for chip testing according to claim 4, wherein: The method of encapsulating the target test vector to obtain simulation data includes: Fill the input data and output data that meet the algorithm protocol into the target test vector to obtain simulation data.

7. A simulation data generation device for chip testing, used to implement the simulation data generation method for chip testing according to any one of claims 1 to 6, characterized in that: The simulation data generating device for chip testing includes: A template acquisition module is used to acquire a source data template, wherein the source data template includes a fixed code and a plurality of configuration filling bits; A parameter configuration module is used to configure each configuration filling bit with a random number according to the parameter type corresponding to the configuration filling bit under preset constraints to obtain a test parameter group corresponding to each configuration filling bit; The source data generation module is used to fill all test parameter groups into the source data template according to the corresponding configuration filling bits to obtain the source data packet, and select the test parameters to be filled in each configuration filling bit in the source data packet according to the preset configuration conditions to generate simulation source data.

8. The simulation data generating device for chip testing according to claim 7, characterized in that: The template acquisition module is provided with a test requirement information table, a configuration extraction unit and a script data platform; the test requirement information table is used to fill in the test requirement information; the configuration extraction unit is used to extract the test configuration information from the test requirement information table; The script data platform is used to parse the test configuration information, generate multiple test source codes, and integrate and analyze the multiple test source codes to separate the fixed codes and configuration fill bits to obtain a source data template.

9. The simulation data generating device for chip testing according to claim 7, characterized in that: The parameter configuration module includes a parameter confirmation unit, a parameter generation unit and a parameter integration unit; the parameter confirmation unit is used to determine whether the parameter type corresponding to each configuration fill bit is a protocol parameter or a configuration parameter; the parameter generation unit is used to determine the value range of the test parameter of the configuration fill bit according to the confirmation result of the parameter confirmation unit, the protocol parameter according to the protocol specification, and the configuration parameter according to the configuration requirements, and randomly generate at least one test parameter within the value range of the test parameter of the configuration fill bit; the parameter integration unit is used to use all the randomly generated test parameters for each configuration fill bit as the test parameter group of the configuration fill bit.

10. The simulation data generating device for chip testing according to claim 7, characterized in that: The simulation data generating device for chip testing also includes a simulation data generating module; the simulation data generating module is used to use a script algorithm platform to generate a target test vector according to at least one simulation source data, and encapsulate the target test vector to obtain simulation data.

11. The simulation data generating device for chip testing according to claim 7, characterized in that: The simulation data generation module includes a script algorithm platform and a vector encapsulation unit; The script algorithm platform is used to simulate the input simulation source data to extract register parameters, protocol parameters, input data and output data from the simulation source data, and perform protocol conversion on the simulation source data according to the register parameters, protocol parameters, input data and output data to obtain target test vectors; The vector encapsulation unit is used to fill the input data and output data that meet the algorithm protocol into the target test vector to encapsulate the target test vector and obtain simulation data.

12. An electronic device, characterized in that: It comprises a memory, a processor and an executable program stored in the memory and capable of being run by the processor; when the processor runs the executable program, it executes the simulation data generation method for chip testing according to any one of claims 1 to 6.

13. A computer storage medium, characterized in that The computer storage medium stores an executable program; when the executable program is executed, the simulation data generation method for chip testing according to any one of claims 1 to 6 is implemented.

14. A chip module, characterized in that: The chip module is coupled to a memory and is configured to execute a computer program stored in the memory to execute the simulation data generation method for chip testing according to any one of claims 1 to 6.

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