Multi-agent-based large-scale chip verification method, device and equipment
Through the multi-intelligent verification method, multiple agents are created for distributed chip verification, solving the problem of insufficient coverage in traditional chip verification methods and achieving more efficient and accurate chip verification.
Patent Information
- Application Number
- CN202510562439.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-08-12
AI Technical Summary
Traditional chip verification methods are difficult to utilize distributed computing power, resulting in insufficient coverage and incomplete handling of abnormal conditions, increasing the risk of chip chip failure.
Using multi-agent-based verification methods, functional verification agents, performance verification agents, boundary verification agents and error verification agents are created, data exchange and task allocation are performed through distributed agent communication networks, and comprehensive analysis is performed using the data fusion center.
It improves the comprehensiveness and accuracy of large-scale chip verification, shortens verification time, enhances the probability of discovering design defects, and improves verification efficiency and accuracy.
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Figure CN120470988A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip verification technology, for example, to a large-scale chip verification method, device, and equipment based on multi-agents. Background Art
[0002] With the continuous development of integrated circuit technology, the scale and design complexity of chips have increased dramatically, which has put higher requirements on chip verification. The accuracy and efficiency of chip verification are directly related to the quality of the product.
[0003] However, traditional chip verification methods mainly rely on single computing resources and verification strategies, making it difficult to utilize distributed computing capabilities. They have problems such as insufficient coverage and incomplete handling of abnormal conditions, increasing the risk of chip tape-out failure.
[0004] Therefore, how to enhance the comprehensiveness and accuracy of large-scale chip verification has become a technical problem that needs to be solved urgently.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application. Summary of the Invention
[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0007] The multi-agent-based large-scale chip verification method, apparatus, device, and storage medium provided by the embodiments of the present disclosure solve the problem of insufficient comprehensiveness and accuracy in traditional large-scale chip verification processes.
[0008] The multi-agent-based large-scale chip verification method in the embodiment of the present disclosure includes:
[0009] Based on the chip specification, obtain the chip's performance parameters and determine the verification target;
[0010] Based on the different focuses of chip verification corresponding to the verification targets, functional verification agents, performance verification agents, boundary verification agents, and error verification agents are created, and independent computing resources are allocated to each agent to determine the corresponding specific verification task scope;
[0011] Building a distributed agent communication network based on each agent to enable real-time exchange of verification data, status information and verification results between agents;
[0012] Based on the chip design architecture and verification requirements, the large-scale chip verification task is decomposed into multiple subtasks. A task allocation algorithm based on task priority and agent capabilities is used to assign the subtasks to the corresponding agents for verification.
[0013] The data generated during the verification process of each intelligent agent is uploaded to the data fusion center for comprehensive analysis to generate verification results.
[0014] In some embodiments, obtaining chip performance parameters and determining verification targets based on the chip specification include:
[0015] Based on the chip specification, the chip performance parameters are obtained. Based on the functions and performance parameters combined with the chip design requirements and application scenarios, a variety of test scenarios and test case generation strategies are adopted to determine the verification goals to ensure that potential design defects and performance issues are discovered.
[0016] In some embodiments, the functional verification agent is used to verify the functional correctness of each functional module of the chip;
[0017] The performance verification agent is used to verify chip performance indicators;
[0018] Boundary verification agents are used to simulate extreme environments to test chip performance;
[0019] The error verification agent is used to test the chip's error handling capabilities.
[0020] In some embodiments, the above method further comprises:
[0021] Each agent obtains the verification progress and status of other agents through the network, and adjusts the task allocation in real time based on the agent's workload, verification progress and results.
[0022] In some embodiments, the above method further comprises:
[0023] Dynamically adjust the priority of the agent based on the problems found during the verification process and their corresponding importance.
[0024] In some embodiments, the data generated during the verification process of each agent is uploaded to the data fusion center for comprehensive analysis to generate verification results, including:
[0025] Upload the data and results generated during the verification process of each intelligent agent to the data fusion center;
[0026] The data fusion center uses machine learning algorithms to associate the data corresponding to the functional verification agent, performance verification agent, boundary verification agent and error verification agent, determine the potential relationship between different verification indicators, and generate verification results.
[0027] In some embodiments, the large-scale chip verification task is decomposed into multiple subtasks based on the chip design architecture and verification requirements, including:
[0028] For functional verification tasks, they are divided into verification subtasks for each functional module;
[0029] The performance verification task is divided into power consumption verification and timing verification subtasks.
[0030] The multi-agent-based large-scale chip verification device in the embodiment of the present disclosure includes:
[0031] The determination module is used to obtain the chip's performance parameters based on the chip specification and determine the verification target;
[0032] The determination module is further configured to create a functional verification agent, a performance verification agent, a boundary verification agent, and an error verification agent based on the different focuses of chip verification corresponding to the verification target, and allocate independent computing resources to each agent to determine the corresponding specific verification task scope;
[0033] A construction module is used to build a distributed agent communication network based on each agent, so that each agent can exchange verification data, status information and verification results in real time;
[0034] The verification module is used to decompose large-scale chip verification tasks into multiple subtasks based on the chip design architecture and verification requirements, and use a task allocation algorithm based on task priority and agent capabilities to assign subtasks to corresponding agents for verification;
[0035] The verification module is also used to upload the data generated during the verification process of each intelligent agent to the data fusion center for comprehensive analysis and generate verification results.
[0036] An electronic device provided by an embodiment of the present disclosure includes at least one processor;
[0037] and a memory communicatively coupled to the at least one processor;
[0038] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned large-scale chip verification method based on multi-agent.
[0039] The storage medium provided by the embodiment of the present disclosure stores program instructions, which, when run, execute the above-mentioned large-scale chip verification method based on multi-agents.
[0040] The multi-agent-based large-scale chip verification method, apparatus, device, and storage medium provided by the embodiments of the present disclosure can achieve the following technical effects:
[0041] The multi-agent based large-scale chip verification method provided by the present invention utilizes the distributed processing, autonomous decision-making and mutual collaboration characteristics of multi-agents, which can give full play to the advantages of each agent and improve the comprehensiveness and accuracy of large-scale chip verification to meet the needs of the rapid development of modern large-scale chips.
[0042] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,
[0044] Figure 1 1 is a flow chart of a multi-agent-based large-scale chip verification method provided by an embodiment of the present disclosure;
[0045] Figure 2 1 is a flow chart of another large-scale chip verification method based on multi-agents provided by an embodiment of the present disclosure;
[0046] Figure 3 Schematic diagram of a large-scale chip verification device based on multi-agents provided by an embodiment of the present disclosure;
[0047] Figure 4 It is a structural diagram of a large-scale chip verification device based on multiple agents provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0048] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0049] The terms "first," "second," and the like in the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to facilitate the description of the embodiments of the present disclosure herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.
[0050] Unless otherwise stated, the term "plurality" means two or more.
[0051] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.
[0052] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0053] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0054] In order to solve the above problems, the present disclosure provides a large-scale chip verification method, apparatus, device and storage medium based on multi-agent.
[0055] The following describes the multi-agent-based large-scale chip verification method, device, equipment and storage medium provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.
[0056] Figure 1 This is a flow chart of a large-scale chip verification method based on multi-agents provided in an embodiment of the present disclosure.
[0057] like Figure 1 As shown, the multi-agent-based large-scale chip verification method may include:
[0058] S101, based on the chip specification, obtain the chip performance parameters and determine the verification target;
[0059] S102: Create a functional verification agent, a performance verification agent, a boundary verification agent, and an error verification agent based on the different focuses of chip verification corresponding to the verification target, allocate independent computing resources to each agent, and determine the corresponding specific verification task scope;
[0060] S103, constructing a distributed agent communication network based on each agent to enable the agents to exchange verification data, status information and verification results in real time;
[0061] S104: Decompose the large-scale chip verification task into multiple subtasks based on the chip design architecture and verification requirements, and use a task allocation algorithm based on task priority and agent capabilities to assign the subtasks to corresponding agents for verification;
[0062] S105, uploading the data generated during the verification process of each intelligent agent to the data fusion center for comprehensive analysis to generate verification results.
[0063] In some embodiments, obtaining chip performance parameters and determining verification targets based on the chip specification include:
[0064] Based on the chip specification, the chip performance parameters are obtained. Based on the functions and performance parameters combined with the chip design requirements and application scenarios, a variety of test scenarios and test case generation strategies are adopted to determine the verification goals to ensure that potential design defects and performance issues are discovered.
[0065] In some embodiments, the functional verification agent is used to verify the functional correctness of each functional module of the chip;
[0066] The performance verification agent is used to verify chip performance indicators;
[0067] Boundary verification agents are used to simulate extreme environments to test chip performance;
[0068] The error verification agent is used to test the chip's error handling capabilities.
[0069] In some embodiments, Figure 1 The method may further include:
[0070] Each agent obtains the verification progress and status of other agents through the network, and adjusts the task allocation in real time based on the agent's workload, verification progress and results.
[0071] In some embodiments, Figure 1 The method may further include:
[0072] Dynamically adjust the priority of the agent based on the problems found during the verification process and their corresponding importance.
[0073] In some embodiments, the data generated during the verification process of each agent is uploaded to the data fusion center for comprehensive analysis to generate verification results, including:
[0074] Upload the data and results generated during the verification process of each intelligent agent to the data fusion center;
[0075] The data fusion center uses machine learning algorithms to associate the data corresponding to the functional verification agent, performance verification agent, boundary verification agent and error verification agent, determine the potential relationship between different verification indicators, and generate verification results.
[0076] In some embodiments, the large-scale chip verification task is decomposed into multiple subtasks based on the chip design architecture and verification requirements, including:
[0077] For functional verification tasks, they are divided into verification subtasks for each functional module;
[0078] The performance verification task is divided into power consumption verification and timing verification subtasks.
[0079] Figure 2 This is a flow chart of another large-scale chip verification method based on multi-agents provided by the embodiment of the present disclosure, combined with Figure 2 ,right Figure 1 The multi-agent based large-scale chip verification method is further described in .
[0080] First, we need to thoroughly analyze the chip datasheet to fully understand the chip's functionality, obtain its performance parameters, and clearly define the verification objectives. Then, based on this understanding of functionality and performance parameters, combined with the chip's design requirements and application scenarios, we will employ a variety of test scenarios and test case generation strategies to ensure that potential design flaws and performance issues are discovered.
[0081] After completing the initial verification planning, you can create various types of agents, such as functional verification agents, performance verification agents, boundary verification agents, and error verification agents, based on the different priorities of chip verification. Independent computing resources are allocated to each agent to clearly define the scope of specific verification tasks.
[0082] The functional verification agent is responsible for verifying the functional correctness of each functional module of the chip and has the ability to generate and execute test cases for the corresponding functional modules.
[0083] The performance verification agent focuses on verifying chip performance indicators, such as power consumption and timing, and has the ability to analyze clock signals, signal propagation delays, power consumption data, etc.
[0084] The boundary verification agent verifies the chip under boundary conditions, such as extreme temperature, extreme voltage, maximum frequency, etc., and tests the chip performance in simulated extreme environments.
[0085] The error verification agent tests the chip's error handling capabilities by injecting errors, such as data errors and control signal errors.
[0086] A distributed agent communication network is constructed, enabling real-time exchange of verification data, status information, and results between agents. For example, if a functional verification agent detects a signal anomaly during verification, it can immediately send this information via the communication network to the performance verification agent and the boundary verification agent for further analysis from different perspectives. Each agent can also access the verification progress and status of other agents through the network, allowing them to dynamically adjust their own verification strategies.
[0087] Based on the chip design architecture and verification requirements, large-scale chip verification tasks are broken down into multiple subtasks. A task allocation algorithm based on task priority and agent capabilities is employed to rationally assign subtasks to agents. For example, functional verification tasks for key functional modules are assigned to highly experienced and computationally powerful functional verification agents and given high priority. During verification, a dynamic scheduling algorithm is used to adjust task allocation in real time based on agent workload, verification progress, and results.
[0088] A verification data fusion center is established. Each agent uploads the data and results generated during the verification process to the fusion center, which uses machine learning algorithms to conduct comprehensive data analysis. By correlating data from functional verification agents, performance verification agents, boundary verification agents, and error verification agents, the center identifies potential relationships between different verification indicators, enabling more accurate determination of chip design flaws.
[0089] The integrated verification results are comprehensively evaluated based on pre-set strict verification standards. If the verification results meet all pre-set standards, the chip is considered to have passed verification. Otherwise, the reasons for the verification failure are deeply analyzed and detailed problem information is fed back to the chip design team.
[0090] To more clearly illustrate the implementation details of the multi-agent-based large-scale chip verification method, the following will be explained in conjunction with detailed steps and specific technical means. Through these specific implementations, the significant advantages of the present invention in improving the comprehensiveness and accuracy of chip verification can be more intuitively demonstrated.
[0091] 1) Verification planning stage
[0092] At the beginning of the project, we first collect detailed chip design specifications and performance parameters. These include, but are not limited to, logic function descriptions, timing requirements, and electrical characteristics. Based on our understanding of the functions and mastery of the parameters, combined with the chip's design requirements and application scenarios, we will adopt a series of test scenarios and a variety of test case generation strategies. These test scenarios include normal operating scenarios, extreme operating scenarios, multi-tasking scenarios, and more.
[0093] 2) Agent Classification
[0094] An agent is an entity capable of autonomous action, information reception, and decision-making. A multi-agent system is a system composed of multiple agents, each interacting and collaborating to solve complex problems or complete specific tasks. Chip verification engineers create various types of agents, including functional verification agents, performance verification agents, boundary verification agents, and error verification agents, based on different verification dimensions.
[0095] The functional verification agent ensures that each functional module of the chip is accurately implemented according to the design specifications. The functional verification agent is responsible for generating test cases that fully cover the chip's functions. These test cases cover various operations and data combinations under the chip's normal operating mode. By executing these test cases, the chip's functions can be carefully checked.
[0096] The performance verification agent evaluates the chip's performance to ensure it meets the design requirements. It analyzes performance data such as clock frequency, instruction execution cycle, and power consumption to determine whether the chip's performance meets the design specifications.
[0097] Boundary verification agents verify the stability and reliability of chips under extreme boundary conditions. Boundary verification simulates various extreme operating conditions, such as extreme temperatures, extreme voltages, and maximum frequencies, to check whether the chip can function properly under these conditions and whether any functional failures or performance degradation will occur.
[0098] The error verification agent checks the effectiveness of the chip's error handling mechanisms, ensuring that the chip responds correctly when encountering errors. The error verification agent injects various types of errors into the chip, such as data errors, control signal errors, and timing errors. It then analyzes the chip's error handling and the results, assessing whether the chip's error handling capabilities meet design requirements.
[0099] Based on a clear verification plan, the four agents are assigned corresponding computing and data storage resources. Computing resources are allocated appropriately based on the tasks and characteristics of each agent. For example, the functional verification agent is allocated sufficient memory and processor resources to support its execution of a large number of functional test cases. The performance verification agent is equipped with high-precision performance monitoring equipment and powerful data analysis computing resources to collect and analyze chip performance data in real time.
[0100] 3) Construction of intelligent communication network
[0101] During the verification process, the various agents interact and share data in real time. When the functional verification agent discovers that a module's output doesn't match expectations, it immediately sends the module's input data, output data, error information, and a detailed description of the test case to the other agents. Upon receiving this information, the performance verification agent examines the module's performance changes when the anomaly occurs, such as whether there's a sudden increase in power consumption or a decrease in computing speed. The analysis results are then fed back to the functional verification agent. The boundary verification agent simulates the module's operation under extreme boundary conditions to determine whether the anomaly will be exacerbated. For example, under extreme high temperatures, would an anomaly in the module cause the chip system to crash? The simulation results and analysis are then fed back to the other agents. The error verification agent attempts to inject similar errors into the module to verify whether the chip's error handling mechanisms remain effective under these anomalies. The verification results are then shared with the other agents. Through this data exchange and collaborative analysis, the four agents can conduct in-depth analysis of the anomaly from different perspectives to pinpoint the root cause.
[0102] 4) Task allocation and dynamic scheduling
[0103] Based on the chip's design architecture and verification requirements, large-scale chip verification tasks are broken down into multiple subtasks. For example, functional verification tasks can be further broken down into verification subtasks for each functional module; performance verification tasks can be broken down into subtasks such as power consumption verification and timing verification. These subtasks are initially assigned using a task allocation algorithm based on task priority and agent capabilities. For example, the functional verification task of a key functional module is assigned to the most appropriate functional verification agent and given a high priority based on factors such as the agent's experience, computing power, and historical verification performance. Clear timelines and quality requirements are also set for each subtask.
[0104] During the verification process, a dynamic scheduling algorithm is used to adjust task allocation in real time based on the agent's workload, verification progress, and results. For example, using a load-balancing-based dynamic scheduling algorithm, if a particular agent's workload exceeds a certain threshold while other agents have idle resources, some of that agent's tasks are reallocated to other agents. For example, if a boundary verification agent is verifying a task in a simulated high-temperature environment, the complexity of the chip causes the task execution time to be too long and the workload to be too high. At this time, the dynamic scheduling algorithm detects that the error verification agent has a lower workload and has the resources and capabilities to assist in handling some boundary verification tasks. Therefore, it will transfer some of the boundary verification agent's tasks to the error verification agent.
[0105] The priority of each agent is dynamically adjusted based on the issues discovered and their importance during the verification process. If an error is discovered in a functional module during functional verification that could affect the basic functionality of the entire chip, the priority of the functional verification task associated with that module will be increased to allow for in-depth verification and analysis. At the same time, the priorities of other tasks are adjusted accordingly to ensure that resources are properly allocated to critical tasks.
[0106] 5) Verification data fusion analysis
[0107] The data and results generated by each agent during the verification process are uploaded to the Data Fusion Center in real time. The Data Fusion Center has established an efficient data transmission and storage system to ensure data integrity and accuracy. For example, test case execution results uploaded by the functional verification agent, performance indicator monitoring data uploaded by the performance verification agent, operational status data under extreme conditions uploaded by the boundary verification agent, and error injection and processing results uploaded by the error verification agent are all stored promptly and accurately in the Data Fusion Center's database.
[0108] The Data Fusion Center uses data mining and machine learning algorithms to conduct in-depth analysis of the fused data. Data mining algorithms can uncover potential relationships between different verification indicators, such as the correlation between anomalies in a functional module and increased overall chip power consumption. Machine learning algorithms can predict and evaluate chip performance, for example, using historical performance data to predict future chip performance under different workloads. Clustering algorithms can also be used to categorize the chip's operating status, distinguishing between normal and abnormal operating states, enabling more accurate assessment of chip issues.
[0109] 6) Verification result evaluation and feedback:
[0110] The Data Fusion Center generates a detailed verification report based on the analysis results. The report includes an overview of the chip's overall verification, the verification results of each intelligent agent, a list of discovered issues, an assessment of the severity of the issues, and related data analysis and recommendations. For example, the report will clearly indicate which functional modules of the chip have problems and the specific manifestations of the problems, such as an output error when a functional module processes a specific type of data. The severity of the problem will also be assessed, with issues that affect the core functions of the chip being marked as high severity, and minor issues that do not affect the main functions being marked as low severity. The report will also provide detailed data analysis for each problem, such as the frequency of the problem and its relationship with other verification indicators, and provide corresponding improvement suggestions.
[0111] Chip verification engineers carefully evaluate the report to determine whether the chip has passed verification. During the evaluation, engineers comprehensively consider factors such as the severity and number of issues, as well as their impact on the chip's overall performance and functionality. If the chip has few issues, the severity of the issues is low, and they can be resolved with simple modifications and optimizations, the chip is considered to have passed verification. If the chip has many serious issues that may affect the chip's normal use and reliability, the chip is considered to have failed verification.
[0112] If the chip fails verification, the report is fed back to the chip design team. The chip design team then makes improvements based on the problem description, data analysis, and suggestions in the report. For example, for issues with functional modules, the design team might redesign the algorithm or optimize the circuit structure. For performance issues, the team might adjust the chip's operating frequency or optimize power management strategies. Once improvements are complete, verification is repeated, repeating the aforementioned preparation phase, agent initialization, agent communication network construction, task allocation and dynamic scheduling, verification data fusion and analysis, and verification result evaluation and feedback until the chip passes verification.
[0113] The large-scale chip verification method based on multi-agents provided by the present disclosure utilizes the distributed processing, autonomous decision-making and mutual collaboration characteristics of multi-agents, which can give full play to the advantages of each agent, improve the comprehensiveness and accuracy of large-scale chip verification, and meet the needs of the rapid development of modern large-scale chips. In addition, the constructed chip verification system is composed of multiple closely collaborating agents, which jointly realize the intelligent chip verification process. Utilizing the distributed collaboration and autonomous decision-making capabilities of multiple agents, large-scale chip tasks are decomposed into multiple sub-tasks such as functions, performance, boundaries and errors, which are executed separately by corresponding agents. Overall, the application of this technology comprehensively and accurately covers various scenarios of large-scale verification, greatly shortens the time of chip verification, improves verification efficiency, and brings new development opportunities to the field of chip research and development.
[0114] Compared with the traditional verification method, the present invention has at least the following beneficial results:
[0115] 1. Improve verification efficiency: The distributed processing capabilities of multiple agents and the dynamic task scheduling mechanism shorten the verification time of large-scale chips and improve verification efficiency.
[0116] 2. Enhanced verification comprehensiveness: Different types of intelligent agents verify the chip from multiple dimensions, comprehensively covering various verification scenarios and increasing the probability of discovering design defects.
[0117] 3. Improve verification accuracy: Through verification data fusion and analysis, explore the potential relationship between different verification indicators and more accurately judge the correctness and reliability of the chip.
[0118] 4. Adaptability: Dynamically adjust verification strategies and task allocation based on verification results and agent working status, making the verification process more intelligent and efficient.
[0119] and Figure 1 Corresponding to the large-scale chip verification method based on multi-agent, the present disclosure also provides a large-scale chip verification device based on multi-agent, such as Figure 3 As shown, the device may specifically include:
[0120] Determination module 301, for obtaining chip performance parameters based on chip specifications and determining verification targets;
[0121] The determination module 301 is further configured to create a functional verification agent, a performance verification agent, a boundary verification agent, and an error verification agent based on the different focuses of chip verification corresponding to the verification target, and allocate independent computing resources to each agent to determine the corresponding specific verification task scope;
[0122] A construction module 302 is used to construct a distributed agent communication network based on each agent, so that each agent can exchange verification data, status information and verification results in real time;
[0123] Verification module 303 is used to decompose the large-scale chip verification task into multiple subtasks according to the chip design architecture and verification requirements, and use a task allocation algorithm based on task priority and agent capabilities to assign the subtasks to corresponding agents for verification;
[0124] The verification module 303 is also used to upload the data generated during the verification process of each intelligent agent to the data fusion center for comprehensive analysis and generate verification results.
[0125] In some embodiments, obtaining chip performance parameters and determining verification targets based on the chip specification include:
[0126] Based on the chip specification, the chip performance parameters are obtained. Based on the functions and performance parameters combined with the chip design requirements and application scenarios, a variety of test scenarios and test case generation strategies are adopted to determine the verification goals to ensure that potential design defects and performance issues are discovered.
[0127] In some embodiments, the functional verification agent is used to verify the functional correctness of each functional module of the chip;
[0128] The performance verification agent is used to verify chip performance indicators;
[0129] Boundary verification agents are used to simulate extreme environments to test chip performance;
[0130] The error verification agent is used to test the chip's error handling capabilities.
[0131] In some embodiments, in the above-mentioned apparatus, each agent obtains the verification progress and status of other agents through the network, and adjusts the task allocation in real time according to the workload, verification progress and results of the agent.
[0132] In some embodiments, the above-mentioned apparatus can also be used to dynamically adjust the priority of the agent according to the problems found during the verification process and their corresponding importance.
[0133] In some embodiments, the data generated during the verification process of each agent is uploaded to the data fusion center for comprehensive analysis to generate verification results, including:
[0134] Upload the data and results generated during the verification process of each intelligent agent to the data fusion center;
[0135] The data fusion center uses machine learning algorithms to associate the data corresponding to the functional verification agent, performance verification agent, boundary verification agent and error verification agent, determine the potential relationship between different verification indicators, and generate verification results.
[0136] In some embodiments, the large-scale chip verification task is decomposed into multiple subtasks based on the chip design architecture and verification requirements, including:
[0137] For functional verification tasks, they are divided into verification subtasks for each functional module;
[0138] The performance verification task is divided into power consumption verification and timing verification subtasks.
[0139] Combine Figure 4 As shown, the embodiment of the present disclosure also provides a large-scale chip verification device 400 based on multi-agents, including a processor 404 and a memory 401. Optionally, the system may also include a communication interface 402 and a bus 403. The processor 404, the communication interface 402, and the memory 401 can communicate with each other through the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can call the logic instructions in the memory 401 to execute the large-scale chip verification method based on multi-agents of the above embodiment.
[0140] In addition, the logic instructions in the memory 401 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.
[0141] Memory 401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 404 executes the program instructions / modules stored in memory 401 to perform functional applications and data processing, thereby implementing the multi-agent-based large-scale chip verification method in the above-mentioned embodiments.
[0142] The memory 401 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 401 may include high-speed random access memory and non-volatile memory.
[0143] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute a large-scale chip verification method based on a multi-agent.
[0144] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
[0145] The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program code, or a transient storage medium.
[0146] The above description and accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replaced with portions and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. Similarly, the term "and / or" as used in this application means including any and all possible combinations of one or more of the associated listed items. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, or device comprising the elements. In this document, each embodiment may focus on the differences from other embodiments, and similar parts between the embodiments can be referenced to each other. For methods, products, etc. disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referenced to the description of the method section.
[0147] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0148] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. A large-scale chip verification method based on multi-agent, characterized in that: The method comprises: Based on the chip specification, obtain the chip's performance parameters and determine the verification target; Based on the different focuses of chip verification corresponding to the verification targets, functional verification agents, performance verification agents, boundary verification agents, and error verification agents are created, and independent computing resources are allocated to each agent to determine the corresponding specific verification task scope; Building a distributed agent communication network based on each agent to enable real-time exchange of verification data, status information and verification results between agents; Based on the chip design architecture and verification requirements, the large-scale chip verification task is decomposed into multiple subtasks. A task allocation algorithm based on task priority and agent capabilities is used to assign the subtasks to the corresponding agents for verification. The data generated during the verification process of each intelligent agent is uploaded to the data fusion center for comprehensive analysis to generate verification results.
2. The method according to claim 1, characterized in that The chip performance parameters are obtained based on the chip specification and the verification targets are determined, including: Based on the chip specification, the chip performance parameters are obtained. Based on the functions and performance parameters combined with the chip design requirements and application scenarios, a variety of test scenarios and test case generation strategies are adopted to determine the verification goals to ensure that potential design defects and performance issues are discovered.
3. The method according to claim 1, characterized in that The functional verification agent is used to verify the functional correctness of each functional module of the chip; The performance verification agent is used to verify chip performance indicators; Boundary verification agents are used to simulate extreme environments to test chip performance; The error verification agent is used to test the chip's error handling capabilities.
4. The method according to claim 1, wherein The method further comprises: Each agent obtains the verification progress and status of other agents through the network, and adjusts the task allocation in real time based on the agent's workload, verification progress and results.
5. The method according to claim 4, characterized in that The method further comprises: Dynamically adjust the priority of the agent based on the problems found during the verification process and their corresponding importance.
6. The method according to claim 1, characterized in that The data generated during the verification process of each intelligent agent is uploaded to the data fusion center for comprehensive analysis to generate verification results, including: Upload the data and results generated during the verification process of each intelligent agent to the data fusion center; The data fusion center uses machine learning algorithms to associate the data corresponding to the functional verification agent, performance verification agent, boundary verification agent and error verification agent, determine the potential relationship between different verification indicators, and generate verification results.
7. The method according to claim 1, characterized in that Based on the chip design architecture and verification requirements, the large-scale chip verification task is decomposed into multiple subtasks, including: For functional verification tasks, they are divided into verification subtasks for each functional module; The performance verification task is divided into power consumption verification and timing verification subtasks.
8. A large-scale chip verification device based on multi-agent, characterized in that: The device comprises: The determination module is used to obtain the chip's performance parameters based on the chip specification and determine the verification target; The determination module is further configured to create a functional verification agent, a performance verification agent, a boundary verification agent, and an error verification agent based on the different focuses of chip verification corresponding to the verification target, and allocate independent computing resources to each agent to determine the corresponding specific verification task scope; A construction module is used to build a distributed agent communication network based on each agent, so that each agent can exchange verification data, status information and verification results in real time; The verification module is used to decompose large-scale chip verification tasks into multiple subtasks based on the chip design architecture and verification requirements, and use a task allocation algorithm based on task priority and agent capabilities to assign subtasks to corresponding agents for verification; The verification module is also used to upload the data generated during the verification process of each intelligent agent to the data fusion center for comprehensive analysis and generate verification results.
9. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.