Circuit structure identification method and device for analog integrated circuit design automation and storage medium

Abstract

The invention discloses a circuit structure identification method and device for analog integrated circuit design automation and a storage medium. According to the method, node features and edge features of a to-be-identified target circuit diagram and a to-be-identified template circuit diagram are processed by using a feature extraction network; through multi-layer stacking and multi-step sampling, long-distance information aggregation can be realized to be integrated, so that a circuit structure can be effectively sensed, device-level topological information can be easily and effectively captured from the circuit structure, a sub-graph isomorphic with a to-be-identified template circuit diagram in a to-be-identified target circuit diagram is identified, and the identification accuracy of the to-be-identified template circuit diagram is improved. Therefore, the key circuit structure in the to-be-recognized target circuit diagram is recognized, the limitation of single instance matching is broken through, the accuracy and universality of key circuit structure extraction are remarkably improved, and the method is suitable for basic structure extraction in an analog integrated circuit netlist in the field of electronic design automation (EDA). The method is widely applied to the technical field of circuit design automation.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design automation, and in particular to a circuit structure recognition method, device and storage medium for simulating integrated circuit design automation. Background Art

[0002] When designing analog integrated circuits, the design quality of some key circuit structures in the analog layout usually has a great impact on the overall quality of the analog integrated circuit, so it is necessary to pay attention to these key circuit structures. For example, the device pairs and circuit structures that are matched, symmetrical, or have a common center of mass structure in the netlist of the analog integrated circuit need to maintain a corresponding relationship in the subsequent layout and wiring links, which helps the performance and accuracy of the analog integrated circuit chip finally produced meet the requirements of the circuit design. More specifically, differential amplifiers and current mirrors have symmetrical structures, and it is necessary to make the matched device pairs in the structure close to each other and make the device directions consistent. The above-mentioned device pairs and circuit structures with matching, symmetrical, or common center of mass structures, as well as more specific structures such as differential amplifiers, current mirrors, and operational amplifiers are all key circuit structures.

[0003] The process of identifying critical circuit structures is called constraint annotation. In traditional analog integrated circuit design, constraint annotation is typically done manually by experienced engineers. This is time-consuming and labor-intensive, and prone to omissions and errors, thus limiting the quality of analog integrated circuit design. Summary of the Invention

[0004] In view of the technical problems such as the difficulty in constraining annotation in current analog integrated circuit design, the purpose of the present invention is to provide a circuit structure identification method, device and storage medium for automated analog integrated circuit design.

[0005] In one aspect, an embodiment of the present invention includes a circuit structure recognition method for analog integrated circuit design automation, the circuit structure recognition method for analog integrated circuit design automation comprising the following steps:

[0006] Obtaining a feature extraction network; the feature extraction network is used to receive input node features and input edge features, process the input node features and the input edge features through a plurality of feature extraction layers, and obtain output node features and output edge features;

[0007] Obtaining a first node feature and a first edge feature corresponding to the target circuit diagram to be identified, and a second node feature and a second edge feature corresponding to the template circuit diagram to be identified;

[0008] Using the first node feature and the first edge feature as input node features and input edge features, inputting them into the feature extraction network, obtaining output node features processed by the feature extraction network as third node features, and obtaining output edge features processed by the feature extraction network as third edge features;

[0009] Using the second node feature and the second edge feature as input node features and input edge features, inputting them into the feature extraction network, obtaining output node features processed by the feature extraction network as fourth node features, and obtaining output edge features processed by the feature extraction network as fourth edge features;

[0010] The following steps are performed during the inference phase:

[0011] The circuit structure of the target circuit diagram to be identified is identified according to the third node feature and the fourth node feature.

[0012] Furthermore, the processing of the input node features and the input edge features through a plurality of feature extraction layers to obtain output node features and output edge features includes:

[0013] For any of the feature extraction layers, perform the following steps:

[0014] According to the formula

[0015] n norm =LayerNormalize(n input )

[0016] N q =n norm W q

[0017] N k =n norm W k

[0018] N v =n norm W v

[0019] E f =LayerNormalize(e input )·W e

[0020] Perform calculation processing; wherein, when the feature extraction layer is the first feature extraction layer, n input is the input node feature received by the feature extraction network, e inputis the input edge feature received by the feature extraction network. When the feature extraction layer is other feature extraction layers, n input is the node processing result of the previous feature extraction layer, e input is the edge processing result of the previous feature extraction layer; LayerNormalize() represents the layer regularization processing, W q 、W k 、W v and W e is the linear transformation matrix in the feature extraction layer;

[0021] According to the formula

[0022]

[0023] Perform calculation processing; among them, score ij represents the intermediate attention score corresponding to the i-th node and the j-th node, exp() represents the exponential operation, Indicates N q The eigenvector corresponding to the i-th node in Indicates N k The eigenvector corresponding to the jth node, e ij Indicates E f The feature vector corresponding to the edge formed by the i-th node and the j-th node, Indicates N k The eigenvector corresponding to the zth node, e iz Indicates e f The feature vector corresponding to the edge formed by the i-th node and the z-th node, z∈n j Indicates that the zth node is selected from all nodes that have an edge connection with the jth node;

[0024] According to the formula

[0025]

[0026] Perform calculation processing; among them, att ij represents the final attention score corresponding to the i-th node and the j-th node, Indicates N v The feature vector corresponding to the i-th node;

[0027] According to the formula

[0028] n output =n input +MLP(sum(att ij ))

[0029] Perform calculation processing; where n outputIndicates the node processing result of this feature extraction layer, MLP() represents multi-layer perception processing;

[0030] According to the formula

[0031] e att =e input +score ij

[0032] e output =e att +MLP(LayerNormalize(e att ))

[0033] Perform calculation processing; where e output Indicates the edge processing result of this feature extraction layer;

[0034] The node processing result of the last feature extraction layer is used as the output node feature, and the edge processing result of the last feature extraction layer is used as the output edge feature.

[0035] Furthermore, performing circuit structure identification on the target circuit diagram to be identified based on the third node feature and the fourth node feature includes:

[0036] Calculating the similarity between the third node feature and the fourth node feature;

[0037] Determining, based on the similarity, a degree of matching between a node corresponding to the third node feature in the target circuit diagram to be identified and a node corresponding to the fourth node feature in the template circuit diagram to be identified;

[0038] According to the matching degree, a mapping relationship is established between the nodes in the target circuit diagram to be identified and the nodes in the template circuit diagram to be identified;

[0039] According to the mapping relationship, mapping the template circuit diagram to be identified to the target circuit diagram to be identified;

[0040] The mapped portion of the target circuit diagram to be identified is output as a circuit structure identification result.

[0041] Furthermore, before mapping the template circuit diagram to be identified to the target circuit diagram to be identified according to the mapping relationship, performing circuit structure identification on the target circuit diagram to be identified according to the third node feature and the fourth node feature further includes:

[0042] Obtaining the confidence level of each node in the target circuit diagram to be identified;

[0043] Nodes whose corresponding confidence levels are lower than an acceptance threshold are deleted from the target circuit diagram to be identified.

[0044] Furthermore, the step of obtaining the confidence level of each node in the target circuit diagram to be identified includes:

[0045] According to the formula

[0046]

[0047]

[0048] Perform calculation processing; wherein conf represents the confidence of each node in the target circuit diagram to be identified, MLP() represents multi-layer perception processing, is the third node feature, is the fourth node feature.

[0049] Furthermore, the circuit structure identification method for simulating integrated circuit design automation also includes:

[0050] The following steps are performed during the training phase:

[0051] The feature extraction network is trained according to the third node feature and the fourth node feature.

[0052] Furthermore, the training phase is performed before the inference phase, and the training of the feature extraction network according to the third node feature and the fourth node feature includes:

[0053] Perform cross entropy loss calculation based on the third node feature and the fourth node feature to obtain a loss function value;

[0054] The feature extraction network is trained by back propagation according to the loss function value.

[0055] On the other hand, an embodiment of the present invention also includes a computer device including a memory and a processor, the memory being used to store at least one program, and the processor being used to load at least one program to execute the circuit structure identification method for simulating integrated circuit design automation in the embodiment.

[0056] On the other hand, an embodiment of the present invention also includes a computer-readable storage medium, which stores a program executable by a processor. When the program is executed by the processor, it is used to execute the circuit structure identification method for simulating integrated circuit design automation in the embodiment.

[0057] The beneficial effects of the present invention are as follows: the circuit structure recognition method for analog integrated circuit design automation in the embodiment processes the node features and edge features of the target circuit diagram to be identified and the template circuit diagram to be identified by using a feature extraction network, and can be integrated by realizing long-distance information aggregation through multi-layer stacking and multi-step sampling, so as to effectively perceive the circuit structure, easily and more effectively capture device-level topology information therefrom, overcome the shortcomings of graph attention networks and the like in circuit characterization, and at the same time use graph mapping (especially bidirectional graph mapping) to map node features, identify the subgraph in the target circuit diagram to be identified that is isomorphic to the template circuit diagram to be identified, thereby identifying the key circuit structure in the target circuit diagram to be identified, breaking through the limitations of single instance matching, and significantly improving the accuracy and versatility of key circuit structure extraction, and is suitable for basic structure extraction in analog integrated circuit netlists in the field of electronic design automation (EDA), such as the automated detection and extraction of repetitive functional structures such as current mirrors, differential pairs, and operational amplifier modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 Schematic diagram of the principle of the circuit structure identification method for simulating integrated circuit design automation in an embodiment;

[0059] Figure 2 Schematic diagram of the steps of a circuit structure identification method for simulating integrated circuit design automation in an embodiment;

[0060] Figure 3 Schematic diagram of the working principle of the feature extraction network in the embodiment;

[0061] Figure 4 Schematic diagram of a template circuit diagram to be identified and a target circuit diagram to be identified in an embodiment;

[0062] Figure 5 This is a schematic diagram of the contents of bits 10-13 in the first node feature in the embodiment;

[0063] Figure 6 Schematic diagram of a circuit topology diagram of a target circuit diagram to be identified and a corresponding first node feature and first edge feature in an embodiment;

[0064] Figure 7 Schematic diagram of a target circuit diagram to be identified after confidence filtering in an embodiment;

[0065] Figure 8 Schematic diagram of the node mapping relationship between the template circuit diagram to be identified and the target circuit diagram to be identified in the embodiment;

[0066] Figure 9 Schematic diagram of a subgraph in a target circuit diagram to be identified that is isomorphic to a template circuit diagram to be identified in an embodiment. DETAILED DESCRIPTION

[0067] In analog layout design, constraint annotation extraction involves identifying matching, symmetrical, or common-center-of-mass device pairs and structures within a circuit from a netlist. These pairs and structures must maintain their corresponding relationships during subsequent layout and routing to ensure chip performance and accuracy meet circuit design requirements. For example, in circuits like differential amplifiers or current mirrors, matching device pairs must be positioned close together and aligned in the same direction. Traditionally, this task is performed manually by experienced engineers, a time-consuming and labor-intensive process. With the rapid advancement of analog electronic design automation technology in recent years, some have begun exploring automated constraint annotation methods, using automated algorithms to identify functional structures within circuits and implement constraint annotation. Given a circuit topology that closely resembles a graph, the components within a given circuit can be viewed as graph vertices, and the connections between components as edges between vertices. After representing the circuit netlist using a graph structure, constraint annotation involves extracting portions of the graph that match the given constraints (subgraphs). Subgraph matching uses predefined constraint templates (such as the topology of differential pairs or current mirrors) to quickly locate candidate device groups within the circuit structure. Furthermore, after layout is complete, subgraph matching can verify whether symmetrical components meet symmetry constraints, such as identical aspect ratios and symmetrical metal trace distribution. Subgraph matching has been proven to be an NP-complete problem, meaning that in the worst case, the computational complexity is factorial. However, a number of heuristic methods have been developed that can find all solutions within a finite timeframe. Consequently, many studies have used graph algorithms for circuit structure identification, but these efforts generally focus on lower-level constraints, such as symmetry, and are unable to handle more complex circuit structures.

[0068] Subgraph matching solutions are typically based on the assumption that the features of corresponding nodes should be as similar as possible. Based on this assumption, the similarity between nodes can be calculated by calculating the cosine similarity between node features, thereby constructing a similarity matrix from subgraph Q to target graph G. Some related techniques employ an injective mapping (Q→G) from subgraph Q to target graph G, requiring that each node in Q strictly corresponds to a node in G. Ideally, the corresponding nodes in G together form an isomorphic subgraph of Q within G, which is the key structure required in a circuit diagram. However, this approach has significant drawbacks. When G contains multiple subgraphs isomorphic to Q (such as repeated current mirrors in a circuit), it is impossible to extract all subgraphs in G that are isomorphic to Q by constructing a Q→G mapping. An alternative approach is to construct a G→Q mapping, but this approach introduces new challenges. Not all nodes in G are part of an isomorphic subgraph, and these nodes cannot be simply distinguished using a similarity threshold. Furthermore, in analog integrated circuits, the electrical characteristics of devices made with different processes and sizes vary significantly, and interconnections between devices also involve port issues. Different ports of circuit devices usually have different functions. The ports connected by each edge have a crucial impact on circuit performance. However, traditional graph attention networks only rely on node features to calculate attention weights, and edges only represent the connection between two nodes. In application scenarios such as molecular structure reasoning, edges usually do not carry key information. This method is feasible, but problems will be encountered when using graphs to represent circuits. Circuit devices such as MOS tubes have active gates and drains. Connecting different ports has a great impact on circuit performance and cannot well meet the requirements of circuit feature extraction.

[0069] In view of the shortcomings of the above-mentioned related technologies, this embodiment proposes a graph key structure extraction technology based on bidirectional mapping and confidence filtering. The technical principle is as follows: Figure 1As shown in the figure, this approach specifically incorporates prior knowledge from the circuit domain into model design and achieves high-precision circuit feature extraction by explicitly modeling the interaction between edge features and nodes. A feature extraction network inputs node and edge feature representations, calculates the cosine similarity of node feature encodings to obtain node similarity, and then filters low-confidence nodes to establish a mapping from the target graph G to the query subgraph Q, achieving efficient subgraph matching. The graph attention network introduces the attention mechanism into spatial-domain graph neural networks. Unlike graph convolutional neural networks, graph attention networks do not require complex computations such as matrix factorization. Instead, they update node features based on the representations of neighboring nodes, making them more interpretable. The attention mechanism is a key mechanism in neural networks. Its goal is to assign weights to given information, focusing attention on the most important information for the system, allowing the network to focus on and process key components. By incorporating this attention mechanism, the graph attention network assigns different weights to each node, thereby incorporating more information from important neighboring nodes into the target node, achieving dynamic feature selection and extraction. This allows the graph attention network to extract key information between nodes, improving the model's representational capabilities. Traditional graph attention networks rely solely on node features to calculate attention weights. This approach is feasible in applications such as molecular structure reasoning, where edges typically do not carry critical information. However, the ports of circuit components often have different functions. For example, if you need to find a diode-connected MOSFET in a circuit, the best approach is to check whether there is an edge connecting the source and gate of the same MOSFET. This shows that the properties of the ports connected by an edge have a significant impact on the circuit's function, making it almost impossible for a neural network to obtain correct results without this crucial information. To address this issue, a joint graph attention layer can be designed based on the circuit's topological characteristics. This improves on traditional graph attention by innovatively incorporating edge features into the feature extraction process. Using edges as a bridge, it fuses node and edge features, forming a joint attention representation of edges and nodes. Based on this joint attention representation, a weighted pooling strategy is used to aggregate neighbor information and dynamically update edge and node features. By explicitly modeling the interaction between edge features and nodes, accurate circuit feature extraction is achieved. Incorporating edge features (such as circuit pin connections) into the attention score enables the model to distinguish circuits with highly similar topologies. In addition, the initial features of nodes and edges can be designed based on the device type, port connection and other characteristics of the analog circuit, so that the attention mechanism can focus on key topological constraints.

[0070] Based on the above principles, this embodiment proposes a circuit structure identification method for simulating integrated circuit design automation.

[0071] Reference Figure 2, a circuit structure identification method for analog integrated circuit design automation includes the following steps:

[0072] S0. Obtain feature extraction network;

[0073] S1. Obtaining the first node feature and the first edge feature corresponding to the target circuit diagram to be identified, and the second node feature and the second edge feature corresponding to the template circuit diagram to be identified;

[0074] S2. The first node feature and the first edge feature are input as the node feature and the edge feature, respectively, into a feature extraction network, and the output node feature processed by the feature extraction network is obtained as the third node feature, and the output edge feature processed by the feature extraction network is obtained as the third edge feature;

[0075] S3. Using the second node feature and the second edge feature as input node features and input edge features, inputting them into the feature extraction network, obtaining output node features processed by the feature extraction network as fourth node features, and obtaining output edge features processed by the feature extraction network as fourth edge features;

[0076] The following steps are performed during the inference phase:

[0077] S4. Perform circuit structure recognition on the target circuit diagram according to the third node feature and the fourth node feature.

[0078] In step S0, the principle of the feature extraction network used is as follows Figure 3 As shown. Figure 3 , the input data of the feature extraction network includes the input node feature n input and input edge feature e input , the feature extraction network calls a feature extraction layer, which can be used to extract the input node feature n input and input edge feature e input Processing to get node processing result n output and edge processing results e output The feature extraction network can call multiple feature extraction layers, where the input data of the first feature extraction layer is the initially obtained input node feature n input and input edge feature e input , the node processing result n output by each feature extraction layer output and edge processing results e output , will be used as the data input to the feature extraction network in the next feature extraction layer (if needed). You can set a certain upper limit on the number of feature extraction layers to be executed. When the number of feature extraction layers executed by the feature extraction network reaches the upper limit, the feature extraction layer will be terminated, and the node processing result n obtained by the last feature extraction layer will be outputIt is the output node feature finally obtained by the feature extraction network, and the edge processing result e obtained by the last feature extraction layer output It is the output edge feature finally obtained by the feature extraction network.

[0079] Specifically, taking any one of the feature extraction layers as an example, the specific data processing flow performed by the feature extraction layer includes:

[0080] A. According to the formula

[0081] n norm =LayerNormalize(n input )

[0082] N q =n norm W q

[0083] N k =n norm W k

[0084] N v =n norm W v

[0085] E f =LayerNormalize(e input )·W e

[0086] Perform calculation processing. If it is the first feature extraction layer, then b input is the input node feature received by the feature extraction network, e input Is the input edge feature received by the feature extraction network. If it is the feature extraction layer after the first feature extraction layer (for example, the second feature extraction layer), then n input is the node processing result of the previous feature extraction layer (for example, the first feature extraction layer), e input is the edge processing result of the previous feature extraction layer (for example, the first feature extraction layer). LayerNormalize() represents the layer regularization processing, W q 、W k 、W v and W e is the linear transformation matrix in the feature extraction layer.

[0087] In step A, the principle of data processing performed by the feature extraction layer is: the input n input After layer regularization and linear transformation, we get N q 、N k and N v , input einput After layer regularization and linear transformation, we get E f .

[0088] B. According to the formula

[0089]

[0090] Perform calculation processing; among them, score ij represents the intermediate attention score corresponding to the i-th node and the j-th node, exp() represents the exponential operation, Indicates N q The eigenvector corresponding to the i-th node in Indicates N k The eigenvector corresponding to the jth node, e oj Indicates E f The feature vector corresponding to the edge formed by the i-th node and the j-th node, Indicates N k The eigenvector corresponding to the zth node, e iz Indicates E f The feature vector corresponding to the edge formed by the i-th node and the z-th node, z∈N j Indicates that the zth node is selected from all nodes that have an edge connection with the jth node.

[0091] In step B, the principle of data processing performed by the feature extraction layer is: the attention median score ij The calculation process is to perform a vector product operation on the feature vectors of the i-th node and the j-th node, and add the result to the feature vector of the edge formed by the connection between the i-th node and the j-th node, so as to realize the interaction between the edge feature and the node feature, and then perform softmax regularization on all edges connected to the j-th node to obtain the attention intermediate score score ij , so the attention intermediate score score ij It contains the interaction information between the i-th node and the j-th node calculated by the attention mechanism.

[0092] C. According to the formula

[0093]

[0094] Perform calculation processing; among them, att ij represents the final attention score corresponding to the i-th node and the j-th node, Indicates N v The eigenvector corresponding to the i-th node in .

[0095] In step C, the principle of data processing performed by the feature extraction layer is: the final attention score att ij The calculation process is to convert the intermediate attention score score ij , obtained by matrix multiplication of the numerical features and edge features of the i-th node and the j-th node, so the final attention score att ij It can represent the importance of the i-th node and the j-th node to the edge formed by their connection.

[0096] D. According to the formula

[0097] n output =n input +MLP(sum(att ij ))

[0098] Perform calculation processing; where n output It represents the node processing result of this feature extraction layer, MLP() represents multi-layer perception processing, and sum() represents traversing all i and j combinations for summation.

[0099] In step D, the principle of data processing performed by the feature extraction layer is to: ij ) The residual n between the input feedforward network and the original input after multi-layer perception processing input Add together to obtain the node processing result n of this feature extraction layer output .

[0100] E. According to the formula

[0101] e att =e input +score ij

[0102] e output =e att +MLP(layernorm(e att ))

[0103] Perform calculation processing; where e output Indicates the edge processing result of this feature extraction layer.

[0104] In step E, the principle of data processing performed by the feature extraction layer is to convert the intermediate attention score ij and the input feature e of the edge input Add up to get the edge attention feature e att , and then the edge feature e att After regularization and multi-layer perceptron, the edge processing result e of this feature extraction layer is obtained output .

[0105] The step AE performed by each feature extraction layer in the feature extraction network can concatenate the features and edge features of any node in the input data (the i-th node) and its neighboring node (the j-th node), and then perform a weighted summation based on the attention weight. The aggregation result is mapped to the node feature space through a linear transformation and added to the original node features through a residual connection. The edge features and node features are then aggregated through a multi-layer perceptron. For each edge (the edge formed by the connection between the i-th node and the j-th node), the edge features and the joint attention representation are superimposed through a residual connection, and then the output features of the edge are obtained through a nonlinear transformation of the multi-layer perceptron. Through the processing of multiple feature extraction layers, the edge information can be iteratively optimized with the depth of the network, thereby more accurately representing the connection characteristics between nodes.

[0106] In this embodiment, the input node feature n received by the feature extraction network input and input edge feature e input , and the output node processing result n output and edge processing results e output , has specific values according to the stage of the feature extraction network and the source of the data to be processed.

[0107] Reference Figure 2 ,The feature extraction network can perform steps S1-S4 when performing the inference phase.

[0108] In step S1, the target circuit diagram G to be identified and the template circuit diagram Q to be identified can be obtained first. Figure 4 As shown, the template circuit diagram Q to be identified can be a circuit diagram of a known key circuit structure (such as a differential amplifier, a current mirror or an operational amplifier, etc.), the target circuit diagram G to be identified can be a circuit diagram of a larger scale, and the key circuit structure represented by the template circuit diagram Q to be identified is equivalent to the search object in the target circuit diagram G to be identified. The task is to find out whether the target circuit diagram G to be identified contains the key circuit structure represented by the template circuit diagram Q to be identified, how many key circuit structures it contains, and the position of the key circuit structure in the target circuit diagram G to be identified.

[0109] In step S1, the first node feature n corresponding to the target circuit diagram G to be identified is obtained. G and the first edge feature e G In this embodiment, the first node feature n GSpecifically, it can be a 15-dimensional vector, which includes a 9-dimensional unique hot vector representing the device type in the target circuit diagram G to be identified, a 4-dimensional unique hot vector representing the device structural features in the target circuit diagram G to be identified, and the last two-dimensional numerical parameter vector representing the aspect ratio and gate length of the device structural features in the target circuit diagram G to be identified. Among them, the numerical parameter vector is mapped to the range of [0,1] using regularization to avoid numerical disturbances on the network convergence. The first edge feature e G It is a 5-dimensional vector that indicates which port of the device the edge is connected to (source, gate, drain, substrate or other passive device port).

[0110] For example, the first node feature n G In the code, bits 1-9 are one-hot vectors, each of which represents the corresponding node device type, IO pin, NMOS, PMOS, capacitor, diode, N-type diode, P-type diode, resistor, and inductor. If the values of bits 1-9 are (1, 0, 0, 0, 0, 0, 0, 0), it means that the corresponding node belongs to the IO pin; bits 10-13 are also one-hot vectors, belonging to the structure code, and their contents are as follows: Figure 5 As shown; the 14th digit represents the aspect ratio of the device, and the 15th digit represents the gate length of the device.

[0111] For example, the first edge feature e G In the example, bits 1 to 5 indicate whether the corresponding edge is connected to the source, gate, drain, substrate, or other passive device ports of the node (device) to which it is connected; for example, if a first edge feature e G If it is (0,0,1,1,0), it means that the corresponding edge connects the drain and substrate of the device.

[0112] In this embodiment, since the target circuit diagram G to be identified generally includes multiple devices, each device corresponds to a node in the diagram, the target circuit diagram G to be identified also includes multiple nodes, each of which corresponds to a first node feature n. G , each edge formed by the node connection corresponds to a first edge feature e G , so the target circuit diagram G to be identified corresponds to multiple first node features n G and multiple first edge features e G .For example, Figure 6 Part (a) shows a circuit topology diagram of the target circuit diagram G to be identified (a part thereof), Figure 6 Part (b) shows the first node features n corresponding to this part of the target circuit diagram G to be identified. G and each first edge feature e GIn this embodiment, since the feature extraction layers and principles for the first node features corresponding to different nodes and the first edge features corresponding to different edges are the same, one of the first edge features and one of the first edge features can be used as examples for explanation. That is, in this embodiment, unless otherwise specified, the first node feature n G and the first edge feature e G It can refer to a specific first node feature and a first edge feature.

[0113] Similarly, in step S1, the second node feature n corresponding to the template circuit diagram Q to be identified is obtained. Q and the second edge feature e Q , the second node feature n Q The form and meaning of the first node feature n G Same, the second edge feature e Q The form and meaning of the first side feature e G Same, the difference is the first node feature n G and the first edge feature e G The object represented is the target circuit diagram G to be identified, and the second node feature n Q and the second edge feature e Q The object represented is the template circuit diagram Q to be identified.

[0114] In step S2, the first node feature n G As Figure 3 Input node features n in input , with the first edge feature e G As Figure 3 The input edge feature e in input , input to the feature extraction network for processing, the feature extraction network outputs the corresponding output node feature n output As the third node feature obtained in step S2 (T represents the result obtained after processing by T feature extraction layers), the corresponding output edge feature e output by the feature extraction network output As the third edge feature obtained in step S2

[0115] Third node characteristics and third side features is the feature extraction network for the first node feature n G and the first edge feature e G The processing result of the third node feature The size and format are the same as the first node feature n G Same, also a 15-dimensional vector, the third edge feature The size and format are the same as the first edge feature e GIt is also a 4-dimensional vector, and they all describe the same circuit, namely the target circuit diagram G to be identified. According to the principle of feature extraction network, it can be seen that the first node feature n G and the first edge feature e G In comparison, the third node feature and third side features The domain information of each node in the network (including the connected adjacent nodes and edges) is integrated through multi-layer stacking and multi-step sampling to achieve long-distance information aggregation, so that the circuit structure can be effectively perceived and the device-level topological information can be captured more easily and effectively.

[0116] In step S3, the principle is the same as that of step S2, and the second node feature n Q As Figure 3 Input node features n in input , with the second edge feature e Q As Figure 3 The input edge feature e in input , input to the feature extraction network for processing, the feature extraction network outputs the corresponding output node feature n output As the fourth node feature obtained in step S3 The corresponding output edge feature e output by the feature extraction network output As the fourth edge feature obtained in step S3

[0117] Similarly, the fourth node feature and the fourth side feature With the second node feature n Q and the second edge feature e Q The same template circuit diagram Q is also described, and its form and size are the same, and it is easier and more effective to identify it from the fourth node feature. and the fourth side feature Capture device-level topology information in

[0118] In this embodiment, since the target circuit graph G to be identified is generally larger than the template circuit graph Q to be identified, not all nodes in the target circuit graph G are nodes of an isomorphic subgraph. Therefore, before executing step S4 to perform circuit structure identification, nodes in the target circuit graph G that are clearly not matching nodes can be eliminated. Specifically, the confidence level of each node in the target circuit graph G to be identified can be calculated, and nodes whose corresponding confidence level is lower than an acceptance threshold (e.g., 0.9) can be deleted from the target circuit graph G to be identified.

[0119] Specifically, the confidence of each node in the target circuit diagram G to be identified can be calculated based on the first node feature in the target circuit diagram G to be identified and the second node feature in the template circuit diagram Q to be identified. The specific formula is as follows:

[0120]

[0121]

[0122] Among them, conf represents the confidence of each node in the target circuit diagram to be identified, MLP() represents multi-layer perception processing, is the third node feature, The principle of this formula is to obtain the fourth node feature from the template circuit diagram Q to be identified. Input into a multi-layer perceptron to obtain the transformed feature vector h Q , let the third node feature obtained from the target circuit graph G to be identified With h Q Perform matrix multiplication and apply Sigmoid function to the result of matrix multiplication, map the result to the interval [0,1], and get the final confidence. With the fourth node feature It can be selected arbitrarily, so the confidence between any node in the target circuit diagram G to be identified and any node in the template circuit diagram Q to be identified can be calculated. For any node in the target circuit diagram G to be identified, as long as there is any node in the template circuit diagram Q to be identified whose confidence between it and the node is less than the acceptance threshold, the node in the target circuit diagram G to be identified will be deleted, so that only all nodes with corresponding confidence higher than 0.9 are retained in the target circuit diagram G to be identified, and all nodes below 0.9 are excluded.

[0123] In this embodiment, Figure 4 The target circuit diagram G shown in FIG1 is filtered with low confidence, and the result can be obtained. Figure 7 Since there will be no ambiguity, the target circuit diagram to be identified after the confidence filtering can still be denoted as G in this embodiment.

[0124] In this embodiment, when executing step S4, that is, performing circuit structure recognition on the target circuit diagram according to the third node feature and the fourth node feature, the following steps may be specifically performed:

[0125] S401. Calculate the similarity between the third node feature and the fourth node feature;

[0126] S402. Based on the similarity, determine the matching degree between the node corresponding to the third node feature in the target circuit diagram to be identified and the node corresponding to the fourth node feature in the template circuit diagram to be identified;

[0127] S403. Based on the matching degree, a mapping relationship is established between nodes in the target circuit diagram to be identified and nodes in the template circuit diagram to be identified;

[0128] S404. According to the mapping relationship, the template circuit diagram to be identified is mapped to the target circuit diagram to be identified;

[0129] S405. Output the mapped portion of the target circuit diagram to be identified as a circuit structure recognition result.

[0130] In step S401, for any third node feature (Describe the target circuit diagram G to be identified) and any fourth node feature (Describe the template circuit diagram Q to be identified), their cosine similarity can be calculated.

[0131] In step S402, the third node feature With the fourth node feature The cosine similarity is normalized by Softmax function to obtain the third node feature With the fourth node feature degree of matching.

[0132] Due to the third node characteristics With the fourth node feature It can be selected arbitrarily, so in step S403, for a specific third node feature All fourth node features of the template circuit diagram Q to be identified can be traversed With this third node feature Perform matching calculation to obtain the third node feature Corresponding to all matching degrees, take the fourth node feature with the highest matching degree The corresponding node in the template circuit diagram Q to be identified is the same as the third node feature A mapping relationship is established between the nodes in the corresponding target circuit diagram G to be identified. This mapping relationship allows multiple nodes in the target circuit diagram G to be identified to be mapped to the same node in the template circuit diagram Q to be identified.

[0133] By executing step S403, it is possible to obtain Figure 8 The mapping relationship shown in FIG. 4 shows that there is a mapping relationship between the two nodes corresponding to the dark grid. In step S404, Figure 8The mapping relationship shown maps the nodes in the template circuit diagram Q to be identified to the nodes in the target circuit diagram G to be identified.

[0134] For example, Figure 9 In the target circuit diagram G to be identified, the nodes with the same color as the template circuit diagram Q to be identified are the mapped parts. Execute step S405 and output this part as the circuit structure identification result. Figure 9 It can be seen that the mapped part of the target circuit diagram G to be identified is a subgraph isomorphic to the template circuit diagram Q to be identified, that is, the key circuit structure of the same type as the template circuit diagram Q to be identified in the target circuit diagram G to be identified, thereby identifying the key circuit structure in the target circuit diagram G to be identified, including determining whether the target circuit diagram G to be identified contains the key circuit structure, the number and position of the key circuit structure, etc.

[0135] In this embodiment, when executing step S0, a trained feature extraction network can be obtained, so after executing step S0, the inference stage, that is, steps S1-S4, can be directly executed.

[0136] If the feature extraction network obtained in step S0 has not been trained yet, you can refer to Figure 2 , choose to perform the training phase after performing steps S1-S3. In this embodiment, the training phase includes performing the following steps:

[0137] S5. Train the feature extraction network through back propagation based on the loss function value.

[0138] In step S5, the cross entropy loss function can be used to calculate the loss value of the third node according to the feature of the third node. and the fourth node feature Calculate the loss function value. Specifically, the following formula

[0139]

[0140] L=L classify +βL conf

[0141] in, Represents the third node feature corresponding to the i-th node in the training target circuit graph G Represents the fourth node feature corresponding to the jth node in the training template circuit diagram Q Represents the fourth node feature corresponding to the kth node in the training template circuit diagram Q Indicates traversing and summing the nodes in the training template circuit diagram Q that are adjacent to the training target circuit diagram G; F(G i )=Q jIndicates that the i-th node in the training target circuit diagram G has a mapping relationship with the j-th node in the training template circuit diagram Q (the mapping relationship can be marked in advance), It means traversing all the i-th nodes and j-th nodes with mapping relationships and summing them up. i represents the confidence corresponding to the i-th node in the training target circuit graph G, ∑ i∈G′ It means to sum up all nodes in the target circuit graph G for training whose confidence is higher than the acceptance threshold (that is, they will not be filtered out by low confidence). Indicates the summation of all nodes in the target circuit diagram G with confidence equal to or lower than the acceptance threshold (that is, they will be filtered out with low confidence), L classify Represents the classification loss term, which reflects the gap between the similarity between the model predicted nodes and the actual similarity, L conf Represents the confidence loss term, which reflects the gap between the node confidence predicted by the model and the actual node confidence. The loss function value L is the classification loss term L classify and the confidence loss term L conf The weighted sum of , β can be taken as 0.1.

[0142] When executing step S5, training can be performed at a learning rate of 1e-3, and the model parameters (such as W in the linear transformation matrix in each feature extraction layer) can be adjusted using the SGD stochastic gradient descent method. q 、W k 、W v and W e ) for optimization and stop training after 200 iterations.

[0143] A computer program for executing the circuit structure identification method for simulating integrated circuit design automation in this embodiment can be written and written into a computer device or storage medium. When the computer program is read out and run, the circuit structure identification method for simulating integrated circuit design automation in this embodiment is executed, thereby achieving the same technical effect as the circuit structure identification method for simulating integrated circuit design automation in the embodiment.

[0144] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature, or it may be indirectly fixed or connected to the other feature. In addition, the descriptions of up, down, left, right, etc. used in this disclosure are only relative to the relative positional relationships of the components of the present disclosure in the accompanying drawings. The singular forms of "a", "" and "the" used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, unless otherwise defined, all technical and scientific terms used in this embodiment have the same meaning as those generally understood by those skilled in the art. The terms used in the specification of this embodiment are only for describing specific embodiments and are not intended to limit the invention. The term "and / or" used in this embodiment includes any combination of one or more related listed items.

[0145] It should be understood that, although the present disclosure may adopt the term first, second, third etc. to describe various elements, these elements should not be limited to these terms.These terms are only used to distinguish the elements of the same type from each other.For example, without departing from the scope of the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element.The use of any and all examples or exemplary language ("for example", "such as" etc.) provided by the present embodiment is only intended to better illustrate embodiments of the present invention, and unless otherwise required, the scope of the present invention will not be limited.

[0146] It should be appreciated that embodiments of the present invention can be implemented or practiced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The methods can be implemented in a computer program using standard programming techniques - including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner - according to the methods and figures described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, the program can be run on a programmed application-specific integrated circuit for this purpose.

[0147] In addition, the operations of the process described in this embodiment may be performed in any suitable order, unless otherwise indicated in this embodiment or otherwise clearly contradicted by the context. The process described in this embodiment (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as a code (e.g., executable instructions, one or more computer programs, or one or more applications) executed on one or more processors, by hardware or a combination thereof. A computer program includes a plurality of instructions that may be executed by one or more processors.

[0148] Furthermore, the method can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the process described herein. In addition, the machine-readable code, or portions thereof, can be transmitted over a wired or wireless network. When such media includes instructions or programs that implement the above steps in conjunction with a microprocessor or other data processor, the invention of this embodiment includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques of the present invention, the present invention also includes the computer itself.

[0149] The computer program can be applied to input data to perform the functions of the present embodiment, thereby converting the input data to generate output data that is stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.

[0150] The above are merely preferred embodiments of the present invention. The present invention is not limited to the aforementioned embodiments. As long as the technical effects of the present invention are achieved by the same means, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, various modifications and variations of the technical solutions and / or implementation methods may be made.

Claims

1. A circuit structure recognition method for analog integrated circuit design automation, characterized in that: The circuit structure identification method for simulating integrated circuit design automation includes: Obtaining a feature extraction network; the feature extraction network is used to receive input node features and input edge features, process the input node features and the input edge features through a plurality of feature extraction layers, and obtain output node features and output edge features; Obtaining a first node feature and a first edge feature corresponding to the target circuit diagram to be identified, and a second node feature and a second edge feature corresponding to the template circuit diagram to be identified; Using the first node feature and the first edge feature as input node features and input edge features, inputting them into the feature extraction network, obtaining output node features processed by the feature extraction network as third node features, and obtaining output edge features processed by the feature extraction network as third edge features; Using the second node feature and the second edge feature as input node features and input edge features, inputting them into the feature extraction network, obtaining output node features processed by the feature extraction network as fourth node features, and obtaining output edge features processed by the feature extraction network as fourth edge features; The following steps are performed during the inference phase: The circuit structure of the target circuit diagram to be identified is identified according to the third node feature and the fourth node feature.

2. The circuit structure recognition method for analog integrated circuit design automation according to claim 1, characterized in that: The step of processing the input node features and the input edge features through a plurality of feature extraction layers to obtain output node features and output edge features includes: For any of the feature extraction layers, perform the following steps: According to the formula n norm =LayerNormalize(n input ) N q =n norm ·W q N k =n norm ·W k N v =n norm ·W v E f =LayerNormalize(e input )·W e Perform calculation processing; wherein, when the feature extraction layer is the first feature extraction layer, n input is the input node feature received by the feature extraction network, e input is the input edge feature received by the feature extraction network. When the feature extraction layer is other feature extraction layers, n input is the node processing result of the previous feature extraction layer, e input is the edge processing result of the previous feature extraction layer; LayerNormalize() represents the layer regularization processing, W q 、W k 、W v and W e is the linear transformation matrix in the feature extraction layer; According to the formula Perform calculation processing; among them, score ij represents the intermediate attention score corresponding to the i-th node and the j-th node, exp() represents the exponential operation, Indicates N q The eigenvector corresponding to the i-th node in Indicates N k The eigenvector corresponding to the jth node, e ij Indicates E f The feature vector corresponding to the edge formed by the i-th node and the j-th node, Indicates N k The eigenvector corresponding to the zth node, e iz Indicates E f The feature vector corresponding to the edge formed by the i-th node and the z-th node, z∈N j Indicates that the zth node is selected from all nodes that have an edge connection with the jth node; According to the formula Perform calculation processing; among them, att ij represents the final attention score corresponding to the i-th node and the j-th node, Indicates N v The feature vector corresponding to the i-th node; According to the formula n output =n input +MLP(sum(to ij )) Perform calculation processing; where n output Indicates the node processing result of this feature extraction layer, MLP() represents multi-layer perception processing; According to the formula And att =and input +score ij yes output =e att +MLP(LayerNormalize(e att )) Perform calculation processing; where e output Indicates the edge processing result of this feature extraction layer; The node processing result of the last feature extraction layer is used as the output node feature, and the edge processing result of the last feature extraction layer is used as the output edge feature.

3. The circuit structure recognition method for analog integrated circuit design automation according to claim 1, characterized in that: The performing circuit structure identification on the target circuit diagram to be identified based on the third node feature and the fourth node feature includes: Calculating the similarity between the third node feature and the fourth node feature; Determining, based on the similarity, a degree of matching between a node corresponding to the third node feature in the target circuit diagram to be identified and a node corresponding to the fourth node feature in the template circuit diagram to be identified; According to the matching degree, a mapping relationship is established between the nodes in the target circuit diagram to be identified and the nodes in the template circuit diagram to be identified; According to the mapping relationship, mapping the template circuit diagram to be identified to the target circuit diagram to be identified; The mapped portion of the target circuit diagram to be identified is output as a circuit structure identification result.

4. The circuit structure recognition method for analog integrated circuit design automation according to claim 3, characterized in that: Before mapping the template circuit diagram to be identified to the target circuit diagram to be identified according to the mapping relationship, performing circuit structure identification on the target circuit diagram to be identified according to the third node feature and the fourth node feature further includes: Obtaining the confidence level of each node in the target circuit diagram to be identified; Nodes whose corresponding confidence levels are lower than an acceptance threshold are deleted from the target circuit diagram to be identified.

5. The circuit structure recognition method for analog integrated circuit design automation according to claim 4, characterized in that: The obtaining of the confidence level of each node in the target circuit diagram to be identified includes: According to the formula Perform calculation processing; wherein conf represents the confidence of each node in the target circuit diagram to be identified, MLP() represents multi-layer perception processing, is the third node feature, is the fourth node feature.

6. The circuit structure recognition method for analog integrated circuit design automation according to claim 1, characterized in that: The circuit structure identification method for simulating integrated circuit design automation also includes: The following steps are performed during the training phase: The feature extraction network is trained according to the third node feature and the fourth node feature.

7. The circuit structure recognition method for analog integrated circuit design automation according to claim 6, characterized in that: The training phase is performed before the inference phase, and the feature extraction network is trained according to the third node feature and the fourth node feature, including: Perform cross entropy loss calculation based on the third node feature and the fourth node feature to obtain a loss function value; The feature extraction network is trained by back propagation according to the loss function value.

8. A computer device, characterized in that: The invention comprises a memory and a processor, wherein the memory is used to store at least one program, and the processor is used to load at least one program to execute the circuit structure recognition method for simulating integrated circuit design automation according to any one of claims 1 to 7.

9. A computer-readable storage medium storing a program executable by a processor, characterized in that: The program executable by the processor is used to execute the circuit structure recognition method for simulating integrated circuit design automation as described in any one of claims 1 to 7 when executed by the processor.

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