Display method, electronic equipment and readable storage medium

Abstract

The invention relates to the field of display, and discloses a display method, electronic equipment and a readable storage medium. In the method, after the electronic equipment with a display screen detects a mode switching command in a command mode, a first moment when a first VSync signal of a video mode should be sent can be determined according to a refresh rate, and a TE signal sent by the display screen is controlled to be switched to a high level state at the first moment. Furthermore, on the basis of the detection of the TE signal for switching to the high-level state at the first time, a first VSync signal for transmitting the video mode at the first time is triggered, and a refresh cycle of the video mode is instructed to start. Wherein the sending time of the first VSync signal in the video mode can be equal to or later than the first time. In this way, the first VSync signal of the video mode cannot be sent out earlier than the first moment, and it is avoided that due to the fact that the VSync signal is sent out earlier, the pixel light-emitting duration before and after the display mode is switched is different, and a display screen is splashed.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display method, an electronic device, and a readable storage medium. Background Art

[0002] The refresh rate indicates the number of times a display refreshes a frame per second. For example, a refresh rate of 120Hz means the display refreshes 120 times per second, with a refresh period of 8.3ms (i.e., 1000ms / 120 = 8.3ms). This means that the display sends an external vertical synchronization (VSync) signal every 8.3ms to refresh a frame. To maintain consistent screen brightness, the emission signal (hereinafter referred to as the EM signal) corresponding to each refresh period is the same. The EM signal is used to control the display's pixel illumination or extinguishing. For example, each 8.3ms refresh period can include three identical EM signals with a period of 2.7ms, and the pixel illumination duration corresponding to each EM signal is the same.

[0003] In addition, the display frame rate indicates the number of image frames rendered per second by the graphics processing unit (GPU). For example, a display frame rate of 120fps means that the GPU renders 120 frames per second, with a rendering cycle of 8.3ms. This means that the GPU sends an internal vertical synchronization (VSync) signal every 8.3ms to indicate the completion of rendering a frame. It is understood that the refresh rate and display frame rate are usually synchronized. That is, the external VSync signal sent by the display and the internal VSync signal sent by the GPU must be synchronized to ensure that each frame of the image is displayed synchronously on the display after rendering, thereby providing a smoother viewing experience.

[0004] However, when the display switches from command mode (the display mode used to display static images or text) to video mode (the display mode used to display dynamic video) based on a mode switch command, the image frames to be displayed corresponding to the video mode are rendered faster, which causes the start time of the first internal VSync signal of the video mode to be advanced, that is, the first refresh cycle of the video mode to be advanced. Based on this, the end time of the last refresh cycle of the command mode before the first refresh cycle of the video mode is also advanced, resulting in different adjacent refresh cycles before and after the switch, and different pixel light-emitting times related to the refresh cycle, causing the display to flicker. Summary of the Invention

[0005] To solve the above problems, the present application provides a display method, an electronic device and a readable storage medium.

[0006] In a first aspect, the present application provides a display method, which is applied to an electronic device, the electronic device including a display screen, and the method including: detecting a mode switching command within a first refresh cycle of a command mode, controlling a first TE signal to switch from a low level state to a high level state at a first moment, wherein the first TE signal is used to indicate that the image frame within the first refresh cycle is completed and displayed, the first moment is the end moment of the first refresh cycle, and the first moment is the start moment of the second refresh cycle of the corresponding video mode, and the first moment is related to the screen refresh rate of the display screen; based on the first TE signal, a vertical synchronization signal is sent at the first moment, the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode within the second refresh cycle of the corresponding video mode.

[0007] It can be understood that the first refresh cycle of the command mode may refer to the first refresh cycle mentioned in the embodiment of the present application. Figure 7 The first moment may refer to the time t0 to the time t1 mentioned in the embodiment of the present application. Figure 7 The second refresh cycle corresponding to the video mode may refer to the time t1 mentioned in the embodiment of the present application. Figure 7 The vertical synchronization signal sent at the first moment may refer to the internal Vsync signal sent at the first moment mentioned in the embodiment of the present application. The image frame corresponding to the video mode may refer to the image frame mentioned in the embodiment of the present application. Figure 7 Image frame N+1 is shown.

[0008] Through the above method, the first time when the first VSync signal corresponding to the video mode should be sent is determined. This first time is also the time when the first refresh cycle of the command mode ends. In addition, the first TE signal emitted by the control display screen is switched to a high level state at the first time, and the display screen can switch from the command mode to the video mode at the first time. This avoids the first VSync signal of the video mode being sent in advance of the first time, thereby avoiding the display screen flickering problem caused by the different pixel light emission durations before and after the display mode switch due to the VSync signal being sent in advance of the first time.

[0009] In a possible implementation of the first aspect above, before displaying an image frame corresponding to the video mode in a second refresh period of the corresponding video mode, the method further includes: switching the first TE signal from a high level state to a low level state.

[0010] It can be understood that the second refresh cycle corresponding to the video mode can refer to the second refresh cycle mentioned in the embodiment of the present application. Figure 7 From the time t1 to the time t2 shown in FIG, the image frame corresponding to the displayed video mode in the second refresh cycle of the corresponding video mode may refer to the image frame mentioned in the embodiment of the present application. Figure 7 Image frame N+1 is shown in .

[0011] Based on this, it is possible to control the Figure 7 At the moment t1 shown in FIG, the first TE signal switches to a high level state. Figure 7 Before the image frame N+1 shown in begins to be displayed, it switches from a high level state to a low level state.

[0012] In a possible implementation of the first aspect above, the method also includes: the method also includes: detecting that the first buffer period of the command mode starts at the first moment and ends at the second moment, the first buffer period is less than or equal to the first refresh period, and the first refresh period is N times the first buffer period, N∈ a positive integer; detecting that the second refresh period of the command mode starts at the second moment and ends at the third moment, corresponding to detecting the mode switching command within the second refresh period of the command mode, controlling the second TE signal to switch from a low level state to a high level state at the third moment; wherein the second TE signal is used to indicate that the image frame within the second refresh period of the command mode is completed and displayed, the third moment is the end moment of the second refresh period of the command mode, and the third moment is the start moment of the third refresh period of the corresponding video mode; based on the second TE signal, sending a vertical synchronization signal at the third moment, the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode within the third refresh period of the corresponding video mode.

[0013] It can be understood that the first refresh cycle may refer to the Figure 8 From time t0 to time t1, the first buffer period may refer to the time period mentioned in the embodiment of the present application. Figure 8 The second moment can refer to the time from t1 to t1+2.7ms. Figure 8 The third moment can refer to the t1+2.7ms moment shown. Figure 8 The second refresh cycle of the command mode may refer to the 2*t1+2.7ms time mentioned in the embodiment of the present application. Figure 8 The third refresh cycle of the corresponding video mode refers to the time t1+2.7ms to the time 2*t1+2.7ms mentioned in the embodiment of the present application. Figure 8 The image frame corresponding to the video mode displayed in the third refresh cycle of the corresponding video mode may refer to the image frame mentioned in the embodiment of the present application. Figure 8 The image frame shown is N+2. In addition, the first refresh period is N times the first buffer period, where N∈ is a positive integer, N=1, 2, 3, etc., which is not limited here.

[0014] Based on this, by reserving a certain buffer time (i.e., the first buffer period) between adjacent refresh cycles in command mode, it is ensured that all commands have been processed and the system is fully ready to receive video data before switching to video mode, thereby avoiding image frame loss or display errors when switching from command mode to video description.

[0015] It is understood that in other embodiments of the present application, when switching from command mode to video mode, a certain buffer time can be reserved between adjacent refresh cycles in command mode. Figure 11 After the time period from t1+2.7ms to 2*t1+2.7ms shown in FIG1 is over, the image frame of the last refresh cycle of the command mode can be repeatedly displayed (eg, Figure 11 After the image frame N+2 (between time 2*t1+2.7ms and time 3*t1+2.7ms) is displayed, the video mode is switched to. Repeating the display of a single image frame provides additional time for timing correction, ensuring a stable and consistent switching process.

[0016] In a possible implementation of the first aspect above, before displaying the image frame corresponding to the video mode in the third refresh period of the corresponding video mode, the method further includes: switching the second TE signal from a high level state to a low level state.

[0017] It can be understood that the third refresh cycle corresponding to the video mode can refer to the third refresh cycle mentioned in the embodiment of the present application. Figure 8 The image frame corresponding to the video mode displayed in the third refresh cycle of the corresponding video mode may refer to the image frame mentioned in the embodiment of the present application. Figure 8 Image frame N+2 is shown in .

[0018] Based on this, it can be controlled at the third moment (such as Figure 8 The second TE signal is switched to a high level state at the moment 2*t1+2.7ms shown in FIG. Figure 8 Before the image frame N+2 shown in begins to be displayed, it switches from a high level state to a low level state.

[0019] In a possible implementation of the first aspect above, the first buffer period corresponding to the detection of the command mode starts at the first moment and ends at the second moment, and the method also includes: the second buffer period corresponding to the detection of the command mode starts at the first moment and ends at the fourth moment, the second buffer period is less than or equal to the first refresh period, and the first refresh period is N times the second buffer period, N∈ a positive integer; the mode switching command is detected within the second buffer period; the end of the second buffer period is detected at the fourth moment, and the third TE signal is controlled to switch from a low level state to a high level state at the fourth moment, wherein the fourth moment is the end moment of the second buffer period of the command mode, and the fourth moment is the start moment of the second refresh period of the corresponding video mode; based on the third TE signal, a vertical synchronization signal is sent at the fourth moment, the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode within the second refresh period of the corresponding video mode.

[0020] It can be understood that the second buffer period of the command mode may refer to the second buffer period of the command mode mentioned in the embodiment of the present application. Figure 9 The fourth moment may refer to the time t1 to t1+5.4ms mentioned in the embodiment of the present application. Figure 9 The second refresh period corresponding to the video mode may refer to the time t1+5.4ms mentioned in the embodiment of the present application. Figure 9 The image frame corresponding to the video mode displayed in the second refresh cycle of the corresponding video mode may refer to the image frame mentioned in the embodiment of the present application. Figure 9 Image frame N+1 is shown.

[0021] Based on this, when switching from command mode to video mode, buffer time can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued in the buffer time reserved for the last refresh cycle in command mode.

[0022] In a possible implementation of the first aspect above, before displaying the image frame corresponding to the video mode in the second refresh period corresponding to the video mode, the method further includes: switching the third TE signal from a high level state to a low level state.

[0023] Based on this, it can be controlled at the fourth moment (such as Figure 9 The third TE signal is switched to a high level state at the time t1+5.4ms shown in FIG. Figure 9 Before the image frame N+1 shown in begins to be displayed, it switches from a high level state to a low level state.

[0024] In a possible implementation of the first aspect above, the content displayed in the command mode includes a static image or a dynamic image, and the content displayed in the video mode includes a video.

[0025] In a possible implementation of the first aspect above, the method also includes: detecting a mode switching command within the first refresh cycle of the command mode, controlling the first TE signal to switch from a low level state to a high level state at the first moment; detecting that the second refresh cycle of the command mode starts at the first moment and ends at the fifth moment, controlling the first TE signal to switch from a low level state to a high level state at the fifth moment; based on the first TE signal, controlling the display screen to switch from the command mode to the video mode at the fifth moment.

[0026] It can be understood that the first refresh cycle of the command mode may refer to the first refresh cycle mentioned in the embodiment of the present application. Figure 10 The time t0 to the time t1 shown in the figure, the first time may refer to the time t1 mentioned in the embodiment of the present application. Figure 10 The second refresh cycle of the command mode may refer to the time t1 mentioned in the embodiment of the present application. Figure 10 The fifth moment may refer to the time from t1 to t2 mentioned in the embodiment of the present application. Figure 10 The time t2 is shown.

[0027] Based on this, when switching from command mode to video mode, by the last refresh cycle in command mode, that is, Figure 10 After the second refresh cycle (from time t1 to time t2) of the command mode shown in the figure ends, the image frame from the last refresh cycle of the command mode can be repeatedly displayed before switching to video mode. In this way, if an error is detected during the switching process, repeating the image frame provides additional time to correct the timing, ensuring a stable and consistent switching process.

[0028] In a second aspect, an embodiment of the present application provides an electronic device, including a memory for storing instructions; and a processor for executing instructions to implement the display method provided in the above-mentioned first aspect and various possible implementations of the first aspect.

[0029] In a third aspect, an embodiment of the present application provides a readable storage medium having instructions stored thereon. When the instructions are executed on a terminal device, the electronic device executes the display method provided by the above-mentioned first aspect and various possible implementations of the first aspect.

[0030] In a fourth aspect, an embodiment of the present application further provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the display method provided by the above-mentioned first aspect and various possible implementations of the first aspect.

[0031] The beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions of the first aspect and various possible implementations of the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 (a) shows a schematic diagram of a mobile phone 10 displaying a static image interface 101 according to a method provided in an embodiment of the present application;

[0033] Figure 1 (b) shows a schematic diagram of a mobile phone 10 displaying a video interface 102 according to a method provided in an embodiment of the present application;

[0034] Figure 2A (a) shows a schematic diagram of a control process corresponding to displaying a static image in command mode according to a method provided in an embodiment of the present application;

[0035] Figure 2A (b) shows a schematic diagram of a control process corresponding to displaying a video screen in video mode according to the method provided in an embodiment of the present application;

[0036] Figure 2B According to the method provided in an embodiment of the present application, a schematic diagram of a control process for displaying a dynamic picture in command mode is shown;

[0037] Figure 3 (a) shows a timing diagram of receiving a mode switching command in command mode according to the method provided in an embodiment of the present application;

[0038] Figure 3 (b) shows another timing diagram of receiving a mode switching command in command mode according to the method provided in an embodiment of the present application;

[0039] Figure 4 According to the method provided in an embodiment of the present application, a timing diagram for switching from command mode to video mode is shown;

[0040] Figure 5 According to the method provided in an embodiment of the present application, a schematic diagram of a graphics processing system 00 of an electronic device is shown;

[0041] Figure 6 According to the method provided in the embodiment of the present application, a flow chart of a display method is shown;

[0042] Figure 7 According to the method provided in the embodiment of the present application, a timing diagram 01 of switching from command mode to video mode is shown;

[0043] Figure 8 According to the method provided in the embodiment of the present application, a timing diagram 02 of switching from command mode to video mode is shown;

[0044] Figure 9 According to the method provided in the embodiment of the present application, a timing diagram 03 of switching from command mode to video mode is shown;

[0045] Figure 10 According to the method provided in the embodiment of the present application, a timing diagram 04 of switching from command mode to video mode is shown;

[0046] Figure 11 According to the method provided in the embodiment of the present application, a timing diagram 05 of switching from command mode to video mode is shown;

[0047] Figure 12 According to the method provided in the embodiment of the present application, a timing diagram 06 of switching from command mode to video mode is shown;

[0048] Figure 13 According to the method provided in the embodiment of the present application, a timing diagram 07 of switching from video mode to command mode is shown;

[0049] Figure 14 According to the method provided in an embodiment of the present application, a structural diagram of a terminal device 100 is shown. DETAILED DESCRIPTION

[0050] The illustrative embodiments of the present application include, but are not limited to, a display method, a terminal device, and a readable storage medium.

[0051] It can be understood that the electronic devices applicable to the present application can be mobile phones with display screens, smart screens, wearable devices, tablet computers (Pads), laptop computers, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, terminal devices in industrial control (industrial control), terminal devices in self-driving, terminal devices in remote medical surgery, terminal devices in smart grids, terminal devices in transportation safety (transportation safety), terminal devices in smart cities (smart cities), terminal devices in smart homes (smart homes), etc.

[0052] It can be understood that in the display system, the GPU sending an internal VSync signal can indicate that the image frame to be displayed has been rendered and is ready for display, and the display screen sending an external VSync signal can indicate that the display screen can start displaying the image frame to be displayed. When displaying image frames corresponding to static images, the display screen can start displaying image frames to be displayed each time based on the external VSync signal. When displaying image frames corresponding to video, the GPU starts sending the rendered image frames to be displayed to the display screen based on the internal VSync signal each time, and then the display screen displays the image frames to be displayed based on the external VSync signal. Among them, based on the fact that the screen refresh rate and the display frame rate are the same, the external VSync signal and the external VSync signal are synchronized and issued at the same time.

[0053] Figure 1 A schematic diagram of a mode switching scenario is shown. Figure 1 In the static image display scene diagram (a), the mobile phone 10 displays a static image interface 101; Figure 1 In the video display scene diagram shown in (b), the mobile phone 10 displays the video interface 102. When the display screen of the mobile phone 10 switches from displaying the static image interface 101 to displaying the video interface 102, the mobile phone 10 needs to first send the first internal VSync signal in the video mode through the GPU to indicate that the image frame rendering is complete in order to display the image frame corresponding to the video interface 102. However, if the GPU renders faster to meet the video playback requirements, the GPU may send the first internal VSync signal in the video mode in advance. Based on this, in order to be able to synchronously display the image frame corresponding to the rendered video interface 102, the display screen also needs to send the first external VSync signal in the video mode in advance.

[0054] In this way, the refresh cycle of the static image interface 101 in the command mode is shorter than the refresh cycle of the video interface 102 in the video mode, and the luminous duration of the relevant image frame of the static image interface 101 displayed on the display screen in the command mode is shorter than the luminous duration of the relevant image frame of the video interface 102 displayed on the display screen in the video mode. That is, the display brightness of the static image interface 101 is different from the display brightness of the video interface 102, causing the display screen to flicker, such as Figure 1 The flashing line 1010 in Figure (a) in FIG.

[0055] For ease of understanding, Figure 2A A schematic diagram of the control process of controlling the display screen display interface related image frames corresponding to the command mode and the video mode is shown.

[0056] like Figure 2AAs shown in (a) of the figure, the control process for displaying a static image in command mode includes: After the GPU renders the image frame corresponding to the static image, it can store it in graphics random access memory (GRAM) for display. When the display sends an external VSync signal based on the screen refresh rate, the display can directly retrieve the rendered image frame from GRAM and display it, without having to wait for the GPU to complete the rendering and store it in GRAM before retrieving the image frame.

[0057] like Figure 2A As shown in (b), the control process for displaying video in video mode includes the following: After the GPU completes rendering an image frame, it sends the rendered image frame to the display for display based on an internal VSync signal sent according to the display frame rate. The display then displays the rendered image frame based on an external VSync signal synchronized with the internal VSync signal.

[0058] It is understood that dynamic images can also be displayed in the above command mode. Figure 2B Schematic diagram of the control process of displaying dynamic images in the command mode shown. When the GPU completes real-time rendering of the image frame, the GPU will send the real-time rendered image frame to the GRAM for storage based on the internal VSync signal sent according to the display frame rate. The display screen obtains the real-time rendered image frame from the GRAM according to the external VSync signal synchronized with the internal VSync signal and displays it.

[0059] For the above Figure 2A The timing relationship between the internal VSync signal and the external VSync signal in the control process shown below is combined with Figure 3 Reference Figure 3 (a) in the figure shows a timing diagram of receiving a mode switching command in command mode. When the display screen receives a mode switching command in command mode, the display screen can send a TE signal after the image frame display in command mode is completed. The TE signal is used to indicate to the GPU that the current display screen is ready to start displaying the next frame of image. The GPU can send an internal VSync signal at any time when the TE signal is in a high level state to send the rendered new frame of image to the display screen for display. Figure 3As shown in (a) of the figure, the refresh cycle of the command mode is [t0, t1]. The TE signal is high in the interval [t03, t1]. t03 falls within [t0, t1]. The GPU sends the internal VSync signal at time t1, when the TE signal is high. This time is exactly when the internal VSync signal should be sent to indicate the start of the next refresh cycle based on the display frame rate. Thus, the display synchronizes the external and internal VSync signals at time t1, and displays the image frame to be displayed at time t1.

[0060] Continue to refer Figure 3 In (a), based on the display frame rate or refresh rate, the VSync signal should be sent at time t1. Therefore, the first internal VSync signal and the first external VSync signal of the video mode are sent at time t1. Based on this, the refresh period before and after the display mode switch is 8.3ms, and each refresh period includes three 2.7ms EM signals. This means that the pixel illumination duration is the same before and after the display mode switch, indicating that the display brightness remains unchanged.

[0061] It is understood that the low level of each EM signal can represent the pixel light-emitting state, and the high level of each EM signal can represent the pixel extinguishing state, which is not limited here. Figure 3 In the refresh cycle of the command mode and video mode in (a), the complete cycle of each EM signal is 2.7ms, which means that the time length of each EM signal being at the low level is the same.

[0062] However, if Figure 3 (b) shows another timing diagram of receiving a mode switching command in command mode. When the display screen receives a mode switching command in command mode, the display screen sends a TE signal after completing the image frame display in command mode. The TE signal starts to be in a high level state at time t03. The GPU can send an internal VSync signal at any time when the TE signal is high. For example, the GPU sends an internal VSync signal at time t05 when the TE signal is high, which is ahead of the GPU. Figure 3 In (a), based on the display frame rate, the internal VSync signal should be sent at time t1. The GPU sends the image frame to the display at time t05, based on the internal VSync signal sent at time t05. To synchronize with the internal VSync signal, the display also sends an external VSync signal at time t05 and displays the image frame.

[0063] pass Figure 3As can be seen in (b), the time when the VSync signal should be sent based on the display frame rate or refresh rate is time t1, but the time interval corresponding to the high level state of the TE signal sent in command mode is before time t1. If the current GPU rendering speed is fast, the GPU can send the internal VSync signal in advance of time t1 after completing the fast rendering. For example, the GPU sends the internal VSync signal at time t05 and sends the image frame to be displayed to the display. As a result, the display also sends the external VSync signal in advance at time t05 to display the image frame in advance.

[0064] Continue to refer Figure 3 In (b) of the video mode, the first internal VSync signal and the first external VSync signal are sent at time t05, which precedes the time t1 at which the VSync signal should be sent based on the display frame rate or refresh rate. Therefore, the last refresh period of the command mode is shortened and is less than the first refresh period of the video mode, 8.3ms. Consequently, the pixel illumination duration corresponding to the last EM signal in the last refresh period of the command mode is less than the pixel illumination duration corresponding to the first EM signal in the video mode.

[0065] As previously mentioned, when the display switches from command mode to video mode based on a mode switch command, the image frames to be displayed in video mode are rendered faster, causing the start time of the first internal VSync signal in video mode to be advanced, that is, the first refresh cycle of video mode to be advanced. Based on this, the end time of the last refresh cycle of command mode, which precedes the first refresh cycle of video mode, is also advanced. As a result, the adjacent refresh cycles before and after the switch are different, and the pixel light-emitting time associated with the refresh cycle is also different, causing the display to flicker.

[0066] Therefore, in order to solve the above problems, an embodiment of the present application provides a display method. In this method, after an electronic device with a display screen detects a mode switching command in a command mode, it can first determine the moment when the first internal VSync signal of the video mode should be sent as the first moment based on the matching display frame rate (such as 120fps) or screen refresh rate (such as 60Hz), and control the TE signal emitted by the display screen to switch to a high level state at the first moment. Wherein, the first moment is later than the moment when the image frame display is completed in the command mode. Furthermore, the GPU of the electronic device can trigger the sending of the first internal VSync signal of the video mode at the first moment based on the detection of the above-mentioned TE signal switched to a high level state at the first moment, indicating that the refresh cycle of the video mode starts. Wherein, the sending moment of the first internal VSync signal of the video mode can be equal to or later than the above-mentioned first moment. In this way, the first external VSync signal of the video mode is then sent synchronously with the first internal VSync signal, so that the first external VSync signal of the video mode can be controlled not to be sent ahead of the above-mentioned first moment.

[0067] For example, when switching from command mode to video mode, assuming that the last refresh cycle of the command mode is determined to start at 0ms and end at 8.3ms based on the screen refresh rate, and the first refresh cycle of the video mode starts at 8.3ms, if the image frame of the command mode is displayed at 6ms, then the control TE signal is not sent at the earlier 6ms moment but at 8.3ms (i.e., the first moment), and the first internal VSync signal of the video mode is also sent at 8.3ms, and thus the first external VSync of the video mode is also sent at 8.3ms. Based on this, the first internal VSync signal and the first external VSync signal of the video mode will not be sent at an earlier moment (e.g., the aforementioned 6ms) than the first moment. In this way, the pixel light emission duration corresponding to the last EM signal in the last refresh cycle of the command mode and the pixel light emission duration corresponding to the first EM signal in the video mode can remain the same, that is, no screen flickering occurs.

[0068] For another example, assuming that the last refresh cycle of the command mode starts at 0ms and ends at 8.3ms, but the image frame of the command mode is not displayed at the first moment (8.3ms) but needs to be displayed at (8.3ms+2.7ms), then the TE signal can be controlled to be sent later than the first moment (8.3ms), that is, at (8.3ms+2.7ms). Based on this, the first internal VSync signal and the first external VSync signal of the video mode will not be sent earlier than (8.3ms+2.7ms). In this way, the pixel light-emitting duration corresponding to the last EM signal in the last refresh cycle of the command mode and the pixel light-emitting duration corresponding to the first EM signal of the video mode can remain the same, that is, there will be no screen flickering.

[0069] Through the display method provided in the embodiment of the present application, a smooth transition of the display screen of an electronic device from a command mode to a video mode can be achieved, avoiding screen flickering.

[0070] It is understood that the first VSync signal (including the internal VSync signal and the external VSync signal) in the video mode can be issued at or after the first time when the VSync signal should be sent based on the matching display frame rate or refresh rate. That is, the first VSync signal in the video mode will not be issued before the first time. Furthermore, the pixel lighting duration corresponding to the last EM signal in the command mode is the same as the pixel lighting duration corresponding to the first EM signal in the video mode. That is, the display brightness of the display screen will not change before and after the mode switch, thereby avoiding screen flickering.

[0071] For example, Figure 4 Based on the display method provided in an embodiment of the present application, a timing diagram when a command mode switches to a video mode is shown.

[0072] refer to Figure 4 After receiving the mode switching command in command mode, the time when the first internal VSync signal should be sent in video mode can be determined to be t1 according to the matching display frame rate or refresh rate. Then the display will send TE signal at t1, which is the same as the above. Figure 3 In (b), the TE signal initiated at time t05 is different. Furthermore, in video mode, the first internal VSync signal is sent synchronously with the rising edge of the TE signal at time t1. Therefore, the first external VSync signal in video mode is also initiated at time t1. This means that the first internal VSync signal in video mode is synchronized with the first external VSync signal, and both are sent at time t1, which corresponds to the time when the VSync signal should be sent based on the display frame rate or refresh rate.

[0073] Based on this, before and after the display mode is switched, the pixel lighting duration corresponding to each EM signal in the refresh cycle of the command mode and the video mode is the same, ensuring that the display brightness of the display screen remains unchanged before and after the display mode is switched, and avoiding the display screen flickering phenomenon.

[0074] To facilitate understanding of the method provided in the embodiments of this application, Figure 5 A structural diagram of a graphics processing system of an electronic device is shown.

[0075] like Figure 5 As shown, the graphics processing system 00 of the electronic device may include a system on a chip (SoC), a display interface integrated circuit (DDIC), a display panel, and the like.

[0076] Specifically, SoC is an integrated circuit that may include an application processor (AP), in which a central processing unit (CPU) and a graphics processing unit (GPU) may be integrated. The CPU is responsible for application-related tasks, and the GPU is responsible for processing graphics rendering tasks. In addition, the GPU may be integrated into the SoC or exist as an independent chip, which is not limited here. In an embodiment of the present application, in command mode, the GPU may be used to send the rendered image frames to GRAM for storage, and in video mode, the GPU may send the rendered image frames to the panel for display.

[0077] It is understood that the AP may also include a display serial interface (DSI) ( Figure 5 (not shown), DSI is an interface for connecting a system on chip (SoC) and a display panel.

[0078] DDIC is an integrated circuit directly connected to the display screen, responsible for processing and driving the display content of the display screen. DDIC can include GRAM, which means that DDIC has certain graphics processing capabilities and can store and process display data. In an embodiment of the present application, the display screen can send an external VSync signal based on the DDIC to indicate that the display screen can start displaying a new image frame. In addition, GRAM is a memory for storing image data, which can be called a frame buffer. GRAM stores image frames rendered by the GPU so that the panel can quickly access and display images.

[0079] A panel refers to the physical surface that makes up a display screen, including the screen that actually displays the image and the associated driving electronics. In some embodiments, the panel can utilize a variety of technologies, such as liquid crystal display (LCD), organic light-emitting diode (OLED), etc., without limitation herein. In embodiments of the present application, the display screen can display image frames based on the panel.

[0080] In some embodiments of the present application, under ideal conditions, the switching of the display mode from the command mode to the video mode can be instant, that is, after the last refresh cycle of the command mode ends, it starts to receive the video signal and switches to the video mode.

[0081] To facilitate understanding of the method provided in the embodiments of this application, Figure 6 A flow chart of a display method provided by the present application is shown. It can be understood that Figure 6 The execution subject of the flowchart shown may be the mobile phone 10 described above.

[0082] S601: A mode switching command is detected in the first refresh cycle of the command mode.

[0083] In some embodiments of the present application, it is assumed that a mode switching command is detected in the first refresh cycle of the command mode, for example, in the above Figure 4 A mode switching command is detected within the refresh period (t0, t1) of the command mode.

[0084] It is understood that the mode switching command may be "set_dsi_mode param=1," where "set_dsi_mode" is a command for configuring the DSI controller mode, and "param=1" indicates a specific operating mode, such as "param=1" indicating "video mode." "set_dsi_mode param=1" may indicate switching the display mode of the display screen from command mode to video mode. Furthermore, the use of "param=1" to indicate video mode in the embodiments of the present application is merely an example. In other embodiments, "param=2" may also be used to indicate video mode, which is not limited here.

[0085] S602: Calculate the first moment when the next refresh cycle starts based on the refresh rate, and control the first TE signal to switch from a low level state to a high level state at the first moment.

[0086] In some embodiments of the present application, the first moment of the next refresh cycle can be calculated based on the refresh rate, and the first TE signal can be controlled to switch from a low level state to a high level state at the first moment. Figure 4 The first moment is calculated to be t1. The first TE signal can then be controlled to switch from a low level state to a high level state at the first moment t1, indicating that the image frame in the current command mode has completed display. Furthermore, after detecting the first TE signal at time t1, an internal VSync signal can be synchronously sent at time t1 to switch from command mode to video mode.

[0087] S603: Based on the first TE signal, a vertical synchronization signal is sent at a first moment to switch from the command mode to the video mode.

[0088] In some embodiments of the present application, after detecting the first TE signal at time t1, an internal VSync signal and an external VSync signal may be synchronously issued at time t1. In response to the internal VSync signal at time t1, the image frame to be displayed is sent to the display screen, and in response to the external VSync signal at time t1, the image frame to be displayed is displayed on the display screen. At this point, the display mode corresponding to the display screen is video mode.

[0089] The following combination Figures 7 to 9 The timing diagrams shown illustrate the corresponding scenarios and processes respectively.

[0090] It can be understood that the display frame rate of the processor illustrated in the embodiment of the present application is 120fps, the refresh rate of the display screen is 120Hz, and the corresponding refresh period is 8.3ms. This is only an exemplary description. In other embodiments, the display frame rate, refresh rate and refresh period of the display screen can also be other values, which are not limited here.

[0091] As an example, Figure 7 FIG01 shows a timing diagram of switching from command mode to video mode.

[0092] like Figure 7As shown in timing diagram 01, in command mode, based on the external VSync signal at time t0, the command mode refresh cycle starts at time t0 and ends at time t1, a total of 8.3ms. The display begins displaying image frame N output by the processor. After the display finishes displaying image frame N and receives a mode switch command, it prepares to send a TE signal to indicate to the processor that image frame N has been displayed. In command mode, the display typically switches the TE signal from low to high at time t01, when the last image frame N in command mode has been displayed. However, considering that the display is switching from command mode to video mode, to avoid prematurely displaying the new image frame corresponding to the video mode (such as image frame N+1), the display controller does not switch the TE signal from low to high at time t01. Instead, it calculates the time when the next external VSync signal should be sent based on the refresh rate, that is, time t1, and controls the TE signal to switch from low to high at time t1.

[0093] Furthermore, after the processor detects that the TE signal switches from a low level to a high level at time t1, the processor sends the first internal VSync signal of the video mode at time t1, the display switches to the video mode, and the processor prepares to send the first image frame of the video mode based on the first internal VSync signal, that is, image frame N+1.

[0094] It can be understood that after the first internal VSync signal is sent, there is a vertical backporch (VBP). VBP is a time period during which the processor is preparing to output image frame N+1 and the display is preparing to receive image frame N+1. When VBP ends, image frame N+1 is output to the display for display. It can be understood that the TE signal can be changed from a high level to a low level during the VBP period. In addition, after the first internal VSync signal based on the video mode is sent at t1, the display can synchronously send the first external VSync signal of the video mode at time t1, and the display displays image frame N+1. After switching to video mode, the second internal VSync signal and the second external VSync signal of the video mode are sent at time t2, and the display then displays image frame N+2.

[0095] based on Figure 7As shown in the mode switching timing diagram 01, the display's last refresh cycle in command mode before switching display modes is 8.3ms. The three EM signals in this refresh cycle (t0, t1) each have the same period of 2.7ms. A low level in each EM signal indicates illumination, and the EM duty cycle (EM duty) of each EM signal is the same. EM duty refers to the duration that the EM signal illuminates during the refresh cycle, i.e., the duration that the pixel illuminates. Furthermore, the display's first refresh cycle in video mode after switching (t1, t2) is 8.3ms. The three EM signals in this refresh cycle (t1, t2) each have the same period of 2.7ms, and the EM duty cycle (EM duty) of each EM signal is the same. Therefore, the EM duty of the last EM signal in command mode and the first EM signal in video mode are also the same. This means that the display's pixel illumination duration is the same before and after the display mode switch, and the corresponding display brightness is the same, meaning the display screen will not flicker.

[0096] It can be understood that corresponding to the above Figure 7 In the VBP, after an image frame (e.g., image frame N+1) is displayed, a corresponding vertical front porch (VFP) exists. The VFP is a short interval before the display is ready to receive and display the next image frame (e.g., image frame N+2). This interval ensures the smooth transmission and processing of image frame N+1.

[0097] It is understood that the mode switching command may be "set_dsi_mode param=1," where "set_dsi_mode" is a command for configuring the DSI controller mode, and "param=1" indicates a specific operating mode, such as "param=1" indicating "video mode." "set_dsi_mode param=1" may indicate switching the display mode of the display screen from command mode to video mode.

[0098] It can be understood that in the embodiment of the present application, using "param=1" to represent the video mode is only an exemplary description. In other embodiments, "param=2" can also be used to represent the video mode, which is not limited here.

[0099] In some embodiments of the present application, a certain buffer time can be reserved between adjacent refresh cycles in command mode to ensure that all commands have been processed and the system is fully prepared to receive video data before switching to video mode, avoiding image frame loss or display errors when switching modes. In addition, the reserved buffer time can be a multiple of the refresh cycle. For example, if the refresh cycle is 8.3ms, the reserved buffer time can be 2.7ms, etc. In other words, the refresh cycle can be N times the buffer cycle, where N∈ is a positive integer, N=1, 2, 3, etc., which is not limited here. This is not limited here.

[0100] As another example, Figure 8 Another timing diagram 02 for switching from command mode to video mode is shown.

[0101] like Figure 8 As shown in timing diagram 02, in command mode, based on the external VSync signal at time t0, the refresh cycle of command mode, which lasts for 8.3ms, runs from time t0 to time t1. The display begins displaying image frame N output by the processor. When the display finishes displaying image frame N and prepares to display image frame N+1 in command mode, it reserves a buffer time. For example, based on an 8.3ms refresh cycle, a 2.7ms buffer is reserved. This buffer time corresponds to the interval (t1, t1+2.7ms). After the buffer time expires, the external VSync signal for command mode is issued at time (t1+2.7ms) to allow the display to display image frame N+1. After displaying image frame N+1, the display, upon receiving a mode switch command, prepares to issue a TE signal to indicate to the processor that image frame N+1 has been displayed. In command mode, the display typically switches the TE signal from low to high at time t11, after the display of the last image frame N+1 in command mode has been completed. However, considering that the display needs to switch from command mode to video mode, to prevent the new image frame corresponding to the video mode (such as image frame N+2) from being displayed prematurely, the display control does not switch the TE signal from low to high at time t11. Instead, it calculates the time when the next external VSync signal should be sent based on the refresh rate plus the buffer time, that is, the time (2*t1+2.7ms). Then, the TE signal is controlled to switch from low to high at time (2*t1+2.7ms).

[0102] Furthermore, after the processor detects that the TE signal switches from a low level to a high level at (2*t1+2.7ms), the processor sends the first internal VSync signal of the video mode at (2*t1+2.7ms), and the display switches to the video mode. The processor prepares to send the first image frame of the video mode based on the first internal VSync signal, that is, image frame N+2.

[0103] based on Figure 8 As shown in the mode switching timing diagram 02, before the display switches to the command mode, each refresh cycle is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. That is, in command mode, each EM signal has a consistent period of 2.7ms, a low level in each EM signal indicates on-state, and the EM duty cycle (EM duty) of each EM signal is the same. On the other hand, after the display switches to video mode, the first refresh cycle (2*t1+2.7ms, 3*t1+2.7ms) of the display is 8.3ms, and within these refresh cycles (2*t1+2.7ms, 3*t1+2.7ms), each EM signal has a consistent period of 2.7ms, with the same EM duty cycle (EM duty) of each EM signal. Therefore, the EM duty of the last EM signal in the command mode is the same as the EM duty of the first EM signal in the video mode. This means that the display's pixel illumination duration is the same before and after the switch, resulting in the same display brightness. This means the display will not experience flickering.

[0104] In some embodiments of the present application, when switching from command mode to video mode, buffer time can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued in the buffer time reserved for the last refresh cycle in command mode.

[0105] As another example, Figure 9 Another timing diagram for switching from command mode to video mode is shown.

[0106] like Figure 9 As shown in timing diagram 03, in command mode, based on the external VSync signal at time t0, the last refresh cycle of command mode lasts 8.3ms, starting at time t0 and ending at time t1. The display begins displaying image frame N output by the processor. After the display finishes displaying image frame N, it reserves a buffer time. For example, based on an 8.3ms refresh cycle, a buffer time of 2.7 + 2.7 = 5.4ms is reserved, corresponding to the time interval (t1, t1 + 5.4ms). During the buffer time interval (t1, t1 + 5.4ms), the display detects the mode switch command and prepares to issue a TE signal to indicate to the processor that image frame N has been displayed. The display first calculates the time (t1 + 5.4ms) at which the next external VSync signal should be issued after image frame N is displayed, plus the reserved buffer time. The TE signal is then switched from low to high at (t1 + 5.4ms).

[0107] Furthermore, after the processor detects that the TE signal switches from a low level to a high level at (t1+5.4ms), the processor sends the first internal VSync signal of the video mode at (t1+5.4ms). The display switches to video mode, and based on the first internal VSync signal of the video description sent at (t1+5.4ms), the processor prepares to send the first image frame of the video mode, i.e., image frame N+1. Furthermore, after switching to video mode, the second internal VSync signal and the second external VSync signal of the video mode are sent at (2t1+5.4ms), and the display displays image frame N+2.

[0108] based on Figure 9 As shown in the mode switching timing diagram 03, before the display switches to the display mode, each refresh cycle in the command mode is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. That is, in command mode, each EM signal has a consistent period of 2.7ms, a low level in each EM signal indicates on-state, and the EM duty cycle (EM duty) of each EM signal is the same. On the other hand, after the display switches to video mode, the first refresh cycle (t1+5.4ms, 2*t1+5.4ms) of the display is 8.3ms, and within this refresh cycle (t1+5.4ms, 2*t1+5.4ms), each EM signal has a consistent period of 2.7ms, with the same EM duty cycle (EM duty) of each EM signal. Therefore, the EM duty of the last EM signal in command mode is the same as the EM duty of the first EM signal in video mode. This means that the display's pixel illumination duration is the same before and after the switch, resulting in the same display brightness. This means that the display will not experience flickering.

[0109] pass Figures 7 to 9 It can be seen from the display methods corresponding to the mode switching timing diagrams shown that in some embodiments, after receiving a mode switching command in command mode, instant switching from command mode to video mode can be achieved, that is, it has been switched to video mode in the next refresh cycle after the current refresh ends, and the response speed to the mode switching command is fast and the mode switching is smooth.

[0110] In addition, based on Figures 7 to 9 It can be seen from the display methods corresponding to the mode switching timing diagrams shown that before and after the switch from command mode to video mode, the EM duty of the last EM signal in the command mode and the EM duty of the first EM signal in the video mode are also the same. That is, before and after the switch, the pixel lighting duration of the display is the same, and the corresponding display brightness is the same, that is, the display does not flicker.

[0111] In some embodiments of the present application, in actual applications, due to the performance limitations of software or hardware, when switching from command mode to video mode, usually after the last refresh cycle of the command mode ends, the image frame of the last refresh cycle of the command mode can be repeatedly displayed once before switching to video mode. For example, if an error is detected during the switching process, repeating the display of one image frame can provide additional time to correct the timing to ensure the stability and consistency of the switching process. Figures 10 and 11 The timing diagrams shown illustrate the corresponding scenarios and processes respectively.

[0112] As an example, Figure 10 FIG04 shows a timing diagram of switching from command mode to video mode.

[0113] For example, Figure 10 A timing diagram 04 showing a switch from command mode to example mode.

[0114] like Figure 10 As shown in the timing diagram 04, in command mode, based on the external VSync signal at time t0, the refresh cycle of the command mode starts at time t0 and ends at time t1, totaling 8.3ms, and the display screen begins to display the image frame N output by the processor. When the display screen has finished displaying image frame N, based on the display screen receiving the mode switching command, the display screen is ready to send a TE signal to indicate to the processor that image frame N has been displayed and is waiting to switch to video mode. Before this, in order to ensure the stability and continuity of the switching process, a frame of image frame can be repeatedly displayed. The refresh cycle corresponding to the repeatedly displayed image frame N+1 is (t1, t2) of 8.3ms. In addition, unlike the conventional method of switching the TE signal from a low level to a high level at time t01 when the image frame N is displayed in the refresh cycle (t0, t1) of the command mode, the present application controls the TE signal to switch from a low level to a high level at time t1 when the refresh cycle corresponding to the repeatedly displayed image frame N+1 is (t1, t2).

[0115] Based on this, after the repeated display of image frame N+1 in the refresh cycle (t1, t2) is completed, the time when the first internal VSync signal of the video mode, determined based on the refresh rate, is sent is time t2, which is also the time when the TE signal switches from a low level to a high level. After the processor detects that the TE signal switches from a low level to a high level at time t2, the processor sends the first internal VSync signal of the video mode at time t2. The display switches to video mode, and the processor prepares to send the first image frame of the video mode, i.e., image frame N+2, based on the first internal VSync signal.

[0116] based on Figure 10As shown in the mode switching timing diagram 04, the refresh period (t0, t1) of the display's command mode before switching to the display mode and the repeated new period (t1, t2) are both 8.3ms. Furthermore, the period of each EM signal in the refresh period (t0, t1) and the repeated new period (t1, t2) are identical at 2.7ms. A low level in each EM signal indicates illumination, and the EM duty cycle (EM duty) of each EM signal is the same. EM duty refers to the duration of the EM signal's illumination within the refresh period, i.e., the duration of pixel illumination. Furthermore, the first refresh period (t2, t3) of the display's video mode after switching to the display mode is 8.3ms, and the period of each of the three EM signals in this refresh period (t2, t3) is the same at 2.7ms. The EM duty cycle (EM duty) of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode and the first EM signal in the video mode are also identical. That is, before and after the display mode is switched, the pixel lighting time of the display screen is the same, and the corresponding display brightness is the same, that is, the display screen will not flicker.

[0117] In some embodiments of the present application, when switching from command mode to video mode, a buffer time may be reserved between adjacent refresh cycles in command mode. Furthermore, after the last refresh cycle in command mode, the image frame from the last refresh cycle in command mode may be repeatedly displayed before switching back to video mode. Repeating the display of one image frame provides additional time to correct the timing, thereby ensuring stability and consistency during the switching process.

[0118] As another example, Figure 11 Another timing diagram 05 for switching from command mode to video mode is shown.

[0119] like Figure 11As shown in timing diagram 05, in command mode, based on the external VSync signal at time t0, the command mode refresh cycle, which lasts for 8.3ms, runs from time t0 to time t1. The display begins displaying image frame N output by the processor. When the display finishes displaying image frame N and is preparing to display image frame N+1 in command mode, it reserves a buffer time. For example, based on an 8.3ms refresh cycle, a 2.7ms buffer is reserved. This buffer time corresponds to the interval (t1, t1+2.7ms). After the buffer time expires, the external VSync signal for command mode is issued at time (t1+2.7ms) to enable the display to display image frame N+1. After the display finishes displaying image frame N+1, the refresh cycle corresponding to image frame N+1 is (t1+2.7ms, 2*t1+2.7ms). Based on the display receiving the mode switch command within the (t1+2.7ms, 2*t1+2.7ms) refresh cycle, the display prepares to send a TE signal to indicate to the processor that image frame N+1 has been displayed. Before this, in order to ensure the stability and continuity of the switching process, a frame of image can be repeatedly displayed. The refresh period corresponding to the repeatedly displayed image frame N+2 is (2*t1+2.7ms, 3*t1+2.7ms) which is 8.3ms. In addition, unlike the conventional refresh period (t1+2.7ms, 2*t1+2.7ms) in the command mode, the TE signal is switched from a low level to a high level at the moment t11 when the display of image frame N+1 is completed. In this application, the refresh period corresponding to the repeatedly displayed image frame N+2 is (2*t1+2.7ms, 3*t1+2.7ms), and the TE signal is controlled to switch from a low level to a high level at the moment (2*t1+2.7ms).

[0120] Based on this, when the image frame N+2 repeatedly displayed in the refresh cycle (2*t1+2.7ms, 3*t1+2.7ms) is completed, the time when the first internal VSync signal of the video mode determined based on the refresh rate is sent is (3*t1+2.7ms), which is also the time when the TE signal switches from a low level to a high level. After the processor detects that the TE signal switches from a low level to a high level at (3*t1+2.7ms), the processor sends the first internal VSync signal of the video mode at (3*t1+2.7ms), and the display screen switches to video mode. The processor prepares to send the first image frame of the video mode based on the first internal VSync signal, that is, image frame N+3.

[0121] based on Figure 11As shown in the mode switching timing diagram 05, on the one hand, each refresh cycle of the display screen in the command mode before switching the display mode is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. In addition, the period of each EM signal in the refresh cycle (t0, t1), the buffer time interval (t1, t1+2.7), the refresh cycle (t1+2.7, 2*t1+2.7) and the refresh cycle corresponding to the repeated display image frame N+2 (2*t1+2.7, 3*t1+2.7) in the command mode is the same, which is 2.7ms. The low level of each EM signal indicates that the display is on, and the EM duty cycle (EM duty) of each EM signal is the same. On the other hand, the first refresh period (3*t1+2.7, 4*t1+2.7) of the display in the video mode after switching is 8.3ms. Each EM signal within this refresh period (3*t1+2.7, 4*t1+2.7) has the same period of 2.7ms, and the EM duty cycle (EM duty) of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode is also the same as the EM duty of the first EM signal in the video mode. This means that the display's pixel illumination duration is the same before and after the switch, and the corresponding display brightness is the same, meaning the display will not flicker.

[0122] In some embodiments of the present application, when switching from command mode to video mode, different buffer times can be reserved between adjacent refresh cycles in command mode, and the mode switching command in command mode can be issued within the buffer time reserved in the last refresh cycle of command mode. In addition, after the last refresh cycle of command mode ends, the image frame of the last refresh cycle of command mode can be repeatedly displayed before switching to video mode. Repeating the display of one image frame can provide additional time to correct the timing, thereby ensuring the stability and consistency of the switching process.

[0123] As another example, Figure 12 FIG06 shows another timing diagram of switching from command mode to video mode.

[0124] like Figure 12As shown in the timing diagram 06, in command mode, based on the external VSync signal at time t0, the refresh cycle of the command mode starts at time t0 and ends at time t1, totaling 8.3ms, and the display starts to display the image frame N output by the processor. When the display has finished displaying image frame N, it is prepared to reserve a certain buffer time. For example, based on the refresh cycle of 8.3ms, a buffer time of (5.4+2.7)ms is reserved, that is, the time interval corresponding to the buffer time is (t1, t1+5.4+2.7ms). During the buffer time interval (t1, t1+5.4ms), the display detects the mode switching command and is ready to send a TE signal to indicate to the processor that the image frame N has been displayed. Prior to this, in order to ensure the stability and consistency of the switching process, an image frame can be repeatedly displayed. The refresh cycle corresponding to the repeatedly displayed image frame N+1 is (t1+5.4+2.7ms, In addition, different from the conventional refresh cycle (t1, t1+5.4ms) in the command mode, the TE signal is switched from a low level to a high level at the moment t12 when the image frame N+1 is displayed based on the completion of the display of the image frame N and the end of the buffering time in the command mode, the present application first calculates the moment when the next external VSync signal should be sent after the display of the image frame N+1 is completed based on the refresh rate plus the moment after the buffering time, that is, the moment (2*t1+5.4+2.7ms), and controls the TE signal to switch from a low level to a high level at the moment (2*t1+5.4+2.7ms).

[0125] Further, after the processor detects that the TE signal switches from a low level to a high level at (2*t1+5.4+2.7ms), the processor sends the first internal VSync signal of the video mode at (2*t1+5.4+2.7ms), and the display switches to the video mode. The processor prepares to send the first image frame of the video mode, that is, image frame N+2, based on the first internal VSync signal of the video description sent at (2*t1+5.4+2.7ms).

[0126] based on Figure 12As shown in the mode switching timing diagram 06 , the display's refresh cycle in command mode before switching display modes is 8.3ms, and the reserved buffer time is a multiple of the refresh cycle. Furthermore, the period of each EM signal in the refresh cycle (t0, t1), the buffer time interval (t1, t1+5.4+2.7), and the refresh cycle corresponding to the repeated display of image frame N+1 (t1+5.4+2.7, 2*t1+5.4+2.7) in command mode is the same, 2.7ms. A low level in each EM signal indicates on-state, and the EM duty cycle (EM duty) of each EM signal is the same. Therefore, the EM duty of the last EM signal in the command mode is also the same as the EM duty of the first EM signal in video mode. This means that the display's pixel illumination duration is the same before and after the switch, and the corresponding display brightness is the same, meaning the display does not experience flickering.

[0127] pass Figures 10 to 12 As shown in the display method corresponding to each mode switching timing diagram, in some embodiments, after receiving a mode switching command in command mode, the image frame of the last refresh cycle of the command mode can be repeatedly displayed after the last refresh cycle of the command mode ends, and then the video mode is switched. Repeating the display of one image frame can provide additional time to correct the timing to ensure the stability and consistency of the switching process. In addition, based on Figures 10 to 12 It can be seen from the display methods corresponding to the mode switching timing diagrams shown that before and after the switch from command mode to video mode, the EM duty of the last EM signal in the command mode and the EM duty of the first EM signal in the video mode are also the same. That is, before and after the switch, the pixel lighting duration of the display is the same, and the corresponding display brightness is the same, that is, the display does not flicker.

[0128] It can be understood that, based on the display method provided in the present application, when the display screen switches from video mode to command mode, the screen flickering problem usually does not occur.

[0129] As an example, Figure 13 FIG07 shows a timing diagram of a display screen switching from a video mode to a command mode.

[0130] like Figure 13As shown in timing diagram 07, in video mode, based on the internal and external VSync signals sent at time t0, the first refresh cycle of the video mode starts at time t0 and ends at time t1, a total of 8.3 ms. The display begins to display image frame N output by the processor. After the display has finished displaying image frame N, based on the internal and external VSync signals sent at time t1, the second refresh cycle of the video mode starts at time t1 and ends at time t2, a total of 8.3 ms. The display begins to display image frame N+1 output by the processor. After the display has finished displaying image frame N+1, based on the internal and external VSync signals sent at time t2, the third refresh cycle of the video mode starts at time t2 and ends at time t3, a total of 8.3 ms. The processor can then output image frame N+2 to the GRAM, and the display displays processor image frame N+2. Based on receiving a mode switch command during a refresh period (t1, t2) in video mode, the display screen can switch the TE signal from a low level to a high level at time t21, after the last image frame N+2 of the video mode is displayed. In addition, to ensure the stability and consistency of the switching process, the display screen can repeatedly display image frame N+2. The refresh period corresponding to the repeated image frame N+2 is 8.3ms (t3, t4). The TE signal in the refresh period (t3, t4) corresponding to the repeated image frame N+2 in video mode also switches from a low level to a high level after the repeated image frame N+2 is displayed. After the display screen finishes displaying the repeated image frame N+2, the refresh rate determines that the first external VSync signal of the command mode is sent at time t4. After the processor detects that the TE signal is high at time t4, the processor sends the first external VSync signal of the command mode at time t4. The display screen switches to command mode. Based on the first external VSync signal corresponding to the command mode at time t4, the processor retrieves image N+3 from the GRAM and displays image N+3.

[0131] based on Figure 13As shown in the mode switching timing diagram 07, when switching from video mode to command mode, the display screen's refresh period in video mode before switching display mode is 8.3ms. Furthermore, the periods of each EM signal in the video mode refresh periods (t0, t1), (t1, t2), (t2, t3), and (t3, t4) corresponding to the repeated display of image frame N+2 are all identical, 2.7ms. A low level in each EM signal indicates an on state, and the EM duty cycle (EM duty) of each EM signal is identical. Therefore, the EM duty of the last EM signal in command mode is identical to the EM duty of the first EM signal in video mode. This means that the display screen's pixel illumination duration is identical before and after switching from video mode to command mode, resulting in the same display brightness. This means that the display screen will not flicker.

[0132] Figure 14 According to an embodiment of the present application, a structural diagram of a terminal device 100 is shown.

[0133] In the embodiment of the present application, the terminal device 100 may be the above Figure 1 The various electronic devices and the like in the illustrated scenario are not limited here.

[0134] like Figure 14 As shown, the terminal device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna A, an antenna B, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, a communication device 196, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc. Among them:

[0135] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0136] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0137] The processor 110 may also include a memory for storing instructions and data.

[0138] The USB interface 130 is an interface that complies with USB standards and may be a Mini USB interface, a Micro USB interface, a USB Type-C interface, or the like. The USB interface 130 can be used to connect a charger to charge the terminal device 100, or to transmit data between the terminal device 100 and peripheral devices. It can also be used to connect headphones to play audio. This interface can also be used to connect other electronic devices, such as AR devices.

[0139] The charging management module 140 is configured to receive charging input from a charger. While charging the battery 142 , the charging management module 140 can also provide power to the electronic device through the power management module 141 .

[0140] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to provide power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160.

[0141] The wireless communication function of the terminal device 100 can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor. Antenna 1 and antenna 2 can be used to send and receive electromagnetic wave signals, that is, wireless carrier information.

[0142] The mobile communication module 150 can provide wireless communication solutions, including 2G / 3G / 4G / 5G / 6G, for the terminal device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low-noise amplifier (LNA), and the like. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module 150 can also amplify the signals modulated by the modem processor and convert them into electromagnetic waves for radiation via the antenna 1.

[0143] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) and ultra wide band (UWB) for application on the mobile phone 10. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 can receive electromagnetic waves from the antenna 2, and filter, amplify and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The wireless communication module 160 can also amplify the signal modulated by the modulation and demodulation processor and convert it into electromagnetic waves for radiation through the antenna 2.

[0144] The terminal device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which is connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or change display information. In an embodiment of the present application, the GPU can send an internal VSync signal to indicate that the image frame to be displayed has been rendered and is ready for display. In addition, corresponding to the command mode, the GPU can send the rendered image frame to be displayed to the GRAM for storage. Corresponding to the video mode, the GPU can send the rendered image frame directly to the display screen for display, which is not limited here.

[0145] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode or an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), Mini-LED, micro-LED, Micro-OLED, a quantum dot light-emitting diode (QLED), etc. It can be understood that the display method provided in the embodiment of the present application can be applied to the display screen 194. In the embodiment of the present application,

[0146] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard format such as RGB, YUV, etc.

[0147] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal device 100. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0148] The internal memory 121 can be used to store computer executable program code, which includes instructions, such as the aforementioned memory 103. The internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system, at least one application required for a function, etc. The data storage area may store data created during the use of the terminal device 100, such as a control identifier of a security control, a screenshot redrawing policy identifier corresponding to the security control, and patterns, images, text, etc. corresponding to the screenshot redrawing policy. In addition, the internal memory 121 may include a graphics random access memory (GRAM), a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications of the terminal device 100 by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor 110. In some embodiments of the present application, the GRAM may store image frames to be displayed after GPU rendering.

[0149] The terminal device 100 can implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0150] The acceleration sensor 180E can detect the magnitude of the acceleration of the terminal device 100 in various directions (generally three axes). When the terminal device 100 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the posture of the terminal device 100.

[0151] The touch sensor 180K, also known as a "touch device," can be mounted on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also known as a "touch screen." The touch sensor 180K detects touch operations applied to or near the touch sensor. The touch sensor can transmit the detected touch operations to the application processor to determine the type of touch event. Visual output related to the touch operations can be provided via the display screen 194.

[0152] Motor 191 can generate vibration prompts.

[0153] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power level changes, messages, missed calls, notifications, etc.

[0154] The SIM card interface 195 is used to connect a SIM card.

[0155] It should be understood that the structure of the terminal device 100 shown in the embodiment of the present application does not constitute a specific limitation on the terminal device 100. In other embodiments of the present application, the terminal device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0156] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0157] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0158] Program code can be implemented with a high-level programming language or an object-oriented programming language to communicate with the processing system. Where necessary, program code can also be implemented in assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0159] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to floppy disks, optical disks, optical discs, compact disc read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media includes any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0160] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0161] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0162] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a" do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0163] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A display method, characterized in that: Applied to an electronic device, the electronic device includes a display screen, and the method includes: A mode switching command is detected in the first refresh cycle of the command mode, and the first TE signal is controlled to switch from a low level state to a high level state at a first moment, wherein, The first TE signal is used to indicate that the image frame in the first refresh period has completed display, the first moment is the end moment of the first refresh period, and the first moment is the start moment of the second refresh period of the corresponding video mode, and the first moment is related to the screen refresh rate of the display screen; Based on the first TE signal, a vertical synchronization signal is sent at the first moment, the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode in the second refresh period corresponding to the video mode.

2. The method according to claim 1, characterized in that Before displaying the image frame corresponding to the video mode in the second refresh period corresponding to the video mode, the method further includes: The first TE signal is switched from a high level state to a low level state.

3. The method according to claim 1, characterized in that The method further comprises: A first buffer period of the command mode is detected to start at the first moment and end at a second moment, the first buffer period is less than or equal to the first refresh period, and the first refresh period is N times the first buffer period, where N∈ is a positive integer; detecting that a second refresh cycle of the command mode starts at the second moment and ends at a third moment, corresponding to detecting a mode switching command within the second refresh cycle of the command mode, controlling the second TE signal to switch from a low level state to a high level state at the third moment; The second TE signal is used to indicate that the image frame in the second refresh period of the command mode has completed display, the third moment is the end moment of the second refresh period of the command mode, and the third moment is the start moment of the third refresh period corresponding to the video mode; Based on the second TE signal, a vertical synchronization signal is sent at the third moment, the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode in the third refresh period corresponding to the video mode.

4. The method according to claim 3, characterized in that Before displaying the image frame corresponding to the video mode in the third refresh period corresponding to the video mode, the method further includes: The second TE signal is switched from a high level state to a low level state.

5. The method according to claim 3, characterized in that When a first buffer period corresponding to detection of the command mode starts at the first moment and ends at a second moment, the method further includes: A second buffer period of the command mode is detected to start at the first moment and end at a fourth moment, the second buffer period is less than or equal to the first refresh period, and the first refresh period is N times the second buffer period, where N∈ is a positive integer; detecting a mode switching command within the second buffer period; In response to detecting the end of the second buffering period at the fourth moment, controlling the third TE signal to switch from a low level state to a high level state at the fourth moment, wherein the fourth moment is the end moment of the second buffering period of the command mode, and the fourth moment is the start moment of the second refresh period corresponding to the video mode; Based on the third TE signal, a vertical synchronization signal is sent at the fourth moment, and the display screen switches from the command mode to the video mode, and displays the image frame corresponding to the video mode in the second refresh period corresponding to the video mode.

6. The method according to claim 5, characterized in that Before displaying the image frame corresponding to the video mode in the second refresh period corresponding to the video mode, the method further includes: The third TE signal is switched from a high level state to a low level state.

7. The method according to claim 1, characterized in that The content displayed in the command mode includes a static image or a dynamic image, and the content displayed in the video mode includes a video.

8. The method according to claim 1, characterized in that The method further comprises: A mode switching command is detected in a first refresh cycle of the command mode, and the first TE signal is controlled to switch from a low level state to a high level state at a first moment; detecting that the second refresh cycle of the command mode starts at the first moment and ends at a fifth moment, and controlling the first TE signal to switch from a low level state to a high level state at the fifth moment; Based on the first TE signal, the display screen is controlled to switch from the command mode to the video mode at the fifth moment.

9. An electronic device, characterized in that: include: A processor and a memory, the memory including physical memory and external memory, for storing instructions executed by one or more processors of the electronic device; And, a processor, configured to execute the instructions so that the electronic device implements the display method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by an electronic device, the electronic device implements the display method according to any one of claims 1 to 8.

11. A computer program product, characterized in that The computer program comprises a computer program / instruction. When the computer program product is run on an electronic device, the electronic device is enabled to implement the display method according to any one of claims 1 to 8.

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