Display driving circuit, display module and display device

Abstract

The invention provides a display driving circuit, a display module and a display device, which can reduce the power consumption of a random access memory-free integrated circuit in a constant display mode and completely display a picture corresponding to picture data. The circuit comprises: an interface sub-circuit; a compensation sub-circuit; the reduction sub-circuit is configured to process the first image data from the interface sub-circuit to obtain second image data, and the data size of the second image data is smaller than that of the first image data; the input end of the first gating switch is connected with the output end of the interface sub-circuit, the output end of the first gating switch is connected with the compensation sub-circuit and the reduction sub-circuit, and the first gating switch is configured to be communicated with the interface sub-circuit and the reduction sub-circuit in a constant display mode; the input end of the second gating switch is connected with the first memory, the output end of the second gating switch is connected with the compensation sub-circuit and the enhancement sub-circuit, and the second gating switch is configured to be communicated with the first memory and the image quality enhancement sub-circuit in a constant display mode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit, a display module, and a display device. Background Art

[0002] A display driver integrated circuit (DDIC) typically includes two types of random access memory (RAM): display RAM and demura RAM. Display RAM is used to temporarily store image data transmitted by a processor (e.g., an application processor (AP) in a user equipment (UE)). Demura RAM is used to temporarily store demura data.

[0003] With the development of high-speed interface technologies (such as the mobile industry processor interface (MIPI)) and low-temperature polycrystalline oxide (LTPO) technology with low-frequency characteristics, DDIC can directly control the display panel display image without relying on display RAM. This has led to the proposal of RAMless integrated circuit (RAMless IC), which removes the display RAM from the DDIC.

[0004] However, because the Ramless IC removes the display RAM, it doesn't temporarily store image data. Consequently, in always-on display (AOD) mode (also known as all-day display mode), the processor continuously sends image data to the Ramless IC, resulting in higher power consumption for the entire device. Therefore, in AOD mode, how to fully display the image corresponding to the screen data while reducing power consumption is a pressing issue. Summary of the Invention

[0005] Embodiments of the present application provide a display driver circuit, display module, and display device that can reduce the power consumption of an integrated circuit without random access memory (RAM) in an always on display (AOD) mode and fully display the image corresponding to the image data.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a display driving circuit is provided, comprising: an interface subcircuit configured to receive first image data; a compensation subcircuit configured to obtain compensation data from a first memory and perform compensation processing based on the compensation data, wherein an output end of the compensation subcircuit is connected to a picture quality enhancement subcircuit; a reduction subcircuit configured to process the first image data to obtain second image data, wherein the data amount of the second image data is smaller than the data amount of the first image data, and the output end of the reduction subcircuit is connected to the first memory; a first selection switch, wherein an input end is connected to the output end of the interface subcircuit, and output ends are respectively connected to the compensation subcircuit and the reduction subcircuit, and is configured to: when a first display mode is converted to a second display mode, convert the connection between the interface subcircuit and the compensation subcircuit to that between the interface subcircuit and the reduction subcircuit; a second selection switch, wherein an input end is connected to the first memory, and an output end is respectively connected to the compensation subcircuit and the enhancement subcircuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the first memory and the compensation subcircuit to that between the first memory and the picture quality enhancement subcircuit.

[0008] It can be understood that the second display mode can be understood as the AOD mode after the screen is turned off, and the first display mode can be understood as the regular display mode before the screen is turned off, that is, in the second display mode, only the pixels in a part of the display panel are activated, and / or the refresh rate is reduced to the minimum refresh rate supported by the display panel. In addition, the reduction sub-circuit processes the first image data, which may refer to compression processing to reduce the data volume of the first image data. The data volume of the second image data obtained after processing is smaller than the data volume of the first image data, but the picture corresponding to the first image data can be fully displayed. For example, the picture content corresponding to the second image data is the same as the picture content corresponding to the first image data, and the clarity of the picture corresponding to the second image data is lower than that of the picture corresponding to the first image data.

[0009] That is to say, in the AOD mode, by transmitting the first image data to be displayed to the reduction sub-circuit for processing, second image data with a smaller data volume is obtained, and the second image data is temporarily stored in the first memory used to load compensation data, so that the display driving circuit can temporarily store the image data with a smaller data volume corresponding to the AOD mode, so that the processor does not need to continuously send image data for each frame, avoiding the interface sub-circuit from being frequently woken up to reduce power consumption, and also avoiding incomplete images displayed in the AOD mode.

[0010] In one possible implementation, the interface subcircuit is further connected to the control terminal of the first selection switch and the control terminal of the second selection switch, respectively. The interface subcircuit is further configured to: receive a first control signal indicating entry into the second display mode; and send the first control signal to the control terminal of the first selection switch and the control terminal of the second selection switch, respectively. In other words, the interface subcircuit can also receive a control signal indicating entry into the second display mode and send the control signal to the control terminals of the first selection switch and the second selection switch, respectively, thereby connecting the interface subcircuit with the reduction subcircuit and connecting the first memory with the image quality enhancement subcircuit. This allows for minimal modification to the display driver circuit and facilitates deployment and implementation.

[0011] In one possible implementation, the control end of the first selection switch and the control end of the second selection switch are respectively connected to a display mode switch. The display mode switch is configured to transmit a first control signal in response to a user's operation instruction, wherein the first control signal indicates entry into the second display mode. In other words, by transmitting the first control signal via the display mode switch, it is unnecessary to transmit the first control signal to the interface subcircuit via the processor side. This allows the interface subcircuit to transmit the first control signal via the communication bus, thereby reducing the occupancy of the communication bus and the risk of potential data transmission conflicts.

[0012] In one possible implementation, the first control signal is synchronized with a vertical synchronization signal, where the vertical synchronization signal indicates the start time for the display driver circuit to drive the display of an image frame. In other words, by synchronizing the first control signal with the vertical synchronization signal, the first and second selection switches can switch data flow channels in a timely manner, allowing the first memory to promptly store the second image data from the reduction sub-circuit, ensuring that the control parameters in the second display mode match the image data in the second display mode, thereby avoiding undesirable phenomena such as screen flickering. Similarly, the second control signal for indicating exit from the second display mode is synchronized with the vertical signal, allowing the first and second selection switches to promptly switch data flow channels, allowing the compensation sub-circuit to retrieve compensation data from the first memory and process the image data in the first display mode from the interface sub-circuit.

[0013] In one possible implementation, the image quality enhancement subcircuit is configured to access the first memory to obtain the second image data. That is, considering that the first memory is a passive device, the image quality enhancement subcircuit actively accesses the first memory and directly obtains the second image data from the first memory. This avoids the image quality enhancement subcircuit obtaining the second image data through other intermediate components, thereby streamlining components, shortening the image data transmission path, and thereby reducing image data transmission delay.

[0014] In one possible implementation, the image quality enhancement subcircuit is configured to access the first memory based on a vertical synchronization signal, where the vertical synchronization signal indicates the start time of the display driver circuit driving the display of an image frame. In other words, considering that the start time of an image frame is triggered by the vertical synchronization signal, and the image data in the second display mode follows this mechanism, the image quality enhancement subcircuit can trigger access to the first memory in response to the vertical synchronization signal, thereby reducing the frequency with which the image quality enhancement subcircuit accesses the first memory, thereby reducing resource overhead. It is understandable that the period of the image quality enhancement subcircuit accessing the first memory can be less than or equal to the period of the vertical synchronization signal, so that the image quality enhancement subcircuit can access the first memory once within an image frame.

[0015] In one possible implementation, the display driver circuit further includes an image data decoder having an input connected to the output of the interface subcircuit and an output connected to the input of the first selection switch, and configured to decode the first image data. Accordingly, the reduction subcircuit is configured to process the decoded first image data to obtain second image data. In other words, by providing the image data decoder between the output of the interface subcircuit and the output of the first selection switch, the first image data from the interface subcircuit can be decoded, allowing the reduction subcircuit to perform only compression processing without decoding the first image data, thereby reducing the processing complexity of the reduction subcircuit.

[0016] In one possible implementation, the display driver circuit further includes a third gating switch, wherein the input of the third gating switch is connected to the output of the second memory and the reduction sub-circuit, respectively, and the output of the third gating switch is connected to the first memory. The third gating switch is configured to switch the connection between the first memory and the second memory to the connection between the first memory and the reduction sub-circuit when the first display mode is switched to the second display mode. In other words, considering that the first memory is a passive device, the third gating switch is provided between the first memory and the reduction sub-circuit to enable the first memory to promptly load the compensation data from the second memory in the first display mode and to promptly load the second image data from the reduction sub-circuit in the second display mode.

[0017] In one possible implementation, the image quality enhancement subcircuit is a first image quality enhancement subcircuit, and the display driver circuit further includes: a second image quality enhancement subcircuit and a fourth selection switch; wherein: the second image quality enhancement subcircuit has an input end connected to the output end of the first selection switch and the output end of the second selection switch, respectively, and an output end connected to the input end of the fourth selection switch; the fourth selection switch has an output end connected to the input end of the compensation subcircuit and the input end of the first enhancement subcircuit, respectively, and is configured to: when the first display mode is switched to the second display mode, switch the connection between the second image quality enhancement subcircuit and the compensation subcircuit to switch the connection between the second image quality enhancement subcircuit and the first image quality enhancement subcircuit. In other words, by adding the second image quality enhancement subcircuit and the fourth selection switch to the display driver circuit, the image quality of the displayed image data can be improved without changing the data processing flow in the first display mode and the second display mode.

[0018] In a second aspect, a display module is provided, comprising: a display panel, and a display driving circuit as described in the first aspect and any one of its aspects, wherein the display driving circuit is connected to the display panel and is used to drive the display panel to display an image.

[0019] In a third aspect, a display device is provided, comprising: a processor and the display module according to the second aspect, wherein the processor is connected to the display module and is configured to transmit image data to be displayed to the display module.

[0020] It can be understood that the beneficial effects of the second and third aspects can be found in the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 1 is a schematic structural diagram of a RAMless integrated circuit (Ramless IC) provided in an embodiment of the present application;

[0023] Figure 2 This is a timing diagram of an application processor (AP) sending image data to a Rameless IC provided by an embodiment of the present application;

[0024] Figure 3-Figure 5 、 Figures 8-101 is a schematic structural diagram of a display driving circuit provided in an embodiment of the present application;

[0025] Figure 6 1 is a timing diagram of a vertical synchronization signal and a triggering mechanism for the first memory 303 to temporarily store image data in the second display mode, provided by an embodiment of the present application;

[0026] Figure 7 1 is a timing diagram of synchronization between a vertical synchronization signal and a control signal of a second display mode provided by an embodiment of the present application;

[0027] Figure 11 1 is a schematic structural diagram of a display module provided in an embodiment of the present application;

[0028] Figure 12 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] To make the above-mentioned purposes, features, and advantages of the embodiments of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described in the specific embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] In order to facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0031] 1. In the embodiments of the present application, descriptions such as "when...", "in the case of...", "if...", and "if" all mean that the device or apparatus will perform corresponding processing under certain objective circumstances. They do not limit the time, nor do they require the device or apparatus to perform judgment actions when implemented, nor do they mean the existence of other limitations.

[0032] 2. In the description of the embodiments of the present application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship. For example, A / B can represent A or B. "And / or" in the embodiments of the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, in the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0033] 3. In the embodiments of the present application, words indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", or "outside" are used to illustrate the positional relationship of the constituent elements in the drawings. This is only for the convenience of description and does not indicate or imply that the referred elements or structures must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the solutions disclosed in the embodiments of the present application.

[0034] In addition, the positional relationship of the constituent elements in the drawings can be appropriately changed according to the direction of describing each constituent element, and is not limited to the positional relationship of the constituent elements in the above-described drawings. It is explained uniformly here and will not be repeated below.

[0035] 4. In the embodiments of this application, the terms "about," "approximately," "substantially," or "approximately" include the stated value and an average value that is within an acceptable range of deviation from the specified value. The acceptable range of deviation may be determined by the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0036] 5. In the embodiments of the present application, unless otherwise expressly stated, the terms "installed", "adjacent", "connected", or "connected", etc., should be understood in a broad sense. For example, the term "connection" includes: mechanical connection, or electrical connection, etc. In physical form, the above-mentioned mechanical connection, or electrical connection, etc. may refer to direct connection, or indirect connection through an intermediate piece, or internal communication between two elements, etc. In addition, the above-mentioned forms of connection include: fixed connection, detachable connection, or integral connection, etc. In other words, in combination with the relevant solutions provided in the embodiments of the present application, the specific meanings corresponding to the above-mentioned terms in the embodiments of the present application can be specifically understood.

[0037] 6. In the embodiments of the present application, “electrical connection” includes situations where constituent elements are connected together through elements having some electrical function. In addition, there is no special restriction on “elements having some electrical function” as long as electrical signals or currents can be transmitted between connected constituent elements. For example, elements having some electrical function may be conductive materials or electrical devices having various functions. For example, conductive materials include electrodes, solder joints, or wiring, etc. For another example, electrical devices having various functions include resistors, capacitors, inductors, or semiconductor elements (such as diodes, transistors, etc.), etc., which are not limited.

[0038] To facilitate understanding of the technical solutions provided by the embodiments of this application, the relevant technical terms and concepts involved in the embodiments of the application are first introduced.

[0039] First, display driver integrated circuit (DDIC)

[0040] The DDCI mainly receives image data from the processor side and controls the display panel to display the screen corresponding to the image data. For example, the processor side may refer to the processor in the display device that is responsible for processing the image data to be displayed.

[0041] A display device can be referred to as a user equipment (UE). A display device can be understood as a mobile device or mobile device that has a display function. For example, a display device can be a mobile phone, a cellular phone, a smart phone, a tablet computer, or an in-vehicle terminal, etc., and this embodiment of the present application does not specifically limit this.

[0042] The processor may be referred to as a controller or a graphics processor center in the above-mentioned display device. For example, the processor may be an application processor (AP) in a mobile phone. For another example, the processor may be a graphics processing unit (GPU) in a tablet computer. For another example, the processor may be a cockpit domain controller (CDC) in a vehicle. It will be understood that the above processors are merely examples and are not specifically limited in the embodiments of the present application.

[0043] The display panel may be a liquid crystal display (LCD) panel, and the backlight source of the display panel may be a light emitting diode (LED) or other light sources, which are not limited.

[0044] In addition, the display panel may also be an organic light-emitting diode (OLED) panel, or a panel composed of micron-sized inorganic LED units (i.e., micron-sized LED (micro LED) display technology), which is not specifically limited in the embodiments of the present application.

[0045] It should be understood that, depending on the refresh rate of the displayed image, the above-mentioned display devices generally have two display modes: dynamic display (also known as real-time display) and static display or low-frequency update display. Dynamic display is mainly suitable for displaying images such as videos or game images. In the case of dynamic display, the display device processor continuously sends each frame of image data to the DDIC, which then performs image quality enhancement and compensation processing on each frame.

[0046] Static or low-frequency refresh displays differ from the aforementioned dynamic displays in that the display device's processor does not need to continuously send each frame of image data to the DDIC. Instead, the display device's processor temporarily stores the image data for static or low-frequency refresh displays in the DDIC, which then refreshes itself based on the refresh rate. This reduces power consumption compared to a processor that continuously sends each frame of image data. Furthermore, the DDIC eliminates the need for image data compensation for static or low-frequency refresh displays, further reducing power consumption.

[0047] As you can understand, DDIC typically includes two types of random access memory (RAM): display RAM and demura RAM (also known as demura RAM). Display RAM can be used to temporarily store image data for static or low-frequency display updates. Demura RAM is used to store demura data for color compensation and / or brightness correction, and is suitable for dynamic displays.

[0048] Furthermore, the storage capacity of the display RAM directly determines the display resolution supported by the DDIC. For example, in pixel data (e.g., red, green, blue, and blue (RGB) data), each color is assigned 256 brightness levels, requiring 8 bits to represent. RGB data consists of three colors, requiring 8 × 3 bits to represent each pixel. Assuming a display resolution of 1280 × 2800 and a compression ratio of 1 / 3, the display RAM storage capacity required is 1280 × 2800 × 8 × 3 × 1 / 3 bits, or 3.59 megabytes (MB).

[0049] It can be understood that the storage capacity of the display RAM is proportional to the size of the display RAM, and the size of the display RAM usually accounts for more than half of the overall size of the DDIC. Therefore, removing the display RAM can reduce the size of the DDIC by half, so that the number of slices on the same wafer can be significantly increased, reducing the production cost of the DDIC.

[0050] In addition, a DDIC without display RAM may also be referred to as a RAMless integrated circuit (Ramless IC), which is described uniformly here and will not be further elaborated below.

[0051] The following combination Figure 1 , introduces the electrical components included in Ramless IC.

[0052] Figure 1 This is a schematic diagram of the structure of a Ramless IC provided in an embodiment of the present application. Figure 1As shown, the Ramless IC includes the following electrical components: a mobile industry processor interface (MIPI) subcircuit, a video electronics standards association (VESA) decoder, an image quality enhancement subcircuit #1, a demura subcircuit, a demura random access memory (RAM), a biphase mark code (BMC) decoder, an image quality enhancement subcircuit #2, and a digital-to-analog converter (DAC) output subcircuit.

[0053] The MIPI subcircuit may also be referred to as a MIPI interface (MIPI I / F). The physical layer properties and related electrical specifications of the communication protocol used by the MIPI interface comply with the MIPI standard protocol. The MIPI subcircuit is used to receive image data sent from the processor side (e.g., AP) in the display device. In addition, the MIPI subcircuit may also receive control information corresponding to the image data, such as brightness, refresh rate, or gamma control commands, etc., without limitation.

[0054] A VESA decoder is used to decode image data transmitted by the MIPI sub-circuit. It should be understood that the processor in the display device can perform VESA encoding on the image data to be displayed to compress the image data, and then decode the image data transmitted by the MIPI sub-circuit through the VESA decoder to facilitate subsequent processing of the image data.

[0055] Image quality enhancement subcircuit #1 is used to enhance the image quality of decoded image data. For example, the image quality enhancement subcircuit can encapsulate (or burn) an image quality enhancement algorithm (or function) licensed by intellectual property (IP), solidifying the algorithm logic in hardware. This significantly improves computational efficiency compared to software-implemented image quality enhancement algorithms. It is understood that the image quality enhancement subcircuit can also be referred to as an IP subcircuit or IP module.

[0056] For example, the image quality enhancement algorithm includes a local dimming algorithm for controlling the backlight brightness in partitions to improve the purity of black displayed by the display panel. For another example, the image quality enhancement algorithm includes an adaptive noise reduction algorithm for dynamically eliminating image noise based on the scene to improve the cleanliness of the display screen in a low-brightness environment. For another example, the image quality enhancement algorithm includes a sharpening algorithm for enhancing the edge details of the image and suppressing noise. It will be understood that the above image quality enhancement algorithms are only examples and are not specifically limited in the embodiments of the present application.

[0057] The demura subcircuit is used to perform color compensation and / or brightness unevenness correction on the image data to eliminate defects in display color and / or brightness. For example, the demura subcircuit compensates (or corrects) the image data processed by the image quality enhancement subcircuit #1 based on the demura data. It will be understood that the demura subcircuit and the image quality enhancement subcircuit #1 use different algorithms or functions, and thus the image quality enhancement subcircuit can also be referred to as other IP subcircuits or other IP modules.

[0058] It should be understood that due to the large amount of demura data (for example, a 2K resolution display panel requires 8 million pixels of compensation data), in order to reduce the size (or area) of the Ramless IC while taking into account the needs of high-speed computing, the demura data is loaded using a two-level memory. The two-level memory loading method includes: first, burning the demura data into a non-volatile memory (such as flash memory), and after the Ramless IC is powered on, according to timing parameters (such as vertical synchronization (V-sync) signal), loading (reloading) part of the demura data stored in the flash memory (i.e., the demura data required for the current frame image) into the demura RAM, and then the demura sub-circuit can obtain the demura data from the demura RAM.

[0059] For example, assuming that the Ramless IC is used to drive an OLED display panel, the storage capacity of the Demura RAM is generally at the level of tens of kilobytes (KB).

[0060] The BMC decoder is used to decode the demura data temporarily stored in the demura RAM. It is understandable that, given the relatively small storage capacity of the demura RAM and the large amount of demura data, the demura data stored in the flash memory is BMC-compressed demura data, and thus the demura RAM temporarily stores BMC-compressed demura data. After the BMC decoder obtains the BMC-compressed demura data from the demura RAM, it performs BMC decoding on the data to obtain the demura data. This allows the demura sub-circuit to obtain the demura data from the BMC decoder.

[0061] Image quality enhancement sub-circuit #2 is used to enhance the image quality of the image data processed by the demura sub-circuit. It is understood that the image quality enhancement algorithm encapsulated in image quality enhancement sub-circuit #2 is different from the image quality enhancement algorithm encapsulated in image quality enhancement sub-circuit #1.

[0062] The DAC output sub-circuit is used to convert the image data from the image quality enhancement sub-circuit #2 into an analog signal, and then output the voltage required to drive the display panel for display.

[0063] Second, always on display (AOD) mode

[0064] With the development of high-speed interface technology and low-frequency low-temperature polycrystalline oxide (LTPO) technology, it is possible to continuously display images on at least part of the display panel even when the display device is in the off state. For example, in AOD mode, the refresh rate of the display panel can be reduced to 1 Hz, that is, once per second (s).

[0065] It can be understood that, in the AOD mode, the display device actually operates in a static display or low-frequency update display mode. In the non-AOD mode (ie, normal display mode), the display device actually operates in a dynamic display mode.

[0066] However, if Figure 1 If the Ramless IC shown is expected to take into account both the above-mentioned AOD mode and the conventional display mode, then when displaying in the AOD mode, the display device will have the problems of high power consumption and incomplete display images.

[0067] The following combination Figure 2 Explain the above problem.

[0068] As described above in "First, Display Driver Integrated Circuit" regarding dynamic display, static display, and Ramless IC, since the Ramless IC does not include display RAM for temporarily storing image data for static display or low-frequency update display, and only retains Demura RAM for temporarily storing Demura data, the image data processing flow of the Ramless IC in AOD mode is similar to that of the Ramless IC in conventional display mode, that is, the AP continuously sends each frame of image data to the Rameless IC, which means that the MIPI sub-circuit in the Ramless IC will be frequently awakened, resulting in high power consumption and difficulty in supporting all-weather AOD mode.

[0069] For example, Figure 2 As shown in the figure, assuming the display screen (i.e., display panel) of the display device supports a minimum refresh rate of 1Hz, and the image data to be displayed does not change within 1 minute (i.e., the image is displayed statically for 1 minute), then the AP will send this image data to the Ramless IC every second during that 1 minute. In other words, the AP will send the same image data to the Ramless IC 60 times within 1 minute, which not only increases power consumption but also results in energy waste.

[0070] In addition, assuming that the Demura RAM in Ramless is used to temporarily store the image data in the AOD mode, this can solve the problem of high power consumption in the AOD mode, but may cause incomplete display images.

[0071] For example, Figure 1 Regarding the storage capacity of demura RAM, for image data with a display resolution of 1280×2800 and a VESA compression ratio of 1 / 3, the compressed data size is 3.59MB. After being decoded by the VESA decoder in the Ramless IC, the data size is 10.77MB. However, the storage capacity of demura RAM is typically tens of KB, which is far smaller than the image data size. As a result, the demura RAM can only store a small portion of the image data, which in turn causes the Ramless IC to drive the display panel to display a small portion of the screen corresponding to the image data.

[0072] Based on this, the embodiments of the present application provide a display driving circuit, a display module, and a display device, which can reduce the power consumption of a Ramless IC in an AOD mode and fully display the image corresponding to the image data.

[0073] In a first aspect, an embodiment of the present application provides a display driving circuit, comprising: an interface sub-circuit configured to receive first image data; a compensation sub-circuit configured to obtain compensation data from a first memory and perform compensation processing based on the compensation data, wherein the output end of the compensation sub-circuit is connected to a picture quality enhancement sub-circuit; a reduction sub-circuit configured to process the first image data to obtain second image data, wherein the data amount of the second image data is smaller than the data amount of the first image data, and the output end of the reduction sub-circuit is connected to the first memory; a first selection switch, wherein the input end is connected to the output end of the interface sub-circuit, and the output end is respectively connected to the compensation sub-circuit and the reduction sub-circuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the interface sub-circuit and the compensation sub-circuit into the connection between the interface sub-circuit and the reduction sub-circuit; a second selection switch, wherein the input end is connected to the first memory, and the output end is respectively connected to the compensation sub-circuit and the enhancement sub-circuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the first memory and the compensation sub-circuit into the connection between the first memory and the picture quality enhancement sub-circuit.

[0074] It can be understood that the number of pixels displayed in the first display mode is greater than the number of pixels displayed in the second display mode, and / or the refresh rate in the first display mode is greater than the refresh rate in the second display mode. In other words, the second display mode can be understood as the AOD mode after the screen is turned off, and the first display mode can be understood as the regular display mode before the screen is turned off, that is, in the second display mode, only pixels in a part of the display panel area are activated, and / or the refresh rate is reduced to the minimum refresh rate supported by the display panel.

[0075] Furthermore, the reduction subcircuit processing the first image data may involve compression to reduce the data size of the first image data. The resulting second image data may be smaller in size than the first image data but still fully display the image corresponding to the first image data. For example, the image content corresponding to the second image data may be similar to the image content corresponding to the first image data, and the clarity of the image corresponding to the second image data may be lower than that of the image corresponding to the first image data.

[0076] It can be understood that compression processing can be understood as: removing redundant information in the first image data (such as the correlation between adjacent elements, or high-frequency details that the human eye is not sensitive to) to reduce the amount of data; or, reducing the resolution of the first image data to reduce the amount of data. Reducing the resolution can refer to: sampling (i.e. extracting one pixel data every N (N is an integer greater than 1) pixels, and discarding the other pixel data), pixel merging (i.e. merging adjacent pixels into new pixels (such as taking the average of a 2×2 pixel area)), or interpolation scaling (i.e. generating new pixel values through an algorithm (such as bilinear interpolation)), which is not specifically limited in the embodiments of the present application.

[0077] That is to say, in the AOD mode, by transmitting the first image data to be displayed to the reduction sub-circuit for processing, second image data with a smaller data volume is obtained, and the second image data is temporarily stored in a first memory (for example, it can be Demura RAM) used to load compensation data, so that the display driving circuit can temporarily store the image data with a smaller data volume corresponding to the AOD mode, so that the processor does not need to continuously send image data for each frame, avoiding the interface sub-circuit from being frequently woken up to reduce power consumption, and also avoiding incomplete images displayed in the AOD mode.

[0078] The solutions in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0079] Figure 3 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 1 .like Figure 3 As shown, the output end of the interface sub-circuit 301 is connected to the first selection switch 306. It can be understood that the interface sub-circuit 301 can refer to Figure 1 The MIPI sub-circuit in the MIPI controller will not be described here.

[0080] In addition, the interface sub-circuit 301 may also be an interface circuit that complies with other communication protocols for display screen data transmission, and the embodiment of the present application does not specifically limit this.

[0081] The output end of the first gating switch 306 is connected to the compensation sub-circuit 302 and the reduction sub-circuit 305, respectively. The first gating switch 306 can be understood as a data stream gating element. The first gating switch 306 can be configured to connect the interface sub-circuit 301 and the compensation sub-circuit 302 in the first display mode, so that the compensation sub-circuit 302 can obtain image data from the interface sub-circuit 301; and to connect the interface sub-circuit 301 and the reduction sub-circuit 305 in the second display mode, so that the reduction sub-circuit 305 can obtain image data from the interface sub-circuit 301.

[0082] The compensation sub-circuit 302 is used to compensate or correct the image data from the interface sub-circuit 301. As described above with respect to the first selection switch 306, the compensation sub-circuit 302 is used in the first display mode. In the first display mode, the compensation sub-circuit 302 can obtain compensation data (i.e., demura data) from the first memory 303 via the second selection switch 307, and then use this compensation data to process the image data from the interface sub-circuit 301. The output of the compensation sub-circuit 302 is connected to the image quality enhancement sub-circuit 304, and the compensation sub-circuit 302 can output the processed image data to the image quality enhancement sub-circuit 304.

[0083] It can be understood that the compensation sub-circuit 302 can refer to Figure 1 The Demura sub-circuit shown is not described here in detail.

[0084] The reduction subcircuit 305 is used to compress the image data from the interface subcircuit 301 to reduce the amount of the image data without compromising the display integrity of the image data. The compression process in the reduction subcircuit 305 can be understood as removing redundant information or reducing the resolution, and will not be further described here.

[0085] In addition, the reduction subcircuit 305 is used in the second display mode. In the second display mode, the reduction subcircuit 305 processes the first image data from the interface subcircuit to obtain second image data, so as to reduce the data volume of the image data in the second display mode.

[0086] The first memory 303 is connected to the output terminal of the reduction sub-circuit 305. Thus, in the second display mode, the first memory 303 can load the second image data output by the reduction sub-circuit 305. In addition, in the first display mode, the first memory 303 loads compensation data (i.e., demura data) so that the compensation sub-circuit 302 can obtain the compensation data for processing.

[0087] It can be understood that the first memory 303 can be understood as Figure 1 The Demura RAM in the display driver circuit is the RAM originally used to temporarily store Demura data. In the embodiment of the present application, the Demura data is also used to temporarily store image data in the second display mode, so that the processor side (such as AP) does not need to continuously send each frame of image data, thereby avoiding the interface sub-circuit 301 from being frequently woken up. In addition, since the image data temporarily stored in the Demura RAM is the second image data compressed by the reduction sub-circuit 305, the Demura RAM with a smaller storage capacity can also completely store the second image data, so as to facilitate the subsequent driving of the display panel to display the complete display screen corresponding to the first image data.

[0088] The input end of the second selection switch 307 is connected to the first memory 303, and the output end is connected to the compensation sub-circuit 302 and the image quality enhancement sub-circuit 304, respectively. In this way, in the first display mode, the compensation sub-circuit 302 can obtain compensation data from the first memory 303, and in the second display mode, the image quality enhancement sub-circuit 304 can obtain second image data from the first memory 303. It is understood that the relevant implementation of the second selection switch 307 can be referred to the first selection switch 306, and will not be repeated here.

[0089] The input terminals of the image quality enhancement sub-circuit 304 are connected to the output terminals of the compensation sub-circuit 302 and the second selection switch 307, respectively. In the first display mode, the image quality enhancement sub-circuit 304 can directly obtain the demura-processed data from the compensation sub-circuit 302 to perform image quality enhancement processing, and then output it to the DAC output sub-circuit. In the second display mode, the image quality enhancement sub-circuit 304 can obtain the second image data through the second selection switch 307, perform image quality enhancement processing, and then output it to the DAC output sub-circuit.

[0090] It can be understood that the image quality enhancement sub-circuit 304 can refer to Figure 1 The image quality enhancement sub-circuit #2 in FIG is not described in detail here.

[0091] It should be understood that the first selection switch 306 and the second selection switch 307 can determine the conversion between the first display mode and the second display mode under the corresponding control signal instruction, and then select the corresponding data stream channel. Figure 3 Provide explanation.

[0092] In one possible implementation, the interface sub-circuit 301 is also connected to the control end of the first selection switch 306 and the control end of the second selection switch 307, respectively, and the interface sub-circuit 301 is also configured to: receive a first control signal, which indicates entering the second display mode; and send the first control signal to the control end of the first selection switch 306 and the control end of the second selection switch 307, respectively.

[0093] It is understood that the first selection switch 306 and the second selection switch 307 also have control terminals to select the same data stream channel under the control of corresponding control signals. For example, in the first display mode, the first selection switch 306 connects the interface sub-circuit 301 and the compensation sub-circuit 302, and the second selection switch 307 connects the first memory 303 and the compensation sub-circuit 302. For another example, in the second display mode, the first selection switch 306 connects the interface sub-circuit 301 and the reduction sub-circuit 305, and the second selection switch 307 connects the first memory 303 and the image quality enhancement sub-circuit 304.

[0094] In addition, under the triggering of the first control signal, the first selection switch 306 responds to the first control signal to connect the interface sub-circuit 1 and the reduction sub-circuit 305; the second selection switch 307 responds to the first control signal to connect the first memory 303 and the image quality enhancement sub-circuit 304.

[0095] In some possible implementations, the first gating switch 306 and the second gating switch 307 each include one or more transistors.

[0096] The first selection switch 306 and the second selection switch 307 can also be described using logic circuits respectively. For example, the first selection switch 306 is a first logic circuit, and the second selection switch 307 is a second logic circuit.

[0097] It can also be understood that the first control signal can be replaced by a control command for entering the AOD mode, which is not specifically limited.

[0098] That is to say, the interface sub-circuit 301 can also receive a control signal for indicating entering the second display mode, and send the control signal to the control ends of the first selection switch 306 and the second selection switch 307 respectively, thereby connecting the interface sub-circuit 301 with the reduction sub-circuit 305, and connecting the first memory 303 with the image quality enhancement sub-circuit 304, so that the changes to the display driving circuit are small and easy to deploy and implement.

[0099] It should be understood that the interface subcircuit 301 can also receive a second control signal and send the second control signal to the control terminals of the first selection switch 306 and the second selection switch 307, respectively. The second control signal is used to indicate exiting the second display mode. For example, the second control signal is used to indicate exiting the AOD mode. It should be understood that when triggered by the second control signal, the first selection switch 306 responds to the second control signal and connects the interface subcircuit 301 with the compensation subcircuit 302; and the second selection switch 307 responds to the second control signal and connects the first memory 303 with the compensation subcircuit 302.

[0100] In order to optimize the wiring layout in the display driving circuit, the first control signal and the second control signal can be transmitted via the communication bus in the display driving circuit. Figure 4 Provide an example.

[0101] Figure 4 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 2 .like Figure 4 As shown, Figure 3 The difference between the display driving circuit shown is that the display driving circuit further includes a communication bus 401, and the interface sub-circuit 301 further includes an output end for outputting a control signal, which is connected to the control end of the first selection switch 306 and the control end of the second selection switch 307 through the communication bus 401.

[0102] in addition, Figure 4 The display driving circuit shown may further include an output sub-circuit 402, the input end of the output sub-circuit 402 is connected to the output end of the image quality enhancement sub-circuit 304, and the output end of the output sub-circuit 402 is connected to the display panel. Figure 1 The DAC output sub-circuit in is not described here in detail.

[0103] That is, the interface subcircuit 301, the control end of the first selection switch 306, and the control end of the second selection switch 307 can be connected via the communication bus 401, thereby simplifying the wiring complexity within the display driving circuit and improving the reliability of the first control signal transmission.

[0104] In another possible implementation, the control end of the first selection switch 306 and the control end of the second selection switch 307 are respectively connected to a display mode switch, which is used to transmit a first control signal indicating entering the second display mode.

[0105] It can be understood that the second display mode is the AOD mode, which can display some auxiliary information when the display device is in the off-screen state. In addition, if the user sets the display device to enter the AOD mode when the screen is off and automatically exit the AOD mode when the screen is on, the user can flexibly enter and exit the AOD mode through some physical buttons on the display device. For example, the user can press a physical button on the display device to turn the screen on or off, thereby triggering entry and exit of the AOD mode.

[0106] It can be understood that the display mode switch can be a physical button used by the above-mentioned display device to turn on or off the screen, and then the display mode switch can trigger the first control signal or the second control signal.

[0107] Figure 5 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 3 .like Figure 5 As shown, Figure 4 The difference between the display driving circuit shown is that the control terminals of the first selection switch 306 and the second selection switch 307 are respectively connected to the display mode switch 501 , and the interface sub-circuit 301 is not connected to the communication bus 401 .

[0108] like Figure 5 As shown, the display mode switch 501 can be connected to the communication bus 401 in the display driving circuit through a signal line, so that the first control signal and the second control signal transmitted by the display mode switch 501 can be transmitted to the control end of the first selection switch 306 and the control end of the second selection switch 307 through the communication bus 401, respectively.

[0109] That is to say, by sending the first control signal through the display mode switch 501, there is no need to send the first control signal to the interface sub-circuit 301 through the processor side, so that the interface sub-circuit 301 transmits the first control signal through the communication bus, thereby reducing the occupancy of the communication bus and the risk of potential data transmission conflicts.

[0110] It should be understood that in the display driving circuit in the embodiment of the present application, the interface sub-circuit 301 and the display mode switch 501 can simultaneously send the first control signal or the second control signal to the control end of the first selection switch 306 and the second selection switch 307 respectively, so that the first selection switch 306 and the second selection switch 307 can redundantly determine whether to enter the second display mode, thereby improving reliability.

[0111] The transmission timing of the first control signal is described below.

[0112] It should be understood that if the control parameters of entering or exiting the second display mode are not synchronized with the corresponding display mode (it can also be understood that the image data switching in different display modes is different), it will cause adverse phenomena such as screen flickering. Figure 6 Provide explanation.

[0113] Figure 6 1 is a timing diagram of a vertical synchronization signal (ie, V-sync) provided by an embodiment of the present application and triggering the first memory 303 to temporarily store image data in the second display mode out of sync. Figure 6 As shown, assuming that the refresh rate included in the display control parameter #1 in the first display mode is 120Hz (i.e., the frequency of V-sync is 120Hz, i.e., the period is 8.33 milliseconds (ms)), and the refresh rate included in the control parameter #2 in the second display mode is 60Hz (i.e., the frequency of V-sync is 60Hz, i.e., the period is 16.67 milliseconds (ms)), if the image data temporarily stored in the second display mode by the first memory 303 is not synchronized with V-sync, or there is a delay causing the image data temporarily stored in the second display mode by the first memory 303 to lag behind V-sync, then the control parameter #2 in the second display mode will drive the image data in the first display mode, which may cause screen flickering. For another example, if Figure 6 As shown, if the compensation data temporarily stored in the first memory 303 is not synchronized with V-sync, or there is a delay causing it to lag behind V-sync, then the first memory 303 will still store the image data in the second display mode instead of the compensation data. As a result, the display driving circuit actually still processes the image data in the second display mode, that is, the compensation sub-circuit 302 does not work, and the reduction sub-circuit 305 is still working, so that the output sub-circuit 402 outputs the processed second image data.

[0114] It can be understood that, in order to solve the above problem, the timing of transmitting the first control signal can be set to match the vertical synchronization signal.

[0115] In a possible implementation, the first control signal is in synchronization with a vertical synchronization signal, and the vertical synchronization signal indicates a start time for the display driving circuit to drive the display of an image frame.

[0116] It can be understood that the vertical synchronization signal (i.e., V-sync) and the first control signal are in a synchronous relationship, for example: the time interval between the two is less than a preset value, which can be 1 microsecond, 2 microseconds, 3 microseconds, 4 microseconds, or 5 microseconds; or, the time interval between the two is less than or equal to the time occupied by the rising edge of the vertical synchronization signal; or, the time interval between the two is less than or equal to the time occupied by the falling edge of the vertical synchronization signal. The embodiments of the present application do not make specific limitations on this.

[0117] For example, Figure 7 1 is a timing diagram of synchronization between a vertical synchronization signal and a control signal of a second display mode provided by an embodiment of the present application. Figure 7 As shown, the transmission timing of the first control signal is located at the falling edge of the synchronization signal, which can enable the first selection switch 306 to connect the interface sub-circuit 301 and the reduction sub-circuit 305 in time, so that the first memory 303 can store the second image data in time; and can enable the second selection switch 307 to connect the first memory 303 and the image quality enhancement sub-circuit 304 in time, so that the image quality enhancement sub-circuit 304 can process the image data in the second display mode according to the display control parameter #2.

[0118] like Figure 7 As shown, the transmission timing of the second control signal is located at the falling edge of the synchronization signal, which enables the first selection switch 306 to connect the interface sub-circuit 301 and the compensation sub-circuit 302 in a timely manner, so that the compensation sub-circuit 302 can receive the image data and display control parameter #1 in the first display mode; and enables the second selection switch 307 to connect the first memory 303 and the compensation sub-circuit 302 in a timely manner, thereby enabling the compensation sub-circuit 302 to process the image data in the first display mode according to the compensation data.

[0119] That is to say, by synchronizing the first control signal with the vertical synchronization signal, the first selection switch 306 and the second selection switch 307 can switch the data flow channel in time, so that the first memory 303 can store the second image data from the reduction sub-circuit 305 in time, so that the control parameters in the second display mode can match the image data in the second display mode, avoiding adverse phenomena such as screen flickering.

[0120] It can be understood that, similarly, the second control signal for indicating exit from the second display mode is synchronized with the vertical signal, and can also enable the first selection switch 306 and the second selection switch 307 to switch the data flow channel in time, so that the compensation sub-circuit 302 can obtain compensation data from the first memory 303 and process the image data in the first display mode from the interface sub-circuit 301.

[0121] In a possible implementation, the image quality enhancement subcircuit 304 is configured to access the first memory 303 to obtain the second image data.

[0122] It can be understood that the first memory 303 is a passively accessed memory device, and thus the first memory 303 will not actively send the second image data to the image quality enhancement sub-circuit 304. In addition, Figure 1 The image quality enhancement sub-circuit #2 in the embodiment of the present application passively receives the image data from the compensation sub-circuit. Therefore, the image quality enhancement sub-circuit 304 in the embodiment of the present application has changed the processing logic of the data stream, that is, Figure 1 The difference of the image quality enhancement sub-circuit #2 shown is that the image quality enhancement sub-circuit 304 can actively access the first memory to obtain the second image data.

[0123] That is to say, considering that the first memory 303 is a passive device, actively accessing the first memory 303 through the image quality enhancement sub-circuit 304 and directly obtaining the second image data from the first memory 303 can avoid the image quality enhancement sub-circuit 304 obtaining the second image data through other intermediate components, thereby streamlining the components, shortening the transmission path of the image data, and thus reducing the transmission delay of the image data.

[0124] It is understandable that Figure 1 As shown, a BMC decoder or other components may also be provided between the first memory 303 and the image quality enhancement sub-circuit 304 , so as to output the second data to the image quality enhancement sub-circuit 304 .

[0125] In a possible implementation, the image quality enhancement sub-circuit 304 is configured to access the first memory 303 according to a vertical synchronization signal, where the vertical synchronization signal indicates a start time for the display driving circuit to drive the display of an image frame.

[0126] It is understood that the image quality enhancement sub-circuit 304 can periodically access the first memory 303, thereby reducing the overhead of the image quality enhancement sub-circuit 304. In addition, considering that the start time of an image frame is triggered by the vertical synchronization signal, and the image data in the second display mode follows this mechanism, the image quality enhancement sub-circuit 304 can trigger access to the first memory 303 in response to the vertical synchronization signal.

[0127] That is to say, considering that the start time of an image frame is triggered by the vertical synchronization signal, and the image data in the second display mode follows this mechanism, the image quality enhancement sub-circuit 304 can respond to the vertical synchronization signal to trigger access to the first memory 303, thereby reducing the frequency of the image quality enhancement sub-circuit 304 accessing the first memory 303, thereby reducing resource overhead.

[0128] It can be understood that the period of the image quality enhancement subcircuit 304 accessing the first memory 303 can be less than or equal to the period of the vertical synchronization signal, so as to ensure that the image quality enhancement subcircuit 304 accesses the first memory 303 once within an image frame.

[0129] In one possible implementation, the display driving circuit further includes an image data decoder, whose input end is connected to the output end of the interface sub-circuit 301 and whose output end is connected to the input end of the first selection switch 306, and is configured to decode the first image data; accordingly, the reduction sub-circuit 305 is configured to process the decoded first image data to obtain second image data.

[0130] It is understandable that, as mentioned above Figure 1 Regarding the VESA decoder, the image data received by the interface sub-circuit 301 may be image data encoded via VESA. Therefore, a VESA encoder is provided between the input end of the first selection switch 306 and the interface sub-circuit 301 to decode the image data transmitted by the interface sub-circuit 301. In other words, the display driver circuit may further include an image data decoder to facilitate decoding of the image data transmitted by the interface sub-circuit 301.

[0131] In addition, the image data decoder can be a VESA decoder or other decoders, depending on the encoding algorithm used on the processor side, and the embodiments of the present application do not make specific limitations on this.

[0132] Figure 8 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 4 .like Figure 8 As shown, Figure 8 and Figure 4 The differences between the display driver circuits shown are: Figure 8 The display driving circuit shown further includes an image data decoder 801 . An input terminal of the image data decoder 801 is connected to an output terminal of the interface sub-circuit 301 , and an output terminal of the image data decoder 801 is connected to an input terminal of the first selection switch 306 .

[0133] That is to say, by setting an image data decoder between the output end of the interface sub-circuit 301 and the output end of the first selection switch 306, the first image data from the interface sub-circuit 301 can be decoded, and then the reduction sub-circuit 305 does not need to decode the first image data, thereby reducing the processing complexity of the reduction sub-circuit 305.

[0134] In a possible implementation, the display driving circuit further includes:

[0135] The third selection switch has its input ends connected to the output ends of the second memory and the reduction sub-circuit 305 respectively, and its output end connected to the first memory 303. The third selection switch is configured to: when the first display mode is converted to the second display mode, convert the connection between the first memory 303 and the second memory into the connection between the first memory 303 and the reduction sub-circuit 305.

[0136] It is understandable that Figure 1 Regarding the description of Demura RAM, since the accessors are all passive devices and the flash memory is large, Demura RAM is controlled to load the Demura data from the flash memory. Similarly, considering that the first memory 303 is a passive device, a third selection switch is provided between the first memory 303 and the reduction sub-circuit 305 to enable the first memory 303 to load compensation data from the second memory in the first display mode and to load the second image data from the reduction sub-circuit 305 in the second display mode.

[0137] In addition, the second memory may refer to a non-volatile memory, which may be referred to as Figure 1 The flash memory in the ,will not be described here.

[0138] Figure 9 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 5 .like Figure 9 As shown, Figure 9 The display driver circuit shown is Figure 8 The differences between the display driver circuits shown are: Figure 9 The display driving circuit shown further includes a third selection switch 901. The third selection switch 901 includes two input terminals, which are respectively connected to the second memory 902 and the output terminal of the reduction sub-circuit 305. The output terminal of the third selection switch 901 is connected to the first memory 303.

[0139] In addition, if Figure 9 As shown, the control end of the third selection switch 901 is connected to the interface sub-circuit 301 through the communication bus 401 to receive the first control signal or the second control signal.

[0140] I understand. Figure 9 The control end of the third selection switch 901 can also communicate with the Figure 5 The display mode switch 501 in is connected to receive a first control signal or a second control signal, which is not specifically limited in this embodiment of the present application.

[0141] That is to say, considering that the first memory 303 is a passive device, a third selection switch is set between the first memory 303 and the reduction sub-circuit 305, so that the first memory 303 can load the compensation data from the second memory in a timely manner in the first display mode, and load the second image data from the reduction sub-circuit 305 in a timely manner in the second display mode.

[0142] In a possible implementation, the image quality enhancement sub-circuit 304 is a first image quality enhancement sub-circuit, and the display driving circuit further includes: a second image quality enhancement sub-circuit and a fourth selection switch; wherein:

[0143] The second image quality enhancement sub-circuit has an input end connected to the output end of the first selection switch 306 and the output end of the second selection switch 307, and an output end connected to the input end of the fourth selection switch;

[0144] The fourth selection switch has an output end connected to the input end of the compensation sub-circuit 302 and the input end of the first enhancement sub-circuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the second image quality enhancement sub-circuit and the compensation sub-circuit 302 into the connection between the second image quality enhancement sub-circuit and the first image quality enhancement sub-circuit.

[0145] It is understandable that Figure 1 As shown, in order to enhance the image quality, the display driving circuit generally includes two image quality enhancement sub-circuits #1 and #2. Furthermore, when one more image quality enhancement sub-circuit is added, a fourth selection switch can be added between the two image quality enhancement sub-circuits to avoid affecting the data flow in different modes. Figure 10 Provide explanation.

[0146] Figure 10 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application. Figure 6 .like Figure 10 As shown, Figure 10 The display driver circuit shown is Figure 9 The differences between the display driver circuits shown are: Figure 10 The display driving circuit shown further includes: a first image quality enhancement sub-circuit 1003 , a fourth selection switch 1002 , and a second image quality enhancement sub-circuit 1001 .

[0147] like Figure 10 As shown, the first image quality enhancement sub-circuit 1003 is Figure 9 The enhancement sub-circuit 304 in the image quality enhancement sub-circuit 1003 has its input end connected to the output end of the compensation sub-circuit 302 and the output end of the fourth selection switch 1002 respectively, and the output end of the first image quality enhancement sub-circuit 1003 is connected to the input end of the output sub-circuit 402.

[0148] The input end of the second image quality enhancement sub-circuit 1001 can be connected to the output end of the first selection switch 306 and the output end of the second selection switch 307 respectively, that is: Figure 9 The output terminal of the first selection switch 306 connected to the compensation sub-circuit 302 is Figure 10 is changed to be connected to the input terminal of the second image quality enhancement sub-circuit 1001; Figure 9 The output terminal of the second selection switch 307 connected to the enhancement sub-circuit 304 is Figure 10 The middle part is further connected to the input end of the second image quality enhancement sub-circuit 1001.

[0149] The input end of the fourth selection switch 1002 is connected to the output end of the second image quality enhancement sub-circuit 1001, and the output end is respectively connected to the input end of the first image quality enhancement sub-circuit 1003 and the input end of the compensation sub-circuit 302, thereby: in the first display mode, the second image quality enhancement sub-circuit 1001 transmits the image data transmitted from the VESA decoder 801 to the compensation sub-circuit 302, and after the compensation sub-circuit 302 processes the image data, the processed data is output to the first image quality enhancement sub-circuit 1003; in the second display mode, the second image quality enhancement sub-circuit 1001 obtains the second image data from the first memory 303 through the second selection switch 307, and outputs the second image data to the first image quality enhancement sub-circuit 1003 through the fourth selection switch 1002.

[0150] It can be understood that the difference between the first image quality enhancement subcircuit 1003 and the aforementioned image quality enhancement subswitch 304 is that the first image quality enhancement subcircuit 1003 does not need to actively access the first memory 303, but the second image quality enhancement subcircuit 1001 actively accesses the first memory 303.

[0151] In addition, if Figure 10 As shown, the control end of the fourth selection switch 1002 is connected to the interface sub-circuit 301 through the communication bus 401 to receive the first control signal or the second control signal.

[0152] I understand. Figure 10 The control terminal of the fourth selection switch 1002 can also communicate with the Figure 5 The display mode switch 501 in is connected to receive a first control signal or a second control signal, which is not specifically limited in this embodiment of the present application.

[0153] That is, by adding the second image quality enhancement subcircuit 1001 and the fourth selection switch 1002 to the display driving circuit, the image quality of the display screen data can be improved without changing the data processing flow in the first display mode and the second display mode.

[0154] In a second aspect, an embodiment of the present application provides a display module, comprising: a display panel, and a display driving circuit as described in the first aspect, wherein the display driving circuit is connected to the display panel and is used to drive the display panel to display an image.

[0155] It can be understood that the display panel can refer to the relevant description of the display panel in the “first display driver integrated circuit”, which will not be repeated here.

[0156] Figure 11 This is a schematic diagram of the structure of a display module provided in an embodiment of the present application. Figure 11 As shown, the display module includes: a display panel 1101 and a display driving circuit 1102. The display driving circuit 1102 can output a driving voltage to the display panel 1101, thereby driving the display panel 1101 to display an image.

[0157] It should be understood that since the display driving circuit is the display driving circuit described in the first aspect above, the technical effects that can be obtained can refer to the embodiment described in the first aspect above, and will not be repeated here.

[0158] In a third aspect, an embodiment of the present application provides a display device, comprising: a processor, and the display module as described in the second aspect, wherein the processor is connected to the display module and is configured to transmit image data to be displayed to the display module.

[0159] It can be understood that the processor can refer to the relevant description on the processor side in the "first display driver integrated circuit", which will not be repeated here.

[0160] In addition, the display device can refer to the relevant description of the display device in the “first display driver integrated circuit”, which will not be repeated here.

[0161] Figure 12 Schematic diagram of a display device provided in an embodiment of the present application. Figure 12 As shown, the display device includes: a processor 1201 and a display module 1202. The processor 1201 can transmit image data to be displayed to the display module 1202, and then the display module displays a screen according to the image data to be displayed.

[0162] It should be understood that since the display module is the display module described in the second aspect above, the technical effects that can be obtained can refer to the embodiment described in the second aspect above, and will not be repeated here.

[0163] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0164] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0165] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0166] Obviously, those skilled in the art may make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if such changes and modifications fall within the scope of the claims of this specification and their equivalents, this specification is intended to include such changes and modifications.

Claims

1. A display driving circuit, characterized in that: include: an interface subcircuit configured to receive first image data; a compensation subcircuit configured to obtain compensation data from the first memory and perform compensation processing according to the compensation data, wherein an output end of the compensation subcircuit is connected to the image quality enhancement subcircuit; a reduction sub-circuit configured to process the first image data to obtain second image data, wherein the amount of the second image data is smaller than the amount of the first image data, and an output end of the reduction sub-circuit is connected to the first memory; a first gating switch, having an input end connected to the output end of the interface subcircuit and an output end connected to the compensation subcircuit and the reduction subcircuit, respectively, and configured to: when the first display mode is switched to the second display mode, switch the connection between the interface subcircuit and the compensation subcircuit to switch the connection between the interface subcircuit and the reduction subcircuit; A second selection switch has an input end connected to the first memory and an output end connected to the compensation sub-circuit and the enhancement sub-circuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the first memory and the compensation sub-circuit into the connection between the first memory and the image quality enhancement sub-circuit.

2. The display driving circuit according to claim 1, wherein: The interface subcircuit is further connected to the control end of the first gating switch and the control end of the second gating switch respectively, and the interface subcircuit is further configured as follows: receiving a first control signal, wherein the first control signal indicates entering the second display mode; The first control signal is sent to a control end of the first gating switch and a control end of the second gating switch respectively.

3. The display driving circuit according to claim 1, wherein: The control end of the first selection switch and the control end of the second selection switch are respectively connected to a display mode switch, and the display mode switch is used to transmit a first control signal, and the first control signal indicates entering the second display mode.

4. The display driving circuit according to claim 2 or 3, wherein: The first control signal is in synchronization with the vertical synchronization signal, and the vertical synchronization signal instructs the display driving circuit The start time of driving the display of an image frame.

5. The display driving circuit according to any one of claims 1 to 3, characterized in that: The image quality enhancement sub-circuit is configured to access the first memory to obtain the second image data.

6. The display driving circuit according to claim 5, wherein: The image quality enhancement subcircuit is configured to access the first memory according to a vertical synchronization signal, where the vertical synchronization signal indicates a start time for the display driving circuit to drive the display of an image frame.

7. The display driving circuit according to any one of claims 1 to 3, characterized in that: The display driving circuit also includes: an image data decoder, whose input end is connected to the output end of the interface sub-circuit, and whose output end is connected to the input end of the first selection switch, and is configured to: decode the first image data; accordingly, the reduction sub-circuit is configured to: process the decoded first image data to obtain the second image data.

8. The display driving circuit according to any one of claims 1 to 3, characterized in that: The display driving circuit further includes: a third selection switch, wherein the input end of the third selection switch is respectively connected to the output end of the second memory and the reduction sub-circuit, and the output end is connected to the first memory, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the first memory and the second memory into the connection between the first memory and the reduction sub-circuit.

9. The display driving circuit according to any one of claims 1 to 3, characterized in that: The image quality enhancement subcircuit is a first image quality enhancement subcircuit, and the display driving circuit further includes: a second image quality enhancement subcircuit and a fourth selection switch; wherein: The second image quality enhancement sub-circuit has an input end connected to the output end of the first selection switch and the output end of the second selection switch respectively, and an output end connected to the input end of the fourth selection switch; The output end of the fourth selection switch is respectively connected to the input end of the compensation sub-circuit and the input end of the first enhancement sub-circuit, and is configured to: when the first display mode is converted to the second display mode, convert the connection between the second image quality enhancement sub-circuit and the compensation sub-circuit into the connection between the second image quality enhancement sub-circuit and the first image quality enhancement sub-circuit.

10. A display module, characterized in that: include: A display panel, and a display driving circuit according to any one of claims 1 to 9; wherein the display driving circuit is connected to the display panel and is used to drive the display panel to display an image.

11. A display device, characterized in that: The device comprises: a processor, and the display module according to claim 10; wherein the processor is connected to the display module and is used to transmit image data to be displayed to the display module.

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