Static random access memory and multi-bit multiplied single-bit calculation method and equipment thereof

Abstract

The invention relates to a static random access memory and a multi-bit multiplied single-bit calculation method and equipment thereof, the static random access memory comprises a weight storage circuit and an input and output circuit, the control ends of a plurality of weight storage units in the weight storage circuit are connected with corresponding word line ends, the first ends of the weight storage units are connected with a first bit line, and the second ends of the weight storage units are connected with a second bit line. The second ends of the plurality of weight storage units are connected with the second bit line, and are used for generating a first control signal and a second control signal of the input / output circuit according to the corresponding weight values; the input / output circuit includes a first input / output unit and a second input / output unit for receiving first input data and second input data, the first input / output unit generating first output data based on a first control signal and the first input data, and the second input / output unit generating second output data based on a second control signal. The second input / output unit generates second output data based on a second control signal and second input data. Therefore, the problem that in-memory calculation parallelism is limited is solved, and the area utilization rate is increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage and computing technology, and in particular to a static random access memory and a multi-bit multiplication by single-bit calculation method and device thereof. Background Art

[0002] Static Random Access Memory (SRAM) is a volatile embedded memory that needs to be constantly refreshed to retain data. It has the characteristics of high access speed and high area overhead. Its traditional basic unit is a 6T structure, such as Figure 1 When reading data, the bit line (BL, BLB) voltage is precharged to VDD / 2, and the word line (WL) is activated to sense the bit line voltage. If the bit line voltage is higher than VDD / 2, the stored value W is 1; if it is lower than VDD / 2, the stored value W is 0.

[0003] For in-memory computing, the SRAM principle is to store the weight in "W", with WL regarded as the input excitation signal and BL as the output, thus realizing the "1×1" bit calculation of "W×WL=BL".

[0004] Unlike DRAM and Flash, SRAM is integrated with the processor to provide cache or temporary data storage. Therefore, how to achieve higher-speed logical operations based on smaller SRAM area is the key to promoting the development of integrated storage and computing. Summary of the Invention

[0005] The present application provides a static random access memory and a multi-bit multiplication single-bit calculation method and device thereof to solve the problem of limited parallelism of in-memory calculations.

[0006] The first embodiment of the present application provides a static random access memory, comprising: a weight storage circuit and an input / output circuit, wherein:

[0007] The weight storage circuit includes multiple weight storage units, the control ends of the multiple weight storage units are all connected to the corresponding word line ends, the first ends of the multiple weight storage units are all connected to the first bit line, and the second ends of the multiple weight storage units are all connected to the second bit line, and are used to generate the first control signal and the second control signal of the input-output circuit according to the weight value stored in each weight storage unit; the input-output circuit includes a first input-output unit and a second input-output unit, and the input-output circuit is used to receive first input data and second input data, the first input-output unit generates first output data according to the first control signal and the first input data, and the second input-output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data.

[0008] Optionally, a first MOS transistor and a second MOS transistor, a first inverter and a second inverter, wherein the gates of the first MOS transistor and the second MOS transistor are both connected to the word line end, the drain of the first MOS transistor is connected to the first bit line, the source of the first MOS transistor is respectively connected to the input end of the first inverter and the output end of the second inverter, and the first MOS transistor is used to read out the weight inverse value stored in the corresponding weight storage unit; the source of the second MOS transistor is connected to the output end of the first inverter and the input end of the second inverter, the drain of the second MOS transistor is connected to the second bit line, and the second MOS transistor is used to read out the weight value stored in the corresponding weight storage unit.

[0009] Optionally, the first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor.

[0010] Optionally, a third MOS transistor and a fourth MOS transistor, wherein the gate of the third MOS transistor is respectively connected to the gate of the fourth MOS transistor and the first bit line, the source of the third MOS transistor and the fourth MOS transistor is used to receive the first input data, and the drain of the third MOS transistor and the fourth MOS transistor is used to generate first output data based on the first control signal, by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal.

[0011] Optionally, the second input-output unit includes: a fifth MOS transistor and a sixth MOS transistor, wherein the gate of the fifth MOS transistor is respectively connected to the gates of the and sixth MOS transistors and the second bit line, the sources of the fifth MOS transistor and the sixth MOS transistor are used to receive second input data, and the drains of the fifth MOS transistor and the sixth MOS transistor are used to generate second output data based on the second control signal, by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal.

[0012] Optionally, the input-output circuit is also used to: based on the first control signal, multiply the first input data and the weight value stored in the weight storage unit in the first control signal to generate first output data; based on the second control signal, multiply the second input data and the weight value stored in the weight storage unit in the second control signal to generate second output data.

[0013] The second aspect of the present application provides a multi-bit multiplication by single-bit calculation method based on a static random access memory, using the above-mentioned static random access memory, including the following steps: judging whether the input stimulus of the i-th word line of the static random access memory is 1; if the input stimulus of the i-th word line is 1, reading the weight value stored in the i-th weight storage unit, and obtaining the N-bit data received by the input and output circuit of the static random access memory; when the weight value stored in the i-th weight storage unit is 1, based on the multiplication of the weight value stored in the i-th weight storage unit and the N-bit data, the input and output circuit outputs the N-bit multiplication result of the single-bit operation, and when the weight value stored in the i-th weight storage unit is 0, the input and output circuit outputs 0.

[0014] Optionally, when the weight value stored in the i-th weight storage unit is 1, the third MOS tube and the fourth MOS tube in the first input-output unit are turned on, and the fifth MOS tube and the sixth MOS tube in the second input-output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third MOS tube and the fourth MOS tube in the first input-output unit are turned off, and the fifth MOS tube and the sixth MOS tube in the second input-output unit are turned off.

[0015] Optionally, after determining whether the input stimulus of the i-th word line of the static random access memory is 1, it includes: if the input stimulus of the i-th word line is 0, not reading the weight value stored in the i-th weight storage unit, and continuing to determine whether the input stimulus of the i+1-th word line is 1.

[0016] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the multi-bit multiplication by single-bit calculation method based on static random access memory as described in the above embodiment.

[0017] The fourth aspect of the present application provides a computer program product having a computer program stored thereon, which is executed by a processor to implement the multi-bit multiplication by single-bit calculation method based on static random access memory as described in the above embodiment.

[0018] In the above embodiment, the static random access memory includes: a weight storage circuit and an input-output circuit, wherein the weight storage circuit includes a plurality of weight storage units, the control ends of the plurality of weight storage units are all connected to the corresponding word line ends, the first ends of the plurality of weight storage units are all connected to the first bit line, and the second ends of the plurality of weight storage units are all connected to the second bit line, for generating a first control signal and a second control signal for the input-output circuit according to the weight value stored in each weight storage unit; the input-output circuit includes a first input-output unit and a second input-output unit, the input-output circuit is used to receive first input data and second input data, the first input-output unit generates first output data according to the first control signal and the first input data, the second input-output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data. In this way, the problem of limited in-memory computing parallelism is solved, and the in-memory computing parallelism and area utilization are improved.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 Schematic diagram of a conventional 6T SRAM structure in related art;

[0022] Figure 2 Schematic diagram of the structure of a split word line SRAM in the related art;

[0023] Figure 3 A schematic diagram of a static random access memory provided according to an embodiment of the present application;

[0024] Figure 4 Flowchart of a multi-bit multiplication by single-bit calculation method based on static random access memory according to an embodiment of the present application;

[0025] Figure 5 A flowchart of a multi-bit multiplication by single-bit calculation method based on static random access memory according to an embodiment of the present application is provided;

[0026] Figure 6 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0028] The following describes the static random access memory and its multi-bit multiplication single-bit calculation method and device of the embodiment of the present application with reference to the accompanying drawings. In response to the problem of limited parallelism of in-memory calculation mentioned in the above background technology, the present application provides a static random access memory, the static random access memory including: a weight storage circuit and an input-output circuit, wherein the weight storage circuit includes a plurality of weight storage units, the control ends of the plurality of weight storage units are all connected to the corresponding word line ends, the first ends of the plurality of weight storage units are all connected to the first bit line, and the second ends of the plurality of weight storage units are all connected to the second bit line, for generating a first control signal and a second control signal of the input-output circuit according to the weight value stored in each weight storage unit; the input-output circuit includes a first input-output unit and a second input-output unit, the input-output circuit is used to receive first input data and second input data, the first input-output unit generates first output data according to the first control signal and the first input data, the second input-output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data. Thus, the problem of limited parallelism of in-memory calculation is solved, and the parallelism of in-memory calculation and area utilization are improved.

[0029] Regarding improving the computing speed in SRAM memory, the existing technical solution is mainly to achieve parallel computing of multiple "1×1" bits by separating word lines. The circuit diagram is as follows Figure 2 The basic principle is that after the word line is precharged, WL[0] and WL[1] are simultaneously stimulated to the input, BL senses the voltage, W[0] is read from BL, and W[1] is read from BLB, thus achieving "1×1" bit dual parallelism calculation.

[0030] However, there are two main problems with existing technical solutions when applied to in-memory computing: the first is that they can only handle "1×1" bit calculation problems and cannot handle multiplication operations of multidimensional vectors and data; the second is that although the parallelism is improved, the area is not reduced, and the parallelism is at most doubled, the overall performance improvement is limited.

[0031] further, Figure 3 A schematic diagram of a static random access memory 10 provided in an embodiment of the present application.

[0032] like Figure 3 As shown, the static random access memory 10 includes: a weight storage circuit 100 and an input-output circuit 200, wherein:

[0033] The weight storage circuit 100 includes multiple weight storage units, the control ends of the multiple weight storage units are all connected to the corresponding word line ends, the first ends of the multiple weight storage units are all connected to the first bit line, and the second ends of the multiple weight storage units are all connected to the second bit line, and are used to generate the first control signal and the second control signal of the input-output circuit 200 according to the weight value stored in each weight storage unit; the input-output circuit 200 includes a first input-output unit and a second input-output unit, and the input-output circuit 200 is used to receive first input data and second input data, the first input-output unit generates first output data based on the first control signal and the first input data, and the second input-output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data.

[0034] Among them, specifically Figure 3 As shown, the word line end is WL, such as WL[0], WL[1]..., the weight storage circuit 100 includes multiple weight storage units, each weight storage unit has a word line end, the first word line is BLB, the second word line is BL, the input data is an N-bit value, the first input data is a partial bit value in the N-bit value, and the second input data is another partial bit value in the N-bit value.

[0035] It can be understood that when the input stimulus at the word line end is 1, that is, WL[i]=1, the weight value stored in the weight storage unit is taken out. If the weight value=1, the first control signal generated is 0, and the second control signal generated is 1. The first control signal is a control signal for multiplying the weight value by the first input data, and the second control signal is a control signal for multiplying the weight value by the second input data. At this time, the first output data and the second output data obtained are the calculation results of multi-bit multiplication by single-bit.

[0036] When the input stimulus at the word line end is 0, that is, WL[i]=0, the weight value stored in the weight storage unit is not retrieved, and it is continued to be determined whether WL[i+1] is 0.

[0037] Optionally, in some embodiments, the input-output circuit 200 is further used to: based on the first control signal, multiply the first input data and the weight value stored in the weight storage unit in the first control signal to generate first output data; based on the second control signal, multiply the second input data and the weight value stored in the weight storage unit in the second control signal to generate second output data.

[0038] It can be understood that after the first input and output unit receives the first input data, it multiplies the first input data based on the weight value in the first control signal to obtain the first output data; after the second input and output unit receives the second input data, it multiplies the second input data based on the weight value in the second control signal to obtain the second output data.

[0039] Optionally, in some embodiments, multiple weight storage units include: a first MOS tube and a second MOS tube, a first inverter and a second inverter, wherein the gates of the first MOS tube and the second MOS tube are both connected to the word line end, the drain of the first MOS tube is connected to the first bit line, the source of the first MOS tube is respectively connected to the input end of the first inverter and the output end of the second inverter, and the first MOS tube is used to read out the weight inverse value stored in the corresponding weight storage unit; the source of the second MOS tube is connected to the output end of the first inverter and the input end of the second inverter, the drain of the second MOS tube is connected to the second bit line, and the second MOS tube is used to read out the weight value stored in the corresponding weight storage unit.

[0040] In some embodiments, the first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor.

[0041] It should be noted that the control end of the weight storage unit is the gate of the first MOS tube and the second MOS tube, the first end of the weight storage unit is the drain of the first MOS tube, and the second end of the weight storage unit is the drain of the second MOS tube.

[0042] Optionally, in some embodiments, the first input-output unit includes: a third MOS transistor and a fourth MOS transistor, wherein the gate of the third MOS transistor is respectively connected to the gate of the fourth MOS transistor and the first bit line, the source of the third MOS transistor and the fourth MOS transistor is used to receive the first input data, and the drain of the third MOS transistor and the fourth MOS transistor is used to generate the first output data based on the first control signal, by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal.

[0043] Optionally, in some embodiments, the second input-output unit includes: a fifth MOS transistor and a sixth MOS transistor, wherein the gate of the fifth MOS transistor is respectively connected to the gate of the sixth MOS transistor and the second bit line, the source of the fifth MOS transistor and the sixth MOS transistor is used to receive the second input data, and the drain of the fifth MOS transistor and the sixth MOS transistor is used to generate the second output data based on the second control signal by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal.

[0044] Among them, the input end of the first input-output unit is IN (including IN1 and IN3), and the output end is OUT (including OUT1 and OUT3); the input end of the second input-output unit is IN (including IN0 and IN2), and the output end is OUT (including OUT0 and OUT2); the weight value is represented by W, and the weight inverse value is represented by Wb.

[0045] It can be understood that the first input-output unit and the second input-output unit multiply each bit of the input N bits by the corresponding weight values in the first control signal and the second control signal based on the corresponding first control signal and the second control signal to generate first output data and second output data, that is, the calculation result of multi-bit multiplication by single bit.

[0046] For example, as shown in Table 1, when WL[i]=1, the weight value W stored in the i-th weight storage unit is taken out. If the weight value W=0, then Wb=1. Although the input-output circuit 100 receives the input N bits, the N bits are not multiplied by the weight value, and all output data are 0.

[0047] When WL[i]=1, the weight value W stored in the i-th weight storage unit is taken out. If W=1, then Wb=0, the generated first control signal is 0, and the generated second control signal is 1. The weight value W in the first control signal is used × the input N-bit value IN1=OUT1 to obtain the first output data, and the weight value W in the second control signal is used × the input N-bit value IN2=OUT2 to obtain the second output data;

[0048] If WL[i]=0, the weight value stored in the i-th weight storage unit is not retrieved, and it is determined whether WL[i+1] is 0.

[0049] In order to enable those skilled in the art to further understand the multi-bit multiplication single-bit calculation method of the static random access memory 10 of the embodiment of the present application, it is described in detail below with reference to specific embodiments.

[0050] (1) “N×1” bit calculation implementation principle

[0051] Now take N=4 as an example to explain the principle of 4bit multiplication by 1bit. The circuit is as follows Figure 3As shown. Consistent with traditional SRAM, the weight value is stored in "W". After the word line and the output terminal OUT of the input-output circuit 200 are precharged to VDD / 2, WL[0] is input stimulated. The second word line BL and the first word line BLB will be charged or discharged according to the data stored in the weight value "W" and the weight inverse value "Wb". The charging and discharging results of BL and BLB will determine whether the input data "IN" value can be transmitted to "OUT". In this structure, the input-output circuit 200 implements "W×IN=OUT". The input stimulus of the word line terminal WL only determines whether the weight value "W" is to be retrieved for calculation.

[0052] To ensure logical correctness, the second MOS transistor connected to "W" is an NMOS transistor, and the first MOS transistor connected to "Wb" is an NMOS transistor. In a calculation cycle, if the input data is 4 bits, the output data is also 4 bits. That is, each input bit is multiplied by the single-bit weight "W" and the output is a 4-bit result.

[0053] (2) Verification of calculation logic correctness

[0054] The improved SRAM implements "N×1" bit operation based on the weight value "W" and the weight complement value "Wb", and needs to use Boolean operations to analyze the correctness of its structural logic.

[0055] Let's analyze a specific case. If "W" = 1, the BL voltage is greater than VDD / 2, the NMOS transistor is on, and when IN0 = 0, OUT0 = 0. When W = 1, OUT0 = 1, and "W × IN0 = OUT0" holds. At this point, "Wb" = 0, the BLB voltage is less than VDD / 2, and the PMOS transistor is on. When IN1 = 0, OUT1 = 0. When IN1 = 1, OUT1 = 1, and "W × IN1 = OUT1" holds. The analysis of other cases is consistent with the above process and all meet the calculation requirements of "W × IN = OUT." The specific results are shown in Table 1.

[0056] Table 1

[0057] W Wb IN0 OUT0 IN1 OUT1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 1

[0058] (3) “N×1” bit SRAM in-memory calculation process

[0059] The overall calculation process is as follows Figure 4 After the word line is precharged, the input stimulus of the word line terminal WL[i] determines whether to read out the weight value "W" corresponding to W[i].

[0060] If the input stimulus of the word line terminal WL[i] is 1, the weight value "W" corresponding to the i-th weight storage unit W[i] is read out, otherwise it is not read out.

[0061] If the weight value "W" = 1, and the first input data is an N-bit IN value, the generated first control signal is 0, and the generated second control signal is 1. The first input-output unit of the input-output circuit 200 multiplies each bit by the weight value in the first control signal (that is, W = 1) and outputs the first output data. The second input-output unit of the input-output circuit 200 multiplies each bit by the weight value in the second control signal (that is, W = 1) and outputs the second output data. The first output data and the second output data are the result of the N-bit multiplication by a single bit. After completion, it is determined whether the input stimulus of the i+1th word line is 1, thereby determining whether to read the weight value stored in the next weight storage unit;

[0062] If the weight value “W”=0, the input-output circuit 200 outputs 0.

[0063] Through the above process, the SRAM structure realizes multi-bit multiplication by single-bit operation in one cycle.

[0064] In summary, the beneficial effects of the embodiments of the present application are:

[0065] This circuit structure achieves N×1 bit multiplication by adding a small number of additional MOS transistors without introducing significant area overhead. Its core is to utilize the BLB word line voltage sensing function in the traditional SRAM readout mode, and to incorporate PMOS transistors to ensure logical correctness. Furthermore, the output result is no longer represented by the bit line voltage (because there are only two bit lines, the upper limit of the output is 2 bits). Instead, the additional readout transistors are used to output N bits of calculation results within the same cycle. This structure provides a reasonable circuit implementation for fields requiring large-scale matrix calculations, such as deep learning and neural network training, and improves the efficiency of in-memory computing.

[0066] According to the static random access memory, weight storage circuit and input-output circuit proposed in the embodiment of the present application, wherein the weight storage circuit includes a plurality of weight storage units, the control ends of the plurality of weight storage units are all connected to the corresponding word line ends, the first ends of the plurality of weight storage units are all connected to the first bit line, and the second ends of the plurality of weight storage units are all connected to the second bit line, for generating a first control signal and a second control signal of the input-output circuit according to the weight value stored in each weight storage unit; the input-output circuit includes a first input-output unit and a second input-output unit, the input-output circuit is used to receive first input data, the first input-output unit generates first output data according to the first control signal and the first input data, the second input-output unit generates second output data based on the second control signal and the first input data, and outputs the first output data and the second output data. Thus, the problem of limited in-memory computing parallelism is solved, and the in-memory computing parallelism and area utilization are improved.

[0067] Next, a multi-bit multiplication by single-bit calculation method based on static random access memory proposed in an embodiment of the present application will be described with reference to the accompanying drawings.

[0068] Figure 5 This is a flow chart of a flow chart of a multi-bit multiplication by single-bit calculation method based on static random access memory according to an embodiment of the present application.

[0069] like Figure 5 As shown, the multi-bit multiplication single-bit calculation method based on static random access memory includes the following steps:

[0070] In step S501 , it is determined whether the input stimulus of the i-th word line of the static random access memory is 1.

[0071] In step S502 , if the input stimulus of the i-th word line is 1, the weight value stored in the i-th weight storage unit is read, and N bits of data received by the input and output circuit of the static random access memory are obtained.

[0072] In step S503, when the weight value stored in the i-th weight storage unit is 1, based on the multiplication of the weight value stored in the i-th weight storage unit and the N-bit data, the input-output circuit outputs the operation result of N bits multiplied by a single bit. When the weight value stored in the i-th weight storage unit is 0, the input-output circuit outputs 0.

[0073] Optionally, in some embodiments, the third MOS transistor and the fourth MOS transistor in the first input-output unit are turned on, and the fifth MOS transistor and the sixth MOS transistor in the second input-output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third MOS transistor and the fourth MOS transistor in the first input-output unit are turned off, and the fifth MOS transistor and the sixth MOS transistor in the second input-output unit are turned off.

[0074] Optionally, in some embodiments, after determining whether the input stimulus of the i-th word line of the static random access memory is 1, the method includes: if the input stimulus of the i-th word line is 0, not reading the weight value stored in the i-th weight storage unit, and continuing to determine whether the input stimulus of the i+1-th word line is 1.

[0075] It should be noted that the aforementioned explanation of the static random access memory embodiment is also applicable to the multi-bit multiplication by single-bit calculation method based on the static random access memory in this embodiment, and will not be repeated here.

[0076] According to the multi-bit multiplication by single-bit calculation method based on static random access memory proposed in an embodiment of the present application, it is determined whether the input stimulus of the i-th word line of the static random access memory is 1; if the input stimulus of the i-th word line is 1, the weight value stored in the i-th weight storage unit is read, and the N-bit data received by the input and output circuit of the static random access memory is obtained; when the weight value stored in the i-th weight storage unit is 1, based on the multiplication of the weight value stored in the i-th weight storage unit and the N-bit data, the input and output circuit outputs the result of the N-bit multiplication by single-bit operation; when the weight value stored in the i-th weight storage unit is 0, the input and output circuit outputs 0. This solves the problem of limited in-memory computing parallelism and improves in-memory computing parallelism and area utilization.

[0077] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0078] A memory 601 , a processor 602 , and a computer program stored in the memory 601 and executable on the processor 602 .

[0079] When the processor 602 executes the program, the multi-bit multiplication by single-bit calculation method based on static random access memory provided in the above embodiment is implemented.

[0080] Furthermore, the electronic device further includes:

[0081] The communication interface 603 is used for communication between the memory 601 and the processor 602 .

[0082] The memory 601 is used to store computer programs that can be run on the processor 602 .

[0083] The memory 601 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0084] If the memory 601, processor 602, and communication interface 603 are implemented independently, the communication interface 603, memory 601, and processor 602 can be interconnected via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0085] Optionally, in a specific implementation, if the memory 601, the processor 602 and the communication interface 603 are integrated on a chip, the memory 601, the processor 602 and the communication interface 603 can communicate with each other through an internal interface.

[0086] The processor 602 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0087] An embodiment of the present application further provides a computer program product having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned multi-bit multiplication by single-bit calculation method based on static random access memory.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0090] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0091] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer program product for use with, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer program product" can be any device that can contain, store, communicate, propagate, or transmit a program for use with, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer program products include the following: an electrical connection having one or N wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). Furthermore, the computer program product may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or, if necessary, processing it in another suitable manner, and then storing it in a computer memory.

[0092] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0093] Those skilled in the art will understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer program product, which, when executed, includes one or a combination of the steps of the method embodiment.

[0094] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer program product.

[0095] The computer program product mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A static random access memory, characterized in that: include: Weight storage circuit and input-output circuit, wherein, The weight storage circuit includes a plurality of weight storage units, wherein the control terminals of the plurality of weight storage units are connected to the corresponding word line terminals, the first terminals of the plurality of weight storage units are connected to the first bit line, and the second terminals of the plurality of weight storage units are connected to the second bit line, and are used to generate the first control signal and the second control signal of the input-output circuit according to the weight value stored in each weight storage unit; The input-output circuit includes a first input-output unit and a second input-output unit. The input-output circuit is used to receive first input data and second input data. The first input-output unit generates first output data based on the first control signal and the first input data. The second input-output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data.

2. The static random access memory according to claim 1, wherein: The plurality of weight storage units each include: A first MOS tube and a second MOS tube, a first inverter and a second inverter, wherein: The gates of the first MOS transistor and the second MOS transistor are both connected to the word line end, the drain of the first MOS transistor is connected to the first bit line, the source of the first MOS transistor is respectively connected to the input end of the first inverter and the output end of the second inverter, and the first MOS transistor is used to read the weight inverse value stored in the corresponding weight storage unit; The source of the second MOS transistor is connected to the output end of the first inverter and the input end of the second inverter, the drain of the second MOS transistor is connected to the second bit line, and the second MOS transistor is used to read out the weight value stored in the corresponding weight storage unit.

3. The static random access memory according to claim 2, wherein: The first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor.

4. The static random access memory according to claim 1, wherein: The first input-output unit includes: The third MOS tube and the fourth MOS tube, wherein, The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor and the first bit line respectively, the source of the third MOS transistor and the fourth MOS transistor is used to receive the first input data, and the drain of the third MOS transistor and the fourth MOS transistor is used to generate first output data based on the first control signal by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal.

5. The static random access memory according to claim 4, wherein: The second input-output unit includes: The fifth MOS tube and the sixth MOS tube, wherein, The gate of the fifth MOS transistor is respectively connected to the gate of the sixth MOS transistor and the second bit line, the source of the fifth MOS transistor and the sixth MOS transistor is used to receive second input data, and the drain of the fifth MOS transistor and the sixth MOS transistor is used to generate second output data based on the second control signal by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal.

6. The static random access memory according to claim 1, wherein: The input-output circuit is also used for: Based on the first control signal, the first output data is generated by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal; based on the second control signal, the second output data is generated by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal.

7. A method for calculating multi-bit multiplication by single-bit based on static random access memory, characterized in that: The static random access memory according to any one of claims 1 to 6, wherein the method comprises the following steps: Determining whether an input stimulus of an i-th word line of the static random access memory is 1; If the input stimulus of the i-th word line is 1, the weight value stored in the i-th weight storage unit is read, and N bits of data received by the input and output circuit of the static random access memory are obtained; When the weight value stored in the i-th weight storage unit is 1, based on the multiplication of the weight value stored in the i-th weight storage unit and the N-bit data, the input-output circuit outputs the operation result of N bits multiplied by a single bit. When the weight value stored in the i-th weight storage unit is 0, the input-output circuit outputs 0.

8. The method according to claim 7, characterized in that When the weight value stored in the i-th weight storage unit is 1, the third MOS tube and the fourth MOS tube in the first input-output unit are turned on, and the fifth MOS tube and the sixth MOS tube in the second input-output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third MOS tube and the fourth MOS tube in the first input-output unit are turned off, and the fifth MOS tube and the sixth MOS tube in the second input-output unit are turned off.

9. The method according to claim 7, characterized in that After determining whether the input stimulus of the i-th word line of the static random access memory is 1, the method includes: If the input stimulus of the i-th word line is 0, the weight value stored in the i-th weight storage unit is not read, and it is continued to be determined whether the input stimulus of the i+1-th word line is 1.

10. An electronic device, characterized in that: It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a multi-bit multiplication by single-bit calculation method based on static random access memory as described in any one of claims 7 to 9.

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