Write-compute parallelizable in-memory computing unit circuit with auxiliary bit line and method
By introducing auxiliary bit line and word line designs into SRAM memory, the problem that in-memory computing cannot be performed in parallel is solved, efficient parallel computing is achieved, and the computing throughput and storage density of the SRAM array are improved.
Patent Information
- Application Number
- CN202510596447.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-09
- Publication Date
- 2025-08-12
AI Technical Summary
In the prior art, in-memory computing cannot be performed in parallel, resulting in low computing throughput of SRAM arrays and reduced storage density and computing power density.
The auxiliary bit line and auxiliary word line are introduced, and the 6T SRAM memory cell and two additional transistors are designed to make the read, write and calculate signal paths independent and realize parallel execution.
It improves the efficiency of in-memory computing, improves the computing throughput and storage density of SRAM arrays, and reduces unit area overhead.
Smart Images
Figure CN120472961A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit design and in-memory computing technology, and in particular to an in-memory computing unit circuit and method with parallel write-calculation and auxiliary bit lines. Background Art
[0002] In-memory computing technology aims to address the computing bottlenecks caused by the excessive power consumption and latency associated with frequent data movement between memory and computational logic in data-intensive computing tasks. Due to the high-density array nature of memory, in-memory computing architectures are well-suited for tasks with well-organized data, high computational parallelism, simple and consistent computational logic, and where it is desirable for some operands to be pre-determined and written to memory for use.
[0003] In related art, by modifying the memory cell structure, adding an AND logic gate to each static random access memory (SRAM) cell, or adding an OR / NAND gate after every two SRAM cells, an AND operation can be performed on an external input signal and a stored voltage signal. A 1-bit AND operation can be viewed as the multiplication of two 1-bit numbers, serving as the basic multiplication unit. Related art also involves attaching logic gates to each column of SRAM cell bit lines, performing operations when the word line is open, or using split word line interleaving to double the degree of parallelism.
[0004] However, due to the characteristics of the SRAM memory array in the related art, all storage cells in the same column share the same pair of bit lines. Therefore, when mounting the operation logic on the bit lines, the bit lines are similar to a bus that is occupied in a time-sharing manner. It can only perform one of the operations of reading, writing, and calculating on any cell at a time. The three operations process the voltage signals on the bit lines differently, and therefore conflict with each other. As a result, when performing in-memory calculations, the entire array must be written first, and then the calculations are performed row by row. Additional write and read operations cannot be performed during the calculation until all data calculations are completed, which blocks the normal use of the SRAM and reduces the throughput of the processing unit. In the related art, if a logic gate is attached to each storage cell for calculation, it will bring about excessive area overhead, reducing the storage density of the SRAM array and also reducing the computing power density of the in-memory calculation array, which needs to be solved urgently. Summary of the Invention
[0005] The present application provides an in-memory computing unit circuit and method with parallel write-calculation of auxiliary bit lines, so as to solve the problem that in-memory computing cannot be performed in parallel in related technologies, thereby improving computing efficiency.
[0006] The first embodiment of the present application provides an in-memory computing unit circuit with parallel write and calculation of auxiliary bit lines, comprising: a 6T SRAM memory cell, first to third transistors, wherein:
[0007] The 6T SRAM memory cell includes a first inverter and a second inverter, wherein the drain of the first inverter is connected to the drain of the first transistor, the gate of the second inverter, and the gate of the second transistor respectively; and the gate of the first inverter is connected to the drain of the second inverter and the gate of the third transistor respectively;
[0008] The drain of the second inverter is connected to the source of the fourth transistor;
[0009] The gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the first bit line;
[0010] The drain of the second transistor is connected to the first auxiliary bit line, and the source of the second transistor is connected to the ground node through the first auxiliary word line;
[0011] A gate of the third transistor is connected to the second word line, and a drain of the third transistor is connected to the second bit line.
[0012] Optionally, the in-memory computing unit circuit with parallel write and calculation functions of auxiliary bit lines further includes:
[0013] The source of the fourth transistor is connected to the power access node through the second auxiliary word line, and the drain of the fourth transistor is connected to the second auxiliary bit line.
[0014] Optionally, the fourth transistor is a PMOS transistor.
[0015] Optionally, the first inverter includes: a fifth transistor and a sixth transistor, wherein:
[0016] The drain of the fifth transistor is connected to the drain of the sixth transistor, the gate of the fifth transistor is connected to the gate of the sixth transistor, the source of the fifth transistor is connected to a power access node, and the source of the sixth transistor is connected to the ground node.
[0017] Optionally, the second inverter includes: a seventh transistor and an eighth transistor, wherein:
[0018] The drain of the seventh transistor is connected to the drain of the eighth transistor, the gate of the seventh transistor is connected to the gate of the eighth transistor, the source of the seventh transistor is connected to the power access node, and the source of the eighth transistor is connected to the ground node.
[0019] Optionally, the second transistor is an NMOS transistor.
[0020] A second aspect of the present application provides a memory, comprising: an in-memory computing unit circuit with auxiliary bit lines capable of parallel writing and calculation as described above.
[0021] A third aspect of the present application provides an in-memory computing method with parallel write and calculation capabilities using auxiliary bit lines, using any of the above-described in-memory computing unit circuits with parallel write and calculation capabilities using auxiliary bit lines, wherein the method comprises the following steps:
[0022] Acquire a first input signal of a first auxiliary bit line, a second input signal of a second auxiliary bit line, and a current signal of a drain of the second inverter;
[0023] converting the second input signal to obtain a target input signal, inputting the first input signal to the second transistor through the first auxiliary bit line, and inputting the target input signal to the fourth transistor through the second auxiliary bit line;
[0024] A first output result is obtained according to the current signal and the first input signal, and a second output result is obtained according to the current signal and the target input signal.
[0025] Optionally, the second input signal and the target input signal are opposite signals.
[0026] Optionally, after obtaining a second output result according to the current signal and the target input signal, the method further includes:
[0027] A final output result is obtained according to the first output result and the second output result.
[0028] Thus, the 6T SRAM memory cell includes a first inverter and a second inverter, wherein the drain of the first inverter is respectively connected to the drain of the first transistor, the gate of the second inverter, and the gate of the second transistor; the gate of the first inverter is respectively connected to the drain of the second inverter and the gate of the third transistor; the drain of the second inverter is connected to the source of the fourth transistor; the gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the first bit line; the drain of the second transistor is connected to the first auxiliary bit line, and the source of the second transistor is connected to the ground node via the first auxiliary word line; the gate of the third transistor is connected to the second word line, and the drain of the third transistor is connected to the second bit line. Thus, the problem of in-memory calculations being unable to be executed in parallel in the related art is solved, and the calculation efficiency is improved.
[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0031] Figure 1 A schematic diagram of an in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines provided according to an embodiment of the present application;
[0032] Figure 2 A schematic diagram of an in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to one embodiment of the present application;
[0033] Figure 3 The present invention provides a flowchart of an in-memory computing method with parallel write-calculation of auxiliary bit lines according to an embodiment of the present application. DETAILED DESCRIPTION
[0034] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0035] Before introducing the in-memory computing unit circuit with parallel write-calculation and auxiliary bit lines according to the embodiment of the present application, a brief introduction to the in-memory computing unit circuit in the related art is first given.
[0036] Specifically, due to the characteristics of the SRAM memory array, all memory cells in the same column share the same pair of bit lines (BL and BLB). Therefore, when the arithmetic logic is mounted on the bit lines, the bit lines are similar to a time-shared bus, which can only perform one of the following operations on any cell at a time: read, write, or arithmetic. A read operation requires precharging both BL and BLB to Vdd / 2. The two differential logic voltage storage nodes of the SRAM are then pulled up and down to generate sufficient read margin. This voltage is then fed into the current sense amplifier (SA) to determine the logical properties of the stored signal. A write operation requires charging BL and BLB to the corresponding high and low levels based on the data to be written, then turning on the write transistors on both sides to flip the level signals latched in the SRAM in the corresponding direction. Arithmetic operations require precharging BL and BLB to Vdd (because the SRAM's read transistor NMOS has threshold loss when transmitting a high level), then turning on the read transistor to flip the BL and BLB signals. The three operations process the voltage signals on the bit lines differently, and therefore conflict with each other. As a result, when performing in-memory calculations, the entire array must be written first, and then the calculations are performed row by row. Additional write and read operations cannot be performed until all data calculations are completed. This operation method blocks the normal use of SRAM and reduces the throughput of the processing unit.
[0037] Furthermore, if a logic gate is added to each storage unit for operation, it will bring about excessive area overhead, which will reduce the storage density of the SRAM array and also reduce the computing power density of the in-memory computing array.
[0038] Based on the above problems, the present application provides an in-memory computing unit circuit with auxiliary bit line write-calculation parallelism, which includes: a 6T SRAM memory cell, first to third transistors, wherein the 6T SRAM memory cell includes a first inverter and a second inverter, the drain of the first inverter is respectively connected to the drain of the first transistor, the gate of the second inverter, and the gate of the second transistor; the gate of the first inverter is respectively connected to the drain of the second inverter and the gate of the third transistor; the drain of the second inverter is connected to the source of the fourth transistor; the gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the first bit line; the drain of the second transistor is connected to the first auxiliary bit line, and the source of the second transistor is connected to the ground node through the first auxiliary word line; the gate of the third transistor is connected to the second word line, and the drain of the third transistor is connected to the second bit line. Thus, the problem of in-memory computing being unable to be executed in parallel in the related art is solved, and computing efficiency is improved.
[0039] Specifically, Figure 1A schematic diagram of an in-memory computing unit circuit with parallel write-calculation and auxiliary bit lines provided in an embodiment of the present application.
[0040] like Figure 1 As shown, the in-memory computing unit circuit 10 with parallel write and calculation of auxiliary bit lines includes: a 6T SRAM memory cell 100, a first transistor 200, a second transistor 300 and a third transistor 400,
[0041] The 6T SRAM memory cell 100 includes a first inverter and a second inverter, wherein the drain of the first inverter is respectively connected to the drain of the first transistor 200, the gate of the second inverter, and the gate of the second transistor 300; the gate of the first inverter is respectively connected to the drain of the second inverter and the gate of the third transistor 400; the drain of the second inverter is connected to the source of the fourth transistor; the gate of the first transistor 200 is connected to the first word line, and the source of the first transistor 200 is connected to the first bit line; the drain of the second transistor 300 is connected to the first auxiliary bit line, and the source of the second transistor 300 is connected to the ground node through the first auxiliary word line; the gate of the third transistor 400 is connected to the second word line, and the drain of the third transistor 400 is connected to the second bit line.
[0042] Optionally, in some embodiments, the second transistor 300 is an NMOS transistor.
[0043] Specifically, if Figure 2 As shown, Figure 2 This is a schematic diagram of an in-memory computation unit circuit with parallel write and computation capabilities using auxiliary bit lines, provided by one embodiment of the present application. WL represents the first word line, BLB represents the first bit line, BLCB represents the first auxiliary bit line, WLCB represents the first auxiliary word line, BL represents the second bit line, WLC represents the second auxiliary word line, and BLC represents the second auxiliary bit line. A single bit of data is stored by locking two inverters. Even if power is turned off and then back on, the stored data remains unchanged as long as the states are not actively changed. Data is read using a first transistor 200 connected to the first bit line and a third transistor 400 connected to the second bit line. The signal on the first word line is controlled to allow data to be written or read when needed.
[0044] Further, if Figure 2As shown, the source potentials of the third transistor 400 and the fourth transistor are not directly connected to a high or ground connection, but are instead set by a pair of lateral signals, which are then converted to the first word line, the first auxiliary word line, and the second auxiliary word line. During the calculation process, the original read and write functions of the SRAM are not disturbed because the original first word line, the first bit line, and the second bit line are not occupied. This allows the writing of the weight data Q and the logical multiplication operation with the external input data to be pipelined in parallel. When a WLi is opened to write to an SRAM cell, the first auxiliary word line and the second auxiliary word line of another cell with weight data already in place are opened simultaneously, and the output can be obtained on the first auxiliary bit line and the second auxiliary bit line. If the array has N rows, such a cell structure and operation logic is expected to reduce the overall storage and calculation delay to approximately 1 / 2N.
[0045] Optionally, in some embodiments, the in-memory computing unit circuit 10 with parallel write-calculation capability and auxiliary bit lines further includes: a source of the fourth transistor is connected to a power access node via a second auxiliary word line, and a drain of the fourth transistor is connected to the second auxiliary bit line.
[0046] Optionally, in some embodiments, the fourth transistor is a PMOS transistor.
[0047] It is understandable that if this degree of parallelism is not required and the unit area needs to be further compressed, the fourth transistor can be removed to construct a 7T unit that implements one one-bit multiplication operation, and the vertical wiring becomes two bit line signals and an auxiliary calculation bit line signal. In addition, if the degree of parallelism needs to be expanded, the second transistor 300 and the fourth transistor can be reduced to two, which will achieve four one-bit multiplications, but the vertical signals become 6, which may put pressure on the wiring. The unit design is based on a unified principle and can be adjusted according to performance requirements during actual circuit design.
[0048] Optionally, in some embodiments, the first inverter includes: a fifth transistor and a sixth transistor, wherein the drain of the fifth transistor is connected to the drain of the sixth transistor, the gate of the fifth transistor is connected to the gate of the sixth transistor, the source of the fifth transistor is connected to the power access node, and the source of the sixth transistor is connected to the ground node.
[0049] Optionally, in some embodiments, the second inverter includes: a seventh transistor and an eighth transistor, wherein the drain of the seventh transistor is connected to the drain of the eighth transistor, the gate of the seventh transistor is connected to the gate of the eighth transistor, the source of the seventh transistor is connected to the power access node, and the source of the eighth transistor is connected to the ground node.
[0050] It is understandable that when the SRAM cell is in a static state, the two cross-coupled inverters maintain the stored data state unchanged through a feedback mechanism; since each inverter contains a PMOS and an NMOS transistor, the resistance to power supply noise and ground noise is improved, making the stored data more stable and reliable. By utilizing the complementary operation of PMOS and NMOS transistors, the problems that may be caused by a single type of transistor, such as threshold voltage drift, are effectively reduced, thereby improving the reliability of the entire circuit.
[0051] Therefore, the embodiment of the present application only uses two additional transistors on the basis of SRAM, which can realize two 1-bit in-memory calculation bitwise AND operations, which is used to accelerate matrix-vector multiplication or matrix-matrix multiplication operations, save unit area, and obtain higher storage and computing power density; the embodiment of the present application introduces an auxiliary bit line to separate the calculation signal path from the read and write signal path, and the introduction of auxiliary word lines can control the reading, writing and calculation enable of units in different rows in parallel, so that the two can be carried out in parallel to obtain higher computing throughput; it solves the defect in the related art that the read and write operations in the SRAM storage and calculation array cannot be carried out in parallel, and adopts pre-charged transmission tube logic, and only one additional transistor is needed to complete the AND operation logic, which greatly compresses the unit area and improves the storage density and computing power density.
[0052] According to the in-memory computing unit circuit with auxiliary bit lines for parallel write-calculation proposed in the embodiment of the present application, the 6T SRAM memory cell includes a first inverter and a second inverter, the drain of the first inverter being connected to the drain of the first transistor, the gate of the second inverter, and the gate of the second transistor, respectively; the gate of the first inverter being connected to the drain of the second inverter and the gate of the third transistor, respectively; the drain of the second inverter being connected to the source of the fourth transistor; the gate of the first transistor being connected to the first word line, and the source of the first transistor being connected to the first bit line; the drain of the second transistor being connected to the first auxiliary bit line, and the source of the second transistor being connected to the ground node via the first auxiliary word line; the gate of the third transistor being connected to the second word line, and the drain of the third transistor being connected to the second bit line. Thus, the problem of in-memory computing being unable to be executed in parallel in the related art is solved, and computing efficiency is improved.
[0053] Next, the in-memory computing method with parallel write-calculation and auxiliary bit line proposed in an embodiment of the present application will be described with reference to the accompanying drawings.
[0054] Figure 3 This is a flow chart of the in-memory calculation method with parallel write-calculation of auxiliary bit lines according to the embodiment of the present application, using the above Figure 1 The embodiment provides an in-memory computing unit circuit with auxiliary bit lines capable of parallel writing and computing.
[0055] like Figure 3As shown, the in-memory computing method with parallel write-calculation of auxiliary bit lines includes the following steps:
[0056] In step S301 , a first input signal of a first auxiliary bit line, a second input signal of a second auxiliary bit line, and a current signal of a drain of a second inverter are acquired.
[0057] In step S302 , the second input signal is converted to obtain a target input signal, the first input signal is input to the second transistor through the first auxiliary bit line, and the target input signal is input to the fourth transistor through the second auxiliary bit line.
[0058] In step S303, a first output result is obtained according to the current signal and the first input signal, and a second output result is obtained according to the current signal and the target input signal.
[0059] Optionally, in some embodiments, the second input signal and the target input signal are opposite signals.
[0060] Optionally, in some embodiments, after obtaining the second output result according to the current signal and the target input signal, the method further includes: obtaining a final output result according to the first output result and the second output result.
[0061] It should be noted that the aforementioned explanation of the embodiment of the in-memory computing unit circuit with auxiliary bit lines capable of parallel writing and calculation is also applicable to the in-memory computing method with auxiliary bit lines capable of parallel writing and calculation in this embodiment, and will not be repeated here.
[0062] According to the in-memory computing method with parallel write-calculation and auxiliary bit lines proposed in an embodiment of the present application, a first input signal of a first auxiliary bit line, a second input signal of a second auxiliary bit line, and a current signal of the drain of a second inverter are obtained; the second input signal is converted to obtain a target input signal, and the first input signal is input to the second transistor via the first auxiliary bit line, and the target input signal is input to the fourth transistor via the second auxiliary bit line; a first output result is obtained based on the current signal and the first input signal, and a second output result is obtained based on the current signal and the target input signal. This solves the problem of in-memory computing being unable to be executed in parallel in related technologies and improves computing efficiency.
[0063] In addition, an embodiment of the present application also provides a memory, including the above-mentioned in-memory computing unit circuit with auxiliary bit line write-calculation parallelism.
[0064] According to the memory of the embodiment of the present application, the above-mentioned in-memory computing unit circuit with auxiliary bit line write-calculation in parallel solves the problem that in-memory computing cannot be executed in parallel in the related art, thereby improving computing efficiency.
[0065] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.
[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.
[0067] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.
[0068] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
[0069] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.
Claims
1. An in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines, characterized in that: include: 6T SRAM memory cell, first to third transistors, wherein, The 6T SRAM memory cell includes a first inverter and a second inverter, wherein the drain of the first inverter is connected to the drain of the first transistor, the gate of the second inverter, and the gate of the second transistor respectively; and the gate of the first inverter is connected to the drain of the second inverter and the gate of the third transistor respectively; The drain of the second inverter is connected to the source of the fourth transistor; The gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the first bit line; The drain of the second transistor is connected to the first auxiliary bit line, and the source of the second transistor is connected to the ground node through the first auxiliary word line; A gate of the third transistor is connected to the second word line, and a drain of the third transistor is connected to the second bit line.
2. The in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to claim 1, characterized in that: Also includes: The source of the fourth transistor is connected to the power access node through the second auxiliary word line, and the drain of the fourth transistor is connected to the second auxiliary bit line.
3. The in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to claim 2, characterized in that: The fourth transistor is a PMOS transistor.
4. The in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to claim 1, characterized in that: The first inverter includes a fifth transistor and a sixth transistor, wherein: The drain of the fifth transistor is connected to the drain of the sixth transistor, the gate of the fifth transistor is connected to the gate of the sixth transistor, the source of the fifth transistor is connected to a power access node, and the source of the sixth transistor is connected to the ground node.
5. The in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to claim 4, characterized in that: The second inverter includes a seventh transistor and an eighth transistor, wherein: The drain of the seventh transistor is connected to the drain of the eighth transistor, the gate of the seventh transistor is connected to the gate of the eighth transistor, the source of the seventh transistor is connected to the power access node, and the source of the eighth transistor is connected to the ground node.
6. The in-memory computing unit circuit with parallel write and calculation functions and auxiliary bit lines according to claim 1, characterized in that: The second transistor is an NMOS transistor.
7. A memory, characterized in that: include: An in-memory computing unit circuit with parallel write and calculation capabilities and auxiliary bit lines as claimed in any one of claims 1 to 6.
8. An in-memory computing method with parallel write-calculation and auxiliary bit lines, characterized in that: The in-memory computing unit circuit with parallel write and calculation capabilities of auxiliary bit lines according to any one of claims 1 to 6 is used, wherein the method comprises the following steps: Acquire a first input signal of a first auxiliary bit line, a second input signal of a second auxiliary bit line, and a current signal of a drain of the second inverter; converting the second input signal to obtain a target input signal, inputting the first input signal to the second transistor through the first auxiliary bit line, and inputting the target input signal to the fourth transistor through the second auxiliary bit line; A first output result is obtained according to the current signal and the first input signal, and a second output result is obtained according to the current signal and the target input signal.
9. The in-memory computing method with parallel write-calculation and auxiliary bit line according to claim 8, characterized in that: The second input signal and the target input signal are opposite signals.
10. The in-memory computing method with parallel write-calculation and auxiliary bit line according to claim 8, characterized in that: After obtaining a second output result according to the current signal and the target input signal, the method further includes: A final output result is obtained according to the first output result and the second output result.