SRAM (Static Random Access Memory) in-memory computing circuit and method suitable for high parallel computing and memory
By introducing differential control logic and pre-charge operations of the combination of PMOS and NMOS transistors in the SRAM memory cell, the problems of low parallelism and large area overhead of traditional in-memory computing circuits are solved, efficient 4x1 bit data calculation is achieved, and parallel computing capabilities are improved.
Patent Information
- Application Number
- CN202510596448.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-09
- Publication Date
- 2025-08-12
AI Technical Summary
Traditional in-memory computing circuits have shortcomings in parallelism and area overhead, which cannot meet the needs of large-scale parallel computing.
A new SRAM in-memory computing circuit structure is adopted, by introducing a combination of PMOS and NMOS transistors in the SRAM memory cell, using differential control logic and pre-charge operations, 4x1 bit data calculation is achieved, and the parallelism is improved.
It improves computing efficiency, enhances data retention capabilities and write stability, reduces area overhead, and is suitable for large-scale parallel computing tasks.
Smart Images
Figure CN120472962A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor storage and computing technology, and in particular to an SRAM in-memory computing circuit, method, and memory suitable for highly parallel computing. Background Art
[0002] With the surge in data volumes and computing demands, traditional processor architectures (such as CPUs and GPUs) face serious challenges in handling large-scale parallel computing tasks, especially in terms of energy efficiency and processing speed. To address these issues, researchers are seeking to reduce data movement within the system by processing data within the memory, thereby improving computing efficiency and reducing power consumption. This approach is called in-memory computing (IMC) or near-memory computing (NMC).
[0003] In related technologies, such as Figure 1 As shown, Figure 1 This is a schematic diagram of an SRAM in-memory computing circuit suitable for highly parallel computing in the related art. The in-memory computing unit structure of a static random-access memory (SRAM) is usually based on a 6T SRAM storage unit, with additional peripheral circuits added to calculate the stored data.
[0004] However, the structures in related technologies often bring about large area overhead, and most in-memory computing units can only perform "1x1" bit data operations. The computing parallelism is far from enough to meet the needs of large-scale parallel computing, which needs to be solved urgently. Summary of the Invention
[0005] The present application provides an SRAM in-memory computing circuit, method and memory suitable for highly parallel computing, so as to solve the problems of low parallelism and large area overhead in in-memory computing in related technologies and improve computing efficiency.
[0006] The first embodiment of the present application provides an SRAM in-memory computing circuit suitable for high parallel computing, comprising: a first inverter, a second inverter, and first to fourth transistors, wherein:
[0007] The input end of the first inverter is connected to the source of the first transistor, the source of the second transistor and the output end of the second inverter respectively; the output end of the first inverter is connected to the source of the third transistor, the source of the fourth transistor and the input end of the second inverter respectively;
[0008] The gate of the first transistor is connected to the first separate word line, the drain of the first transistor is connected to the first bit line, the gate of the second transistor is connected to the third separate word line, the drain of the second transistor is connected to the third bit line, the gate of the third transistor is connected to the second separate word line, the drain of the third transistor is connected to the second bit line, the gate of the fourth transistor is connected to the fourth separate word line, and the drain of the fourth transistor is connected to the fourth bit line;
[0009] When the first weight data and the second weight data are written, the values of the first to fourth bit lines are determined according to the first weight value of the first weight data and the second weight value of the second weight data.
[0010] Optionally, the second transistor and the fourth transistor are NMOS transistors.
[0011] Optionally, the first transistor and the third transistor are PMOS transistors.
[0012] Optionally, the third separated word line is an opposite signal of the third word line, and the fourth separated word line is an opposite signal of the fourth word line.
[0013] Optionally, the output signal of the first bit line and the output signal of the third bit line are both inverted signals of the original output signal.
[0014] A second aspect of the present application provides a memory, comprising: an SRAM in-memory computing circuit suitable for high-parallel computing as described in any one of the above.
[0015] A third aspect of the present application provides an SRAM in-memory computing method suitable for highly parallel computing, using the SRAM in-memory computing circuit suitable for highly parallel computing as described in any one of the above items, wherein the method comprises the following steps:
[0016] Determining whether the first weight data and the second weight data are written;
[0017] If the writing of the first weight data and the second weight data is completed, obtaining a first weight value of the first weight data and a second weight value of the second weight data;
[0018] precharging the first bit line, the second bit line, the third bit line, and the fourth bit line, obtaining input signals corresponding to the first to fourth separation word lines, and controlling the first to fourth transistors to be in a conducting state;
[0019] Output results corresponding to the first to fourth bit lines are obtained based on the first weight value, the second weight value, and input signals corresponding to the first to fourth split word lines.
[0020] Optionally, the first weight value and the second weight value are opposite values.
[0021] Optionally, precharging the first bit line, the second bit line, the third bit line, and the fourth bit line includes:
[0022] The first bit line and the third bit line are precharged to a first level, and the second bit line and the fourth bit line are precharged to a second level, wherein the first level is greater than the second level.
[0023] Optionally, after determining whether the first weight data and the second weight data are written, the method further includes:
[0024] If the first weight data and the second weight data have not been written, determining the first weight value and the second weight value;
[0025] The values of the first to fourth bit lines are determined according to the first weight value and the second weight value, so that the first weight value is written in the first weight data and the second weight value is written in the second weight data based on the values of the first to fourth bit lines.
[0026] Thus, in the embodiment of the present application, the input end of the first inverter is respectively connected to the source of the first transistor, the source of the second transistor, and the output end of the second inverter; the output end of the first inverter is respectively connected to the source of the third transistor, the source of the fourth transistor, and the input end of the second inverter; the gate of the first transistor is connected to the first separation word line, and its drain is connected to the first bit line; the gate of the second transistor is connected to the third separation word line, and its drain is connected to the third bit line; the gate of the third transistor is connected to the second separation word line, and its drain is connected to the second bit line; the gate of the fourth transistor is connected to the fourth separation word line, and its drain is connected to the fourth bit line; the values of the first to fourth bit lines are determined according to the first weight value and the second weight value. Thus, the problems of low in-memory computing parallelism and large area overhead in the related art are solved, and computing efficiency is improved.
[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0029] Figure 1 Schematic diagram of an SRAM in-memory computing circuit suitable for high-parallel computing in the related art;
[0030] Figure 2A schematic diagram of an SRAM in-memory computing circuit suitable for highly parallel computing provided according to an embodiment of the present application;
[0031] Figure 3 A schematic diagram of an SRAM in-memory computing circuit suitable for highly parallel computing provided according to one embodiment of the present application;
[0032] Figure 4 This is a flowchart of an SRAM in-memory computing method suitable for highly parallel computing provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0033] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0034] The following describes an SRAM in-memory computing circuit, method, and memory suitable for high parallel computing according to an embodiment of the present application with reference to the accompanying drawings. In response to the problems of low parallelism and large area overhead in the related art mentioned in the background technology, the present application provides an SRAM in-memory computing circuit suitable for high parallel computing, comprising: a first inverter, a second inverter, and first to fourth transistors, wherein the input end of the first inverter is respectively connected to the source of the first transistor, the source of the second transistor, and the output end of the second inverter; the output end of the first inverter is respectively connected to the source of the third transistor, the source of the fourth transistor, and the input end of the second inverter; the gate of the first transistor is connected to the first separation word line, and the drain thereof is connected to the first bit line; the gate of the second transistor is connected to the third separation word line, and the drain thereof is connected to the third bit line; the gate of the third transistor is connected to the second separation word line, and the drain thereof is connected to the second bit line; the gate of the fourth transistor is connected to the fourth separation word line, and the drain thereof is connected to the fourth bit line; the values of the first to fourth bit lines are determined according to the first weight value and the second weight value. This solves the problems of low in-memory computing parallelism and large area overhead in related technologies, and improves computing efficiency.
[0035] Specifically, Figure 2 A schematic diagram of an SRAM in-memory computing circuit suitable for highly parallel computing provided in an embodiment of the present application.
[0036] like Figure 2 As shown, the SRAM in-memory computing circuit 10 suitable for high parallel computing includes: a first inverter 100, a second inverter 200, a first transistor 300, a second transistor 400, a third transistor 500 and a fourth transistor 600;
[0037] The input end of the first inverter 100 is connected to the source of the first transistor 300, the source of the second transistor 400, and the output end of the second inverter 200, respectively; the output end of the first inverter 100 is connected to the source of the third transistor 500, the source of the fourth transistor 600, and the input end of the second inverter 200, respectively; the gate of the first transistor 300 is connected to the first separation word line, the drain of the first transistor 300 is connected to the first bit line, the gate of the second transistor 400 is connected to the third separation word line, the drain of the second transistor 400 is connected to the third bit line, the gate of the third transistor 500 is connected to the second separation word line, the drain of the third transistor 500 is connected to the second bit line, the gate of the fourth transistor 600 is connected to the fourth separation word line, and the drain of the fourth transistor 600 is connected to the fourth bit line;
[0038] When the first weight data and the second weight data are written, the values of the first to fourth bit lines are determined according to the first weight value of the first weight data and the second weight value of the second weight data.
[0039] Specifically, the embodiments of the present application achieve precise writing of weight data in the storage cell by controlling the signals on different separate word lines and bit lines, providing enhanced data retention and read-write stability, emphasizing the improvement of computing efficiency and flexibility, while reducing the area overhead problem in related technologies.
[0040] Optionally, in some embodiments, the second transistor 400 and the fourth transistor 600 are NMOS transistors.
[0041] Optionally, in some embodiments, the first transistor 300 and the third transistor 500 are PMOS transistors.
[0042] It can be understood that PMOS transistors are usually used to pull up the potential (close to the power supply voltage), have good noise resistance and driving capabilities, and are suitable for connecting to bit lines or pre-charge nodes; NMOS transistors are good at pulling down the potential (close to the ground potential), can discharge quickly, and are suitable for use as switches or control signal paths; through this configuration, the write stability of the SRAM cell can be enhanced, while improving the efficiency and reliability of the overall circuit.
[0043] It should be noted that the circuit structure of the embodiment of the present application makes the SRAM structure Figure 1 The structure has a stronger write noise tolerance. Figure 1In the structure, the write tubes on the left and right sides are both NMOS tubes, which have poor ability to drive level 1 and strong ability to drive level 0. When writing, the circuit structure of the embodiment of the present application has one side of BL and BLB as 1 and one side as 0. The bit line on the side of 0 can be better written into the SRAM latch unit, while the bit line on the side of 1 has a weaker effect on the SRAM latch value. When there is a deviation in the device or noise in the signal, the value in the SRAM may not be successfully written. The circuit structure of the embodiment of the present application can improve the writing stability. Since there is a PMOS tube and an NMOS tube on both sides of the SRAM latch unit, the driving ability to 1 and the driving ability to 0 are both strong, and data is easier to be written into the SRAM latch unit.
[0044] Optionally, in some embodiments, the third separated word line is an opposite signal of the third word line, and the fourth separated word line is an opposite signal of the fourth word line.
[0045] Optionally, in some embodiments, the output signal of the first bit line and the output signal of the third bit line are both inverted signals of the corresponding original output signals.
[0046] It is understandable that the embodiment of the present application forms differential control logic by separating the inverse signals of the word line and the bit line, suppresses noise interference, and simplifies wiring by utilizing signal complementarity. Figure 3 As shown, Figure 3 A schematic diagram of an SRAM in-memory computing circuit 10 suitable for high-parallel computing provided for an embodiment of the present application, IN0 is the first separated word line, IN1 is the second separated word line, IN2B is the third separated word line, IN3B is the fourth separated word line, OUT0B is the first bit line, OUT1 is the second bit line, OUT2B is the third bit line, and OUT3 is the fourth bit line; the bit lines connected on both sides of the embodiment of the present application are OUT0B, OUT1, OUT2B, and OUT3, respectively, wherein OUT0B and OUT2B are the inversions of the OUT0 and OUT2 signals; the separated word line connections are IN0B, IN1, IN2, and IN3B, respectively, wherein IN0B and IN3B are the inversions of the IN0 and IN3 signals.
[0047] Therefore, the embodiment of the present application realizes "4x1" bit data calculation by adopting a pre-charging operation method, and also includes other deformed calculation structures of adding or reducing left and right input tubes, which is suitable for large-scale storage and computing arrays. At the same time, there are multiple configurable schemes when writing weights, and the design is flexible.
[0048] In order to facilitate those skilled in the art to further understand the SRAM memory computing circuit suitable for high parallel computing in the embodiment of the present application, the following is combined with Figure 3 The illustrated embodiment is described in detail.
[0049] Specifically, if Figure 3 As shown, M0 is the first transistor, M1 is the second transistor, M2 is the third transistor, and M3 is the fourth transistor. IN0 is the first separated word line, IN1 is the second separated word line, IN2B is the third separated word line, and IN3B is the fourth separated word line. OUT0B is the first bit line, OUT1 is the second bit line, OUT2B is the third bit line, and OUT3 is the fourth bit line. In the middle is a dual-inverter interlocking structure that stores weight data. To fully utilize the weights W and WB, the PMOS transistor implements a "4x1" bit multiplication operation by separating the word lines. That is, each in-memory computing unit can simultaneously perform logical operations on 4-bit input and 1-bit weight.
[0050] Furthermore, the following describes in detail the SRAM in-memory computing circuit suitable for high-parallel computing in an embodiment of the present application in combination with the SRAM in-memory computing method suitable for high-parallel computing in an embodiment of the present application.
[0051] The calculation unit is pre-written with weight data W, and the weight data is positive logic W and negative logic WB on both sides of the inverter lock. When writing weight data, IN0 and IN1 should be 1, and IN2B and IN3B should be 0. If the weight value to be written is 1, that is, W=1, WB=0, then OUT1=1, OUT3=1, OUT0B=0, OUT2B=0. OUT1 and OUT3 simultaneously drive W to 1; OUT0B and OUT2B simultaneously drive WB to 0. Conversely, if the weight value to be written is 0, that is, W=0, WB=1, then OUT1=0, OUT3=0, OUT0B=1, OUT2B=1; OUT1 and OUT3 simultaneously drive W to 0, and OUT0B and OUT2B simultaneously drive WB to 1.
[0052] After writing the weight data, when data calculation is required, OUT0B and OUT2B are first precharged to a high potential, such as VDD, and OUT1 and OUT3 are precharged to a low potential, such as VSS. Then, the IN0, IN1, IN2B, and IN3B signals are connected, the four transistors M0, M1, M2, and M3 are turned on, and OUT0B, OUT1, OUT2B, and OUT3 are read. This can realize the logical AND operation of the four-bit input IN0, IN1, IN2, IN3 and the 1-bit weight W, and the output can further obtain the results OUT0, OUT1, OUT2, and OUT3.
[0053] Calculate the truth table (the one with B requires logical inversion), and the calculation formula for OUT0 is as follows:
[0054] OUT0=IN0*W;
[0055] Among them, OUT0B is the first bit line, IN0 is the first separation word line, and W is the first weight data. The results are shown in Table 1.
[0056] Table 1
[0057]
[0058] OUT1 is calculated as follows:
[0059] OUT1=IN1*W;
[0060] Wherein, OUT1 is the second bit line, IN1 is the second separation word line, and W is the first weight data. The results are shown in Table 2.
[0061] Table 2
[0062]
[0063] OUT2 is calculated as follows:
[0064] OUT2=IN2*W;
[0065] Among them, OUT2B is the third bit line, IN2B is the third separated word line, and W is the first weight data. The results are shown in Table 3.
[0066] Table 3
[0067]
[0068] OUT3 is calculated as follows:
[0069] OUT3=IN3*W;
[0070] Wherein, OUT3 is the fourth bit line, IN3B is the fourth separated word line, and W is the first weight data. The results are shown in Table 4.
[0071] Table 4
[0072]
[0073] Therefore, by modifying the SRAM cell structure, adding PMOS computing transistors on both sides of the SRAM latch cell, and changing the connection method of the control lines, the embodiment of the present application has the ability to calculate the multiplication of four 1-bit inputs and 1-bit weights. At the same time, the introduction of PMOS computing input transistors also improves the data writing stability of the SRAM latch cell, which can be used in accelerated computing applications based on in-memory computing technology.
[0074] According to the SRAM in-memory calculation circuit suitable for high parallel calculation proposed in the embodiment of the present application, the input end of the first inverter is respectively connected to the source of the first transistor, the source of the second transistor, and the output end of the second inverter; the output end of the first inverter is respectively connected to the source of the third transistor, the source of the fourth transistor, and the input end of the second inverter; the gate of the first transistor is connected to the first separation word line, and its drain is connected to the first bit line, the gate of the second transistor is connected to the third separation word line, and its drain is connected to the third bit line, the gate of the third transistor is connected to the second separation word line, and its drain is connected to the second bit line, the gate of the fourth transistor is connected to the fourth separation word line, and its drain is connected to the fourth bit line; the values of the first to fourth bit lines are determined according to the first weight value and the second weight value. Thus, the problems of low parallelism and large area overhead of in-memory calculation in the related art are solved, and the calculation efficiency is improved.
[0075] Next, the SRAM in-memory computing method suitable for high parallel computing proposed in the embodiment of the present application is described with reference to the accompanying drawings. Figure 2 The embodiment provides an SRAM in-memory computing circuit suitable for high-parallel computing.
[0076] like Figure 4 As shown, the SRAM in-memory calculation method suitable for high parallel computing includes the following steps:
[0077] In step S401 , it is determined whether the first weight data and the second weight data have been written.
[0078] In step S402 , if the writing of the first weight data and the second weight data is completed, a first weight value of the first weight data and a second weight value of the second weight data are obtained.
[0079] In step S403 , the first bit line, the second bit line, the third bit line and the fourth bit line are precharged, and input signals corresponding to the first to fourth separation word lines are obtained, and the first to fourth transistors are controlled to be in a conducting state.
[0080] In step S404 , output results corresponding to the first to fourth bit lines are obtained based on the first weight value, the second weight value, and input signals corresponding to the first to fourth split word lines.
[0081] Optionally, in some embodiments, the first weight value and the second weight value are opposite values.
[0082] Optionally, in some embodiments, the first bit line, the second bit line, the third bit line and the fourth bit line are precharged, including: precharging the first bit line and the third bit line to a first level, and precharging the second bit line and the fourth bit line to a second level, wherein the first level is greater than the second level.
[0083] Optionally, in some embodiments, after determining whether the first weight data and the second weight data have been written, it also includes: if the first weight data and the second weight data have not been written, determining the first weight value and the second weight value; determining the values of the first to fourth bit lines based on the first weight value and the second weight value, so as to write the first weight value in the first weight data and write the second weight value in the second weight data based on the values of the first to fourth bit lines.
[0084] It should be noted that the aforementioned explanation of the embodiment of the SRAM in-memory computing circuit suitable for high-parallel computing is also applicable to the SRAM in-memory computing method suitable for high-parallel computing of this embodiment, and will not be repeated here.
[0085] According to the SRAM in-memory calculation method suitable for high-parallel calculation proposed in an embodiment of the present application, when the first weight data and the second weight data are written, the first weight value of the first weight data and the second weight value of the second weight data are obtained; the first bit line, the second bit line, the third bit line, and the fourth bit line are precharged, and the input signals corresponding to the first to fourth separated word lines are obtained, and the first to fourth transistors are controlled to be in a conductive state; based on the first weight value, the second weight value, and the input signals corresponding to the first to fourth separated word lines, the output results corresponding to the first to fourth bit lines are obtained. This solves the problems of low in-memory calculation parallelism and large area overhead in related technologies, and improves calculation efficiency.
[0086] In addition, an embodiment of the present application also provides a memory, including the above-mentioned SRAM in-memory computing circuit suitable for high-parallel computing.
[0087] According to the memory of the embodiment of the present application, the above-mentioned SRAM in-memory computing circuit suitable for high-parallel computing solves the problems of low in-memory computing parallelism and large area overhead in related technologies, thereby improving computing efficiency.
[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.
[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.
[0090] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.
[0091] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
[0092] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.
Claims
1. An SRAM in-memory computing circuit suitable for high parallel computing, characterized in that: include: A first inverter, a second inverter, and first to fourth transistors, wherein: The input end of the first inverter is connected to the source of the first transistor, the source of the second transistor and the output end of the second inverter respectively; the output end of the first inverter is connected to the source of the third transistor, the source of the fourth transistor and the input end of the second inverter respectively; The gate of the first transistor is connected to the first separate word line, the drain of the first transistor is connected to the first bit line, the gate of the second transistor is connected to the third separate word line, the drain of the second transistor is connected to the third bit line, the gate of the third transistor is connected to the second separate word line, the drain of the third transistor is connected to the second bit line, the gate of the fourth transistor is connected to the fourth separate word line, and the drain of the fourth transistor is connected to the fourth bit line; When the first weight data and the second weight data are written, the values of the first to fourth bit lines are determined according to the first weight value of the first weight data and the second weight value of the second weight data.
2. The circuit according to claim 1, wherein: The second transistor and the fourth transistor are NMOS transistors.
3. The circuit according to claim 1, wherein: The first transistor and the third transistor are PMOS transistors.
4. The circuit according to claim 1, wherein: include: The third separate word line is an opposite signal of the third word line, and the fourth separate word line is an opposite signal of the fourth word line.
5. The circuit according to claim 1, wherein: The output signal of the first bit line and the output signal of the third bit line are both inverted signals of the original output signal.
6. A memory, characterized in that: include: An SRAM in-memory computing circuit suitable for high parallel computing as described in any one of claims 1 to 5.
7. A SRAM in-memory computing method suitable for highly parallel computing, characterized in that: The SRAM in-memory computing circuit suitable for high parallel computing according to any one of claims 1 to 5 is used, wherein the method comprises the following steps: Determining whether the first weight data and the second weight data are written; If the writing of the first weight data and the second weight data is completed, obtaining a first weight value of the first weight data and a second weight value of the second weight data; precharging the first bit line, the second bit line, the third bit line, and the fourth bit line, obtaining input signals corresponding to the first to fourth separation word lines, and controlling the first to fourth transistors to be in a conducting state; Output results corresponding to the first to fourth bit lines are obtained based on the first weight value, the second weight value, and input signals corresponding to the first to fourth split word lines.
8. The method according to claim 7, characterized in that The first weight value and the second weight value are opposite values.
9. The method according to claim 7, characterized in that The precharging of the first bit line, the second bit line, the third bit line, and the fourth bit line includes: The first bit line and the third bit line are precharged to a first level, and the second bit line and the fourth bit line are precharged to a second level, wherein the first level is greater than the second level.
10. The method according to claim 7, characterized in that After determining whether the writing of the first weight data and the second weight data is completed, the method further includes: If the first weight data and the second weight data have not been written, determining the first weight value and the second weight value; The values of the first to fourth bit lines are determined according to the first weight value and the second weight value, so that the first weight value is written in the first weight data and the second weight value is written in the second weight data based on the values of the first to fourth bit lines.