Efficient data programming and error correction method and system for memory chip

Abstract

The application discloses an efficient data burning and error correction method and system for a storage chip, relates to the field of data burning and error correction, and realizes the cooperative optimization of the performance and reliability of a storage system through a multi-level cache and a dynamic adjustment mechanism; through hierarchical design of the first and second level caches, high-frequency access data is preferentially retained in a low-delay storage medium, a time delay mapping model can predict performance under different capacity configurations, and the blindness of traditional threshold setting is avoided; in combination with the dual determination conditions of the storage error number and time delay data, early signs of hardware degradation can be identified; the storage load balancing degree is improved by dynamically adjusting the hot and cold data migration threshold; in addition, when the cache adjustment fails, the storage area capacity expansion and contraction is automatically triggered, and service continuity in an extreme scenario is ensured.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of data burning and error correction, and particularly relates to an efficient data burning and error correction method and system for storage chips. BACKGROUND

[0002] As one of the indispensable core components in modern electronic devices, the data burning (programming) and error correction (ECC, Error Correction Code) technology of storage chips plays a crucial role in ensuring the integrity and reliability of data. However, in practical applications, the burning and error correction management of storage chips faces many challenges: low data burning efficiency: as the capacity of storage chips increases, traditional burning methods gradually expose the problems of slow processing speed and large resource consumption, especially in high-density storage chips, how to improve the burning speed and reduce the processing time becomes a technical problem to be solved. Insufficient error correction capability: during the use of storage chips, data bit flipping may occur due to various factors (such as radiation, temperature fluctuations, electromagnetic interference, etc.), and traditional error correction technology is difficult to provide sufficient error correction capability, especially when errors occur frequently or error types are complex, the efficiency and reliability of error correction are particularly important. Error propagation and complex management: in a multi-level storage structure, the propagation of errors may lead to the spread of data errors, increasing the complexity of error management and repair. Traditional methods often rely on relatively static error correction strategies, which cannot flexibly adapt to changing error patterns. Traditional burning systems cannot predict the latency changes under different capacity loads, and static migration thresholds in traditional methods may lead to insufficient utilization of storage media; in addition, the traditional scheme is prone to avalanche effect caused by full cache writing. SUMMARY

[0003] In view of the problems in the related art, the present application proposes an efficient data burning and error correction method and system for storage chips to overcome the above technical problems existing in the prior art.

[0004] To solve the above technical problems, the present application is realized by the following technical scheme:

[0005] The present application is an efficient data burning and error correction method for storage chips, comprising the following steps:

[0006] S1, constructing a one-level cache and a two-level cache for each to-be-burned storage area;

[0007] S2, collecting historical capacity and historical latency data of each to-be-burned storage area and the one-level cache and the two-level cache in S1;

[0008] S3, constructing a latency mapping model corresponding to each to-be-burned storage area according to the historical capacity and historical latency data collected in S2;

[0009] S4, collecting current capacity data of each to-be-burned storage area, the first-level cache and the second-level cache and the number of storage errors of each to-be-burned storage area; and inputting the same into the latency mapping model constructed in S3 respectively for mapping to obtain a current region latency data set;

[0010] S5, constructing a current region adjustment judgment condition set according to the current region latency data set and the number of storage errors collected in S4, and adjusting the migration standard threshold of hot data, warm data and cold data; if the adjusted judgment condition is still established, executing S6;

[0011] S6, first adjusting the current storage capacity data of the first-level cache and the second-level cache according to the current region adjustment judgment condition set; if the adjusted judgment condition is still established, adjusting the current storage capacity data of each to-be-burned storage area until there is no condition established in the current region adjustment judgment condition set.

[0012] Preferably, the S1 comprises the following steps:

[0013] S11, setting a to-be-burned storage chip; dividing data storage areas of the to-be-burned storage chip to obtain a to-be-burned storage area set; the to-be-burned storage area set comprises a program storage area, a metadata storage area, a hot data storage area, a warm data storage area and a cold data storage area;

[0014] S12, constructing a first-level cache of the program storage area, the metadata storage area, the hot data storage area and the warm data storage area respectively to obtain a to-be-burned first-level cache set; and constructing a second-level cache of the metadata storage area and the hot data storage area on the basis of the to-be-burned first-level cache set to obtain a to-be-burned second-level cache;

[0015] By cooperating the hot / warm / cold data partition isolation with the two-level cache, the high-frequency access data is preferentially stored in the low-latency cache, the number of direct access to the main memory is reduced, the overall data access latency is reduced, the metadata separate cache design is reduced to further shorten the retrieval time of the key control information, the hierarchical standard is provided for subsequent data dynamic grading, so that the hot data area wear concentration of high write frequency is concentrated, the overall service life of the chip is prolonged, the cold data area is not provided with a cache to reduce static energy consumption, and the combination of the large-capacity low-speed storage of the cold data area and the high-speed cache of the hot data area is realized, the use proportion of the high-speed storage medium is reduced while the performance demand is met, the hardware cost is saved, and the energy efficiency is optimized.

[0016] Preferably, the S2 comprises the following steps:

[0017] S21, according to the to-be-burned storage area set, the to-be-burned primary cache set and the to-be-burned secondary cache, the historical storage capacity data of each to-be-burned storage area, the primary cache and the secondary cache is collected multiple times to obtain the to-be-burned storage area historical capacity data set, the to-be-burned primary cache historical capacity data set and the to-be-burned secondary cache historical capacity data;

[0018] S22, the data amount of code program data, meta, hot, warm and cold data in the historical to-be-burned data corresponding to the historical capacity data obtained in S21 is obtained again to obtain a historical to-be-burned data amount set; and the historical average time delay data of accessing each to-be-burned storage area in the to-be-burned storage area set corresponding to the historical to-be-burned data amount set is collected again to obtain a region time delay historical data set;

[0019] By quantifying the capacity of each level of storage medium, accurate space allocation of program, meta, hot, warm and cold data is realized, and invalid occupation of high-speed storage medium is avoided; matching analysis of the capacity data set and the data amount set improves the storage utilization rate; by comparing the time delay data with the threshold value, potential performance conflict areas can be identified before data burning, so that the system can perform load balancing adjustment in advance, and the storage access delay fluctuation is reduced; in cooperation with the delay threshold control, the risk of data loss can be greatly reduced; based on the joint analysis of capacity and delay data, the power supply strategy of different storage areas can be dynamically adjusted, and the power consumption of non-active storage units is reduced.

[0020] Preferably, the S3 comprises the following steps:

[0021] S31, according to the to-be-burned storage area historical capacity data set, the to-be-burned primary cache historical capacity data set, the to-be-burned secondary cache historical capacity data, the historical to-be-burned data amount set and the region time delay historical data set, program region time delay mapping models, meta region time delay mapping models, hot region time delay mapping models, warm region time delay mapping models and cold region time delay mapping models are constructed;

[0022] By constructing the program region time delay mapping model, the meta region time delay mapping model, the hot region time delay mapping model, the warm region time delay mapping model and the cold region time delay mapping model, adjustment basis is provided for subsequent adjustment of the cache capacity or the region capacity according to the mapping of each region, cache capacity and the data amount of to-be-burned data to the time delay data of each corresponding region.

[0023] Preferably, the program region time delay mapping model, the meta region time delay mapping model, the hot region time delay mapping model, the warm region time delay mapping model and the cold region time delay mapping model in S31 all adopt LSTM models;

[0024] The LSTM (Long Short Term Memory Network) can effectively capture the time sequence dependence of the storage capacity fluctuation and the historical delay data, solve the gradient disappearance problem of the traditional RNN, process the time dynamic characteristics of the storage system through the gating mechanism, and in addition, the LSTM is suitable for high-frequency delay prediction of the program storage area and the hot data area, wherein the program area has strict real-time requirements, and the multi-step prediction capability of the LSTM can early warn the performance bottleneck.

[0025] Preferably, the S4 comprises the following steps:

[0026] S41, according to the set of to-be-burned storage areas, the set of to-be-burned first-level caches, and the set of to-be-burned second-level caches, collecting the current storage capacity data of each to-be-burned storage area, the first-level cache, and the second-level cache of the to-be-burned storage chip, obtaining the set of current capacity data of to-be-burned storage areas, the set of current capacity data of to-be-burned first-level caches, and the set of current capacity data of to-be-burned second-level caches;

[0027] Further, the data amount of the code program data, the meta data, the hot data, the warm data, and the cold data in the current to-be-burned data corresponding to the current storage capacity data of each to-be-burned storage area, the first-level cache, and the second-level cache obtained in S41 is obtained, and the set of current to-be-burned data amounts is obtained;

[0028] S42, constructing the data migration standard rule of each area on the to-be-burned storage chip;

[0029] S43, setting the data storage error number threshold corresponding to each to-be-burned storage area on the to-be-burned storage chip, obtaining the set of current data storage error number thresholds; according to the data migration standard rule, on the basis of the set of current capacity data of to-be-burned storage areas, the set of current capacity data of to-be-burned first-level caches, the set of current capacity data of to-be-burned second-level caches, and the set of current to-be-burned data amounts, the data storage error number of each to-be-burned storage area is counted, and the set of current storage error numbers of the area is obtained;

[0030] S44, setting the current time delay threshold of each to-be-burned storage area, obtaining the set of current area time delay thresholds; combining the data amount of the code program data, the meta data, the hot data, the warm data, and the cold data in the set of current to-be-burned data amounts with the set of current capacity data of to-be-burned storage areas, the set of current capacity data of to-be-burned first-level caches, and the set of current capacity data of to-be-burned second-level caches, respectively, and then inputting them into the program area time delay mapping model, the meta area time delay mapping model, the hot area time delay mapping model, the warm area time delay mapping model, and the cold area time delay mapping model, respectively, for mapping, to obtain the set of current area time delay data;

[0031] By dynamically monitoring the capacity state of the storage area, the primary cache and the secondary cache, and combining the differentiated processing of data classification, the storage error risk is effectively reduced. At the same time, the real-time statistical mechanism based on the error number threshold can early warn potential storage failure; the hierarchical cache architecture reduces repeated IO operations, and provides data support for significantly reducing access delay by matching the optimal storage capacity for different data types; by setting data migration standard rules, the storage strategy is dynamically adjusted to adapt to different sizes of data sets and changes in access patterns; and data migration has a certain degree of influence on the number of data storage errors and data storage latency, so as to provide decision basis for subsequent multi-level capacity data set and error statistical mechanism for resource elastic allocation.

[0032] Preferably, the S42 comprises the following steps:

[0033] S421, respectively set the migration standard threshold values of hot, warm and cold data to obtain the hot access frequency threshold value, the warm access frequency threshold value and the cold access frequency threshold value; and then set the hot migration frequency acquisition number threshold value, the warm migration frequency acquisition number threshold value and the cold migration frequency acquisition number threshold value;

[0034] S422, construct data migration standard rules according to the migration frequency acquisition number threshold value, the hot access frequency threshold value, the warm access frequency threshold value and the cold access frequency threshold value; as follows,

[0035] In addition to program data and metadata, when the access frequency of the data in the to-be-burned storage chip is greater than or equal to the hot access frequency threshold value for a number of times greater than or equal to the hot migration frequency acquisition number threshold value, the data is migrated to the hot data storage area; otherwise, no migration is performed;

[0036] When the access frequency is less than the hot access frequency threshold value and greater than or equal to the warm access frequency threshold value for a number of times greater than or equal to the warm migration frequency acquisition number threshold value, the data is migrated to the warm data storage area; otherwise, no migration is performed;

[0037] When the access frequency is less than the cold access frequency threshold value for a number of times greater than or equal to the cold migration frequency acquisition number threshold value, the data is migrated to the cold data storage area; otherwise, no migration is performed;

[0038] The continuous period threshold determination strategy effectively filters the interference of transient access fluctuations on data migration, and improves system operation stability; the migration frequency threshold mechanism avoids performance jitter caused by frequent data transfer; the hot access frequency threshold ensures that only continuously high-frequency access data occupies high-speed storage media, improving the utilization rate of high-speed storage space; the cold data delay degradation strategy can accurately identify truly idle data through long-term low-frequency verification, improving the accuracy of the timing of enabling low-power storage media; in addition, the isolated storage of metadata and program data avoids the impact of migration strategies on critical data, shortening the system crash recovery time.

[0039] Preferably, the S5 comprises the following steps:

[0040] S51, set the current region adjustment condition set in combination with the current data storage error number threshold set and the current region latency threshold set;

[0041] S52, set the first maximum number of repetitions, if there is a condition in the current region adjustment condition set that is established, adjust the hot access frequency threshold, the warm access frequency threshold, and the cold access frequency threshold, and repeat S42, S43, S44, S51, and S52; if the adjustment repetition number is greater than or equal to the first maximum number of repetitions and there is no condition in the current region adjustment condition set that is established, the adjustment is complete; otherwise, go to S61;

[0042] The dual condition determination avoids the limitations of single indicator monitoring, such as the error rate rising caused by hardware failure, which can be detected earlier than latency deterioration, and the dual threshold mechanism can trigger fault tolerance processing in advance; the linkage adjustment of hot / warm / cold data access frequency thresholds realizes the automatic rebalancing of storage load; when the performance of hot data area decreases, part of the load is migrated to the warm data area by increasing the access frequency threshold, and vice versa to shrink the warm data range to protect the performance of core data; the maximum number of repetitions is set as the adjustment termination condition to prevent excessive adjustment caused by threshold oscillation; the system stops only when the iteration limit is reached and all indicators meet the requirements, otherwise it goes to S61 to ensure business continuity in extreme scenarios.

[0043] Preferably, the S6 comprises the following steps:

[0044] S61, set the second maximum number of repetitions, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the current capacity data set of the first cache to be burned, and the current capacity data of the second cache to be burned, and repeat S42, S43, S44, S51, and S61; if the adjustment repetition number is greater than or equal to the second maximum number of repetitions and there is no condition in the current region adjustment condition set that is established, the adjustment is complete; otherwise, go to S62;

[0045] S62, the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the to-be-burned first cache current capacity data set, the to-be-burned second cache current capacity data and the to-be-burned storage area current capacity data set are adjusted, and S42, S43, S44, S51 and S62 are repeated until there is no determination condition in the current region adjustment determination condition set The condition is established;

[0046] The second maximum number of repetitions is introduced as a safety threshold, which starts the high-order fault-tolerant process when the primary adjustment, that is, S52, fails to adjust; by expanding the adjustment object to the first and second cache capacities, the problem of stubborn performance degradation caused by cache overflow or IO bottleneck is solved; the capacity data set of the to-be-burned storage area is adjusted in linkage, so that the cold data migration and cache space release form a synergistic effect; when S61 still cannot eliminate the abnormality, the full parameter adjustment mode of S62 will trigger the overall chip-level self-healing; wherein, adjusting the access frequency threshold is only for the numerical value, which is relatively simple; the capacity adjustment of the cache is relatively simple compared with the actual capacity of the chip region, therefore, in the present scheme, the access frequency threshold, the capacity of the cache and the actual capacity of the chip region are adjusted in turn, which can maximize the adjustment time consumption, greatly shortening the business interruption time caused by hardware failure.

[0047] The efficient data burning and error correction system for the storage chip comprises a to-be-burned storage chip region division module, a to-be-burned storage cache setting module, a region cache capacity acquisition module, a region time delay mapping model construction module, a to-be-burned storage chip region current data acquisition module, a current region time delay mapping module, a region data migration access frequency threshold adjustment module and a chip cache actual region capacity adjustment module.

[0048] The present application has the following beneficial effects:

[0049] 1. In the present application, through the multi-level cache and dynamic adjustment mechanism, the performance and reliability of the storage system are cooperatively optimized; through the hierarchical design of the first and second caches, high-frequency access data is preferentially retained in low-delay storage media, the time delay mapping model can predict the performance under different capacity configurations, avoiding the blindness of traditional threshold setting; in combination with the dual determination conditions of storage error number and time delay data, early signs of hardware degradation can be identified; dynamically adjusting the cold and hot data migration threshold improves the storage load balancing degree; in addition, when the cache adjustment fails, the storage area capacity expansion and contraction is automatically triggered, ensuring the service continuity in extreme scenarios.

[0050] 2. The application constructs program area latency mapping model, meta area latency mapping model, hot area latency mapping model, warm area latency mapping model and cold area latency mapping model, which provides adjustment basis for subsequent adjustment of cache capacity or region capacity according to the latency data of each region, cache capacity and data volume of to-be-burned data mapped to each corresponding region.

[0051] 3. The application adjusts the access frequency threshold, cache capacity and actual region capacity of the chip in turn and gradually, which can minimize the adjustment time consumption and greatly shorten the service interruption time caused by hardware failure.

[0052] 4. The application captures storage abnormalities in real time through double determination conditions (error number exceeding limit, latency exceeding limit), avoids the limitation of single index monitoring, for example, the error rate rising caused by hardware failure can be discovered earlier than latency deterioration, the double threshold mechanism can trigger fault-tolerant processing in advance, and the linkage adjustment of hot / warm / cold data access frequency threshold realizes the automatic rebalancing of storage load.

[0053] Of course, any product implementing the application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0055] Figure 1 The whole flowchart of the efficient data burning and error correction method for the storage chip of the application;

[0056] Figure 2 The flowchart of constructing region latency mapping model and data migration standard rule of the application;

[0057] Figure 3 The flowchart of adjusting the access frequency threshold, cache capacity and actual region capacity of the chip in turn and gradually of the application;

[0058] Figure 4 The module schematic diagram of the efficient data burning and error correction system for the storage chip of the application. DETAILED DESCRIPTION

[0059] With reference to the drawings of the embodiments of the application, the technical solutions in the embodiments of the application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments of the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0060] Embodiment one

[0061] Please refer to Figures 1-3 The embodiment is a high-efficiency data burning and error correction method for a storage chip, comprising the following steps.

[0062] S1, constructing a one-level cache and a two-level cache of each to-be-burned storage area;

[0063] The S1 comprises the following steps.

[0064] S11, setting a to-be-burned storage chip; dividing a data storage area of the to-be-burned storage chip to obtain a to-be-burned storage area set; the to-be-burned storage area set comprises a program storage area, a metadata storage area, a hot data storage area, a warm data storage area, and a cold data storage area; the metadata storage area, the hot data storage area, the warm data storage area, and the cold data storage area are respectively used for storing metadata, hot data, warm data, and cold data in to-be-burned data; the metadata is structured information used for describing data attributes, including file index, address mapping table, and other control data, and needs to ensure nanosecond-level access speed; the program storage area is used for storing code program data; the hot data is usually real-time transaction log, cache data, etc.; the warm data includes recent business records, user portrait, etc.; the cold data is like archived log, backup file, etc.

[0065] S12, constructing a one-level cache of the program storage area, the metadata storage area, the hot data storage area, and the warm data storage area respectively to obtain a to-be-burned one-level cache set; and then constructing a two-level cache of the metadata storage area and the hot data storage area on the basis of the to-be-burned one-level cache set to obtain a to-be-burned two-level cache;

[0066] By hot / warm / cold data partition isolation and two-level cache cooperation, high-frequency access data is preferentially stored in low-latency cache, reducing the number of direct access to main memory, and the overall data access delay is reduced by more than 40%; the separate cache design of metadata further shortens the retrieval time of key control information; the subsequent dynamic grading of data provides grading criteria, thereby reducing the wear concentration of hot data regions with high write frequency by 30%, prolonging the overall service life of the chip; the cold data area does not set up cache to reduce static energy consumption; the combination of high-capacity low-speed storage in the cold data area and high-speed cache in the hot data area reduces the use ratio of high-speed storage media while meeting performance requirements, saving hardware costs by 25%, and optimizing energy efficiency;

[0067] S2, collect the historical capacity and historical time delay data of each to-be-burned storage area and the first and second level caches in S1;

[0068] The S2 includes the following steps:

[0069] S21, according to the set of to-be-burned storage areas, the set of to-be-burned first level caches, and the set of to-be-burned second level caches, collect the historical storage capacity data of each to-be-burned storage area, first level cache, and second level cache multiple times to obtain the set of historical storage capacity data of to-be-burned storage areas, the set of historical capacity data of to-be-burned first level caches, and the set of historical capacity data of to-be-burned second level caches;

[0070] S22, further obtain the data amount of code program data, metadata, hot data, warm data, and cold data in the historical to-be-burned data corresponding to the historical capacity data obtained in S21 to obtain the set of historical to-be-burned data amounts; and further collect the historical average time delay data of accessing each to-be-burned storage area in the set of to-be-burned storage areas corresponding to the set of historical to-be-burned data amounts to obtain the set of historical time delay data of regions;

[0071] By quantifying the capacity of each level of storage medium, accurate spatial allocation of program, metadata, hot, warm, and cold data is realized, and invalid occupation of high-speed storage medium is avoided; matching analysis of the capacity data set and the data amount set can improve the storage utilization rate to more than 95% of the theoretical limit; by comparing the time delay data with the threshold value, potential performance conflict areas can be identified before data burning, so that the system can perform load balancing adjustment in advance, and the storage access delay fluctuation is reduced by more than 40%; in combination with delay threshold control, the data loss risk can be reduced by 99.9%; based on the joint analysis of capacity and delay data, the power supply strategy of different storage areas can be dynamically adjusted, and the power consumption of non-active storage units is reduced by 60%;

[0072] S3, construct a time delay mapping model corresponding to each to-be-burned storage area according to the historical capacity and historical time delay data collected in S2;

[0073] The S3 includes the following steps:

[0074] S31, constructing a program region time delay mapping model, a meta region time delay mapping model, a hot region time delay mapping model, a warm region time delay mapping model and a cold region time delay mapping model according to the to-be-burned storage region historical capacity data set, the to-be-burned primary cache historical capacity data set, the to-be-burned secondary cache historical capacity data, the historical to-be-burned data volume set and the region time delay historical data set;

[0075] By constructing the program region time delay mapping model, the meta region time delay mapping model, the hot region time delay mapping model, the warm region time delay mapping model and the cold region time delay mapping model, a basis for adjusting the cache capacity or the region capacity is provided for subsequent mapping of the time delay data of each region, cache capacity and to-be-burned data volume to the corresponding each region, and further adjusting the cache capacity or the region capacity;

[0076] The S31 includes the following steps:

[0077] S311, setting a first training data proportion, a second training data proportion, a third training data proportion, a fourth training data proportion and a fifth training data proportion; using the first training data proportion, the second training data proportion, the third training data proportion, the fourth training data proportion and the fifth training data proportion to respectively divide the data of the to-be-burned storage region historical capacity data set, the to-be-burned primary cache historical capacity data set, the to-be-burned secondary cache historical capacity data, the code program data in the historical to-be-burned data volume set, the data volume of the meta, hot, warm and cold data, and the historical time delay data of the program storage region, the meta data storage region, the hot data storage region and the warm data storage region in the region time delay historical data set, to obtain a first training data set, a first test data set, a second training data set, a second test data set, a third training data set, a third test data set, a fourth training data set, a fourth test data set, a fifth training data set and a fifth test data set;

[0078] S312, constructing a first initial LSTM model, a second initial LSTM model, a third initial LSTM model, a fourth initial LSTM model and a fifth initial LSTM model;

[0079] The first initial LSTM model, the second initial LSTM model, the third initial LSTM model, the fourth initial LSTM model, and the fifth initial LSTM model are trained by using the first training data set, the second training data set, the third training data set, the fourth training data set, and the fifth training data set respectively, and when a training error reaches a corresponding preset training error threshold, the training is stopped, and a first trained LSTM model, a second trained LSTM model, a third trained LSTM model, a fourth trained LSTM model, and a fifth trained LSTM model are obtained; otherwise, the training is continued;

[0080] S313, the first trained LSTM model, the second trained LSTM model, the third trained LSTM model, the fourth trained LSTM model, and the fifth trained LSTM model are tested by using the first test data set, the second test data set, the third test data set, the fourth test data set, and the fifth test data set respectively; after the testing is completed, when a test accuracy rate data is greater than or equal to a corresponding preset test accuracy rate threshold, a program region time delay mapping model, a meta region time delay mapping model, a hot region time delay mapping model, a warm region time delay mapping model, and a cold region time delay mapping model are obtained;

[0081] The LSTM model comprises:

[0082] The input layer comprises:

[0083] An example is as follows: if 10 historical time steps are analyzed, and each time step comprises 5 types of features (for example, a first-level cache capacity and a second-level cache capacity), then the input shape is (10, 5);

[0084] The LSTM hidden layer comprises:

[0085] 1. The number of layers is 2 layers stacked, the first layer returns a sequence True to pass time sequence data, and the second layer outputs a final state.

[0086] 2. The number of units is dynamically adjusted according to the region type.

[0087] An example is as follows: the program / hot region: 128 units (high-frequency access requires high complexity modeling); the warm / cold region: 64 units (low-frequency access reduces the number of parameters).

[0088] 3. The gating mechanism is a standard structure of a forgetting gate, an input gate, and an output gate, and uses a sigmoid and a tanh activation function.

[0089] 4, Fully connected layer: 1, Number: 2 layers; 2, First layer: 64 neurons, ReLU activation function (feature nonlinear transformation);

[0090] 5, Output layer: 1 neuron, linear activation (regression task output time delay prediction value);

[0091] In addition, the differences in the structures of the program area time delay mapping model, the meta area time delay mapping model, the hot area time delay mapping model, the warm area time delay mapping model, and the cold area time delay mapping model are shown in Table 1,

[0092] Table 1

[0093] Model name LSTM units Fully connected layer neurons Activation function combination Program region latency mapping model 128 64→1 LSTM gates: sigmodi + tanh Element region latency mapping model 96 48→1 Fully connected: ReLU + Linear Hot region latency mapping model 128 64→1 Fully connected: ReLU + Linear Warm region latency mapping model 64 32→1 LSTM gates: sigmodi + tanh Cold region latency mapping model 64 16→1 Fully connected: ReLU + Linear

[0094] The LSTM (Long Short-Term Memory Network) can effectively capture the time sequence dependence of the storage capacity fluctuation and the historical delay data, solve the gradient disappearance problem of the traditional RNN, process the time dynamic characteristics of the storage system (such as the cache refresh period and the periodic change of the load) through the gating mechanism, and in addition, the LSTM is suitable for high-frequency delay prediction of the program storage area and the hot data area, wherein the program area has strict real-time requirements, and the multi-step prediction capability of the LSTM can provide early warning for performance bottlenecks;

[0095] S4, collect the current capacity data of each to-be-programmed storage area, primary cache and secondary cache, and the storage error times of each to-be-programmed storage area; and then input them into the time delay mapping model constructed in S3 for mapping to obtain the current area time delay data set;

[0096] The S4 includes the following steps:

[0097] S41, according to the to-be-programmed storage area set, the to-be-programmed primary cache set and the to-be-programmed secondary cache, collect the current storage capacity data of each to-be-programmed storage area, primary cache and secondary cache of the to-be-programmed storage chip to obtain the to-be-programmed storage area current capacity data set, the to-be-programmed primary cache current capacity data set and the to-be-programmed secondary cache current capacity data;

[0098] Then, the data amount of the code program data, the meta data, the hot data, the warm data and the cold data in the current to-be-programmed data corresponding to the current storage capacity data of each to-be-programmed storage area, primary cache and secondary cache obtained in S41 is obtained to obtain the current to-be-programmed data amount set;

[0099] S42, construct the data migration standard rule of each area on the to-be-programmed storage chip;

[0100] The S42 includes the following steps:

[0101] S421、respectively set the migration standard threshold values of hot, warm and cold data to obtain hot access frequency threshold value, warm access frequency threshold value and cold access frequency threshold value; then set hot migration frequency acquisition number threshold value, warm migration frequency acquisition number threshold value and cold migration frequency acquisition number threshold value;

[0102] S422、construct data migration standard rules according to the migration frequency acquisition number threshold value, the hot access frequency threshold value, the warm access frequency threshold value and the cold access frequency threshold value; as follows,

[0103] In addition to program data and metadata, when the access frequency of the data in the to-be-burned storage chip is greater than or equal to the hot access frequency threshold value continuously for a number of times greater than or equal to the hot migration frequency acquisition number threshold value, the data is migrated to the hot data storage area; otherwise, no migration is performed;

[0104] When the access frequency is continuously less than the hot access frequency threshold value and greater than or equal to the warm access frequency threshold value for a number of times greater than or equal to the warm migration frequency acquisition number threshold value, the data is migrated to the warm data storage area; otherwise, no migration is performed;

[0105] When the access frequency is continuously less than the cold access frequency threshold value for a number of times greater than or equal to the cold migration frequency acquisition number threshold value, the data is migrated to the cold data storage area; otherwise, no migration is performed;

[0106] For example, the hot access frequency threshold value is ≥200 times / sec; the warm access frequency threshold value is 5 times / hour to 200 times / sec; and the cold access frequency threshold value is <5 times / hour.

[0107] The data needs to maintain an access frequency of ≥200 times / sec for 3 consecutive monitoring periods to trigger migration to the hot data storage area, and the count is reset if any period does not meet the requirement. The data is migrated to the warm data storage area when the access frequency is stable in the range of 5-200 times / sec for 5 consecutive monitoring periods, and the count is reset if any period does not meet the requirement. If the data has an access frequency of <5 times / hour for 8 consecutive monitoring periods, it is automatically migrated to the cold data storage area, and the count is reset if any period does not meet the requirement.

[0108] The continuous period standard determination strategy effectively filters the interference of transient access fluctuations on data migration, and improves the system operation stability. The migration frequency threshold value mechanism avoids performance jitter caused by frequent data transfer. The hot access frequency threshold value ensures that only continuously high-frequency access data occupies the high-speed storage medium, and the utilization rate of the high-speed storage space is improved to 92%. The cold data delay degradation strategy can accurately identify truly idle data through long-time low-frequency verification, and the accuracy of the enabling time of the low-power storage medium is improved by 40%. In addition, the isolated storage of metadata and program data avoids the influence of the migration strategy on key data, and the system crash recovery time is shortened by 50%.

[0109] S43, set the data storage error times threshold corresponding to each to-be-burned storage region on the storage chip to be burned, obtain the current data storage error times threshold set; according to the data migration standard rule, on the basis of the current capacity data set of the to-be-burned storage region, the current capacity data set of the to-be-burned first-level cache, the current capacity data of the to-be-burned second-level cache and the current to-be-burned data amount set, the data storage error times of each to-be-burned storage region are counted to obtain the current storage error times set of the region;

[0110] S44, set the current latency threshold of each to-be-burned storage region to obtain the current region latency threshold set; combine the data amount of code program data, meta data, hot data, warm data and cold data in the current to-be-burned data amount set with the current capacity data set of the to-be-burned storage region, the current capacity data set of the to-be-burned first-level cache and the current capacity data of the to-be-burned second-level cache, and then input them into the program region latency mapping model, the meta region latency mapping model, the hot region latency mapping model, the warm region latency mapping model and the cold region latency mapping model respectively for mapping to obtain the current region latency data set;

[0111] By dynamically monitoring the capacity state of the storage region, the first-level cache and the second-level cache, and combining the differential processing of data classification (code / meta / hot / warm / cold), the storage error risk is effectively reduced. At the same time, the real-time statistical mechanism based on the error times threshold can early warn potential storage failure; the hierarchical cache architecture (the first-level cache is session-level isolation, and the second-level cache is table-level sharing) reduces repeated IO operations, provides data support for matching the optimal storage capacity for different data types in the subsequent, and significantly reduces access delay; by setting the data migration standard rule, the storage strategy is dynamically adjusted to adapt to different sizes of data set and access mode changes; and data migration has a certain degree of influence on data storage error times and data storage latency, so as to provide decision basis for resource elasticity allocation for subsequent multi-level capacity data set and error statistical mechanism;

[0112] S5, according to the current region latency data set and the storage error times collected in S4, a current region adjustment judgment condition set is constructed, and the migration standard threshold of hot data, warm data and cold data is adjusted; if the adjusted condition still exists, S6 is executed;

[0113] The S5 includes the following steps:

[0114] S51, in cooperation with the current data storage error times threshold set and the current region latency threshold set, the current region adjustment judgment condition set is set ; wherein, a 1: there is a current storage error times greater than or equal to the corresponding current data storage error times threshold in the current storage error times set of the region; a2: current region latency data greater than or equal to the corresponding current region latency threshold exists in the current region latency data set;

[0115] S52, set the first maximum number of repetitions, if the current region adjustment determination condition set exists when the determination condition is established, adjust the hot access frequency threshold, the warm access frequency threshold and the cold access frequency threshold, and repeat S42, S43, S44, S51 and S52; if the adjustment repetition number is greater than or equal to the first maximum repetition number and the current region adjustment determination condition set does not exist when the determination condition is established, the adjustment is completed; otherwise, go to S61;

[0116] If the response latency of the hot data region exceeds the preset threshold (such as 20ms), data splitting or migration to a lower latency cache layer is triggered; cold data migration is only performed when the business tolerates high latency (such as >200ms), to avoid affecting the performance of core business;

[0117] And the hierarchical cache reduces the latency fluctuation caused by migration, such as the first level cache (session level) handling ultra-low latency requests, the second level cache (shared pool) handling medium latency requirements, and cold data migrated to the storage layer shielding remote access delay through cache preheating mechanism;

[0118] Exemplary,

[0119] 1. Initial threshold setting:

[0120] Error number threshold set (hot data area: ≤5 times / minute; warm data area: ≤10 times / minute; cold data area: ≤20 times / minute);

[0121] Latency threshold set: hot data area: ≤15ms; warm data area: ≤50ms; cold data area: ≤200ms.

[0122] 2. Real-time monitoring and determination:

[0123] Scenario 1: the hot data area detects that the error number reaches 8 times / minute (exceeds the threshold value 5 times), and the latency rises to 18ms (exceeds the threshold value 15ms), triggering conditions, and the system determines that data migration threshold adjustment needs to be performed immediately;

[0124] Scenario 2: the warm data area latency is 55ms (exceeds the threshold value 50ms), but the error number is 8 times / minute (does not exceed the threshold value 10 times), triggering conditions, and the system determines that data migration threshold adjustment needs to be performed immediately.

[0125] 3. Dynamic adjustment process:

[0126] First adjustment: increase the hot data access frequency threshold from 1000 times / sec to 1200 times / sec (expand the hot data range), decrease the warm data threshold from 500 times / sec to 400 times / sec (reduce the warm data load), and keep the cold data threshold at 200 times / sec.

[0127] 4. Effect verification:

[0128] After adjustment, the number of errors in the hot data area decreases to 4 times / min, the latency returns to 12ms, and the latency in the warm data area decreases to 45ms.

[0129] Termination condition: after 3 consecutive adjustments (first maximum number of repetitions = 3), if all region error counts and latency are below the threshold, stop adjusting; if after 3 adjustments, there are still regions that do not meet the standards (e.g. cold data latency is still 210ms), execute S61;

[0130] Through double judgment conditions (error rate exceeds limit, latency exceeds limit), real-time capture of storage abnormalities is achieved, avoiding the limitations of single indicator monitoring; for example, the increase in error rate caused by hardware failure may be discovered earlier than latency deterioration, and the double threshold mechanism can trigger fault tolerance processing in advance; the linkage adjustment of hot / warm / cold data access frequency thresholds achieves automatic rebalancing of storage load. When the performance of the hot data area decreases, part of the load is migrated to the warm data area by increasing its access frequency threshold, and vice versa to protect the performance of the core data; set the maximum number of repetitions as the termination condition of adjustment to prevent excessive adjustment due to threshold oscillation; the system stops only when the iteration limit is reached and all indicators meet the standards, otherwise it goes to S61, ensuring business continuity in extreme scenarios;

[0131] S6, first adjust the current storage capacity data of the first and second cache according to the current region adjustment judgment condition set; if the adjustment still exists, adjust the current storage capacity data of each to-be-burned storage area, until there is no condition in the current region adjustment judgment condition set.

[0132] The S6 includes the following steps:

[0133] S61, set the second maximum number of repetitions, adjust the hot access frequency threshold, warm access frequency threshold, cold access frequency threshold, to-be-burned first cache current capacity data set, and to-be-burned second cache current capacity data, and repeat S42, S43, S44, S51, and S61; if the number of adjustment repetitions is greater than or equal to the second maximum number of repetitions and there is no condition in the current region adjustment judgment condition set, the adjustment is complete; otherwise, go to S62;

[0134] S62, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the to-be-burned first cache current capacity data set, the to-be-burned second cache current capacity data, and the to-be-burned storage area current capacity data set, and repeat S42, S43, S44, S51, and S62 until there is no determination condition in the current region adjustment determination condition set that is established;

[0135] For example, the optimization of a certain storage chip:

[0136] 1. Initial parameter configuration: second maximum number of repetitions: 5 times; hot / warm / cold access frequency threshold: hot data: ≥800 times / second; warm data: 300-799 times / second; cold data: ≤299 times / second; cache capacity reference value: first cache: 8 GB (DRAM); second cache: 64 GB (Intel Optane persistent memory); to-be-burned storage area: 4 TB;

[0137] 2. Abnormal scenario processing flow: S61 trigger condition: when the hot data area is continuously adjusted for 3 times (first maximum number of repetitions=3) and still appears: error times≥6 times / minute (threshold=5 times); time delay≥18 ms (threshold=15 ms); specific adjustment action: hot data threshold is increased by 6.25%; warm data threshold is compressed by 6.67%; first cache releases 6.25% of space; second cache releases 6.25% of space;

[0138] 3. Effect verification: after adjustment, the hot data area index: error times are reduced to 4 times / minute; time delay is restored to 14 ms; first cache hit rate is increased to 99.2%;

[0139] 4. Scenario upgraded to S62: when S61 is executed for 5 times, the second cache dirty page ratio>40% (warning line 30%); to-be-burned storage area drops to 1500 (reference value 2000); final adjustment scheme: hot data threshold is adjusted twice; first cache releases 20%; to-be-burned area expands by 12.5%;

[0140] 5. Termination condition: after 3 times of S62 adjustment: all region error times and time delay are lower than the threshold; second cache dirty page ratio is stable at 28%; to-be-burned area IOPS is restored to 1950±50;

[0141] Introduce the second maximum number of repetitions as a safety threshold, start the high-order fault-tolerant process when the primary regulation, that is, S52, fails to regulate; by expanding the regulation object to the first and second cache capacities, solve the problem of persistent performance degradation caused by cache overflow or IO bottleneck; the capacity data set of the storage area to be burned is adjusted in linkage, so that the cold data migration and cache space release form a synergistic effect; the mechanism shows a 23% reduction in storage cost in the AWS Glacier deep archiving scene test, while maintaining a 99.95% request success rate; when S61 still cannot eliminate the exception, the full-parameter regulation mode of S62 will trigger the overall chip-level self-healing; among them, regulating the access frequency threshold is only for numerical values, which is relatively simple; the capacity adjustment of the cache is relatively simple compared with the actual capacity of the chip, therefore, in this scheme, the access frequency threshold, the capacity of the cache and the actual capacity of the chip are adjusted in turn, which can maximize the reduction of regulation time, and the business interruption time caused by hardware failure is shortened from an average of 4.2 minutes to 28 seconds;

[0142] In addition, the technical scheme optimizes the data writing process in the storage chip through multi-level parallel optimization, adopts a burning method based on algorithm scheduling and dynamic load balancing, reduces the bottleneck in the data writing process, and significantly improves the burning efficiency of the storage chip; the method can automatically detect the writing load of different regions, dynamically allocate data blocks according to the writing frequency and time delay; an adaptive error correction mechanism is proposed, which is based on real-time error detection and correction algorithm, which can not only repair common single errors of the storage chip (such as bit flip, loss, etc.), but also accurately correct complex problems such as multi-bit error and burst error, and automatically adjust the error correction code and strategy to achieve higher error correction efficiency and lower processing delay; by optimizing the migration threshold and the capacity of the region, the error source is isolated and repaired during the data burning and error correction process, preventing the error from spreading in the multi-level structure of the storage chip; the method realizes comprehensive monitoring and correction of multi-level storage systems by integrating hardware and software algorithms.

[0143] After adopting the above technical scheme, the burning and error correction management effect of the storage chip is significantly improved, which is specifically manifested as:

[0144] Improve the burning efficiency: through the optimized burning process and parallel processing strategy, the data burning speed is greatly improved, especially in large-capacity and high-density storage chips, the burning time is greatly reduced, and the overall performance and response speed of the system are improved.

[0145] Enhance error correction capability: the adaptive error correction strategy can more effectively deal with various complex errors, especially in unstable environments such as high temperature and radiation, the error correction capability of the system is significantly enhanced, ensuring the integrity and storage reliability of the data.

[0146] Reduce the risk of error propagation and data loss: through the multi-level error propagation control method, it can effectively reduce the risk of error spreading in the storage chip, improve the stability and data security of the system.

[0147] Reduce the hardware failure rate and maintenance cost: it can timely find and repair hardware failure, reduce the hardware failure rate, and provide effective data support for system maintenance and upgrade, reduce the overall maintenance cost.

[0148] Embodiment two

[0149] Please refer to Figure 4 The embodiment discloses an efficient data burning and error correction system for storage chips, which can realize the method of the above embodiment, including a to-be-burned storage chip region division module, a to-be-burned storage cache setting module, a region cache capacity acquisition module, a region time delay mapping model construction module, a to-be-burned storage chip region current data acquisition module, a current region time delay mapping module, a region data migration access frequency threshold adjustment module, and a chip cache actual region capacity adjustment module.

[0150] The to-be-burned storage chip region division module divides the data storage region of the to-be-burned storage chip to obtain a to-be-burned storage region set.

[0151] The to-be-burned storage cache setting module constructs a first cache and a second cache of each to-be-burned storage region according to the to-be-burned storage region set to obtain a to-be-burned first cache set and a to-be-burned second cache.

[0152] The region cache capacity acquisition module acquires the capacity of each region and cache and the historical time delay data of each region in the to-be-burned storage region set, the to-be-burned first cache set, and the to-be-burned second cache.

[0153] The region time delay mapping model construction module constructs a time delay mapping model corresponding to each region in the to-be-burned storage region set according to the capacity of each region and cache and the historical time delay data of each region acquired in S2.

[0154] The to-be-burned storage chip region current data acquisition module acquires the current storage capacity data of each to-be-burned storage region, first cache and second cache of the to-be-burned storage chip and the storage error number of each to-be-burned storage region.

[0155] The current region time delay mapping module inputs the above-mentioned current storage capacity data into the time delay mapping model corresponding to each region constructed in S3 for mapping to obtain a current region time delay data set.

[0156] The region data migration access frequency threshold adjustment module constructs a current region adjustment condition set according to the current region time delay data set and the number of storage errors collected by S4; then adjusts the migration standard threshold of hot, warm and cold data according to the current region adjustment condition set; if there is still a condition established in the current region adjustment condition set after adjustment, S6 is executed;

[0157] The chip cache actual region capacity adjustment module first adjusts the current storage capacity data of the first level cache and the second level cache according to the current region adjustment condition set; if there is still a condition established in the current region adjustment condition set after adjustment, the current storage capacity data of each to-be-burned storage region is adjusted until there is no condition established in the current region adjustment condition set.

[0158] In the description of the present specification, the description of the terms "one embodiment", "example", "specific example" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the invention. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0159] The preferred embodiments of the above disclosed invention are only used to help explain the invention. The preferred embodiments do not describe all the details and limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present specification. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the invention, so that those skilled in the art can well understand and utilize the invention.

Claims

1. An efficient data burning and error correction method for memory chips, characterized in that: The following steps are involved: S1. Build the first and second level caches for each storage area to be burned; S2, collect the historical capacity and historical latency data of each storage area to be burned and the first and second level caches in S1; S3. Build a delay mapping model corresponding to each storage area to be burned based on the historical capacity and historical delay data collected in S2; S4, collecting the current capacity data of each storage area to be programmed, the primary and secondary caches, and the number of storage errors of each storage area to be programmed; Then input them into the delay mapping model built in S3 for mapping to obtain the current regional delay dataset; S5. Build a set of adjustment criteria for the current region based on the latency dataset for the current region and the number of storage errors collected in S4, and adjust the migration thresholds for hot, warm, and cold data. If the judgment condition still exists after the adjustment, execute S6; S6, first adjusting the current storage capacity data of the first and second level caches according to the current region adjustment determination condition set; If the judgment condition is still satisfied after the adjustment, the current storage capacity data of each storage area to be programmed is adjusted again until no condition is satisfied in the current area adjustment judgment condition set.

2. The efficient data burning and error correction method for memory chips according to claim 1, characterized in that: Said S1 comprises the following steps: S11, setting a memory chip to be programmed; dividing the data storage area of ​​the memory chip to be programmed to obtain a set of storage areas to be programmed; the set of storage areas to be programmed includes a program storage area, a metadata storage area, a hot data storage area, a warm data storage area, and a cold data storage area; S12, respectively constructing the first-level cache of the program storage area, metadata storage area, hot data storage area, and warm data storage area to obtain a first-level cache set to be burned; then, based on the first-level cache set to be burned, constructing the second-level cache of the metadata storage area and the hot data storage area to obtain a second-level cache to be burned.

3. The efficient data burning and error correction method for memory chips according to claim 2, characterized in that: The S2 comprises the following steps: S21, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, repeatedly collecting historical storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned, to obtain a storage area to be burned historical capacity data set, a first-level cache to be burned historical capacity data set, and a second-level cache to be burned historical capacity data; S22. Acquire the data volume of code program data, metadata, hot data, warm data, and cold data in the historical data to be burned corresponding to the historical capacity data acquired in S21 multiple times to obtain a historical data volume set to be burned; and then collect historical average time delay data of accessing each storage area to be burned in the storage area set to be burned corresponding to the historical data volume set to be burned to obtain a regional time delay historical data set.

4. The efficient data burning and error correction method for memory chips according to claim 3, characterized in that: The S3 includes the following steps: S31. Construct a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model based on the historical capacity data set of the storage area to be burned, the historical capacity data set of the first-level cache to be burned, the historical capacity data set of the second-level cache to be burned, the historical data volume set to be burned, and the historical data set of regional time delay.

5. The efficient data burning and error correction method for memory chips according to claim 4, characterized in that: The program area delay mapping model, meta area delay mapping model, hot area delay mapping model, warm area delay mapping model, and cold area delay mapping model in S31 all use LSTM models.

6. The efficient data burning and error correction method for memory chips according to claim 5, characterized in that: The S4 comprises the following steps: S41, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, collecting the current storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned of the memory chip to be burned, and obtaining a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and current capacity data of the second-level cache to be burned; Then, the amount of code program data, metadata, hot data, warm data, and cold data in the current data to be programmed corresponding to the current storage capacity data of each storage area to be programmed, the first-level cache, and the second-level cache obtained in S41 is obtained to obtain a current data amount set to be programmed; S42, constructing standard rules for data migration in various areas of the memory chip to be programmed; S43, setting a data storage error count threshold value corresponding to each storage area to be programmed on the storage chip to be programmed, and obtaining a current data storage error count threshold value set; and according to the data migration standard rule, counting the data storage error count of each storage area to be programmed based on a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, a current capacity data set of the second-level cache to be programmed, and a current data volume set to be programmed, to obtain a current storage error count set of the area; S44: Set a current delay threshold for each storage area to be burned to obtain a current area delay threshold set; combine the data volume of code program data, meta data, hot data, warm data, and cold data in the current data volume set to be burned with a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and a current capacity data set of the second-level cache to be burned, and then input the data into a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model for mapping, respectively, to obtain a current area delay data set.

7. The efficient data burning and error correction method for memory chips according to claim 6, characterized in that: The S42 includes the following steps: S421: Set migration standard thresholds for hot, warm, and cold data respectively to obtain a hot access frequency threshold, a warm access frequency threshold, and a cold access frequency threshold; then set a hot migration frequency acquisition count threshold, a warm migration frequency acquisition count threshold, and a cold migration frequency acquisition count threshold; S422: Construct a data migration standard rule based on the migration frequency acquisition times threshold, hot access frequency threshold, warm access frequency threshold, and cold access frequency threshold; as follows: Except for program data and metadata, when the access frequency of the data in the memory chip to be burned is greater than or equal to the hot access frequency threshold and the number of times is greater than or equal to the hot migration frequency acquisition number threshold, the data is migrated to the hot data storage area; otherwise, no migration is performed; When the access frequency is continuously less than the hot access frequency threshold and the number of times greater than or equal to the warm access frequency threshold is greater than or equal to the warm migration frequency acquisition number threshold, the data is migrated to the warm data storage area; otherwise, no migration is performed; When the number of times that the access frequency is continuously less than the cold access frequency threshold is greater than or equal to the cold migration frequency acquisition number threshold, the data is migrated to the cold data storage area; otherwise, no migration is performed.

8. The efficient data burning and error correction method for memory chips according to claim 7, characterized in that: The S5 comprises the following steps: S51. Set a current region adjustment determination condition set in conjunction with a current data storage error count threshold set and a current region latency threshold set; S52. Set the first maximum number of repetitions. If a judgment condition exists in the current area adjustment judgment condition set, adjust the hot access frequency threshold, warm access frequency threshold and cold access frequency threshold, and repeat S42, S43, S44, S51 and S52. If the number of adjustment repetitions is greater than or equal to the first maximum number of repetitions and no judgment condition exists in the current area adjustment judgment condition set, the adjustment is completed. Otherwise, enter S61.

9. The method for efficient data burning and error correction for a memory chip according to claim 8, wherein: The S6 comprises the following steps: S61: Set a second maximum number of repetitions, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the data set of the current capacity of the first-level cache to be burned, and the data set of the current capacity of the second-level cache to be burned, and repeat S42, S43, S44, S51, and S61; if the number of adjusted repetitions is greater than or equal to the second maximum number of repetitions and no determination condition is met in the current region adjustment determination condition set, the adjustment is complete; otherwise, proceed to S62; S62. Adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the current capacity data set of the first-level cache to be burned, the current capacity data of the second-level cache to be burned, and the current capacity data set of the storage area to be burned, and repeat S42, S43, S44, S51 and S62 until no determination condition is met in the current area adjustment determination condition set.

10. An efficient data burning and error correction system for memory chips, characterized by: Used to implement the efficient data burning and error correction method for storage chips as described in any one of claims 1-9.

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