Packaging method of IGBT chip with ultra-large current plane

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a packaging method of a super-large current plane IGBT (Insulated Gate Bipolar Translator) chip. According to the technical scheme, the method comprises the following steps that 1, a high-thermal-conductivity copper-molybdenum alloy substrate with the thermal expansion coefficient close to that of a silicon material is provided; step 2, bonding an IGBT chip to the upper surface of the substrate through a silver sintering technology in a pressure welding process; step 3, current parallel distribution of a plurality of chips is realized by adopting a multi-point voltage-sharing wiring structure, and thermal resistance and resistance coupling design is carried out on each chip path; step 4, introducing a thermal resistance adjusting method based on a position-dependent variable coefficient in the packaging process; and step 5, carrying out passivation treatment on the surface of the chip through plasma treatment, and completing structure curing by using a low-stress molding packaging material. Through the collaborative design of the copper-molybdenum gradient substrate and the current-sharing packaging structure, thermal stress slow release, current balance and interface reliability improvement are realized, and the packaging performance and the service life of the ultra-large current IGBT chip are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging method for an ultra-large current planar IGBT chip. Background Art

[0002] As a power electronic device that combines the high-speed switching capabilities of a MOSFET with the high-current carrying capacity of a BJT, the insulated-gate bipolar transistor (IGBT) holds broad application prospects in high-power applications such as new energy vehicles, rail transit, power conversion, and high-voltage direct current transmission. As power density continues to increase, planar IGBT chips with ultra-high current ratings (≥800A) are becoming the mainstream choice for module packaging.

[0003] However, in existing technologies, IGBT chip packaging still faces the following key technical challenges: Serious thermal expansion mismatch between the chip and substrate: IGBT chips are typically made of silicon or SiC materials, and the thermal expansion coefficient of traditional substrates differs significantly from that of the chip. This results in periodic stress at the interface during power thermal cycling, which can easily cause microcracks in the silver sintering layer and ultimately lead to package failure. Uneven current density causes hotspot concentration: Under high current operating conditions, if the chip surface wiring structure is not properly optimized, current concentration paths are likely to occur, leading to local overheating or electromigration failure. Difficulty balancing substrate thermal conductivity and structural matching: Traditional copper-molybdenum alloys have a homogeneous structure, which cannot balance the stress buffering requirements of the upper layer and the heat dissipation and thermal conductivity requirements of the lower layer, resulting in high thermal resistance and limited overall package stability. The package life is limited by structural rigidity: under high voltage and high current conditions, the chip structure is subjected to large shear stress during thermal cycling, and the interface design of the traditional packaging structure cannot effectively release thermal mechanical strain.

[0004] To this end, we propose a packaging method for ultra-high current planar IGBT chips to solve the existing problems. Summary of the Invention

[0005] The purpose of the present invention is to address the problems existing in the background technology and to propose a packaging method for an ultra-high current planar IGBT chip.

[0006] To achieve the above object, the present invention provides the following technical solution: a packaging method for an ultra-high current planar IGBT chip, comprising the following steps: Step 1, providing a high thermal conductivity copper-molybdenum alloy substrate having a thermal expansion coefficient close to that of silicon material; Step 2: Bonding the IGBT chip to the upper surface of the substrate using silver sintering technology in a pressure welding process to achieve chip fixation with high thermal performance and high mechanical strength; Step 3: Use a multi-point voltage-balanced wiring structure to achieve parallel current distribution for multiple chips. Each chip path is designed with thermal resistance and resistance coupling to ensure balanced current distribution across the current path in the package structure and avoid single-point thermal failure caused by current concentration. Step 4: Introduce a thermal resistance adjustment method based on position-dependent variable coefficients during the packaging process to control the uniformity of heat flow diffusion within the chip or at different locations of the module, thereby enhancing the overall heat dissipation performance; Step 5: Passivate the chip surface through plasma treatment and use low-stress molding packaging materials to complete structural solidification to improve the long-term reliability and anti-puncture capability of the chip under high temperature and high current density conditions.

[0007] Preferably, the heat diffusion design in step 4 realizes the non-uniform distribution control of thermal resistance by constructing a function model with the spatial position of the chip surface as a variable. In this function model, the center point of the chip has the minimum thermal resistance value, while the thermal resistance gradually increases towards the edge of the chip, and the increase is in a certain power exponential function relationship with the sum of the squares of the chip coordinates. This model can more realistically reflect the changing trend of the heat flux density inside the package, thereby effectively alleviating the problem of thermal stress concentration.

[0008] Preferably, in the design of current distribution between parallel chip paths in step 3, a current distribution function model is established, and the comprehensive resistance and thermal resistance coupling factor of each path are used as weighted basis to ensure that the total current is reasonably distributed according to the path performance ratio. This method significantly improves the uneven current phenomenon caused by impedance differences in traditional parallel packaging.

[0009] Preferably, the thickness of the silver sintered layer between the chip and the substrate in step 2 shows a periodic change trend during the sintering temperature change process. This change trend is regulated by the thermal expansion compensation factor to ensure that the sintered layer still has good interface contact and thermal conductivity under high temperature conditions. By constructing a thickness change model based on temperature variables, this method further improves the reliability of the chip in a high temperature environment.

[0010] Preferably, the packaging structure in step 5 reduces the thermomechanical mismatch stress at the material interface by minimizing the welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of the transverse and longitudinal thermal stresses, as well as the Poisson effect of the material on the overall stress field, thereby improving the overall mechanical strength and thermal shock resistance of the package.

[0011] Preferably, the thermal density optimization design in step 3 achieves dynamic matching of the package heat dissipation capacity and the power processing capacity by establishing a relationship model between the power load per unit package area and the average thermal resistance. This model helps to determine the optimal package area to power density ratio, thereby improving the overall heat dissipation efficiency of the device without expanding the package size.

[0012] Preferably, the power cycle life assessment model in step 5 is based on the coupling relationship between the temperature cycle amplitude, the average junction temperature and the material activation energy, and is estimated using an exponential function established with empirical fitting parameters. This model can be used to accurately predict the fatigue life of the packaging structure under long-cycle, high-power cycles, thereby providing a theoretical basis for packaging material selection and structural optimization.

[0013] Preferably, the temperature distribution inside the package in step 4 establishes a Gaussian distribution superposition model based on the dual heat source diffusion effect, which describes that the temperature at the center of the chip is the highest, and it shows an exponential decay trend along two directions, and finally approaches the substrate temperature. This temperature distribution model can effectively reflect the position and area of the hot spot inside the package, which helps to assist in wiring and module layout design to avoid hot spot risks.

[0014] Preferably, the copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, in which the arrangement ratio of the copper layer and the molybdenum layer is nonlinearly distributed along the thickness direction, so that the overall thermal expansion coefficient of the substrate is more accurately matched with the silicon material on the side close to the chip, thereby reducing the thermal stress coupling between the chip and the substrate, wherein the nonlinear distribution relationship is: near the chip interface, the copper layer accounts for the smallest proportion, and as the distance from the chip surface increases, the copper layer proportion increases layer by layer, and the specific change trend satisfies a power function model that changes along the thickness direction, so as to optimize the thermal stress gradient distribution and improve the thermal shock life.

[0015] Compared with the prior art, the present invention has the following beneficial effects: Dynamic thermal stress adaptive release: Using a copper-molybdenum alloy gradient structure substrate, the copper volume fraction is distributed and controlled along the thickness direction using a nonlinear power function. This ensures that the chip interface area has a low thermal expansion coefficient, and the middle and bottom areas gradually transition to high thermal conductivity areas. While maintaining mechanical integrity, it effectively releases thermal shock stress and improves the stability and reliability of the package interface. Package thermal resistance is reduced by over 10%: The high copper content at the bottom of the gradient copper-molybdenum structure provides an excellent thermal conduction path. This, in synergy with the stress buffering area at the top, significantly reduces the overall thermal resistance of the package and the chip junction temperature, meeting the requirements of long-term high-current operation scenarios. Improving the consistency of multi-chip current sharing: A multi-point current sharing structure is introduced into the chip top wiring. Combined with the thermal resistance-resistance coupling optimization design of the wiring path, the current deviation of each chip is effectively controlled. The maximum deviation is less than ±5%, avoiding failures caused by local overload or hot spots. Enhanced silver sintering interface reliability: By optimizing the substrate thermal expansion matching relationship and surface plasma cleaning / passivation treatment, the adhesion performance and thermal cycle life of the silver sintering layer are significantly improved. After 3,000 power cycles, the interface resistance increases by less than 10%, and no detectable cracks are found. Compatible with mass production process routes: The copper-molybdenum composite material, silver sintering process, and molded packaging method used are highly compatible with existing high-end IGBT module production line processes, eliminating the need for large-scale equipment replacement and demonstrating good industrial feasibility and promotion prospects. In summary, the method proposed in the present invention is not only significantly innovative in structural design, but also achieves technological breakthroughs in thermal performance, electrical balance and packaging stability. It is suitable for planar IGBT module packaging with current levels of 1200A and above, and is particularly suitable for industrial and new energy applications with high reliability and high life requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of the copper-molybdenum alloy substrate of the present invention; Figure 2 For the present invention Figure 1 Schematic diagram of text description distributed along the thickness direction; Figure 3 Schematic diagram of the gradient copper content function of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] Example 1 like Figure 1-Figure 3 As shown, the present invention proposes a packaging method for an ultra-high current planar IGBT chip, comprising the following steps: Step 1: Provide a high thermal conductivity copper-molybdenum alloy substrate with a thermal expansion coefficient close to that of silicon material. The copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, wherein the arrangement ratio of the copper layer and the molybdenum layer is nonlinearly distributed along the thickness direction, so that the thermal expansion coefficient of the entire substrate is more accurately matched with the silicon material on the side close to the chip, thereby reducing the thermal stress coupling between the chip and the substrate. The nonlinear distribution relationship is as follows: near the chip interface, the copper layer accounts for the smallest proportion, and as the distance from the chip surface increases, the copper layer proportion increases layer by layer. The specific change trend satisfies a power function model that changes along the thickness direction, so as to optimize the thermal stress gradient distribution and improve the thermal shock life. The volume fraction C(h) of the copper layer at a depth of h from the chip contact surface satisfies the following power function relationship:

[0019] In the above parameters: represents the volume fraction of the copper layer at a depth of h from the chip surface; h represents the depth from the chip contact surface, ranging from 0 to H; H is the total thickness of the entire copper-molybdenum alloy substrate; is the initial volume fraction of copper at the substrate surface (h = 0); is the maximum volume fraction of copper at the bottom of the substrate (h=H); k is the power exponent that controls the curvature of the volume fraction change, and its value is greater than zero.

[0020] By adjusting the parameters 、 By adjusting the value of k, the proportion of the copper layer gradually increases from the surface to the inside, so that the thermal expansion behavior of the area close to the chip is closer to the characteristics of the silicon chip, effectively reducing the interface stress concentration caused by thermal mismatch, and improving the mechanical stability and thermal reliability of the package structure under thermal cycling conditions.

[0021] In step 2, the IGBT chip is bonded to the upper surface of the substrate through the silver sintering technology in the pressure welding process to achieve chip fixation with high thermal performance and high mechanical strength. In step 2, the thickness of the silver sintering layer between the chip and the substrate shows a periodic change trend during the sintering temperature change process. This change trend is regulated by the thermal expansion compensation factor to ensure that the sintering layer still has good interface contact and thermal conductivity under high temperature conditions. By constructing a thickness change model based on temperature variables, this method further improves the reliability of the chip in a high temperature environment. The thickness of the silver sintering layer satisfies the dynamic optimization function relationship:

[0022] in: is the thickness of the sintered silver layer at temperature T (K); is the initial sintering thickness at room temperature; is the thermal expansion compensation factor; It is the highest temperature of the sintering process.

[0023] Step 3: Use a multi-point voltage-sharing wiring structure to achieve parallel current distribution of multiple chips, where each chip path is designed with thermal resistance and resistance coupling to ensure balanced current distribution in each current path in the package structure and avoid single-point thermal failure caused by current concentration. In the design of current distribution between parallel chip paths in step 3, by establishing a current distribution function model, the comprehensive resistance and thermal resistance coupling factor of each path are used as the weighting basis to ensure that the total current is reasonably distributed according to the path performance ratio. This method significantly improves the uneven current phenomenon caused by impedance differences in traditional parallel packaging, and its current balancing function meets the following distribution optimization conditions:

[0024] in: is the actual operating current of the ith parallel chip path, is the total design current, is the thermal-resistance coupling coefficient of the i-th path (reflecting the influence of line width, solder layer, and copper foil thermal resistance).

[0025] Furthermore, the thermal density optimization design in step 3 achieves dynamic matching between the package heat dissipation capacity and the power handling capacity by establishing a relationship model between the power load per unit package area and the average thermal resistance. This model helps determine the optimal package area to power density ratio, thereby improving the overall heat dissipation efficiency of the device without increasing the package size. The package thermal density optimization objective function is:

[0026] in: is the thermal power density per unit area (W / mm²·K), is the maximum operating power of the package, is the package projected area, is the average thermal resistance.

[0027] In step 4, a thermal resistance adjustment method based on position-dependent variable coefficient is introduced during the packaging process to control the diffusion uniformity of heat flow inside the chip or at different locations of the module, thereby enhancing the overall heat dissipation performance. In step 4, the heat diffusion design realizes the non-uniform distribution control of thermal resistance by constructing a function model with the spatial position of the chip surface as a variable. In this function model, the center of the chip has the minimum thermal resistance value, while the thermal resistance gradually increases towards the edge of the chip, and the increase is in a certain power exponential function relationship with the sum of the squares of the chip coordinates. This model can more realistically reflect the changing trend of the heat flux density inside the package, thereby effectively alleviating the problem of thermal stress concentration. Its heat diffusion balance function is defined as:

[0028] in: is the thermal resistance reference value of the chip center point (unit: K / W), (x,y) is the coordinate of any point on the chip (unit: mm), is the chip side length (unit: mm), 、 is the nonlinear expansion coefficient and exponent of material heat flow (independent of dimension).

[0029] Furthermore, in step 4, the temperature distribution inside the package is modeled based on the dual heat source diffusion effect to establish a Gaussian distribution superposition model. This model describes the highest temperature at the center of the chip, which decays exponentially in both directions, ultimately approaching the substrate temperature. This temperature distribution model can effectively reflect the location and area of hot spots inside the package, helping to assist in wiring and module layout design to avoid hot spot risks. Its internal temperature distribution function is approximately a double Gaussian superposition model:

[0030] in: is the temperature at any point inside the package, is the maximum temperature rise at the center point, ( , ) is the center position of the heat source, 、 is the standard deviation of thermal diffusion, is the substrate temperature.

[0031] Step 5: Passivate the chip surface through plasma treatment and use low-stress molding packaging materials to complete structural curing to improve the long-term reliability and anti-puncture capability of the chip under high temperature and high current density conditions. In step 5, the packaging structure reduces the thermomechanical mismatch stress at the material interface by minimizing the welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of transverse and longitudinal thermal stresses, as well as the Poisson effect of the material on the overall stress field, thereby improving the overall mechanical strength and thermal shock resistance of the package. The welding stress minimization function is:

[0032] in: is the equivalent stress, 、 is the thermal stress along the X and Y axes, is the Poisson's ratio of the material.

[0033] Furthermore, the power cycle life assessment model in step 5 is based on the coupling relationship between the temperature cycle amplitude, average junction temperature and material activation energy, and uses an exponential function established with empirical fitting parameters for estimation. This model can be used to accurately predict the fatigue life of the package structure under long-cycle, high-power cycles, thereby providing a theoretical basis for package material selection and structure optimization. Its power cycle life prediction function is:

[0034] in: is the expected number of power cycles, is the temperature difference cycle amplitude, is the average junction temperature, is the reference temperature, is the material activation energy, is the Boltzmann constant, 、 is the empirical constant of the packaging structure.

[0035] The above specific embodiments are only several preferred embodiments of the present invention. Based on the technical solutions of the present invention and the relevant inspirations of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

[0036] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

Claims

1. A packaging method for an ultra-high current planar IGBT chip, characterized in that: The following steps are involved: Step 1, providing a high thermal conductivity copper-molybdenum alloy substrate having a thermal expansion coefficient close to that of silicon material; Step 2: Bonding the IGBT chip to the upper surface of the substrate using silver sintering technology in a pressure welding process to achieve chip fixation with high thermal performance and high mechanical strength; Step 3: Use a multi-point voltage-balanced wiring structure to achieve parallel current distribution for multiple chips. Each chip path is designed with thermal resistance and resistance coupling to ensure balanced current distribution across the current path in the package structure and avoid single-point thermal failure caused by current concentration. Step 4: Introduce a thermal resistance adjustment method based on position-dependent variable coefficients during the packaging process to control the uniformity of heat flow diffusion within the chip or at different locations of the module, thereby enhancing the overall heat dissipation performance; Step 5: Passivate the chip surface through plasma treatment and use low-stress molding packaging materials to complete structural solidification to improve the long-term reliability and anti-puncture capability of the chip under high temperature and high current density conditions.

2. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: The heat diffusion design in step 4 achieves non-uniform distribution control of thermal resistance by constructing a function model with the spatial position of the chip surface as a variable. In this function model, the center of the chip has the minimum thermal resistance value, while the thermal resistance gradually increases towards the edge of the chip, and the increase is in a power exponential function relationship with the sum of the squares of the chip coordinates.

3. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: In the design of current distribution between parallel chip paths in step 3, a current distribution function model is established, and the comprehensive resistance and thermal resistance coupling factor of each path are used as weighting basis to ensure that the total current is reasonably distributed according to the path performance ratio.

4. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: In step 2, the thickness of the silver sintered layer between the chip and the substrate shows a periodic change trend during the sintering temperature change process. This change trend is regulated by the thermal expansion compensation factor to ensure that the sintered layer still has good interface contact and thermal conductivity under high temperature conditions, and to construct a thickness change model based on temperature variables.

5. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: In step 5, the packaging structure reduces the thermomechanical mismatch stress at the material interface by minimizing the welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of transverse and longitudinal thermal stresses, as well as the Poisson effect of the material on the overall stress field.

6. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: The thermal density optimization design in step 3 achieves dynamic matching between the package heat dissipation capability and the power handling capability by establishing a relationship model between the power load per unit package area and the average thermal resistance. This model helps determine the optimal package area to power density ratio.

7. The packaging method of a planar IGBT chip with ultra-high current according to claim 1, characterized in that: The power cycle life assessment model in step 5 is based on the coupling relationship between the temperature cycle amplitude, the average junction temperature and the material activation energy, and is estimated using an exponential function established with empirical fitting parameters. This model can be used to accurately predict the fatigue life of the packaging structure under long-cycle, high-power cycles.

8. The method for packaging an ultra-high current planar IGBT chip according to claim 1, wherein: In step 4, the temperature distribution inside the package is based on the dual heat source diffusion effect to establish a Gaussian distribution superposition model, which describes that the temperature at the center of the chip is the highest, and it shows an exponential decay trend along two directions, and finally approaches the substrate temperature. This temperature distribution model can effectively reflect the position and area of the hot spot inside the package.

9. The method for packaging an ultra-high current planar IGBT chip according to claim 1, wherein: The copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, in which the arrangement ratio of the copper layer and the molybdenum layer is nonlinearly distributed along the thickness direction, so that the overall thermal expansion coefficient of the substrate is more accurately matched with the silicon material on the side close to the chip, thereby reducing the thermal stress coupling between the chip and the substrate. The nonlinear distribution relationship is as follows: near the chip interface, the copper layer accounts for the smallest proportion, and as the distance from the chip surface increases, the copper layer proportion increases layer by layer. The specific change trend satisfies a power function model that varies along the thickness direction, which is used to optimize the thermal stress gradient distribution and improve the thermal shock life.

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