Method of monitoring chamber drift

Abstract

A method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles are provided, where each cycle includes depositing a deposition layer over a chuck in a plasma processing chamber, plasma etching the deposition layer, and measuring a time for plasma etching the deposition layer to etch through the deposition layer. The measured time for plasma etching is used to determine the drift of the plasma processing chamber.

Description

This application is a divisional application of the application with application number 201980015547.X, application date February 21, 2019, and invention name “Method for monitoring chamber drift”. CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 15 / 906,332, filed February 27, 2018, which is incorporated herein by reference for all purposes. Technical Field

[0002] The present disclosure relates to the formation of semiconductor devices. More particularly, the present disclosure relates to forming semiconductor devices in a plasma processing chamber for depositing and etching layers. Background Art

[0003] In semiconductor processing, blank wafers may be processed and then removed from the chamber to be measured using metrology tools to determine the condition and performance of the chamber. Summary of the Invention

[0004] To achieve the aforementioned objectives and in accordance with the present disclosure, a method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles are provided, wherein each cycle includes depositing a deposition layer on a chuck in the plasma processing chamber, plasma etching the deposition layer, and measuring the time it takes for the plasma to etch through the deposition layer. The measured time for the plasma etching is used to determine drift of the plasma processing chamber.

[0005] These and other features of the present disclosure will be described in more detail below in the detailed description of the disclosure and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings and in which like references indicate similar elements and in which:

[0007] Figure 1 is a high-level flow chart of an implementation plan.

[0008] Figure 2 is a schematic diagram of a plasma processing chamber that may be used in one embodiment.

[0009] Figure 3 is a schematic diagram of a computer system that can be used to implement one embodiment.

[0010] Figure 4A -B is a cross-sectional view of a portion of an ESC processed according to one embodiment.

[0011] Figure 5A -B is a cross-sectional view of a portion of a stack processed according to another embodiment. DETAILED DESCRIPTION

[0012] The present disclosure will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without some or all of these specific details. In other cases, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0013] Integrated circuit manufacturers monitor tool parameters, such as deposition and etch rates, to maintain control over yield. Deposition rates are collected by depositing material and then measuring the deposited thickness or some other parameter at a location outside the deposition chamber to determine thickness using metrology tools. Etch rates are determined by loading pre-deposited wafers with known thickness (as measured by metrology tools) into the etch module. The wafers are then etched, and ex situ measurements are taken using metrology tools to determine the amount of material removed. Using such test wafers to monitor wafers increases costs and reduces tool utilization in the fab. Increased monitoring can help identify tool problems more quickly, resulting in less product loss. However, increased monitoring also means less product uptime. Furthermore, there is the cost of using test wafers to monitor tools. The fab must purchase or invest time in the deposition tool to create test wafers for the etch tool. The deposition tool must give up operating space or tool time to run deposition monitoring. Maintaining a recycling cycle for reused wafers is also costly.

[0014] If a fab can monitor tool performance parameters such as flow rate, power, and pressure and correlate them with etch and deposition rates, it provides a way for the fab to monitor tool health without constantly running monitoring test wafers. The downside is that the deposition and etch rates are unknown. As a result, drift in deposition and etch rates due to chamber adjustments, tool idle time, and contamination are not detected by tool performance parameters.

[0015] For ease of understanding, Figure 11 is a high-level flow chart of one embodiment. A deposited layer is deposited (step 104). The deposited layer is plasma etched (step 108). The time taken to etch the deposited layer is measured (step 112). Steps 104 to 112 may be repeated one or more times (step 116). The measured time is used to determine the drift of the plasma processing chamber (step 120). Steps 104 to 120 may be repeated one or more times (step 124). When it is determined that the plasma processing chamber has drifted too far, the plasma processing chamber is adjusted (step 128). Example

[0016] Figure 2 2 is a schematic diagram of a plasma processing chamber that can be used in one embodiment. In one or more embodiments, plasma processing chamber 200 includes a gas distribution plate 206 providing a gas inlet and an electrostatic chuck (ESC) 208 within a chamber 249 surrounded by chamber walls 252. Within chamber 249, wafer 203 is positioned above ESC 208, which is a substrate support. Edge ring 209 surrounds ESC 208. ESC source 248 can provide bias to ESC 208. Gas source 210 is connected to chamber 249 via gas distribution plate 206. ESC temperature controller 250 is connected to ESC 208. Radio frequency (RF) source 230 provides RF power to a lower electrode and / or an upper electrode, which in this embodiment is ESC 208 and gas distribution plate 206. In an exemplary embodiment, 400 kHz power supply, 60 MHz power supply, and optionally 2 MHz power supply, 27 MHz power supply constitute RF source 230 and ESC source 248. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators can be in separate RF sources, or separate RF generators can be connected to different electrodes. For example, the upper electrode can have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes can be used in other embodiments. The optical detector is optically connected to the chamber 249. The controller 235 is controllably connected to the RF source 230, the ESC source 248, the exhaust pump 220, the optical detector 240, and the gas source 210. An example of such a chamber is the Striker manufactured by Lam Research Corporation (Fremont, CA). TM Oxide system.

[0017] Figure 33 is a high-level block diagram illustrating a computer system 300 suitable for implementing the controller 235 used in the embodiments. Computer systems can have many physical forms, from integrated circuits, printed circuit boards, and small handheld devices to large computers. The computer system 300 includes one or more processors 302 and may also include an electronic display device 304 (for displaying graphics, text, and other data), a main memory 306 (e.g., random access memory (RAM)), a storage device 308 (e.g., a hard drive), a removable storage device 310 (e.g., an optical drive), a user interface device 312 (e.g., a keyboard, touch screen, keypad, mouse or other pointing device, etc.), and a communication interface 314 (e.g., a wireless network interface). The communication interface 314 allows software and data to be transmitted between the computer system 300 and external devices via a link. The system may also include a communication infrastructure 316 (e.g., a communication bus, a crossbar, or a network) connected to the above-mentioned devices / modules.

[0018] The information transmitted via the communication interface 314 can be in the form of signals such as electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 314 via a communication link that carries signals and can be implemented using wires or cables, optical fibers, telephone lines, cellular phone links, radio frequency links, and / or other communication channels. Using such a communication interface, it is contemplated that the one or more processors 302 can receive information from a network or output information to a network while performing the above-described method steps. Furthermore, the method embodiments can be executed solely on a processor or can be executed over a network such as the Internet with a remote processor that shares a portion of the processing.

[0019] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as encompassing transient subject matter such as carrier waves or signals. Examples of computer code include machine code (such as produced by a compiler) and files containing higher-level code that are executed by a computer using an interpreter. A computer-readable medium may also be computer code that is transmitted by a computer data signal embodied in a carrier wave and represents a sequence of instructions that can be executed by a processor.

[0020] In one embodiment, a deposited layer is deposited on a chuck (step 104). In this example, the deposition is done without a wafer in the plasma processing chamber 200. In this example, the deposited layer is silicon oxide. An example recipe for depositing silicon oxide may first provide a silicon-containing precursor, such as polysilane (H3Si-(SiH2) n -SiH3), where n> O, silane (SiH4), disilane (Si2H6) and organosilanes, such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc. A silicon-containing precursor can be provided to deposit a silicon-containing layer. An oxidant also flows into the plasma processing chamber 200. The oxidant can include one or more of oxygen, water, carbon dioxide, nitrous oxide, or carbon monoxide. In some embodiments, the silicon-containing precursor and the oxidant can flow simultaneously. In other embodiments, the silicon-containing precursor and the oxidant can flow sequentially. Figure 4A is a cross-sectional view of a portion of ESC 208 where deposited layer 404 has been deposited directly on the top surface of ESC 208. In other embodiments, other layers may be between ESC 208 and deposited layer 404, where a wafer is not between ESC 208 and deposited layer 404.

[0021] The deposited layer is plasma etched (step 108). An example of an etching recipe for etching the silicon oxide deposited layer provides an etchant gas containing a halogen-containing component to the plasma processing chamber 200. The halogen-containing component can include a fluorine-containing component, such as one or more of nitrogen trifluoride (NF3), fluoroform (CHF3), octafluorocyclobutane (C4F8) and tetrafluoromethane (CF4). The etchant gas is formed into an in-situ plasma in the plasma processing chamber 200, which etches the silicon oxide deposited layer. When the endpoint is detected, the etching stops. This can be accomplished by stopping the flow of the etchant gas or by stopping the RF power energized to the plasma.

[0022] The time for plasma etching the deposited layer is measured (step 112). In this example, the optical detector 240 uses optical emission spectroscopy (OES) to measure the optical emission spectrum to determine the time when the deposited layer has been etched through. Optical emission spectroscopy can be used to detect when the concentration of the substance from the etched silicon oxide decreases or when the concentration of the substance from the layer below the silicon oxide increases. In some embodiments, the silicon nitride layer can be between the surface of the ESC 208 and the silicon oxide deposited layer. In such an embodiment, the presence of the substance from the silicon nitride layer can be used to indicate that the silicon oxide deposited layer has been etched through. When the endpoint is detected, etching stops. This can be done by stopping the flow of the etchant gas or by stopping the RF power energizing the plasma. Figure 4B is a cross-sectional view of a portion of the ESC 208 after the deposited layers have been etched.

[0023] Depositing the deposited layer (step 104), plasma etching the deposited layer (step 108), and measuring the time for plasma etching (step 112) can be repeated one or more times in a cycle (step 116). The measured time is used to determine the drift of the plasma processing chamber (step 120). In this embodiment, after each cycle, the measured time is compared to a reference time. If the measured time is not outside the threshold distance from the reference time, steps 104 through 120 are repeated (step 124). If the measured time is outside the threshold distance from the reference time, indicating threshold plasma drift, a flag can be raised to indicate that the plasma processing chamber needs to be adjusted. In this case, the plasma processing chamber is adjusted (step 128), such as cleaned, to obtain an etching time within the threshold distance from the reference time. Other embodiments may provide for adjustments that clean the plasma processing chamber 200 before depositing a layer on a portion of the interior of the plasma processing chamber 200. Between each cycle, one or more production wafers can be processed.

[0024] In another embodiment, after multiple cycles of steps 104 to 116, a plurality of measured times are plotted against the cycles, wherein the graph is used to determine drift of the plasma processing chamber (step 120). If the graph does not indicate that the plasma processing chamber requires conditioning, steps 104 to 120 are repeated (step 124). The graph may show a sudden change in etch time. Such a sudden change may indicate a malfunction of a plasma processing chamber component. The chamber may be repaired. A gradual change in etch time may indicate a buildup of deposits in the plasma processing chamber that may require cleaning at a particular point. The shape of the graph may be used to indicate the type of cleaning and the location of the cleaning required. After conditioning the chamber (step 128), the wafer may be processed.

[0025] This embodiment allows for measuring the condition of a plasma processing chamber while minimizing the combination of downtime and production wafer defects. The condition of the plasma processing chamber can be quickly determined, reducing or eliminating the need and waiting time for test wafers to be inspected off-site by metrology equipment. Furthermore, since test wafers are not used, the time required to load and unload test wafers is eliminated. Furthermore, the cost of preparing such test wafers is eliminated.

[0026] In another embodiment, a deposition layer is deposited on a chuck (step 104). In this example, the deposition is performed using a production wafer in a plasma processing chamber 200. In this example, the deposited layer is silicon nitride over a silicon oxide layer. Figure 5A5 is a cross-sectional view of a portion of a stack 500, wherein a substrate 504 is beneath a silicon oxide layer 508, on which a silicon nitride layer 512 has been deposited. In this example, an etched feature 516 having sidewalls is formed in the silicon oxide layer 508. The etched feature 516 may be a trench, a hole, or some other type of aperture. A silicon nitride layer 512 is deposited on the sidewalls of the etched feature 516 and on the horizontal surfaces of the stack. When processing a production wafer, part of the process will be to etch away the silicon nitride layer 512 formed on the horizontal surfaces, leaving only the silicon nitride deposited on the sidewalls. In other embodiments, one or more layers may be between the substrate 504 and the silicon nitride layer 512. In other embodiments, other layers of other materials may be used in place of the silicon nitride layer 512, as long as the endpoint of the etching of the deposited layer can be determined during the etching process.

[0027] The deposited layer is plasma etched (step 108). Figure 5B is a cross-sectional view of a portion of stack 500 after etching of deposited layer 512. Portions of silicon nitride layer 512 on horizontal surfaces have been etched away, while at least a portion of the vertical sidewalls remain.

[0028] The time taken for the plasma to etch the deposited layer is measured (step 112). In this example, an optical detector 240 is used with an OES to determine when the deposited layer has been etched through. The OES can be used to detect when the concentration of the species from the etched silicon nitride decreases or when the concentration of the species from the silicon oxide increases.

[0029] Depositing the deposited layer (step 104), plasma etching the deposited layer (step 108), and measuring the time for plasma etching (step 112) can be repeated one or more times in a cycle (step 116). For each cycle, a production wafer is removed and a new production wafer is provided. The measured times are used to determine the drift of the plasma processing chamber (step 120). In one embodiment, after multiple cycles of steps 104 through 116, the multiple measured times are plotted into a graph, where the graph is used to determine the drift of the plasma processing chamber (step 120). If the graph does not indicate that the plasma processing chamber requires conditioning, steps 104 through 120 are repeated (step 124). The graph may show sudden changes in etching time. Such sudden changes may indicate a malfunction of a plasma processing chamber component. The chamber may be repaired. Gradual changes in etching time may indicate a buildup of deposits in the plasma processing chamber, which may require cleaning at a specific point. The shape of the graph can be used to indicate the type of cleaning and the location of the cleaning required. After conditioning the chamber (step 128), additional production wafers can be processed.

[0030] Various embodiments enable increased throughput with fewer defective production wafers by reducing or eliminating the need for ex-situ measurements on metrology tools while more frequently measuring chamber performance using in-situ processing. By measuring performance more frequently, problems are detected more quickly, thereby reducing the number of defective wafers. Some embodiments eliminate the need for test wafers, thereby reducing cost and testing time. Some embodiments are able to measure how changes in process parameters affect chamber performance. In another embodiment, the target deposition thickness can be a target in a recipe, allowing embodiments to be used in a plasma processing chamber to determine a recipe for achieving the target deposition thickness.

[0031] Various embodiments may use different processes to determine when etching has penetrated the deposited layer. In one embodiment, optical emission spectroscopy will be used. In another embodiment, laser interferometry will be used.

[0032] Although the present disclosure has been described in terms of several preferred embodiments, there are changes, modifications, permutations, and various alternative equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways to implement the methods and apparatus of the present disclosure. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations, and various alternative equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A semiconductor processing device comprising: plasma processing chamber; a substrate support and a gas distribution plate disposed within the plasma processing chamber; a radio frequency (RF) source connected to one or more of the substrate support and the gas distribution plate; and A controller configured to: For each of the multiple loops, depositing a deposition layer directly on the surface of the substrate support without a wafer, etching the deposited layer using the plasma generated by the RF source, and measuring the time it takes for the plasma to etch through the deposited layer; as well as A plasma processing chamber drift of the plasma processing chamber is determined using the time measured relative to each cycle of the plurality of cycles.

2. The semiconductor processing device of claim 1 , further comprising an optical detector optically connected to the plasma processing chamber, and wherein the controller is configured to measure a time for the plasma to etch through the deposited layer based at least on an output of the optical detector. 3 . The semiconductor processing device of claim 2 , wherein the optical detector is configured to use at least one of optical emission spectroscopy or laser interferometry. 4 . The semiconductor processing device of claim 1 , wherein the controller is configured to determine that the plasma processing chamber drifts by determining whether the measured time is outside a threshold distance from a reference time. 5 . The semiconductor processing device of claim 1 , wherein the controller is configured to determine the plasma processing chamber drift by generating a graph of the measured time versus each cycle of the plurality of cycles.

6. The semiconductor processing device of claim 5 , wherein the controller is further configured to determine a chamber condition via the graph, wherein a change in time measured relative to each of the plurality of cycles is displayed in the graph, wherein the change is indicative of the chamber condition.

7. The semiconductor processing device of claim 5 , wherein the controller is further configured to determine whether the plasma processing chamber requires maintenance via the graph, wherein a change in time measured relative to each of the plurality of cycles is displayed in the graph, wherein the change indicates that the plasma processing chamber requires maintenance.

8. The semiconductor processing device of claim 1, wherein the controller is further configured to process at least one production wafer between each of the plurality of cycles.

9. The semiconductor processing device of claim 1, wherein the controller is further configured to determine when to clean the plasma processing chamber based on determining that the plasma processing chamber is drifting by measuring the time it takes for plasma to etch through the deposited layer.

10. A semiconductor processing device comprising: plasma processing chamber; a substrate support and a gas distribution plate disposed within the plasma processing chamber; a radio frequency (RF) source connected to one or more of the substrate support and the gas distribution plate; and A controller configured to: For each of the multiple loops, depositing a deposition layer on a production wafer on said substrate support, etching the deposited layer using the plasma generated by the RF source, and measuring the time it takes for the plasma to etch through the deposited layer; as well as A plasma processing chamber drift of the plasma processing chamber is determined using the time measured relative to each cycle of the plurality of cycles.

11. The semiconductor processing device of claim 10, wherein the controller is configured to deposit the deposition layer on the production wafer by depositing the deposition layer on a stack on the production wafer, wherein the stack has at least one feature having a sidewall.

12. The semiconductor processing device of claim 11 , wherein the controller is configured to etch the deposited layer using the plasma: etching away the deposited layer deposited on horizontal surfaces of the stack and leaving at least some of the deposited layer deposited on sidewalls of at least one feature.

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