Chip packaging device and manufacturing method and debugging test method thereof
By setting the conductive component window and zero-ohm resistor in the chip package device, and setting indicator marks on the plastic sealing layer, the problem of disassembly of chip debugging and analysis is solved, and accurate and efficient debugging and analysis without disassembly is achieved.
Patent Information
- Application Number
- CN202510410170.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-08-12
AI Technical Summary
In the prior art, the debugging and analysis of chip package devices requires disassembly of the chip, resulting in complex operations and easy to damage the chip, affecting the accuracy and efficiency of the debugging and analysis.
In the chip package device, the conductive component window and zero-ohmic resistance are provided, and the indicators are covered by a plastic sealing layer and placed on it, allowing the conductive component to be exposed without disassembling the chip, and debugging and testing is performed using the test leads.
It realizes accurate and efficient debugging and analysis without disassembling the chip, reducing the probability of chip damage and reducing the interference of the external environment on debugging and analysis.
Smart Images
Figure CN120473450A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging device and a manufacturing method, as well as a debugging and testing method thereof. Background Art
[0002] After passing the FT test (Final Test), chips such as eMMC memory chips and UFS chips are shipped to end customers as qualified products. When a customer discovers a defective memory chip after testing it on a machine after mounting it on a PCB, the defective memory chip needs to be debugged and analyzed. However, the manufacturer does not make the chip's debug pins available to users. Therefore, if debugging and analysis of a defective chip is required, the abnormal chip needs to be removed with a hot air gun, then re-balled and placed on a test board with debug pins for debugging and analysis; or wires need to be connected to the relevant pins on the chip, and these pins are connected one by one to a programmer or card reader using wires to ensure that all connections are secure and reliable before debugging and analysis. Both debugging methods require removing the chip from the board, which is a relatively complicated operation. If the disassembly technique is improper or violent, the original failure site may be destroyed or other failure issues may be introduced, interfering with the debug analysis results, resulting in inaccurate debug analysis results and making the analysis extremely difficult. Summary of the Invention
[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a chip packaging device, a manufacturing method thereof, and a debugging and testing method thereof, which can debug and analyze the chip packaging device without disassembling the chip packaging device, reduce interference with the debugging and analysis results, and facilitate accurate and efficient debugging and analysis of the chip packaging device.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging device, comprising:
[0005] A substrate comprising a first surface and a second surface disposed in opposite directions;
[0006] The debugging pins of the chip are arranged on the second surface;
[0007] A conductive element window is provided on the first surface; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window;
[0008] A plastic sealing layer covers the first surface of the substrate so that the conductive element window is located below the plastic sealing layer; an indicator mark is provided on the plastic sealing layer corresponding to a target position of the conductive element window.
[0009] According to some embodiments of the present application, the conductive element window further includes: a component assembly area provided between the first terminal window and the second terminal window, and the zero-ohm resistor is mounted in the component assembly area.
[0010] According to some embodiments of the present application, the shortest vertical distance between the second terminal window and the edge of the substrate is 150 um.
[0011] According to some embodiments of the present application, the distance between the upper surface of the zero-ohm resistor and the surface of the plastic layer close to the substrate is 100 um.
[0012] According to some embodiments of the present application, a chip is provided on the first surface, and the chip is electrically connected to the zero-ohm resistor through the debugging pin.
[0013] In a second aspect, an embodiment of the present application provides a method for manufacturing a chip packaging device, comprising:
[0014] Obtaining a substrate to be processed, the substrate comprising a first surface and a second surface disposed in back-to-back relationship; the second surface being fixed with debug pins of a chip;
[0015] A conductive element window is provided on the first surface of the substrate; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window;
[0016] Covering the first surface of the substrate with a plastic layer so that the conductive element opening is located under the plastic layer;
[0017] An indicator mark is provided on the plastic packaging layer corresponding to a target position of the window opening of the conductive element.
[0018] According to some embodiments of the present application, providing an indicator mark on the plastic packaging layer corresponding to a target position of the window opening of the conductive element includes:
[0019] Determining a target position corresponding to a window opening of the conductive element on the plastic packaging layer;
[0020] The indicator mark is formed on the target position by printing; or, the indicator mark is formed on the target position by laser.
[0021] According to some embodiments of the present application, providing a conductive element window on the first surface of the substrate includes:
[0022] determining a component assembly area between the first terminal opening and the second terminal opening;
[0023] The zero-ohm resistor is mounted on the component assembly area.
[0024] In a third aspect, an embodiment of the present application provides a debugging and testing method for a chip packaging device, which is applied to the chip packaging device as described in any one of the embodiments of the first aspect; wherein the chip packaging device includes: a substrate, a debugging pin of the chip, a conductive element window, and a plastic encapsulation layer; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debugging pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; the plastic encapsulation layer covers the first surface of the substrate; and an indicator mark is provided on the plastic encapsulation layer corresponding to the target position of the conductive element window;
[0025] The debugging test method comprises:
[0026] For a chip package device with a defective chip, according to the target position indicated by the indicator mark, the plastic sealing layer of the portion corresponding to the target position is removed, and the conductive element in the chip package device is exposed by opening a window;
[0027] electrically connecting the test lead electrically connected to the second terminal window to the test board through a wire;
[0028] The chip in the chip packaging device is debugged and tested via the test board.
[0029] According to some embodiments of the present application, removing the portion of the plastic sealing layer corresponding to the target position includes:
[0030] The plastic sealing layer of the portion corresponding to the target position is removed by laser etching, chemical corrosion, or scraping with an instrument.
[0031] The embodiment of the present application includes: a chip packaging device including: a substrate, a debugging pin of a chip, a conductive element window, and a plastic packaging layer; wherein the substrate includes a first surface and a second surface arranged in back to back; the debugging pin of the chip is arranged on the second surface; the conductive element window is arranged on the first surface; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debugging pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; the plastic packaging layer covers the first surface of the substrate so that the conductive element window is located at Under the plastic sealing layer; an indicator mark is provided on the plastic sealing layer corresponding to the target position of the conductive element window; therefore, when it is necessary to debug and test the chip in the chip packaging device, there is no need to disassemble the chip packaging device from the PCB, but only the plastic sealing layer covering the conductive element window needs to be removed according to the indicator mark to expose the conductive element window, and the test lead electrically connected to the second terminal window is connected to the test board through a wire, so that the defective chip in the chip packaging device can be debugged and tested, reducing the probability of the chip packaging device being damaged; and the use environment is kept consistent with the debugging and testing environment, reducing the interference of external environmental changes on the debugging and analysis results; thereby, the chip packaging device can be debugged and analyzed accurately and efficiently. That is to say, the embodiment of the present application can debug and analyze the chip packaging device without disassembling the chip packaging device, reducing the interference on the debugging and analysis results, so as to facilitate accurate and efficient debugging and analysis of the chip packaging device.
[0032] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 This is a schematic diagram of the specific structure of a chip packaging device provided by an embodiment of the present application;
[0034] Figure 2 is a schematic diagram of a first surface of a chip packaging device provided by one embodiment of the present application;
[0035] Figure 3 is a schematic diagram of the second surface of a chip packaging device provided by one embodiment of the present application;
[0036] Figure 4 This is a schematic diagram of exposing a conductive element in a chip packaging device through a window provided by an embodiment of the present application;
[0037] Figure 5 This is a schematic flow chart of the steps of a method for manufacturing a chip packaging device provided by one embodiment of the present application;
[0038] Figure 6 This is a schematic flow chart of the steps of a method for manufacturing a chip packaging device provided by one embodiment of the present application; Description of the drawings:
[0040] Chip package device 100 , substrate 110 , first surface 111 , second surface 112 , chip 130 , debug pin 131 , conductive element window 140 , first terminal window 141 , second terminal window 142 , zero-ohm resistor 143 , test lead 144 , plastic layer 120 , indicator mark 150 . DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of this application more clear, this application is further described in detail below with reference to the accompanying drawings and embodiments.
[0042] It should be understood that in the description of this application, descriptions of orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.
[0043] It should be noted that although a logical order is shown in the flowchart in the description of this application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of this application, "several" means one or more, and "more" means two or more. The description of "first" and "second" is only used to distinguish technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.
[0045] First, some terms used in this application are explained:
[0046] FT testing (Final Test) is the last test step in the chip manufacturing process after packaging is completed. Its main purpose is to ensure the performance and reliability of the chip in actual applications.
[0047] The present application provides a chip packaging device, a method for manufacturing the chip packaging device, and a method for debugging and testing the chip packaging device; the chip packaging device includes: a substrate including a first surface and a second surface disposed in opposite directions; a debugging pin of the chip is disposed on the second surface; a conductive element window is disposed on the first surface; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debugging pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; a plastic encapsulation layer covers the first surface of the substrate so that the conductive element window is located below the plastic encapsulation layer; and an indicator mark is disposed on the plastic encapsulation layer corresponding to a target position of the conductive element window. The chip packaging device can be debugged and analyzed without disassembling the chip packaging device, and the chip packaging device can be debugged and analyzed accurately and efficiently.
[0048] The embodiments of the present application are further described below with reference to the accompanying drawings.
[0049] First, combining Figures 1 to 3 , Figure 1 This is a schematic diagram of the specific structure of a chip packaging device provided by an embodiment of the present application; Figure 2 is a schematic diagram of a first surface of a chip packaging device provided by one embodiment of the present application; Figure 3 Schematic diagram of the second surface of a chip packaging device according to an embodiment of the present application. The present embodiment provides a chip packaging device 100 , comprising: a substrate 110 , debug pins 131 of a chip 130 , a conductive element window 140 , and a plastic layer 120 .
[0050] The substrate 110 includes a first surface 111 and a second surface 112 facing each other. Specifically, the substrate 110 is used as a carrier to provide physical support for the entire chip package device 100.
[0051] like Figure 3 As shown, the debug pin 131 of the chip 130 is provided on the second surface 112. Specifically, the debug pin 131 is used to directly electrically connect to the debug module within the chip 130, supporting functions such as real-time debugging, fault diagnosis, and performance analysis of the chip 130. The structure of the embodiment of the present application is suitable for BGA packaging. During the design stage of the substrate 110, the debug pin is provided on the second surface 112 (i.e., the bottom surface) of the substrate 110 and is set in a fixed position.
[0052] Combine Figure 2 and Figure 3The conductive element window 140 is disposed on the first surface 111. The conductive element window 140 includes a first terminal window 141, a second terminal window 142, and a zero-ohm resistor 143. The first terminal window 141 is electrically connected to the debug pin 131 of the chip 130, and the second terminal window 142 is electrically connected to a test lead 144. One end of the zero-ohm resistor 143 is electrically connected to the first terminal window 141, and the other end of the zero-ohm resistor 143 is electrically connected to the second terminal window 142. The conductive element window 140 is used to electrically connect to the debug pin 131, and the debug pin 131 is led out through the visible test lead 144 to perform debugging and testing on the chip package device 100. It can be understood that the conductive element window 140 provided in the embodiment of the present application is disposed in an open area on the first surface 111 of the substrate 110, and does not affect the other wiring layouts on the first surface 111 of the substrate 110.
[0053] like Figure 1 As shown, the plastic encapsulation layer 120 covers the first surface 111 of the substrate 110 so that the conductive element window 140 is located below the plastic encapsulation layer 120; an indicator mark 150 is provided on the plastic encapsulation layer 120 corresponding to the target position of the conductive element window 140. The plastic encapsulation layer 120 covers the first surface 111 of the substrate 110, which can prevent dust and particle contamination to avoid short circuits caused by dust or foreign matter, and can also play a role in moisture and corrosion resistance, which is beneficial to extending the life of the device. Specifically, the indicator mark 150 is used to prompt the user to the target position of the conductive element window 140, thereby facilitating the positioning and confirmation of the conductive element window 140, and guiding the user to obtain the test lead 144 electrically connected to the debug pin 131.
[0054] Specifically, the test lead 144 is obtained in a simple manner without damaging the substrate 110 structure. The conductive element window 140 can be exposed by using a sharp device removal tool or laser etching. Alternatively, the conductive element window 140 can be exposed by chemically corroding the surface plastic material corresponding to the conductive element window 140. It is understood that commonly used conductive elements are made of metal and are easily corroded. If the chemical reagents are not handled properly, the test interface can be completely corroded, making it impossible to perform the test. However, resistor components are not easily corroded and have a wide operating range.
[0055] Combine Figure 2 and Figure 3According to some embodiments of the present application, the conductive element window 140 also includes: a component assembly area arranged between the first terminal window 141 and the second terminal window 142, and the zero-ohm resistor 143 is mounted on the component assembly area. The zero-ohm resistor 143 is equivalent to a section of wire, which is used to connect the debug pin 131 and the test lead 144. While leading out the debug pin 131, it will not affect the signal quality. The zero-ohm resistor 143 is technically easy to implement and low-cost. It can be achieved through conventional soldering with printed solder paste and can be mounted together with conventional components without the need for other soldering processes. The use of the zero-ohm resistor 143 reduces the production cost. The component mounted using the zero-ohm resistor 143 is larger in size, and the debug location can be easily found.
[0056] It can be understood that during the packaging stage, the resistance component is mounted on the conductive element window 140 of the substrate 110. The resistance component used is a zero-ohm resistor 143. The chip 130 is packaged through the normal packaging production process. The mounted components do not affect the normal function of the chip 130. If other conductive materials are used, a more complex welding process is required for welding, which increases the cost.
[0057] It is understandable that, in the embodiment of the present application, by disposing a resistor component on the first surface 111 of the substrate 110 , the warping problem of the substrate 110 can be improved to a certain extent because the resistor component occupies a certain volume.
[0058] Specifically, two windows are set in the conductive element window 140 of the substrate 110, one of which is defined as the first terminal window 141, and the other is set as the second terminal window 142; the first terminal window 141 is connected to the debug pin 131 of the chip 130, and the second terminal window 142 is used to lead the lead to the edge of the board and is in a suspended state; thereby leading out the debug pin.
[0059] Specifically, zero-ohm resistor 143 has two terminals. One terminal is electrically connected to debug pin 131 via a debug signal line, and the other terminal is connected to test lead 144. Test lead 144 is left floating when debugging and testing are not required. Zero-ohm resistor 143 is mounted on first surface 111 of substrate 110. Both terminals of zero-ohm resistor 143 are located on first surface 111 of substrate 110, on the same surface as chip 130.
[0060] According to some embodiments of the present application, the shortest vertical distance between the second terminal window 142 and the edge of the substrate 110 is 150 μm. Specifically, the conductive element window 140 is positioned close to the edge of the substrate 110, and the shortest vertical distance between the second terminal window 142 and the edge of the substrate 110 is 150 μm. By positioning the conductive element window 140 as close to the board edge as possible, placement and cutting accuracy requirements can be met. Furthermore, positioning the conductive element window 140 at the board edge makes it easier to access the debug pin 131 without affecting the other wiring arrangements on the substrate 110.
[0061] According to some embodiments of the present application, the distance between the upper surface of the zero-ohm resistor 143 and the surface of the plastic layer 120 close to the substrate 110 is 100 μm, so as to facilitate subsequent debugging operations.
[0062] Specifically, if Figures 1 to 3 As shown, when the package includes two chips 130, two debug pins 131 can be brought out. Correspondingly, the conductive element window 140 is provided with two first terminal windows 141 and two second terminal windows 142. A zero-ohm resistor 143 is mounted between each first terminal window 141 and a corresponding second terminal window 142. Thus, two zero-ohm resistors 143 can be provided in the conductive element window 140. It will be appreciated that when there are multiple chips 130, multiple debug pins 131 can be brought out accordingly.
[0063] Specifically, the size of the conductive element window 140 matches the size of the zero-ohm resistor 143. Depending on the package thickness, different component sizes are selected, with 0201 or 0402 being the typical sizes. It is understood that 0201 and 0402 are imperial component size codes, corresponding to metric sizes of 0.6×0.3 mm and 1.0×0.5 mm, respectively.
[0064] According to some embodiments of the present application, a chip 130 is disposed on the first surface 111, and the chip 130 is electrically connected to a zero-ohm resistor 143 via a debug pin 131. Thus, the debug pin 131 of the chip 130 is brought out to the edge of the board via the conductive element window 140 including the zero-ohm resistor 143. This allows debugging and testing to be performed using the brought-out debug pin 131 when a defective chip 130 is discovered, without requiring the chip 130 to be disassembled.
[0065] When a defective chip 130 is found during terminal testing, it is not necessary to disassemble it for analysis. The position of the zero-ohm resistor 143 can be obtained through a specific marking position. The marking position can be located by using the positive printing on the surface of the chip 130 as a reference point. Use a sharp tool or laser etching or chemical reagent corrosion to remove the plastic layer 120 on the surface to expose the zero-ohm resistor surface, and then lead the debug pin 131 out through a flying wire. Figure 4 As shown, the debug pin 131 is directly connected to a programmer or a card reader, and flying line analysis can be performed directly on the surface of the chip 130, protecting the first scene and accurately and efficiently analyzing the problem.
[0066] Specifically, the chip packaging device 100 according to the embodiment of the present application can be applied to eMMC memory and UFS memory.
[0067] Based on the chip package device 100 of the embodiment of the present application, when debugging and testing the chip 130 in the chip package device 100 is required, the chip package device 100 does not need to be disassembled from the PCB. Instead, the plastic encapsulation layer 120 covering the conductive element window 140 is removed according to the indicator mark 150 to expose the conductive element window 140. The test lead 144 electrically connected to the second terminal window 142 is connected to the test board via a wire. Then, the defective chip 130 in the chip package device 100 can be debugged and tested, thereby reducing the probability of damage to the chip package device 100. The operating environment and the debugging and testing environment are kept consistent, reducing the interference of external environmental changes on the debugging and analysis results. Therefore, the chip package device 100 can be debugged and analyzed accurately and efficiently. In other words, the embodiment of the present application can debug and analyze the chip package device 100 without disassembling the chip package device 100, reducing the interference with the debugging and analysis results, and facilitating accurate and efficient debugging and analysis of the chip package device 100.
[0068] Those skilled in the art will understand that the device structure shown in the figures does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figures, or a combination of certain components, or a different arrangement of components.
[0069] Those skilled in the art will understand that the device structure and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will know that with the evolution of device structures and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0070] Based on the above system structure, various embodiments of the method for manufacturing the chip packaging device of the present application are proposed below.
[0071] Second, as Figure 5 As shown, Figure 5 1 is a flowchart of the steps of a method for manufacturing a chip packaging device provided by an embodiment of the present application. The method for manufacturing a chip packaging device may include but is not limited to steps S110 to S140.
[0072] Step S110: obtaining a substrate to be processed, the substrate comprising a first surface and a second surface disposed in opposite directions; the debugging pins of the chip are fixedly disposed on the second surface.
[0073] Step S120: a conductive element window is provided on the first surface of the substrate; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to the test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window.
[0074] Step S130: Covering the first surface of the substrate with a plastic layer so that the conductive element opening is located under the plastic layer.
[0075] Step S140: setting an indicator mark on the plastic layer corresponding to the target position of the window for the conductive element.
[0076] According to some embodiments of the present application, step S120 is further described. Step S120: providing a conductive element window on the first surface of the substrate, including but not limited to steps S121 to S122.
[0077] Step S121: determining a component assembly area between the first terminal window and the second terminal window.
[0078] Step S122: Mounting the zero-ohm resistor on the component mounting area.
[0079] Through step S121 to step S122, a zero-ohm resistor is mounted on the component assembly area to connect the debug pin and the test lead, and the signal quality will not be affected while the debug pin is led out.
[0080] In some embodiments, step S130 is further described by covering the first surface of the substrate with a plastic layer so that the conductive element window is located under the plastic layer to protect against dust and particle contamination to avoid short circuits caused by dust or foreign matter, and to prevent moisture and corrosion, which is beneficial to extending the life of the device.
[0081] According to some embodiments of the present application, step S140 is further described. Step S140: setting an indicator mark on the plastic layer corresponding to the target position of the window of the conductive element, including but not limited to steps S141 to S142.
[0082] Step S141: determining a target position corresponding to a window for the conductive element on the plastic packaging layer.
[0083] Step S142: forming an indicator mark on the target position by printing; or forming an indicator mark on the target position by laser.
[0084] Through steps S141 to S142, an indicator mark is printed on the plastic layer at the target position corresponding to the conductive element window opening, thereby prompting the user of the target position of the conductive element window opening, guiding the user to remove the plastic layer corresponding to the target position to open the conductive element window, and obtain the test lead electrically connected to the debug pin.
[0085] It can be understood that the embodiment of the present application performs steps S110 to S140 by fully automated manufacturing equipment to produce chip packaging devices, which can improve the manufacturing efficiency of chip packaging devices and ensure the quality of chip packaging devices.
[0086] It can be understood that the manufacturing method provided in the embodiment of the present application is applicable to the BGA packaging stage and can be applied to the packaging and manufacturing process of eMMC memory and UFS memory.
[0087] Through steps S110 to S140, a chip packaging device is manufactured, which includes: a substrate, a debugging pin of the chip, a conductive element window, and a plastic packaging layer; wherein the substrate includes a first surface and a second surface arranged in back to back; the debugging pin of the chip is arranged on the second surface; the conductive element window is arranged on the first surface; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debugging pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; the plastic packaging layer covers the first surface of the substrate so that the conductive element window is located under the plastic packaging layer ; An indicator mark is provided on the plastic sealing layer at the target position corresponding to the window of the conductive element; therefore, when it is necessary to debug and test the chip in the chip packaging device, there is no need to disassemble the chip packaging device from the PCB, but only the plastic sealing layer covering the portion of the conductive element window needs to be removed according to the indicator mark to expose the conductive element window, and the test lead electrically connected to the second terminal window is connected to the test board through a wire, so that the defective chip in the chip packaging device can be debugged and tested, thereby reducing the probability of the chip packaging device being damaged; and the use environment is kept consistent with the debugging and testing environment, thereby reducing the interference of external environmental changes on the debugging and analysis results; thereby enabling the debugging and analysis of the chip packaging device to be performed accurately and efficiently. Therefore, the embodiment of the present application can debug and analyze the chip packaging device without disassembling the chip packaging device, thereby reducing the interference on the debugging and analysis results, so as to facilitate the debugging and analysis of the chip packaging device to be performed accurately and efficiently.
[0088] Based on the above system structure, various embodiments of the method for manufacturing the chip packaging device of the present application are proposed below.
[0089] Thirdly, as Figure 6 As shown, Figure 6 This is a step flow diagram of a method for manufacturing a chip packaging device provided by an embodiment of the present application. A debugging and testing method for a chip packaging device provided by an embodiment of the present application is applied to a chip packaging device such as any one of the embodiments of the first aspect; wherein the chip packaging device includes: a substrate, a debugging pin of the chip, a conductive element window, and a plastic layer; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debugging pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; the plastic layer covers the first surface of the substrate; an indicator mark is provided on the plastic layer corresponding to the target position of the conductive element window; the method for manufacturing the chip packaging device may include but is not limited to steps S210 to S230.
[0090] Step S210: For a chip package device with a defective chip, remove the plastic packaging layer at a portion corresponding to the target position indicated by the indicator mark, and open a window to expose the conductive element in the chip package device.
[0091] Step S220: electrically connecting the test lead electrically connected to the second terminal window to the test board through a wire.
[0092] Step S230: Debugging and testing the chip in the chip package device through a test board.
[0093] According to some embodiments of the present application, Figure 4 As shown, Figure 4 This is a schematic diagram of an embodiment of the present application providing a window to expose the conductive element in the chip packaging device, further illustrating step S210, wherein removing the plastic layer corresponding to the target position includes: removing the plastic layer corresponding to the target position by laser etching, chemical corrosion, or scraping with an instrument. By removing the plastic layer to expose the conductive element through the window, the debugging pin is led out by flying wires. Figure 4 As shown, the chip can be debugged in the original test environment without destroying the original scene, eliminating other interference factors, greatly improving the accuracy of debugging and analysis. Furthermore, there is no need to disassemble the chip, which helps save debugging time and improve the efficiency of debugging and analysis.
[0094] It is understandable that the specific content of the debugging test on the chip in step S230 can be determined according to time requirements, and the embodiment of the present application does not impose specific restrictions on the debugging test process.
[0095] In one embodiment, because the test leads are easy to connect and occupy few interfaces, the test leads of one or more chip package devices can be connected to the same test board, and the test board can debug and analyze defective chips in one or more chip package devices at the same time.
[0096] In one embodiment, when the chip in the chip packaging device is debugged, troubleshooted, and restored to use, the exposed conductive element window can be re-covered with new plastic packaging material to form a new complete plastic packaging layer, and a new indicator mark can be re-printed at the target position corresponding to the conductive element window; to facilitate the next debugging and analysis.
[0097] Through steps S210 to S230, when it is necessary to debug and test the chip in the chip packaging device, first, for the chip packaging device with a defective chip, the plastic packaging layer of the corresponding part of the target position is removed according to the target position indicated by the indicator mark, and the conductive element in the chip packaging device is exposed through the window; secondly, the test lead electrically connected to the second terminal window is electrically connected to the test board through a wire; finally, the chip in the chip packaging device is debugged and tested through the test board; in this way, there is no need to disassemble the chip packaging device from the PCB, but only needs to remove the plastic packaging layer of the part covering the conductive element window according to the indicator mark to expose the conductive element window, and connect the test lead electrically connected to the second terminal window to the test board through a wire, so that the defective chip in the chip packaging device can be debugged and tested, thereby reducing the probability of the chip packaging device being damaged; and keeping the use environment consistent with the debugging and testing environment, reducing the interference of external environmental changes on the debugging and analysis results; thereby, the chip packaging device can be debugged and analyzed accurately and efficiently. Therefore, the embodiment of the present application can debug and analyze the chip packaging device without disassembling the chip packaging device, reducing interference with the debugging and analysis results, so as to accurately and efficiently debug and analyze the chip packaging device.
[0098] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the present application.
Claims
1. A chip packaging device, characterized in that: include: A substrate comprising a first surface and a second surface disposed in opposite directions; The debugging pins of the chip are arranged on the second surface; A conductive element window is provided on the first surface; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; A plastic sealing layer covers the first surface of the substrate so that the conductive element window is located below the plastic sealing layer; an indicator mark is provided on the plastic sealing layer corresponding to a target position of the conductive element window.
2. The chip packaging device according to claim 1, wherein: The conductive element window further includes: a component mounting area provided between the first terminal window and the second terminal window, and the zero-ohm resistor is mounted in the component mounting area.
3. The chip packaging device according to claim 1, wherein: The shortest vertical distance between the second terminal window and the edge of the substrate is 150 μm.
4. The chip packaging device according to claim 1, wherein: The distance between the upper surface of the zero-ohm resistor and the surface of the plastic layer close to the substrate is 100 um.
5. The chip packaging device according to claim 1, wherein: A chip is provided on the first surface, and the chip is electrically connected to the zero-ohm resistor through the debugging pin.
6. A method for manufacturing a chip packaging device, characterized in that: include: Obtaining a substrate to be processed, the substrate comprising a first surface and a second surface disposed in back-to-back relationship; the second surface being fixed with debug pins of a chip; A conductive element window is provided on the first surface of the substrate; the conductive element window includes a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; Covering the first surface of the substrate with a plastic layer so that the conductive element opening is located under the plastic layer; An indicator mark is provided on the plastic packaging layer corresponding to a target position of the window opening of the conductive element.
7. The method for manufacturing a chip packaging device according to claim 6, wherein: The step of setting an indicator mark on the plastic packaging layer corresponding to a target position of the conductive element window opening comprises: Determining a target position corresponding to a window opening of the conductive element on the plastic packaging layer; The indicator mark is formed on the target position by printing; or, the indicator mark is formed on the target position by laser.
8. The method for manufacturing a chip packaging device according to claim 6, wherein: The step of providing a conductive element window on the first surface of the substrate includes: determining a component assembly area between the first terminal opening and the second terminal opening; The zero-ohm resistor is mounted on the component assembly area.
9. A debugging and testing method for a chip packaging device, characterized in that: Applicable to a chip packaging device according to any one of claims 1 to 5; wherein the chip packaging device comprises: a substrate, a debug pin of a chip, a conductive element window, and a plastic layer; the conductive element window comprises a first terminal window, a second terminal window, and a zero-ohm resistor; the first terminal window is electrically connected to the debug pin of the chip, and the second terminal window is electrically connected to a test lead; one end of the zero-ohm resistor is electrically connected to the first terminal window, and the other end of the zero-ohm resistor is electrically connected to the second terminal window; the plastic layer covers the first surface of the substrate; an indicator mark is provided on the plastic layer corresponding to the target position of the conductive element window; The debugging test method includes: For a chip package device with a defective chip, according to the target position indicated by the indicator mark, the plastic sealing layer of the portion corresponding to the target position is removed, and the conductive element in the chip package device is exposed by opening a window; electrically connecting the test lead electrically connected to the second terminal window to the test board through a wire; The chip in the chip packaging device is debugged and tested via the test board.
10. The debugging and testing method of a chip packaging device according to claim 9, characterized in that: The removing of the plastic sealing layer corresponding to the target position includes: The plastic sealing layer of the portion corresponding to the target position is removed by laser etching, chemical corrosion, or scraping with an instrument.