Chip interface safety protection control circuit

Abstract

The invention discloses a chip interface safety protection control circuit, which relates to the technical field of chip interface protection, and comprises a power supply control module which is used for carrying out rectification filtering and voltage stabilization processing on accessed electric energy, meeting power supply requirements, carrying out overcurrent detection, constant current regulation and overcurrent power-off protection control, and carrying out power-off protection on the power supply control module during power-off protection. The interface voltage of the chip module is lowered, the interface sampling module can carry out sampling and peak detection on pulse signals accessed or output by the chip module, the state detection module can judge the type of the pulse signals, namely square wave pulses or sine pulses, and the first sampling module and the second sampling module carry out peak sampling according to the type of the pulse signals. The micro-control module controls the threshold value setting module to set a comparison threshold value, then the abnormity detection module detects the peak value state of the pulse signal, and when the peak value state is larger than the normal peak value state, chip interface protection is carried out. The chip interface safety protection control circuit can automatically carry out interface signal detection and interface protection control.

Description

Technical Field

[0001] The present invention relates to the technical field of chip interface protection, in particular to a chip interface security protection control circuit. Background Art

[0002] A chip refers to a silicon wafer containing an integrated circuit. It is very small and is often a part of a computer or other electronic device. With the development of the times and the continuous improvement of people's living standards, the functions of chips are constantly increasing, and the interfaces of chips are constantly increasing. If the voltage and current of the chip interface are abnormal, it may cause the chip to malfunction, or even cause the chip to burn or the chip interface to burn. Therefore, in the existing technology, the power detection sampling and voltage and current comparison of the chip interface will be carried out, and then protection control will be performed. However, since the signal accessed by the chip interface can be a sinusoidal pulse or a square wave pulse, it is impossible to determine the type of accessible signal and it is impossible to perform interface protection control according to the type of access signal. In addition, when making an abnormal judgment on the signal input to the chip interface, it is necessary to know the working information of the chip interface in advance, otherwise it will not be possible to automatically perform power abnormality protection control. Therefore, there is room for improvement. Summary of the Invention

[0003] An embodiment of the present invention provides a chip interface security protection control circuit to solve the problems raised in the above background technology.

[0004] According to an embodiment of the present invention, a chip interface safety protection control circuit is provided, comprising: a power control module, configured to rectify, filter, and stabilize incoming electrical energy and transmit first electrical energy; perform overcurrent detection and, when overcurrent occurs, perform constant current regulation on the first electrical energy; and output a first protection signal and stop transmitting the first electrical energy when the processed first electrical energy exceeds a set overcurrent threshold; A chip module is connected to the power control module and the abnormality detection module, and is used to receive the first electric energy and start, access or output the pulse signal, and stop accessing or outputting the pulse signal when receiving the first protection signal or the second protection signal output by the abnormality detection module; an interface sampling module connected to the chip module, the microcontroller module, and the state detection module, configured to perform peak detection on the pulse signal and output a first detection signal; upon receiving a first control signal output by the microcontroller module, stop peak detection and transmit the pulse signal to the state detection module; and when the voltage of the pulse signal drops, output a second detection signal and stop peak detection; a state detection module, configured to perform voltage detection on the first detection signal and the input pulse signal and output a first state signal when the voltages of the first detection signal and the pulse signal are equal, and output a second state signal when the voltages are not equal; A first sampling module is connected to the interface sampling module and the state detection module, and is used to perform voltage division sampling on the first detection signal and output a first sampling signal when receiving the first state signal; A second sampling module is connected to the interface sampling module and the state detection module, and is used to perform voltage division sampling on the first detection signal and output a second sampling signal when the second state signal is received and the pulse signal voltage drops; a microcontroller module connected to the state detection module, the second sampling module, the first sampling module, the interface sampling module, the power control module, and the threshold setting module, configured to control the power control module to transmit power, receive the first protection signal, the first state signal, and the second state signal, periodically provide the first control signal, receive the second detection signal, and control the threshold setting module to set a comparison threshold based on the voltages of the received first sampling signal and the second sampling signal; A threshold setting module, used for setting a comparison threshold; The abnormality detection module is connected to the threshold setting module and is used to output a second protection signal when the voltage of the first detection signal is greater than the comparison threshold.

[0005] As a further solution of the present invention: the power control module includes a power processing device, a first resistor, a second resistor, a first switch tube, a first diode, a fifth resistor, a second switch tube, a third resistor, a fourth resistor, a second power tube, a third diode and an eighth resistor; the micro control module includes a first controller; Preferably, the first end of the power processing device is connected to the emitter of the first switching tube and is connected to one end of the second resistor, the cathode of the first diode, one end of the third resistor, the source of the second power tube and one end of the eighth resistor through the first resistor. The other end of the eighth resistor is connected to one end of the third diode, the anode of the third diode is connected to the source of the second power tube, the gate of the second power tube is connected to the other end of the third resistor, the anode of the first diode, one end of the fifth resistor and the collector of the first switching tube through the fourth resistor. The base of the first switching tube is connected to the other end of the second resistor, the other end of the fifth resistor is connected to the collector of the first switching tube, the emitter of the second switching tube and the second end of the power processing device are both grounded, and the base of the second switching tube is connected to the IO2 end of the first controller.

[0006] As a further solution of the present invention: the power control module further includes a first power tube, a first logic chip, a sixth resistor, a seventh resistor and a second diode; Preferably, the drain of the first power tube is connected to the first end of the power processing device, the gate of the first power tube is connected to the Y end of the first logic core, the IO1 end of the first controller and the chip module, the B end of the first logic chip is connected to the anode of the second diode, the cathode of the second diode is connected to the drain of the second power tube, the A end of the first logic chip is connected to one end of the sixth resistor and is connected to the source and ground of the first power tube through the seventh resistor, and the other end of the sixth resistor is connected to the collector of the first switching tube.

[0007] As a further solution of the present invention: the chip module includes a chip to be detected, a third switch tube and a fourth diode; Preferably, the VCC end of the chip to be detected is connected to the cathode of the third diode, the GND end of the chip to be detected is connected to the emitter of the third switching tube and the ground end, the collector of the third switching tube is connected to the IO end of the chip to be detected and the interface sampling module, the cathode of the fourth diode is connected to the base of the third switching tube, and the anode of the fourth diode is connected to the Y end of the first logic chip.

[0008] As a further solution of the present invention: the interface sampling module includes a first amplifier, a first control tube, a second control tube, a fifth diode, a first capacitor and a first analog switch; Preferably, the non-inverting end of the first amplifier is connected to the IO end of the chip to be detected and the IN end of the first analog switch, the inverting end of the first amplifier is connected to the first end of the first capacitor and the drain of the second control tube, the gate of the second control tube is connected to the gate of the first control tube and the cathode of the fifth diode, the source of the first control tube is connected to the source of the second control tube, the power supply end of the first amplifier and the first end of the power processing device, the ground end of the first amplifier is connected to the second end of the first capacitor, the anode of the fifth diode is connected to the CTRL end of the first analog switch and the IO4 end of the first controller, the OUT end of the first analog switch is connected to the status detection module, and the output end of the first amplifier is connected to the drain of the first control tube and the IO3 end of the first controller.

[0009] As a further solution of the present invention: the state detection module includes a first comparator, a second comparator, a second logic chip and a first inverter; Preferably, the inverting end of the first comparator is connected to the non-inverting end of the second comparator and the first end of the first capacitor, the non-inverting end of the first comparator is connected to the inverting end of the second comparator and the OUT end of the first analog switch, the output end of the first comparator and the output end of the second comparator are respectively connected to the A end and the B end of the second analog switch, the Y end of the second analog switch is connected to the IO5 end of the first controller, the input end of the first inverter and the first sampling module, and the output end of the first inverter is connected to the IO6 end of the first controller and the second sampling module.

[0010] As a further solution of the present invention: the first sampling module includes a third control tube, a ninth resistor and a tenth resistor; Preferably, the gate of the third control tube is connected to the Y end of the second logic chip, the drain of the third control tube is connected to the first end of the first capacitor, the source of the third control tube is connected to the IO7 end of the first controller and one end of the tenth resistor through the ninth resistor, and the other end of the tenth resistor is grounded.

[0011] As a further solution of the present invention: the second sampling module includes a third logic chip, a fourth control tube, an eleventh resistor and a twelfth resistor; Preferably, the A end and the B end of the third logic chip are respectively connected to the output end of the first inverter and the output end of the first amplifier, the Y end of the third logic chip is connected to the gate of the fourth control tube, the drain of the fourth control tube is connected to the first end of the first capacitor, the source of the fourth control tube is connected to the IO8 end of the first controller and one end of the twelfth resistor through the eleventh resistor, and the other end of the twelfth resistor is grounded.

[0012] As a further solution of the present invention: the threshold setting module includes a thirteenth resistor, a second capacitor and a third power tube; Preferably, the gate of the third power tube is connected to the IO9 terminal of the first controller, the drain of the third power tube is connected to the first terminal of the power processing device, the source of the third power tube is connected to the first terminal of the second capacitor and the abnormality detection module and is connected to the second terminal of the second capacitor and the ground terminal through the thirteenth resistor.

[0013] As a further solution of the present invention: the abnormality detection module includes a third comparator and a sixth diode; Preferably, the in-phase terminal and the inverting terminal of the third comparator are respectively connected to the first terminal of the first capacitor and the first terminal of the second capacitor, the output terminal of the third comparator is connected to the anode of the sixth diode, and the cathode of the sixth diode is connected to the base of the third switching tube.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: the chip interface safety protection control circuit of the present invention can rectify, filter and stabilize the input electric energy by the power control module to meet the power supply demand, and perform overcurrent detection, constant current regulation and overcurrent power-off protection control, and during power-off protection, lower the interface voltage of the chip module, and the interface sampling module can sample and peak detect the pulse signal input or output by the chip module, and cooperate with the state detection module to determine the type of the pulse signal, that is, square wave pulse or sine pulse, the first sampling module and the second sampling module perform peak sampling processing according to the type of the pulse signal, so that the micro-control module controls the threshold setting module to set the comparison threshold, and then the abnormality detection module detects the peak state of the pulse signal, and performs chip interface protection control when it is greater than the normal peak state. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic block diagram of a chip interface security protection control circuit provided by an embodiment of the present invention.

[0017] Figure 2 A circuit diagram of a chip interface security protection control circuit provided by an embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram of a status detection module provided by an embodiment of the present invention.

[0019] Figure 4 This is a circuit diagram of a first sampling module provided in an embodiment of the present invention.

[0020] Figure 5 This is a circuit diagram of the second sampling module provided in an embodiment of the present invention.

[0021] Figure 6 This is a circuit diagram of a threshold setting module provided in an embodiment of the present invention.

[0022] Figure 7 This is a circuit diagram of an anomaly detection module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] In one embodiment, see Figure 1 A chip interface safety protection control circuit includes: a power control module 1, configured to rectify, filter, and stabilize input power and transmit first power, perform overcurrent detection, and, when overcurrent occurs, perform constant current regulation on the first power, and output a first protection signal and stop transmitting the first power when the processed first power exceeds a set overcurrent threshold; The chip module 2 is connected to the power control module 1 and the abnormality detection module 9, and is used to receive the first electric energy and start, access or output the pulse signal, and stop accessing or outputting the pulse signal when receiving the first protection signal or the second protection signal output by the abnormality detection module 9; The interface sampling module 3 is connected to the chip module 2, the microcontroller module 7, and the state detection module 4, and is used to perform peak detection on the pulse signal and output a first detection signal. Upon receiving the first control signal output by the microcontroller module 7, the interface sampling module 3 stops the peak detection and transmits the pulse signal to the state detection module 4. When the voltage of the pulse signal drops, the interface sampling module 3 outputs a second detection signal and stops the peak detection. The state detection module 4 is used to perform voltage detection on the first detection signal and the input pulse signal and output a first state signal when the voltages of the first detection signal and the pulse signal are equal, and output a second state signal when the voltages are not equal; The first sampling module 5 is connected to the interface sampling module 3 and the state detection module 4, and is used to perform voltage division sampling on the first detection signal and output a first sampling signal when receiving the first state signal; The second sampling module 6 is connected to the interface sampling module 3 and the state detection module 4, and is used to perform voltage division sampling on the first detection signal and output a second sampling signal when the second state signal is received and the pulse signal voltage drops; The microcontroller module 7 is connected to the state detection module 4, the second sampling module 6, the first sampling module 5, the interface sampling module 3, the power control module 1, and the threshold setting module 8, and is used to control the power control module 1 to transmit power, receive the first protection signal, the first state signal, and the second state signal, provide the first control signal at regular intervals, receive the second detection signal, and control the threshold setting module 8 to set a comparison threshold based on the voltage of the received first sampling signal and the second sampling signal; A threshold setting module 8, used for setting a comparison threshold; The abnormality detection module 9 is connected to the threshold setting module 8 and is used to output a second protection signal when the voltage of the first detection signal is greater than the comparison threshold.

[0025] In a specific embodiment, the power control module 1 can adopt a power control circuit composed of an energy processing device, a resistor, a logic chip, a field effect transistor, a triode, etc., which can rectify, filter and stabilize the connected electric energy, control the transmission of electric energy, detect overcurrent of the transmitted electric energy, and perform constant current regulation when overcurrent occurs. When the regulated electric energy is greater than the set overcurrent threshold, power-off control will be performed; the chip module 2 can adopt a chip circuit composed of a chip to be detected IC1, a triode and a diode, which can be connected to the electric energy transmitted by the power control module 1 and start and work, and can be connected or output pulse signals through the interface of the chip to be detected IC1, and the signal state of the interface can be controlled by the power control module 1 or the abnormality detection module 9; the interface sampling module 3 can adopt an interface sampling circuit composed of a field effect transistor, an amplifier, a capacitor, an analog switch, etc., which can perform peak detection and signal transmission control; the state detection module 4 can adopt a state detection circuit composed of a comparator, a logic chip and an inverter, which can be used according to the interface sampling The level state of the signal output by the module 3 is used to determine whether the output signal is a square wave pulse or a sine pulse; the above-mentioned first sampling module 5 can adopt a first sampling circuit composed of a field effect transistor and a resistor, and can perform voltage division sampling processing on the signal output by the interface sampling module 3; the above-mentioned second sampling module 6 can adopt a second sampling circuit composed of a field effect transistor, a logic chip and a resistor, and can perform voltage division sampling processing on the signal output by the interface sampling module 3; the above-mentioned micro-control module 7 can adopt a micro-control circuit composed of a single-chip microcomputer, which integrates many components such as an arithmetic unit, a controller, a memory and an input and output device to realize functions such as signal processing, data storage, module control, and timing control; the above-mentioned threshold setting module 8 can adopt a threshold setting circuit composed of a field effect transistor, a resistor and a capacitor, and can set a comparison threshold, which is equal to the signal voltage output by the first sampling module 5 or the second sampling module 6; the above-mentioned abnormality detection module 9 can adopt an abnormality detection circuit composed of a comparator and a diode, which can perform peak value comparison and control the chip module 2 to perform interface protection.

[0026] In another embodiment, see Figure 1 、 Figure 2 and Figure 3 The power control module 1 includes a power processing device, a first resistor R1, a second resistor R2, a first switch tube V1, a first diode D1, a fifth resistor R5, a second switch tube V2, a third resistor R3, a fourth resistor R4, a second power tube Q2, a third diode D3 and an eighth resistor R8; the micro control module 7 includes a first controller U1; Specifically, the first end of the power processing device is connected to the emitter of the first switching tube V1 and is connected to one end of the second resistor R2, the cathode of the first diode D1, one end of the third resistor R3, the source of the second power tube Q2 and one end of the eighth resistor R8 through the first resistor R1. The other end of the eighth resistor R8 is connected to one end of the third diode D3, the anode of the third diode D3 is connected to the source of the second power tube Q2, the gate of the second power tube Q2 is connected to the other end of the third resistor R3, the anode of the first diode D1, one end of the fifth resistor R5 and the collector of the first switching tube V1 through the fourth resistor R4, the base of the first switching tube V1 is connected to the other end of the second resistor R2, the other end of the fifth resistor R5 is connected to the collector of the first switching tube, the emitter of the second switching tube V2 and the second end of the power processing device are both grounded, and the base of the second switching tube V2 is connected to the IO2 terminal of the first controller U1.

[0027] In a specific embodiment, the above-mentioned power processing device can be composed of a rectifier, a filter and a voltage stabilizer to perform rectification, filtering and voltage stabilization processing; the above-mentioned first switching tube V1 can be a PNP type transistor, which can be used in conjunction with the second resistor R2 to perform overcurrent detection; the above-mentioned second switching tube V2 can be an NPN type transistor to control the conduction degree of the second power tube Q2, and then perform constant current regulation processing; the above-mentioned second power tube Q2 can be an enhanced P-channel field effect transistor to form a dynamic balance of cascade negative feedback with the first switching tube V1, and further perform constant current regulation; the above-mentioned first controller U1 can be an STM32 microcontroller.

[0028] Furthermore, the power control module 1 further includes a first power tube Q1, a first logic chip J1, a sixth resistor R6, a seventh resistor R7 and a second diode D2; Specifically, the drain of the first power tube Q1 is connected to the first end of the power processing device, the gate of the first power tube Q1 is connected to the Y end of the first logic core, the IO1 end of the first controller U1 and the chip module 2, the B end of the first logic chip J1 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the drain of the second power tube Q2, the A end of the first logic chip J1 is connected to one end of the sixth resistor R6 and is connected to the source of the first power tube Q1 and the ground end through the seventh resistor R7, and the other end of the sixth resistor R6 is connected to the collector of the first switching tube V1.

[0029] In a specific embodiment, the first power transistor Q1 may be an enhancement mode N-channel field effect transistor; and the first logic chip J1 may be an AND gate chip.

[0030] Furthermore, the chip module 2 includes a chip to be detected IC1, a third switch tube V3 and a fourth diode D4; Specifically, the VCC end of the chip to be detected IC1 is connected to the cathode of the third diode D3, the GND end of the chip to be detected IC1 is connected to the emitter of the third switch tube V3 and the ground end, the collector of the third switch tube V3 is connected to the IO end of the chip to be detected IC1 and the interface sampling module 3, the cathode of the fourth diode D4 is connected to the base of the third switch tube V3, and the anode of the fourth diode D4 is connected to the Y end of the first logic chip J1.

[0031] In a specific embodiment, the chip to be detected IC1 is a chip that needs protection control and can receive or output sinusoidal pulses or square wave pulses, and the specific model is not limited; the third switch tube V3 can be an NPN transistor.

[0032] Furthermore, the interface sampling module 3 includes a first amplifier OP1, a first control tube M1, a second control tube M2, a fifth diode D5, a first capacitor C1 and a first analog switch IC2; Specifically, the non-inverting end of the first amplifier OP1 is connected to the IO end of the chip to be detected IC1 and the IN end of the first analog switch IC2, the inverting end of the first amplifier OP1 is connected to the first end of the first capacitor C1 and the drain of the second control tube M2, the gate of the second control tube M2 is connected to the gate of the first control tube M1 and the cathode of the fifth diode D5, the source of the first control tube M1 is connected to the source of the second control tube M2, the power supply end of the first amplifier OP1 and the first end of the power processing device, the ground end of the first amplifier OP1 is connected to the second end of the first capacitor C1, the anode of the fifth diode D5 is connected to the CTRL end of the first analog switch IC2 and the IO4 end of the first controller U1, the OUT end of the first analog switch IC2 is connected to the status detection module 4, and the output end of the first amplifier OP1 is connected to the drain of the first control tube M1 and the IO3 end of the first controller U1.

[0033] In a specific embodiment, the first control transistor M1 and the second control transistor M2 can be depletion-type P-channel field-effect transistors; the first amplifier OP1 can be a transconductance amplifier; and the first analog switch IC2 can be a CD4066 chip.

[0034] Furthermore, the state detection module 4 includes a first comparator A1, a second comparator A2, a second logic chip J2 and a first inverter INV1; Specifically, the inverting end of the first comparator A1 is connected to the non-inverting end of the second comparator A2 and the first end of the first capacitor C1, the non-inverting end of the first comparator A1 is connected to the inverting end of the second comparator A2 and the OUT end of the first analog switch IC2, the output end of the first comparator A1 and the output end of the second comparator A2 are respectively connected to the A end and the B end of the second analog switch, the Y end of the second analog switch is connected to the IO5 end of the first controller U1, the input end of the first inverter INV1 and the first sampling module 5, and the output end of the first inverter INV1 is connected to the IO6 end of the first controller U1 and the second sampling module 6.

[0035] In a specific embodiment, the first comparator A1 and the second comparator A2 may both be LM358 comparators; the second logic chip J2 may be an AND gate chip; and the first inverter INV1 may be a NOT gate chip.

[0036] In another embodiment, see Figure 1 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 , the first sampling module 5 includes a third control tube M3, a ninth resistor R9 and a tenth resistor R10; Specifically, the gate of the third control tube M3 is connected to the Y end of the second logic chip J2, the drain of the third control tube M3 is connected to the first end of the first capacitor C1, the source of the third control tube M3 is connected to the IO7 end of the first controller U1 and one end of the tenth resistor R10 through the ninth resistor R9, and the other end of the tenth resistor R10 is grounded.

[0037] In a specific embodiment, the third control transistor M3 can be a depletion-type N-channel field effect transistor.

[0038] Furthermore, the second sampling module 6 includes a third logic chip J3, a fourth control transistor M4, an eleventh resistor R11 and a twelfth resistor R12; Specifically, the A terminal and the B terminal of the third logic chip J3 are respectively connected to the output terminal of the first inverter INV1 and the output terminal of the first amplifier OP1, the Y terminal of the third logic chip J3 is connected to the gate of the fourth control tube M4, the drain of the fourth control tube M4 is connected to the first end of the first capacitor C1, the source of the fourth control tube M4 is connected to the IO8 terminal of the first controller U1 and one end of the twelfth resistor R12 through the eleventh resistor R11, and the other end of the twelfth resistor R12 is grounded.

[0039] In a specific embodiment, the third logic chip J3 may be an AND gate chip; and the fourth control transistor M4 may be a depletion-type N-channel field effect transistor.

[0040] Furthermore, the threshold setting module 8 includes a thirteenth resistor R13, a second capacitor C2 and a third power tube Q3; Specifically, the gate of the third power tube Q3 is connected to the IO9 terminal of the first controller U1, the drain of the third power tube Q3 is connected to the first terminal of the power processing device, and the source of the third power tube Q3 is connected to the first terminal of the second capacitor C2 and the abnormality detection module 9 and is connected to the second terminal of the second capacitor C2 and the ground terminal through the thirteenth resistor R13.

[0041] In a specific embodiment, the third power transistor Q3 may be an enhanced N-channel field effect transistor, and cooperates with the thirteenth resistor R13 and the second capacitor C2 to set a comparison threshold.

[0042] Furthermore, the abnormality detection module 9 includes a third comparator A3 and a sixth diode D6; Specifically, the non-inverting terminal and the inverting terminal of the third comparator A3 are respectively connected to the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2, the output terminal of the third comparator A3 is connected to the anode of the sixth diode D6, and the cathode of the sixth diode D6 is connected to the base of the third switch tube V3.

[0043] In a specific embodiment, the third comparator A3 can be a LM358 comparator.

[0044] In a chip interface safety protection control circuit of this embodiment, the power processing device performs rectification, filtering and voltage stabilization on the incoming power and outputs the first power. The IO2 terminal of the first controller U1 controls the conduction state of the second switch tube V2, and then controls the conduction state of the second power tube Q2, performs constant current regulation, and supplies power to the VCC terminal of the chip to be detected IC1. When overcurrent occurs, the first switch tube V1 is turned on and the conduction angle of the second power tube Q2 is reduced, and then the output current is adjusted. When the adjusted power current still exceeds the overcurrent threshold set by the second diode D2, the second diode D2 is broken down. At this time, the first logic chip J1 will control the first power tube Q1 to turn on, perform power-off control, and control the third switch tube V3 to turn on, pulling The signal potential of the IO terminal of the chip to be detected IC1 is low and received by the IO1 terminal of the first controller U1. When the power supply is normal, the IO terminal of the chip to be detected IC1 is connected to or outputs a pulse signal and it is a positive pulse signal, the timing starts, the output voltage of the first operational amplifier is reduced, the second control tube M2 is turned on, the first capacitor C1 stores energy and holds the signal, after the timing ends, the IO4 terminal of the first controller U1 outputs the first control signal, controls the second control tube M2 to be cut off early, the first capacitor C1 holds the signal, and the IN terminal and OUT terminal of the first analog switch IC2 are turned on, and the voltage of the real-time transmitted signal and the held signal is compared by the first comparator A1 and the second comparator A2. When the voltages are equal, the second logic chip J 2 outputs a high level, which is received by the IO5 terminal of the first controller U1 and is known to be a square wave pulse at this time. At the same time, the third control tube M3 is controlled to be turned on, and the ninth resistor R9 and the tenth resistor R10 sample the signal held by the first capacitor C1. Then, the IO9 terminal of the first controller U1 controls the third power tube Q3, the thirteenth resistor R13 and the second capacitor C2 to set a comparison threshold equal to the voltage of the signal held by the first capacitor C1, and cooperates with the third comparator A3 to perform voltage abnormality comparison. When the voltage changes, the third switch tube V3 is controlled to be turned on, pulling down the IO terminal potential of the chip to be detected IC1. Similarly, when the voltage of the real-time transmitted signal and the voltage of the held signal are not equal, the first inverter INV1 outputs a high level, and the first controller The IO6 terminal interface of U1 knows that it is a sine pulse at this time, and stops outputting the first control signal at the same time. When the voltage of the pulse signal drops, the first operational amplifier, the first capacitor C1, the first control tube M1 and the second control tube M2 know the peak value of the pulse signal and control the fourth control tube M4 to be turned on. The eleventh resistor R11 and the twelfth resistor R12 sample the signal held by the first capacitor C1. Then, the IO9 terminal of the first controller U1 controls the third power tube Q3, the thirteenth resistor R13 and the second capacitor C2 to set a comparison threshold equal to the voltage of the signal held by the first capacitor C1. The third comparator A3 then performs peak state detection. When a voltage greater than the peak value appears, the IO terminal potential of the chip to be detected IC1 is lowered.

[0045] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0046] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A chip interface security protection control circuit, characterized in that: The circuit includes: a power supply control module, configured to rectify, filter, and stabilize the input electric energy and transmit the first electric energy, perform overcurrent detection, and, when overcurrent occurs, perform constant current regulation on the first electric energy, and output a first protection signal and stop transmitting the first electric energy when the processed first electric energy exceeds a set overcurrent threshold; A chip module is connected to the power control module and the abnormality detection module, and is used to receive the first electric energy and start, access or output the pulse signal, and stop accessing or outputting the pulse signal when receiving the first protection signal or the second protection signal output by the abnormality detection module; an interface sampling module connected to the chip module, the microcontroller module, and the state detection module, configured to perform peak detection on the pulse signal and output a first detection signal; upon receiving a first control signal output by the microcontroller module, stop peak detection and transmit the pulse signal to the state detection module; and when the voltage of the pulse signal drops, output a second detection signal and stop peak detection; a state detection module, configured to perform voltage detection on the first detection signal and the input pulse signal and output a first state signal when the voltages of the first detection signal and the pulse signal are equal, and output a second state signal when the voltages are not equal; A first sampling module is connected to the interface sampling module and the state detection module, and is used to perform voltage division sampling on the first detection signal and output a first sampling signal when receiving the first state signal; A second sampling module is connected to the interface sampling module and the state detection module, and is used to perform voltage division sampling on the first detection signal and output a second sampling signal when the second state signal is received and the pulse signal voltage drops; a microcontroller module connected to the state detection module, the second sampling module, the first sampling module, the interface sampling module, the power control module, and the threshold setting module, configured to control the power control module to transmit power, receive the first protection signal, the first state signal, and the second state signal, periodically provide the first control signal, receive the second detection signal, and control the threshold setting module to set a comparison threshold based on the voltages of the received first sampling signal and the second sampling signal; A threshold setting module, used for setting a comparison threshold; The abnormality detection module is connected to the threshold setting module and is used to output a second protection signal when the voltage of the first detection signal is greater than the comparison threshold.

2. The chip interface security protection control circuit according to claim 1, characterized in that: The power control module includes a power processing device, a first resistor, a second resistor, a first switch tube, a first diode, a fifth resistor, a second switch tube, a third resistor, a fourth resistor, a second power tube, a third diode and an eighth resistor; the micro control module includes a first controller; The first end of the power processing device is connected to the emitter of the first switching tube and is connected to one end of the second resistor, the cathode of the first diode, one end of the third resistor, the source of the second power tube and one end of the eighth resistor through the first resistor. The other end of the eighth resistor is connected to one end of the third diode, the anode of the third diode is connected to the source of the second power tube, the gate of the second power tube is connected to the other end of the third resistor, the anode of the first diode, one end of the fifth resistor and the collector of the first switching tube through the fourth resistor. The base of the first switching tube is connected to the other end of the second resistor, and the other end of the fifth resistor is connected to the collector of the first switching tube. The emitter of the second switching tube and the second end of the power processing device are both grounded, and the base of the second switching tube is connected to the IO2 end of the first controller.

3. The chip interface security protection control circuit according to claim 2, characterized in that: The power control module further includes a first power tube, a first logic chip, a sixth resistor, a seventh resistor and a second diode; The drain of the first power tube is connected to the first end of the power processing device, the gate of the first power tube is connected to the Y end of the first logic core, the IO1 end of the first controller and the chip module, the B end of the first logic chip is connected to the anode of the second diode, the cathode of the second diode is connected to the drain of the second power tube, the A end of the first logic chip is connected to one end of the sixth resistor and is connected to the source and ground of the first power tube through the seventh resistor, and the other end of the sixth resistor is connected to the collector of the first switching tube.

4. The chip interface security protection control circuit according to claim 3, characterized in that: The chip module includes a chip to be detected, a third switch tube and a fourth diode; The VCC end of the chip to be detected is connected to the cathode of the third diode, the GND end of the chip to be detected is connected to the emitter of the third switching tube and the ground end, the collector of the third switching tube is connected to the IO end of the chip to be detected and the interface sampling module, the cathode of the fourth diode is connected to the base of the third switching tube, and the anode of the fourth diode is connected to the Y end of the first logic chip.

5. The chip interface security protection control circuit according to claim 4, characterized in that: The interface sampling module includes a first amplifier, a first control tube, a second control tube, a fifth diode, a first capacitor and a first analog switch; The non-inverting end of the first amplifier is connected to the IO end of the chip to be detected and the IN end of the first analog switch, the inverting end of the first amplifier is connected to the first end of the first capacitor and the drain of the second control tube, the gate of the second control tube is connected to the gate of the first control tube and the cathode of the fifth diode, the source of the first control tube is connected to the source of the second control tube, the power supply end of the first amplifier and the first end of the power processing device, the ground end of the first amplifier is connected to the second end of the first capacitor, the anode of the fifth diode is connected to the CTRL end of the first analog switch and the IO4 end of the first controller, the OUT end of the first analog switch is connected to the status detection module, and the output end of the first amplifier is connected to the drain of the first control tube and the IO3 end of the first controller.

6. The chip interface security protection control circuit according to claim 5, characterized in that: The state detection module includes a first comparator, a second comparator, a second logic chip and a first inverter; The inverting terminal of the first comparator is connected to the non-inverting terminal of the second comparator and the first terminal of the first capacitor, the non-inverting terminal of the first comparator is connected to the inverting terminal of the second comparator and the OUT terminal of the first analog switch, the output terminal of the first comparator and the output terminal of the second comparator are respectively connected to the A terminal and the B terminal of the second analog switch, the Y terminal of the second analog switch is connected to the IO5 terminal of the first controller, the input terminal of the first inverter and the first sampling module, and the output terminal of the first inverter is connected to the IO6 terminal of the first controller and the second sampling module.

7. The chip interface security protection control circuit according to claim 6, characterized in that: The first sampling module includes a third control tube, a ninth resistor and a tenth resistor; The gate of the third control tube is connected to the Y end of the second logic chip, the drain of the third control tube is connected to the first end of the first capacitor, the source of the third control tube is connected to the IO7 end of the first controller and one end of the tenth resistor through the ninth resistor, and the other end of the tenth resistor is grounded.

8. The chip interface security protection control circuit according to claim 7, characterized in that: The second sampling module includes a third logic chip, a fourth control tube, an eleventh resistor and a twelfth resistor; The A terminal and the B terminal of the third logic chip are respectively connected to the output terminal of the first inverter and the output terminal of the first amplifier, the Y terminal of the third logic chip is connected to the gate of the fourth control tube, the drain of the fourth control tube is connected to the first end of the first capacitor, the source of the fourth control tube is connected to the IO8 terminal of the first controller and one end of the twelfth resistor through the eleventh resistor, and the other end of the twelfth resistor is grounded.

9. The chip interface security protection control circuit according to claim 8, characterized in that: The threshold setting module includes a thirteenth resistor, a second capacitor and a third power tube; The gate of the third power tube is connected to the IO9 terminal of the first controller, the drain of the third power tube is connected to the first terminal of the power processing device, and the source of the third power tube is connected to the first terminal of the second capacitor and the abnormality detection module and is connected to the second terminal of the second capacitor and the ground terminal through the thirteenth resistor.

10. The chip interface security protection control circuit according to claim 9, characterized in that: The abnormality detection module includes a third comparator and a sixth diode; The non-inverting terminal and the inverting terminal of the third comparator are respectively connected to the first terminal of the first capacitor and the first terminal of the second capacitor, the output terminal of the third comparator is connected to the anode of the sixth diode, and the cathode of the sixth diode is connected to the base of the third switch tube.

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