A high-precision slope compensation circuit

Abstract

The present invention discloses a high-precision slope compensation circuit. In the first stage, PWM generates first and second inverted signals G1 and 2 via first and second inverters INV1 and 2 connected in series. The output of an operational amplifier OP1 is connected to the gate of a first NMOS transistor NM1 to form VSAW. The second stage consists of a transconductance amplifier and an RC network to stabilize the negative feedback network. In the third stage, a first constant current source I1 provides a bias current, and a second constant current source I2 is grounded via R4 to generate the DC portion of a reference voltage VREF. A set voltage VSET indirectly cooperates with R4 to generate the slope compensation portion. This application implements built-in compensation and adaptively compensates a fixed voltage, effectively improving the accuracy of the output voltage.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and more specifically relates to the field of DC-DC switching power supplies, in particular to a high-precision slope compensation circuit. Background Art

[0002] In the field of integrated circuit DC-DC switching power supplies, a COT (Constant on Time) structure, also known as a fixed conduction time structure, is often used in DC-DC power supplies, especially when high voltage input is required (such as when the maximum input voltage is 80V~100V). This structure has a simple circuit and fast transient response, but it has certain requirements for the ripple of the feedback node. If the ripple voltage of the feedback node is out of phase or the ripple voltage is too low, the COT structure DC-DC power supply will cause abnormal operation.

[0003] Usually, for stable operation, the VFB voltage is required to increase monotonically when VSW is at a high level, and is required to decrease monotonically when VSW is at a low level. This is a conventional design method. At the same time, for stable operation, the peak-to-peak value of VFB is usually required to reach the order of tens of mV (typical value 20mV).

[0004] In order to solve the above problems, there are currently two main solutions.

[0005] One approach is to address this issue externally. This involves configuring appropriate peripheral components to meet the feedback node ripple requirements. This approach is highly versatile, but requires extensive calculations and is not user-friendly for power supply designers. Furthermore, the feedback node ripple voltage is also dependent on the power supply's operating conditions (input voltage, output voltage, output current, etc.) and device parameters. Furthermore, the feedback node ripple voltage affects both the output voltage accuracy and the output voltage ripple.

[0006] The second method is to solve the problem within the chip. That is, the chip generates a suitable slope voltage for compensation based on the input and output conditions through the built-in ripple compensation circuit. Summary of the Invention

[0007] The purpose of the present invention is to provide a high-precision slope compensation circuit, which is an internal chip solution to solve the defects of the existing technology. The circuit is simple and reliable, can adapt to various working conditions, and effectively improves the accuracy of the output voltage.

[0008] To achieve the above technical objectives, the present invention provides a high-precision slope compensation circuit, comprising a ramp voltage as a first-stage circuit STAGE1, a frequency compensation network as a second-stage circuit STAGE2, and a slope compensation circuit as a third-stage circuit STAGE3. The first-stage circuit STAGE1 includes a pulse width modulation (PWM) circuit providing an input signal that generates first and second inverted signals G1 and G2 via first and second inverters INV1 and INV2 connected in series. The output of an operational amplifier OP1 is connected to the gate of a first NMOS transistor NM1 to form a sawtooth voltage VSAW. The second-stage circuit STAGE2 comprises a transconductance amplifier and an RC network for stabilizing the negative feedback network. The circuit includes an external voltage VB for providing a bias voltage and a set voltage VSET for controlling the maximum potential of the sawtooth voltage VSAW. The third-stage circuit STAGE3 includes a first constant current source I1 for providing a bias current and a second constant current source I2 connected to ground via a fourth resistor R4 to generate a DC portion of a reference voltage VREF. The set voltage VSET indirectly cooperates with the fourth resistor R4 to generate the slope compensation portion.

[0009] The present invention provides a high-precision slope compensation circuit that can be used as an internal compensation method for a chip. The circuit method is simple and can adapt to various operating conditions (different input and output conditions, different operating frequencies, etc.). On the one hand, it realizes built-in compensation, and on the other hand, it can adaptively compensate a fixed voltage, which can effectively improve the accuracy of the output voltage.

[0010] As a further improvement, the external voltage VB is connected to the gate of the third PMOS transistor PM3 serving as a current mirror. The fourth and fifth PMOS transistors PM4 and PM5 form a differential pair and their gates are connected to the sawtooth voltage VSAW and the set voltage VSET, respectively.

[0011] As a further improvement, the gate and drain of the seventh NMOS transistor NM7 are connected and connected to the first constant current source I1, the source is connected to the sawtooth voltage VSAW, the eighth and ninth PMOS transistors PM8 and PM9 form a common-gate current mirror, and the drain of the ninth PMOS transistor PM9 is connected to the second constant current source I2 and grounded via the fourth resistor R4.

[0012] As a further improvement, the gate and drain of the eighth PMOS transistor PM8 are connected and connected to the drain of the eighth NMOS transistor NM8. The source of the eighth NMOS transistor NM8 is grounded via a third resistor R3, and its gate is connected to the gate of the seventh NMOS transistor NM7. The inverting input terminal of the operational amplifier OP1 is connected to the source of the first NMOS transistor NM1 and grounded via a first resistor R1.

[0013] As a further improvement, the first-stage circuit STAGE1 further includes: first and second PMOS transistors PM1 and PM2 forming a common-gate current mirror, wherein the gate and drain of the first PMOS transistor PM1 are connected and connected to the drain of the first NMOS transistor NM1, the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2 and is grounded via a first capacitor C1 to form the sawtooth voltage VSAW, and the gate of the second NMOS transistor NM2 is connected to the second inverted signal G2; and a first transmission gate TG1, wherein the input end of the first transmission gate TG1 is connected to the drain of the second PMOS transistor PM2, the positive and negative control ends of the first transmission gate TG1 are connected to the first and second inverted signals G1 and G2, respectively, and the output end of the first transmission gate TG1 is connected to the gate of the fourth PMOS transistor PM4 and is grounded via a second capacitor C2 to form a second control voltage VC2.

[0014] As a further improvement, the fourth and fifth PMOS transistors PM4 and PM5 have a common source and are connected to the drain of the third PMOS transistor PM3. The gates and drains of the third and fourth NMOS transistors NM3 and NM4 are connected and respectively connected to the drains of the fourth and fifth PMOS transistors PM4 and PM5. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 share a common gate. The third NMOS transistor NM3 and the sixth NMOS transistor NM6 share a common gate. The sixth and seventh PMOS transistors PM6 and PM7 share a common gate and their drains are respectively connected to the drains of the fifth and sixth NMOS transistors NM5 and MN6. The gate and drain of the seventh PMOS transistor PM7 are connected.

[0015] As a further improvement, the drain of the fifth NMOS transistor NM5 is connected to the second transmission gate TG2 via the second resistor R2 and is grounded via the third capacitor C3 to form a third control voltage VC3. The third control voltage VC3 is connected to the non-inverting input terminal of the operational amplifier OP1. The second transmission gate TG2 is used to control when error amplification is performed, and its positive and negative control terminals are connected to the second and first inverting signals G2 and G1, respectively.

[0016] As a further improvement, when the DC-DC power supply upper tube is turned on and off, the pulse width modulation PWM signal is high and low respectively, and the second capacitor C2 is much smaller than the first capacitor C1 to ensure that the VSAW voltage rises almost from 0V.

[0017] As a further improvement, the current of the fourth PMOS transistor PM4 is sequentially replicated through the third and sixth NMOS transistors NM3 and MN6, and the seventh and sixth PMOS transistors PM7 and PM6. After the current of the fifth PMOS transistor PM5 is replicated through the fourth and fifth NMOS transistors NM4 and NM5, it is output to the second resistor R2 at the drains of the sixth PMOS transistor PM6 and the sixth NMOS transistor NM6. When the set voltage VSET is higher than the second control voltage VC2, the differential current flows from the fifth PMOS transistor PM5 into the second resistor R2; when the set voltage VSET is lower than the second control voltage VC2, the differential current flows out of the second resistor R2 to the fifth NMOS transistor NM5.

[0018] As a further improvement, the second resistor R2 and the third capacitor C3 form a frequency compensation network, so that the system can operate stably. The first and second circuits STAGE1 and STAGE2 generate the sawtooth voltage VSAW voltage, so that regardless of changes in the operating frequency or the pulse width modulation PWM duty cycle, the sawtooth voltage VSAW rises at a certain slope when the DC-DC power supply is turned off, and the maximum voltage is controlled by the set voltage VSET.

[0019] As a further improvement, the sawtooth voltage VSAW is controlled by the set voltage VSET, and at the same time, the current IPM9 flowing through the ninth PMOS transistor PM9 is controlled by the sawtooth voltage VSAW, and the slope compensation part of the reference voltage VREF is finally controlled by the current IPM9, so as to achieve the highest value of the slope compensation of the reference voltage VREF controlled by the set voltage VSET. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the circuit principle of the present invention;

[0021] Figure 2 This is a schematic diagram of the superposition principle of the present invention;

[0022] Figure 3 Schematic diagram of the simulation of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] like Figures 1 to 3 As shown, the present invention provides a high-precision slope compensation circuit, which provides an embodiment with relatively set NMOS tubes and PMOS tubes, and can be correspondingly transformed according to the common sense in the field under the technical solutions and effects disclosed in the present invention.

[0025] The present invention provides a high-precision slope compensation circuit, comprising a ramp voltage as a first-stage circuit STAGE1, a frequency compensation network as a second-stage circuit STAGE2, and a slope compensation circuit as a third-stage circuit STAGE3. The first-stage circuit STAGE1 includes a pulse width modulation (PWM) circuit providing an input signal that generates first and second inverted signals G1 and G2 via first and second inverters INV1 and INV2 connected in series, and an operational amplifier OP1 whose output is connected to the gate of a first NMOS transistor NM1 to form a sawtooth voltage VSAW. The second-stage circuit STAGE2 includes a transconductance amplifier and an RC network for stabilizing a negative feedback network, and includes an external voltage VB for providing a bias voltage and a set voltage VSET for controlling the maximum potential of the sawtooth voltage VSAW. The third-stage circuit STAGE3 includes a first constant current source I1 for providing a bias current, a second constant current source I2 connected to ground via a fourth resistor R4 to generate a DC portion of a reference voltage VREF, and the set voltage VSET indirectly cooperates with the fourth resistor R4 to generate the slope compensation portion.

[0026] The present invention provides a high-precision slope compensation circuit that can be used as an internal compensation method for a chip. The circuit method is simple and can adapt to various operating conditions (different input and output conditions, different operating frequencies, etc.). On the one hand, it realizes built-in compensation, and on the other hand, it can adaptively compensate a fixed voltage, which can effectively improve the accuracy of the output voltage.

[0027] As a further improvement, the external voltage VB is connected to the gate of the third PMOS transistor PM3 serving as a current mirror. The fourth and fifth PMOS transistors PM4 and PM5 form a differential pair and their gates are connected to the sawtooth voltage VSAW and the set voltage VSET, respectively.

[0028] As a further improvement, the gate and drain of the seventh NMOS transistor NM7 are connected and connected to the first constant current source I1, the source is connected to the sawtooth voltage VSAW, the eighth and ninth PMOS transistors PM8 and PM9 form a common-gate current mirror, and the drain of the ninth PMOS transistor PM9 is connected to the second constant current source I2 and grounded via the fourth resistor R4.

[0029] As a further improvement, the gate and drain of the eighth PMOS transistor PM8 are connected and connected to the drain of the eighth NMOS transistor NM8. The source of the eighth NMOS transistor NM8 is grounded via a third resistor R3, and its gate is connected to the gate of the seventh NMOS transistor NM7. The inverting input terminal of the operational amplifier OP1 is connected to the source of the first NMOS transistor NM1 and grounded via a first resistor R1.

[0030] As a further improvement, the first-stage circuit STAGE1 further includes: first and second PMOS transistors PM1 and PM2 forming a common-gate current mirror, wherein the gate and drain of the first PMOS transistor PM1 are connected and connected to the drain of the first NMOS transistor NM1, the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2 and is grounded via a first capacitor C1 to form the sawtooth voltage VSAW, and the gate of the second NMOS transistor NM2 is connected to the second inverted signal G2; and a first transmission gate TG1, wherein the input end of the first transmission gate TG1 is connected to the drain of the second PMOS transistor PM2, the positive and negative control ends of the first transmission gate TG1 are connected to the first and second inverted signals G1 and G2, respectively, and the output end of the first transmission gate TG1 is connected to the gate of the fourth PMOS transistor PM4 and is grounded via a second capacitor C2 to form a second control voltage VC2.

[0031] As a further improvement, the fourth and fifth PMOS transistors PM4 and PM5 have a common source and are connected to the drain of the third PMOS transistor PM3. The gates and drains of the third and fourth NMOS transistors NM3 and NM4 are connected and respectively connected to the drains of the fourth and fifth PMOS transistors PM4 and PM5. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 share a common gate. The third NMOS transistor NM3 and the sixth NMOS transistor NM6 share a common gate. The sixth and seventh PMOS transistors PM6 and PM7 share a common gate and their drains are respectively connected to the drains of the fifth and sixth NMOS transistors NM5 and MN6. The gate and drain of the seventh PMOS transistor PM7 are connected.

[0032] As a further improvement, the drain of the fifth NMOS transistor NM5 is connected to the second transmission gate TG2 via the second resistor R2 and is grounded via the third capacitor C3 to form a third control voltage VC3. The third control voltage VC3 is connected to the non-inverting input terminal of the operational amplifier OP1. The second transmission gate TG2 is used to control when error amplification is performed, and its positive and negative control terminals are connected to the second and first inverting signals G2 and G1, respectively.

[0033] As a further improvement, when the DC-DC power supply upper tube is turned on and off, the pulse width modulation PWM signal is high and low respectively, and the second capacitor C2 is much smaller than the first capacitor C1 to ensure that the VSAW voltage rises almost from 0V.

[0034] As a further improvement, the current of the fourth PMOS transistor PM4 is sequentially replicated through the third and sixth NMOS transistors NM3 and MN6, and the seventh and sixth PMOS transistors PM7 and PM6. After the current of the fifth PMOS transistor PM5 is replicated through the fourth and fifth NMOS transistors NM4 and NM5, it is output to the second resistor R2 at the drains of the sixth PMOS transistor PM6 and the fifth NMOS transistor NM5. When the set voltage VSET is higher than the second control voltage VC2, the differential current flows from the sixth PMOS transistor PM6 to the second resistor R2; when the set voltage VSET is lower than the second control voltage VC2, the differential current flows out of the second resistor R2 to the fifth NMOS transistor NM5.

[0035] As a further improvement, the second resistor R2 and the third capacitor C3 form a frequency compensation network, so that the system can operate stably. The first and second circuits STAGE1 and STAGE2 generate the sawtooth voltage VSAW voltage, so that regardless of changes in the operating frequency or the pulse width modulation PWM duty cycle, the sawtooth voltage VSAW rises at a certain slope when the DC-DC power supply is turned off, and the maximum voltage is controlled by the set voltage VSET.

[0036] As a further improvement, the sawtooth voltage VSAW is controlled by the set voltage VSET, and at the same time, the current IPM9 flowing through the ninth PMOS transistor PM9 is controlled by the sawtooth voltage VSAW, and the slope compensation part of the reference voltage VREF is finally controlled by the current IPM9, so as to achieve the highest value of the slope compensation of the reference voltage VREF controlled by the set voltage VSET.

[0037] As a further improvement, the first, second, third, sixth, seventh, eighth and ninth PMOS transistors PM1, PM2, PM3, PM6, PM7, PM8 and PM9 have a common source and are connected to the power supply VDD, and the second, third, fourth, fifth and sixth NMOS transistors NM2, NM3, NM4, NM5 and NM6 have a common source and are grounded.

[0038] The following is combined with Figure 1 The preferred example of the present invention is shown to specifically illustrate the circuit principle of the present invention.

[0039] STAGE1: This stage is mainly used to generate ramp voltage.

[0040] PWM is the input signal. The PWM signal has the following characteristics: when the DC-DC power supply's upper transistor is on, the PWM signal is high; when the DC-DC power supply's upper transistor is off, the PWM signal is low. After being inverted by the inverter, the PWM signal generates the G1 and G2 signals, which are used to control the on and off of some transistors in the present invention.

[0041] OP1 is an operational amplifier with NM1 connected to its output terminal as the output transistor. NM1 is connected to R1 and PM1 respectively. OP1's non-inverting terminal is connected to the VC3 voltage in STAGE2. Due to the negative feedback of the entire system, the voltage across R1 equals VC3. At the same time, all the current in R1 flows through PM1. Therefore, PM1's current IPM1 can be written as: IPM1 = VC3 / R1.

[0042] When the DC-DC power supply's high-side transistor is turned off, PWM is low, G2 is in phase with the PWM signal and is also low, and the G1 signal is high. At this time, NM2 is off, transmission gate TG1 is on, and PM2 charges capacitors C1 and C2.

[0043] During stable operation, the VC3 voltage is basically constant, so the IPM1 current is also constant. Since PM2 and PM1 form a current mirror, assuming that the ratio of IPM1 to IPM2 is M, and at the TOFF moment (that is, when the PWM signal changes from high to low), the voltage of C2 is 0V. For the convenience of expression, let the TOFF moment be t=0. Then, in the same period, the voltage of VSAW can be expressed as:

[0044] .

[0045] Because IPM1 is a fixed value, the VSAW voltage rises at a constant rate from almost zero volts. When the DC-DC power supply's high-side transistor (SMOSFET) is on, PWM is high, G2 is in phase with the PWM signal and also high, and G1 is low. At this point, NM2 is on, transmission gate TG1 is off, and NM2 discharges capacitor C1. Because TG1 is off, capacitor C2 has no discharge path, so the voltage on capacitor C2 remains at the instantaneous VSAW value when PWM transitions from low to high. To ensure that the VSAW voltage rises almost from zero volts, capacitor C2 must be designed to be much smaller than capacitor C1.

[0046] STAGE2: This stage is a frequency compensation network composed of a transconductance amplifier and an RC network, which is used to stabilize the negative feedback network.

[0047] PM3 is a current mirror, providing appropriate current to the differential pair below it. VB is the bias voltage for PM3's gate terminal, and the VB voltage is supplied externally. PM4 and PM5 form a differential pair. VSET is the set voltage, which controls the maximum potential of VSAW.

[0048] The PM4 current is replicated via NM3->NM6->PM7->PM6, and the PM5 current is replicated via NM4->NM5 before being output to R2 at the drains of PM6 and NM5. When the VSET voltage is higher than VC2, the differential current flows from PM6 into R2; when the VSET voltage is lower than VC2, the differential current flows out from R2 to NM5.

[0049] TG2 controls when error amplification occurs. When the high-side transistor is off, PWM is low, G2 is low, and G1 is high. Transmission gate TG2 is off, and C3 maintains its previous voltage. When the high-side transistor is on, PWM is high, G2 is high, and G1 is low. Transmission gate TG2 is on. At this point, negative feedback adjusts the voltage of VC3 based on the error between VC2 and VSET, thereby controlling the maximum voltage of VSAW via VSET.

[0050] Due to the negative feedback loop of the entire system, theoretically, regardless of changes in operating frequency or duty cycle, the minimum and maximum VSAW voltages remain fixed, with the minimum being approximately 0V and the maximum approximately the VSET voltage. R2 and C3 form a frequency compensation network, ensuring stable operation of the system. Appropriate values ​​can be determined through calculation, but the details are not discussed here.

[0051] STAGE1 and STAGE2 generate a VSAW voltage. Regardless of whether the operating frequency changes or the PWM duty cycle changes, the voltage rises at a certain slope when the upper tube is turned off, and the maximum voltage of VSAW is controlled by the VSET voltage.

[0052] STAGE3: Slope compensation circuit.

[0053] I1 is a constant current source that provides bias current for NM7. NM7 and NM8 are of the same type. Within a certain current range, the VSAW voltage can be roughly assumed to be consistent with the voltage applied to R3. The current from R3 flows through PM8. PM8 and PM9 form a 1:N electron microscope, so the current flowing through PM9 can be written as: .

[0054] Finally, the maximum level of VREF slope compensation is: .

[0055] I2 is a constant current source. It works with R4 to generate the DC portion of the VREF voltage, while VSET indirectly works with R4 to generate the slope compensation portion. This configuration achieves slope compensation by superimposing a relatively constant DC voltage on VREF and a voltage that rises when the high-side transistor is turned off. Since VSAW is controlled by VSET, and IPM9 is also controlled by VSAW, and the slope compensation portion of VREF is controlled by IPM9, VSET can be used to control the maximum VREF slope compensation value.

[0056] Reference Attachment Figure 2 The third row is a schematic diagram of the superposition principle of VFB and VREF in the present invention. In the prior art, when VSW is low, the VREF voltage rises. Since the comparator within the COT compares the VFB and VREF voltages, the insufficient VFB falling slope can be addressed by increasing the VREF slope. These two methods are mathematically equivalent. The present invention (third row) reduces the VFB falling slope by adding the VREF rising slope, thereby reducing VFB ripple and, consequently, output voltage ripple.

[0057] As can be seen above, the truly effective VREF is the maximum VREF value, that is, the instantaneous VREF value when VSW decreases. This value can be fixed through reasonable internal circuit design, thereby improving output voltage accuracy (this is because the fixed internal ripple can reduce the ripple at the feedback node, thereby improving output accuracy and reducing output ripple). The present invention generates a rising VREF when VSW decreases. At the same time, the maximum VREF value is a designed fixed value (typically approximately 20mV higher than the minimum VREF value). Regardless of changes in operating conditions, this maximum VREF value remains unchanged.

[0058] To make the above description clearer, please refer to the following Figure 3 The simulation diagram in .

[0059] The first line is the PWM level. When PWM is high, it means the upper tube is turned on; when PWM is low, it means the upper tube is turned off.

[0060] The second line shows the VSAW voltage. It can be seen that when the PWM is at a low level, the VSAW voltage rises linearly. When it rises to about 1.5V, it drops almost linearly, and the voltage after the drop is almost 0V.

[0061] The third row shows VC2 and VSET. First, consider VC2, referring to the VSAW signal in the previous row. When the VSAW signal rises, VC2 matches the VSAW voltage. When the VSAW signal falls, VC2 maintains the voltage before the VSAW signal falls and maintains this voltage until the next cycle. When a new cycle arrives, the VSAW signal starts rising from almost 0V because the capacitance of C1 is much greater than that of C2. The VSET signal sets the maximum VSAW voltage level. As can be seen, due to the presence of negative feedback, the highest point of the VSAW signal (the flat section of VC2) is essentially the same as the voltage of the VSET signal.

[0062] The fourth row shows the VC3 signal, which is essentially flat, indicating stable system operation. Due to negative feedback, the VC3 voltage varies under different conditions, leading to different charging currents for capacitor C1. This ultimately causes the maximum VSAW signal to be roughly equal to the VSET voltage.

[0063] The fifth line shows the VREF voltage after compensation. It can be seen that the DC value (or minimum value) of VREF is approximately 1.2V. When the PWM is low, the VREF voltage rises linearly. When the PWM is high again, the VREF voltage rises to about 1.23V, which meets the general compensation requirements of the COT structure.

[0064] It should be understood that the scope of the present invention is not limited to the non-limiting embodiments, and it should be understood that the non-limiting embodiments are only provided as examples. The substantial scope of protection required by this application is further reflected in the scope provided by the independent claims and their dependent claims.

Claims

1. A high-precision slope compensation circuit, comprising a ramp voltage as a first-stage circuit STAGE1, a frequency compensation network as a second-stage circuit STAGE2, and a slope compensation circuit as a third-stage circuit STAGE3, characterized in that: The first stage circuit STAGE1 includes: a pulse width modulation PWM provides an input signal which is connected in series to first and second inverters INV1 and INV2 to generate first and second inverted signals G1 and G2; an output end of the operational amplifier OP1 is connected to the gate of the first NMOS transistor NM1 to form a sawtooth wave voltage VSAW; The second stage circuit STAGE2 is composed of a transconductance amplifier and an RC network for stabilizing the negative feedback network, and includes: an external voltage VB for providing a bias voltage, a setting voltage VSET for controlling the highest potential of the sawtooth wave voltage VSAW; The third stage circuit STAGE3 includes: a first constant current source I1 providing bias current, a second constant current source I2 grounded via a fourth resistor R4 to generate a DC portion of a reference voltage VREF, and the set voltage VSET indirectly cooperates with the fourth resistor R4 to generate a slope compensation portion.

2. The high-precision slope compensation circuit according to claim 1, characterized in that: The external voltage VB is connected to the gate of the third PMOS transistor PM3 serving as a current mirror. The fourth and fifth PMOS transistors PM4 and PM5 form a differential pair and their gates are connected to the sawtooth voltage VSAW and the set voltage VSET, respectively.

3. The high-precision slope compensation circuit according to claim 2, wherein: The gate and drain of the seventh NMOS transistor NM7 are connected to the first constant current source I1, and the source is connected to the sawtooth voltage VSAW. The eighth and ninth PMOS transistors PM8 and PM9 form a common-gate current mirror. The drain of the ninth PMOS transistor PM9 is connected to the second constant current source I2 and grounded via the fourth resistor R4.

4. The high-precision slope compensation circuit according to claim 3, wherein: The gate and drain of the eighth PMOS transistor PM8 are connected to each other and to the drain of the eighth NMOS transistor NM8. The source of the eighth NMOS transistor NM8 is grounded via a third resistor R3, and its gate is connected to the gate of the seventh NMOS transistor NM7. The inverting input terminal of the operational amplifier OP1 is connected to the source of the first NMOS transistor NM1 and to ground via a first resistor R1.

5. The high-precision slope compensation circuit according to claim 4, characterized in that: The first stage circuit STAGE1 further includes: The first and second PMOS transistors PM1 and PM2 form a common-gate current mirror, wherein the gate and drain of the first PMOS transistor PM1 are connected and connected to the drain of the first NMOS transistor NM1, the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2 and grounded via the first capacitor C1 to form the sawtooth voltage VSAW, and the gate of the second NMOS transistor NM2 is connected to the second inverted signal G2; a first transmission gate TG1, wherein an input terminal of the first transmission gate TG1 is connected to the drain of the second PMOS transistor PM2, and a positive and reverse control terminal of the first transmission gate TG1 is connected to the first and second inverted signals G1 and G2, respectively; and an output terminal of the first transmission gate TG1 is connected to the gate of the fourth PMOS transistor PM4 and is grounded via a second capacitor C2 to form a second control voltage VC2.

6. The high-precision slope compensation circuit according to claim 5, characterized in that: The fourth and fifth PMOS transistors PM4 and PM5 share a common source and are connected to the drain of the third PMOS transistor PM3. The gates and drains of the third and fourth NMOS transistors NM3 and NM4 are connected and respectively connected to the drains of the fourth and fifth PMOS transistors PM4 and PM5. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 share a common gate. The third NMOS transistor NM3 and the sixth NMOS transistor NM6 share a common gate. The sixth and seventh PMOS transistors PM6 and PM7 share a common gate and their drains are respectively connected to the drains of the fifth and sixth NMOS transistors NM5 and MN6. The gate and drain of the seventh PMOS transistor PM7 are connected.

7. The high-precision slope compensation circuit according to claim 6, characterized in that: The drain of the fifth NMOS transistor NM5 is connected to the second transmission gate TG2 via the second resistor R2 and is grounded via the third capacitor C3 to form a third control voltage VC3. The third control voltage VC3 is connected to the non-inverting input terminal of the operational amplifier OP1. The second transmission gate TG2 is used to control when error amplification is performed, and its positive and negative control terminals are connected to the second and first inverted signals G2 and G1, respectively.

8. The high-precision slope compensation circuit according to claim 7, characterized in that: When the upper tube of the DC-DC power supply is turned on and off, the pulse width modulation PWM signal is high and low respectively, and the second capacitor C2 is much smaller than the first capacitor C1 to ensure that the VSAW voltage rises almost from 0V.

9. The high-precision slope compensation circuit according to claim 8, characterized in that: The current of the fourth PMOS transistor PM4 is sequentially replicated through the third and sixth NMOS transistors NM3 and MN6, and the seventh and sixth PMOS transistors PM7 and PM6. The current of the fifth PMOS transistor PM5 is replicated through the fourth and fifth NMOS transistors NM4 and NM5, and then output to the second resistor R2 through the drains of the sixth PMOS transistor PM6 and the fifth NMOS transistor NM5. When the set voltage VSET is higher than the second control voltage VC2, the differential current flows from the sixth PMOS transistor PM6 to the second resistor R2; when the set voltage VSET is lower than the second control voltage VC2, the differential current flows out of the second resistor R2 to the fifth NMOS transistor NM5.

10. The high-precision slope compensation circuit according to claim 9, characterized in that: The second resistor R2 and the third capacitor C3 form a frequency compensation network to ensure stable operation of the high-precision slope compensation circuit. The first and second circuits STAGE1 and STAGE2 generate the sawtooth wave voltage VSAW, so that regardless of changes in the operating frequency or the pulse width modulation (PWM) duty cycle, the sawtooth wave voltage VSAW rises at a certain slope when the DC-DC power supply is turned off, and the maximum voltage is controlled by the set voltage VSET.

11. The high-precision slope compensation circuit according to claim 10, characterized in that: The sawtooth voltage VSAW is controlled by the set voltage VSET, and at the same time, the current IPM9 flowing through the ninth PMOS transistor PM9 is controlled by the sawtooth voltage VSAW, and the slope compensation portion of the reference voltage VREF is finally controlled by the current IPM9, so as to achieve the maximum value of the slope compensation of the reference voltage VREF controlled by the set voltage VSET.

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