A switching power supply for controlling load current sharing

Abstract

The present invention discloses a switching power supply for controlling load current sharing, and relates to the technical field of switching power supply management. The present invention connects a plurality of identical power modules in parallel, connects the output VOUT pins of the plurality of identical power modules to form an output pin VCOMP, connects the ISHARE pins of the plurality of identical power modules to form a current sharing pin ISHARE, connects the positive input terminal of an operational amplifier A1 to the current sharing pin ISHARE, connects the negative input terminal of the operational amplifier A1 to the output pin VCOMP, and connects the output terminal of the operational amplifier A1 to a soft-start reference voltage pin SS. That is, the operational amplifier A1 of the present invention controls the operational amplifier A1 to inject or extract current into or from the soft-start reference voltage pin SS by comparing the voltage difference between the output pin VCOMP and the current sharing pin ISHARE, and adjusts the voltage of the soft-start reference voltage pin SS to change the output voltage of the power module, thereby achieving high-precision dynamic load current sharing control.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supply management, and in particular to a switching power supply for controlling load current sharing. Background Art

[0002] In distributed power systems, the building block architecture of multiple modules connected in parallel is widely used in high-power scenarios such as data centers, renewable energy power generation, and electric vehicle charging due to its high efficiency, reliability, and scalability. However, parameter differences between modules (such as internal resistance and output voltage drift) can lead to unbalanced load current distribution, causing local overloads, uneven thermal stress, and reduced system efficiency.

[0003] To address the problem of unbalanced load current distribution, load current sharing technology has gradually been applied to distributed power supply systems due to its high efficiency, reliability and intelligence when applied to distributed power supply systems. The current load current sharing technologies include droop control method and active current sharing method. The droop control method achieves approximate current sharing by adjusting the output impedance, but has low accuracy (≥10%) and sacrifices voltage regulation rate, and is only suitable for low-cost industrial power supplies. The active current sharing method includes average current method, maximum current method and master-slave control method. The average current method achieves high accuracy by collecting the average current value of the current sharing bus, but there is a risk of bus short circuit. The maximum current method relies on dynamic switching of the master module and is easily affected by diode voltage drop error and low-frequency oscillation. The master-slave control method specifies that the master module provides the current reference, and the slave module tracks the master module current. Although it solves the accuracy problem of the impedance method, a failure of the master module will cause the system to crash.

[0004] Therefore, there is an urgent need for a switching power supply that can achieve high-precision dynamic current sharing to improve the safety and efficiency of multi-channel parallel power supply systems. Summary of the Invention

[0005] The embodiment of the present invention provides a switching power supply for controlling load current sharing, which can solve the problems existing in the prior art.

[0006] An embodiment of the present invention provides a switching power supply for controlling load current sharing, comprising a plurality of identical power modules and an operational amplifier A1;

[0007] The power pins VIN of the multiple identical power modules are connected, the ground GND pins of the multiple identical power modules are connected, the output VOUT pins of the multiple identical power modules are connected to form an output pin VCOMP, and the ISHARE pins of the multiple identical power modules are connected to form a current sharing pin ISHARE;

[0008] The positive input terminal of the operational amplifier A1 is connected to the current sharing pin ISHARE, the negative input terminal of the operational amplifier A1 is connected to the output pin VCOMP, and the output terminal of the operational amplifier A1 is connected to the soft-start reference voltage pin SS;

[0009] The operational amplifier A1 controls the operational amplifier A1 to inject or extract current into or from the soft-start reference voltage pin SS based on the voltage difference between the output pin VCOMP and the current sharing pin ISHARE, and adjusts the voltage of the soft-start reference voltage pin SS to change the output voltage of the power module and control the load current sharing.

[0010] Preferably, it further includes a resistor R1;

[0011] The resistor R1 is connected between the output pin VCOMP and the current sharing pin ISHARE. The resistor R1 is used to connect ISHARE and VCOMP to avoid erroneous output when using a single-channel power module.

[0012] Preferably, the operational amplifier A1 includes: a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, a fourth P-type MOS transistor P4, a fifth P-type MOS transistor P5, a sixth P-type MOS transistor P6, a seventh P-type MOS transistor P7, an eighth P-type MOS transistor P8, a ninth P-type MOS transistor P9, a tenth P-type MOS transistor P10, a first N-type MOS transistor N1, a second N-type MOS transistor N2, a third N-type MOS transistor N3, a fourth N-type MOS transistor N4, a fifth N-type MOS transistor N5, a sixth N-type MOS transistor N6, a seventh N-type MOS transistor N7, and an eighth N-type MOS transistor N8;

[0013] The first P-type MOS transistor P1, the second P-type MOS transistor P2, the third P-type MOS transistor P3, the fourth P-type MOS transistor P4, the fifth P-type MOS transistor P5, the sixth P-type MOS transistor P6, the seventh P-type MOS transistor P7, the eighth P-type MOS transistor P8, the ninth P-type MOS transistor P9 and the tenth P-type MOS transistor P10 form a current mirror structure with the first N-type MOS transistor N1, the second N-type MOS transistor N2, the third N-type MOS transistor N3, the fourth N-type MOS transistor N4, the fifth N-type MOS transistor N5, the sixth N-type MOS transistor N6, the seventh N-type MOS transistor N7 and the eighth N-type MOS transistor N8.

[0014] Preferably, the source of the first P-type MOS transistor P1, the source of the second P-type MOS transistor P2, the source of the third P-type MOS transistor P3, the source of the fourth P-type MOS transistor P4, the source of the ninth P-type MOS transistor P9 and the source of the tenth P-type MOS transistor P10 are connected to the power supply VCC;

[0015] The source of the first N-type MOS transistor N1, the source of the second N-type MOS transistor N2, the source of the third N-type MOS transistor N3, the source of the fourth N-type MOS transistor N4, the source of the fifth N-type MOS transistor N5, the source of the sixth N-type MOS transistor N6, the source of the seventh N-type MOS transistor N7 and the source of the eighth N-type MOS transistor N8 are connected to the ground GND;

[0016] The gate of the first P-type MOS transistor P1, the drain of the first P-type MOS transistor P1, the gate of the second P-type MOS transistor P2, the gate of the third P-type MOS transistor P3 and the gate of the fourth P-type MOS transistor P4 are connected to the external bias current IBIAS;

[0017] The drain of the second P-type MOS transistor P2 is connected to the source of the fifth P-type MOS transistor P5 and the source of the sixth P-type MOS transistor P6;

[0018] The drain of the third P-type MOS transistor P3 is connected to the drain of the third N-type MOS transistor N3 and the gate of the fourth N-type MOS transistor N4;

[0019] The drain of the fourth P-type MOS transistor P4 is connected to the drain of the fourth N-type MOS transistor N4, and the source of the seventh P-type MOS transistor P7 is connected to the source of the eighth P-type MOS transistor P8;

[0020] The gate of the fifth P-type MOS transistor P5 is connected to the current sharing pin ISHARE, and the drain of the fifth P-type MOS transistor P5 is connected to the drain of the first N-type MOS transistor N1, the gate of the second N-type MOS transistor N2, and the gate of the first N-type MOS transistor N1;

[0021] The gate of the sixth P-type MOS transistor P6 is connected to the voltage limiting protection pin Vlim, and the drain of the sixth P-type MOS transistor P6 is connected to the drain of the second N-type MOS transistor N2 and the gate of the third N-type MOS transistor N3;

[0022] The gate of the seventh P-type MOS transistor P7 is connected to the output pin VCOMP, and the drain of the seventh P-type MOS transistor P7 is connected to the drain of the sixth N-type MOS transistor N6, the gate of the sixth N-type MOS transistor N6, and the gate of the fifth N-type MOS transistor N5;

[0023] The gate of the eighth P-type MOS transistor P8 is connected to the current sharing pin ISHARE, and the drain of the eighth P-type MOS transistor P8 is connected to the drain of the seventh N-type MOS transistor N7, the gate of the seventh N-type MOS transistor N7, and the gate of the eighth N-type MOS transistor N8;

[0024] The gate of the ninth P-type MOS transistor P9 is connected to the drain of the ninth P-type MOS transistor P9, the drain of the fifth N-type MOS transistor N5, and the gate of the tenth P-type MOS transistor P10;

[0025] The drain of the tenth P-type MOS transistor P10 is connected to the soft-start reference voltage pin SS and the drain of the eighth N-type MOS transistor N8.

[0026] Preferably, the fifth N-type MOS transistor N5 and the sixth N-type MOS transistor N6 form a first current mirror;

[0027] The ninth P-type MOS transistor P9 and the tenth P-type MOS transistor P10 form a second current mirror;

[0028] The seventh N-type MOS transistor N7 and the eighth N-type MOS transistor N8 form a third current mirror.

[0029] Preferably, when the load current of one of the multiple identical power modules is smaller than the load current of the other power modules, the voltage of the output pin VCOMP is lower than the voltage of the current sharing pin ISHARE, and the current flowing through the seventh P-type MOS transistor P7 is greater than the current flowing through the eighth P-type MOS transistor P8;

[0030] The first current mirror and the second current mirror mirror the current flowing through the seventh P-type MOS transistor P7 to the tenth P-type MOS transistor P10; the third current mirror mirrors the current flowing through the eighth P-type MOS transistor P8 to the eighth N-type MOS transistor N8. Therefore, the current flowing through the seventh P-type MOS transistor P7 is higher than the current flowing through the eighth P-type MOS transistor P8, and the current flowing through the tenth P-type MOS transistor P10 is higher than the current flowing through the eighth N-type MOS transistor N8. Therefore, current is injected into the soft-start reference voltage pin SS to increase the voltage of the soft-start reference voltage pin SS, thereby increasing the voltage of the output pin VOUT of the power module, thereby increasing the load current of the power module.

[0031] Preferably, when the load current of one of the multiple identical power modules is higher than the load current of the other power modules, the voltage of the output pin VCOMP is higher than the voltage of the current sharing pin ISHARE, and the current flowing through the seventh P-type MOS transistor P7 is smaller than the current flowing through the eighth P-type MOS transistor P8;

[0032] The first current mirror and the second current mirror mirror the current flowing through the tenth P-type MOS transistor P10 to the seventh P-type MOS transistor P7; the third current mirror mirrors the current flowing through the eighth N-type MOS transistor N8 to the eighth P-type MOS transistor P8. Then, the current flowing through the seventh P-type MOS transistor P7 is smaller than the current flowing through the eighth P-type MOS transistor P8, and the current flowing through the tenth P-type MOS transistor P10 is smaller than the current flowing through the eighth N-type MOS transistor N8. Then, current is drawn from the soft-start reference voltage pin SS to reduce the voltage of the soft-start reference voltage pin SS, thereby reducing the voltage of the output pin VOUT of the power module, thereby reducing the load current of the power module.

[0033] Preferably, when there is only one power module, the voltage of the current sharing pin ISHARE is floating, that is, the voltage of the current sharing pin ISHARE is lower than the voltage of the voltage limiting protection pin Vlim, then the gate voltage of the third N-type MOS transistor N3 is reduced, the drain voltage of the third N-type MOS transistor N3 and the gate voltage of the fourth N-type MOS transistor N4 are increased, so as to increase the drain voltage of the fourth P-type MOS transistor P4, the operational amplifier A1 is turned off, and the soft-start reference voltage pin SS does not generate an erroneous output.

[0034] The embodiment of the present invention provides a switching power supply for controlling load current sharing. Compared with the prior art, the embodiment of the present invention has the following advantages:

[0035] The present invention connects multiple identical power modules in parallel, connects the output VOUT pins of the multiple identical power modules to form an output pin VCOMP, connects the ISHARE pins of the multiple identical power modules to form a current sharing pin ISHARE, connects the positive input terminal of an operational amplifier A1 to the current sharing pin ISHARE, connects the negative input terminal of the operational amplifier A1 to the output pin VCOMP, and connects the output terminal of the operational amplifier A1 to a soft-start reference voltage pin SS. That is, the operational amplifier A1 of the present invention controls the operational amplifier A1 to inject or extract current into or from the soft-start reference voltage pin SS by comparing the voltage difference between the output pin VCOMP and the current sharing pin ISHARE, and adjusts the voltage of the soft-start reference voltage pin SS to change the output voltage of the power module, thereby achieving high-precision dynamic load current sharing control.

[0036] Moreover, when the load current of the power module is smaller than the load current of other power modules, the voltage of the output pin VCOMP is lower than the voltage of the current sharing pin ISHARE, and the operational amplifier A1 injects current into the soft-start reference voltage pin SS to increase the voltage of the soft-start reference voltage pin SS, so that the output VOUT pin voltage of the power module becomes larger, resulting in an increase in the load current of the power module; when the load current of the power module is higher than the load current of other power modules, the voltage of the output pin VCOMP is higher than the voltage of the current sharing pin ISHARE, and the operational amplifier A1 draws current from the soft-start reference voltage pin SS to reduce the voltage of the soft-start reference voltage pin SS, so that the output VOUT pin voltage of the power module is reduced, resulting in a reduction in the load current of the power module, thereby realizing dynamic load current sharing. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of multiple parallel connection of switching power supplies for controlling load current sharing provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the load current sharing principle of a switching power supply for controlling load current sharing provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the implementation principle of an operational amplifier of a switching power supply for controlling load current sharing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0041] See also Figure 1 The embodiment of the present invention provides a switching power supply for controlling load current sharing, which solves the problem of uneven load when the switching power supply power modules are connected in parallel in multiple ways; Figure 1 It is a structural diagram of a multi-channel parallel power module, where the VIN pin is the power input pin of the power unit module, the ISHARE pin is the load current sharing pin, the OUT pin is the output voltage pin, and the GND is the ground pin; at the same time, the chip has VCOMP as the error amplifier output pin and SS as the soft-start reference voltage pin.

[0042] The connection relationship is as follows: the power pins VIN of multiple identical power modules are connected, the ground GND pins of multiple identical power modules are connected, the output VOUT pins of multiple identical power modules are connected, and the ISHARE pins of multiple identical power modules are connected.

[0043] When multiple switching power modules are connected in parallel, the load of each switching power module usually remains consistent. However, when one of the switching power modules is short-circuited or damaged, the loads of other modules may no longer remain consistent during the change process. In this case, the load current sharing solution is used to keep the load borne by each module consistent.

[0044] like Figure 2 As shown, it is a schematic diagram of the principle of the load current sharing method provided by the present invention; wherein VCOMP is the error amplifier output pin, ISHARE is the load current sharing pin, and SS is the soft-start reference voltage pin; wherein the positive input terminal of the operational amplifier A1 is connected to ISHARE, the negative input terminal is connected to VCOMP, and the output terminal is connected to SS; the resistor R1 is connected between ISHARE and VCOMP; the function of the resistor R1 is to connect ISHARE and VCOMP when using a single-channel power module to avoid generating erroneous output.

[0045] like Figure 3FIG. 1 is a schematic diagram showing the implementation principle of the operational amplifier A1 provided by the present invention.

[0046] Among them, Vlim is the voltage limit protection pin, VCOMP is the error amplifier output pin, ISHARE is the load current sharing pin, and SS is the soft-start reference voltage pin.

[0047] Specifically, they include: a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, a fourth P-type MOS transistor P4, a fifth P-type MOS transistor P5, a sixth P-type MOS transistor P6, a seventh P-type MOS transistor P7, an eighth P-type MOS transistor P8, a ninth P-type MOS transistor P9, a tenth P-type MOS transistor P10, a first N-type MOS transistor N1, a second N-type MOS transistor N2, a third N-type MOS transistor N3, a fourth N-type MOS transistor N4, a fifth N-type MOS transistor N5, a sixth N-type MOS transistor N6, a seventh N-type MOS transistor N7, and an eighth N-type MOS transistor N8.

[0048] The source of the first P-type MOS transistor P1, the source of the second P-type MOS transistor P2, the source of the third P-type MOS transistor P3, the source of the fourth P-type MOS transistor P4, the source of the ninth P-type MOS transistor P9, and the source of the tenth P-type MOS transistor P10 are connected to the internal power supply VCC.

[0049] The source of the first N-type MOS transistor N1, the source of the second N-type MOS transistor N2, the source of the third N-type MOS transistor N3, the source of the fourth N-type MOS transistor N4, the source of the fifth N-type MOS transistor N5, the source of the sixth N-type MOS transistor N6, the source of the seventh N-type MOS transistor N7, and the source of the eighth N-type MOS transistor N8 are connected to the ground GND.

[0050] The gate of the first P-type MOS transistor P1, the drain of the first P-type MOS transistor P1, the gate of the second P-type MOS transistor P2, the gate of the third P-type MOS transistor P3, and the gate of the fourth P-type MOS transistor P4 are connected to the external bias current IBIAS.

[0051] The drain of the second P-type MOS transistor P2 is connected to the source of the fifth P-type MOS transistor P5 and the source of the sixth P-type MOS transistor P6.

[0052] The drain of the third P-type MOS transistor P3 is connected to the drain of the third N-type MOS transistor N3 and the gate of the fourth N-type MOS transistor N4.

[0053] The drain of the fourth P-type MOS transistor P4 is connected to the drain of the fourth N-type MOS transistor N4, the source of the seventh P-type MOS transistor P7, and the source of the eighth P-type MOS transistor P8.

[0054] The gate of the fifth P-type MOS transistor P5 is connected to ISHARE, and the drain of the fifth P-type MOS transistor P5 is connected to the drain of the first N-type MOS transistor N1, the gate of the second N-type MOS transistor N2, and the gate of the first N-type MOS transistor N1.

[0055] The gate of the sixth P-type MOS transistor P6 is connected to Vlim, and the drain of the sixth P-type MOS transistor P6 is connected to the drain of the second N-type MOS transistor N2 and the gate of the third N-type MOS transistor N3.

[0056] The gate of the seventh P-type MOS transistor P7 is connected to VCOMP, and the drain of the seventh P-type MOS transistor P7 is connected to the drain of the sixth N-type MOS transistor N6, the gate of the sixth N-type MOS transistor N6 and the gate of the fifth N-type MOS transistor N5.

[0057] The gate of the eighth P-type MOS transistor P8 is connected to ISHARE, and the drain of the eighth P-type MOS transistor P8 is connected to the drain of the seventh N-type MOS transistor N7, the gate of the seventh N-type MOS transistor N7, and the gate of the eighth N-type MOS transistor N8.

[0058] The gate of the ninth P-type MOS transistor P9 is connected to the drain of the ninth P-type MOS transistor P9 , the drain of the fifth N-type MOS transistor N5 , and the gate of the tenth P-type MOS transistor P10 .

[0059] The drain of the tenth P-type MOS transistor P10 is connected to SS and the drain of the eighth N-type MOS transistor N8.

[0060] The working principle of the solution provided by the present invention is as follows: multiple parallel power modules are connected to ISHARE. During normal operation, the multiple parallel power modules share the load current. The VCOMP voltage on each power unit is roughly equal and ISHARE is connected to each other, so the SS end will not be affected by the load current sharing circuit; the load current sharing circuit amplifies the difference between ISHARE and VCOMP to inject or drain current into the SS voltage, thereby adjusting the SS soft-start reference voltage, and the SS soft-start reference voltage will adjust the output voltage, thereby adjusting the load current borne by the power unit; when the load on a power unit is When the load current is too large or too small, the voltage of VCOMP will be different. For example, when the load current on the power unit is too small, the VCOMP voltage will be lower than the ISHARE voltage. The current flowing through P7 is greater than the current flowing through P8. The current mirrors N5, N6 and P9, P10 mirror the current flowing through P7 to P10, and the current mirrors N7, N8 mirror the current flowing through P8 to N8. Since the current flowing through P7 is greater than the current flowing through P8, the current of P10 is greater than the current of N8, and the current is injected into the SS pin to increase the SS pin voltage, increase the VOUT voltage, and increase the load current.

[0061] When the application is a single-channel power module, the ISHARE voltage is floating. In order to avoid the output voltage being too low, when the ISHARE voltage is detected to be lower than the limit value Vlim, the N3 gate voltage is pulled down, so that the N3 drain and N4 gate voltages are raised, thereby pulling down the P4 drain voltage and turning off the main amplifier of the load current sharing circuit.

[0062] The present invention can satisfy the requirement that each power module bears the same load under the working condition of multiple power units connected in parallel, and at the same time realize the current equalization control of the output current of the power supply to the combined output terminal, avoiding the safety hazards caused by power supply short circuit, excessive voltage at the combined output terminal and fluctuation of output current, thereby realizing safe current equalization control of the power supply of multiple power supplies.

[0063] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A switching power supply for controlling load current sharing, characterized in that: include: Multiple identical power modules and operational amplifier A1; The power pins VIN of the multiple identical power modules are connected, the ground GND pins of the multiple identical power modules are connected, the output VOUT pins of the multiple identical power modules are connected to form an output pin VCOMP, and the ISHARE pins of the multiple identical power modules are connected to form a current sharing pin ISHARE; The positive input terminal of the operational amplifier A1 is connected to the current sharing pin ISHARE, the negative input terminal of the operational amplifier A1 is connected to the output pin VCOMP, and the output terminal of the operational amplifier A1 is connected to the soft-start reference voltage pin SS; The operational amplifier A1 controls the operational amplifier A1 to inject or extract current into or from the soft-start reference voltage pin SS based on the voltage difference between the output pin VCOMP and the current sharing pin ISHARE, thereby adjusting the voltage of the soft-start reference voltage pin SS to change the output voltage of the power module and control the load current sharing. The operational amplifier A1 includes: a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, a fourth P-type MOS transistor P4, a fifth P-type MOS transistor P5, a sixth P-type MOS transistor P6, a seventh P-type MOS transistor P7, an eighth P-type MOS transistor P8, a ninth P-type MOS transistor P9, a tenth P-type MOS transistor P10, a first N-type MOS transistor N1, a second N-type MOS transistor N2, a third N-type MOS transistor N3, a fourth N-type MOS transistor N4, a fifth N-type MOS transistor N5, a sixth N-type MOS transistor N6, a seventh N-type MOS transistor N7, and an eighth N-type MOS transistor N8; The first P-type MOS transistor P1, the second P-type MOS transistor P2, the third P-type MOS transistor P3, the fourth P-type MOS transistor P4, the fifth P-type MOS transistor P5, the sixth P-type MOS transistor P6, the seventh P-type MOS transistor P7, the eighth P-type MOS transistor P8, the ninth P-type MOS transistor P9 and the tenth P-type MOS transistor P10, together with the first N-type MOS transistor N1, the second N-type MOS transistor N2, the third N-type MOS transistor N3, the fourth N-type MOS transistor N4, the fifth N-type MOS transistor N5, the sixth N-type MOS transistor N6, the seventh N-type MOS transistor N7 and the eighth N-type MOS transistor N8, form a current mirror structure; The source of the first P-type MOS transistor P1, the source of the second P-type MOS transistor P2, the source of the third P-type MOS transistor P3, the source of the fourth P-type MOS transistor P4, the source of the ninth P-type MOS transistor P9 and the source of the tenth P-type MOS transistor P10 are connected to the power supply VCC; The source of the first N-type MOS transistor N1, the source of the second N-type MOS transistor N2, the source of the third N-type MOS transistor N3, the source of the fourth N-type MOS transistor N4, the source of the fifth N-type MOS transistor N5, the source of the sixth N-type MOS transistor N6, the source of the seventh N-type MOS transistor N7 and the source of the eighth N-type MOS transistor N8 are connected to the ground GND; The gate of the first P-type MOS transistor P1, the drain of the first P-type MOS transistor P1, the gate of the second P-type MOS transistor P2, the gate of the third P-type MOS transistor P3 and the gate of the fourth P-type MOS transistor P4 are connected to the external bias current IBIAS; The drain of the second P-type MOS transistor P2 is connected to the source of the fifth P-type MOS transistor P5 and the source of the sixth P-type MOS transistor P6; The drain of the third P-type MOS transistor P3 is connected to the drain of the third N-type MOS transistor N3 and the gate of the fourth N-type MOS transistor N4; The drain of the fourth P-type MOS transistor P4 is connected to the drain of the fourth N-type MOS transistor N4, and the source of the seventh P-type MOS transistor P7 is connected to the source of the eighth P-type MOS transistor P8; The gate of the fifth P-type MOS transistor P5 is connected to the current sharing pin ISHARE, and the drain of the fifth P-type MOS transistor P5 is connected to the drain of the first N-type MOS transistor N1, the gate of the second N-type MOS transistor N2, and the gate of the first N-type MOS transistor N1; The gate of the sixth P-type MOS transistor P6 is connected to the voltage limiting protection pin Vlim, and the drain of the sixth P-type MOS transistor P6 is connected to the drain of the second N-type MOS transistor N2 and the gate of the third N-type MOS transistor N3; The gate of the seventh P-type MOS transistor P7 is connected to the output pin VCOMP, and the drain of the seventh P-type MOS transistor P7 is connected to the drain of the sixth N-type MOS transistor N6, the gate of the sixth N-type MOS transistor N6, and the gate of the fifth N-type MOS transistor N5; The gate of the eighth P-type MOS transistor P8 is connected to the current sharing pin ISHARE, and the drain of the eighth P-type MOS transistor P8 is connected to the drain of the seventh N-type MOS transistor N7, the gate of the seventh N-type MOS transistor N7, and the gate of the eighth N-type MOS transistor N8; The gate of the ninth P-type MOS transistor P9 is connected to the drain of the ninth P-type MOS transistor P9, the drain of the fifth N-type MOS transistor N5, and the gate of the tenth P-type MOS transistor P10; The drain of the tenth P-type MOS transistor P10 is connected to the soft-start reference voltage pin SS and the drain of the eighth N-type MOS transistor N8; The fifth N-type MOS transistor N5 and the sixth N-type MOS transistor N6 form a first current mirror; The ninth P-type MOS transistor P9 and the tenth P-type MOS transistor P10 form a second current mirror; The seventh N-type MOS transistor N7 and the eighth N-type MOS transistor N8 form a third current mirror.

2. A switching power supply for controlling load current sharing according to claim 1, characterized in that: Also includes resistor R1; The resistor R1 is connected between the output pin VCOMP and the current sharing pin ISHARE. The resistor R1 is used to connect ISHARE and VCOMP to avoid erroneous output when using a single-channel power module.

3. The switching power supply for controlling load current sharing according to claim 1, characterized in that: When the load current of one of the multiple identical power modules is smaller than the load current of the other power modules, the voltage of the output pin VCOMP is lower than the voltage of the current sharing pin ISHARE, and the current flowing through the seventh P-type MOS transistor P7 is greater than the current flowing through the eighth P-type MOS transistor P8; The first current mirror and the second current mirror mirror the current flowing through the seventh P-type MOS transistor P7 to the tenth P-type MOS transistor P10; the third current mirror mirrors the current flowing through the eighth P-type MOS transistor P8 to the eighth N-type MOS transistor N8. Therefore, the current flowing through the seventh P-type MOS transistor P7 is higher than the current flowing through the eighth P-type MOS transistor P8, and the current flowing through the tenth P-type MOS transistor P10 is higher than the current flowing through the eighth N-type MOS transistor N8. Therefore, current is injected into the soft-start reference voltage pin SS to increase the voltage of the soft-start reference voltage pin SS, thereby increasing the voltage of the output pin VOUT of the power module, thereby increasing the load current of the power module.

4. The switching power supply for controlling load current sharing according to claim 1, characterized in that: When the load current of one of the multiple identical power modules is higher than the load current of the other power modules, the voltage of the output pin VCOMP is higher than the voltage of the current sharing pin ISHARE, and the current flowing through the seventh P-type MOS transistor P7 is lower than the current flowing through the eighth P-type MOS transistor P8; The first current mirror and the second current mirror mirror the current flowing through the tenth P-type MOS transistor P10 to the seventh P-type MOS transistor P7; the third current mirror mirrors the current flowing through the eighth N-type MOS transistor N8 to the eighth P-type MOS transistor P8. Then, the current flowing through the seventh P-type MOS transistor P7 is smaller than the current flowing through the eighth P-type MOS transistor P8, and the current flowing through the tenth P-type MOS transistor P10 is smaller than the current flowing through the eighth N-type MOS transistor N8. Then, current is drawn from the soft-start reference voltage pin SS to reduce the voltage of the soft-start reference voltage pin SS, thereby reducing the voltage of the output pin VOUT of the power module, thereby reducing the load current of the power module.

5. The switching power supply for controlling load current sharing according to claim 1, characterized in that: When there is only one power module, the voltage of the current sharing pin ISHARE is floating, that is, the voltage of the current sharing pin ISHARE is lower than the voltage of the voltage limiting protection pin Vlim, then the gate voltage of the third N-type MOS transistor N3 decreases, the drain voltage of the third N-type MOS transistor N3 and the gate voltage of the fourth N-type MOS transistor N4 increase, so as to increase the drain voltage of the fourth P-type MOS transistor P4, the operational amplifier A1 is turned off, and the soft-start reference voltage pin SS does not generate an erroneous output.

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