Signal level conversion circuit and electronic device

Abstract

The invention discloses a signal level conversion circuit and an electronic device. The circuit includes: an input electrically coupled to a first supply voltage; an output electrically coupled to a second supply voltage; a voltage regulation module electrically coupled to the second supply voltage, configured to perform voltage regulation based on the second supply voltage to output a control voltage from the control node; a transistor including a first conductive terminal electrically coupled to the input terminal, a second conductive terminal electrically coupled to the output terminal, a control terminal electrically coupled to the control node of the voltage regulation module, and configured to be powered on at the first conductive terminal prior to the second conductive terminal, the second conductive terminal is turned on when the first conductive terminal is at a first level such that the second conductive terminal is at the first level, and turned off when the first conductive terminal is at a second level corresponding to the first supply voltage such that the second conductive terminal is at a third level corresponding to the second supply voltage. The problem of electric leakage when the low-voltage power supply is powered on firstly can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a signal level conversion circuit and electronic equipment. Background Art

[0002] With the continuous advancement of chip technology, the GPIO (General Purpose Input / Output) voltage of AP (Application Processor) chips is decreasing. Communication between low-level signals from AP chips and high-level signals from peripheral chips requires level conversion. Furthermore, most AP chips have specific timing requirements for power supply: the low-voltage power supply must be powered on before the high-voltage power supply. However, existing level conversion circuits on the market have certain drawbacks: first, the circuit design is complex, increasing the difficulty of manufacturing and integration; second, power supply security cannot be guaranteed. When the low-voltage power supply is powered on first, current can leak to the high-voltage power supply, causing application reliability issues. Summary of the Invention

[0003] The present invention provides a signal level conversion circuit and an electronic device, and more specifically provides a leakage-free low-voltage to high-voltage signal level conversion circuit, which can achieve level conversion based on a simple circuit while avoiding leakage problems that occur when a low-voltage power supply is powered on first.

[0004] In one aspect of the present invention, a signal level conversion circuit is provided. The circuit includes: an input terminal electrically coupled to a first power supply voltage; an output terminal electrically coupled to a second power supply voltage, the second power supply voltage being greater than the first power supply voltage; a voltage regulation module electrically coupled to the second power supply voltage and configured to perform voltage regulation based on the second power supply voltage to output a control voltage from a control node, the control voltage being less than the first power supply voltage; and a transistor including a first conduction terminal electrically coupled to the input terminal, a second conduction terminal electrically coupled to the output terminal, and a control terminal electrically coupled to the control node of the voltage regulation module, and configured to be powered on at the first conduction terminal before the second conduction terminal, to conduct when the first conduction terminal is at a first level so that the second conduction terminal is at the first level, and to be turned off when the first conduction terminal is at a second level corresponding to the first power supply voltage so that the second conduction terminal is at a third level corresponding to the second power supply voltage, the third level being greater than the second level, and the second level being greater than the first level.

[0005] In another aspect of the present invention, an electronic device is provided. The electronic device includes an application processor, a peripheral device, and the above-mentioned signal level conversion circuit, wherein the application processor includes a transmitting end, the peripheral device includes a receiving end, wherein the input end is electrically coupled to the transmitting end, and the output end is electrically coupled to the receiving end.

[0006] According to the technical solution of the present invention, the input terminal is connected to a first power supply voltage, the output terminal is connected to a second power supply voltage, a voltage regulation module outputs a control voltage based on the second power supply voltage, and a transistor controls the conduction or disconnection of the first and second conduction terminals according to the control voltage, so that the output terminal outputs different voltage levels. When the first conduction terminal is at a first voltage level, the transistor is turned on, and the second conduction terminal coupled to the output terminal outputs the first voltage level of the first conduction terminal. When the first conduction terminal is at a second voltage level corresponding to the first power supply voltage, the transistor is turned off, and the second conduction terminal coupled to the output terminal outputs a third voltage level corresponding to the second power supply voltage. When the first power supply voltage is applied first and the second power supply voltage is applied later, the transistor is turned off, eliminating a leakage path from the first power supply to the second conduction terminal, thereby preventing leakage problems that may occur when the low-voltage power supply is applied first.

[0007] The present invention achieves level conversion between the input and output terminals solely through transistors, effectively reducing circuit complexity and simplifying circuit manufacturing and integration. Because the first power supply voltage is always lower than the second power supply voltage, level signal conversion from the low-voltage side to the high-voltage side is achieved. Furthermore, because the control voltage output by the voltage regulation module is always lower than the first power supply voltage, this prevents the low-voltage side from powering up first and leaking electricity to the high-voltage side. This also limits the power-up timing of the low-voltage and high-voltage sides, effectively improving the reliability of the application chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 1 is a circuit diagram of a signal level conversion circuit according to an embodiment of the present invention; Figure 2 Schematic diagram of parameters of a signal level conversion circuit according to an embodiment of the present invention; Figure 3 2 is a structural block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0010] In existing technologies, communication between low-level signals from the AP chip and high-level signals from peripheral chips requires level conversion. Furthermore, most AP chips have specific timing requirements for power supply, requiring the low-voltage power supply to be powered on before the high-voltage power supply. However, existing level conversion circuits on the market have certain drawbacks: first, the circuit design is complex, increasing the difficulty of manufacturing and integration; second, power supply security cannot be guaranteed. When the low-voltage power supply is powered on first, current can leak to the high-voltage power supply, causing reliability issues in the application.

[0011] To address at least the aforementioned technical issues, the present disclosure provides a signal level conversion circuit. According to the present disclosure, an input terminal is connected to a first power supply voltage, an output terminal is connected to a second power supply voltage, a voltage regulation module outputs a control voltage based on the second power supply voltage, and a transistor controls the conduction or disconnection of a first conduction terminal and a second conduction terminal according to the control voltage, so that the output terminal outputs different levels. When the first conduction terminal is at a first level, the transistor is turned on, and a second conduction terminal coupled to the output terminal outputs the first level of the first conduction terminal. When the first conduction terminal is at a second level corresponding to the first power supply voltage, the transistor is turned off, and a second conduction terminal coupled to the output terminal outputs a third level corresponding to the second power supply voltage. In this way, according to an embodiment of the present disclosure, level conversion between the input terminal and the output terminal is achieved solely through transistors, effectively reducing circuit complexity and easing the difficulty of circuit manufacturing and integration. Because the first power supply voltage is always lower than the second power supply voltage, level signal conversion from the low voltage side to the high voltage side is achieved. In addition, since the control voltage output by the voltage regulation module is always lower than the first power supply voltage, it avoids the low-voltage side from being powered on first and leaking to the high-voltage side. At the same time, it limits the power-on timing of the low-voltage side and the high-voltage side, effectively improving the reliability of the application chip.

[0012] According to an embodiment of the present disclosure, when the first power supply voltage is powered on first and the second power supply voltage is powered on later, the transistor is cut off, and there will be no leakage path from the first power supply to the second conduction terminal, thereby avoiding the leakage problem that occurs when the low-voltage power supply is powered on first.

[0013] According to an embodiment of the present disclosure, the second power supply voltage is divided by a first resistor and a second resistor so that the control voltage of the base of the input transistor is half of the second power supply voltage. When the input terminal receives a second level corresponding to the first power supply voltage, the base voltage of the transistor is lower than the emitter voltage, and the transistor cannot turn on the input terminal and the output terminal. Therefore, the level state of the output terminal is pulled up by the fourth resistor, thereby outputting a third level corresponding to the second power supply voltage. When the input terminal receives a first level with a voltage of 0, the base voltage of the transistor is higher than the emitter voltage, and the transistor turns on the input terminal and the output terminal. Therefore, the level state of the output terminal is pulled down by the first level, thereby outputting a first level with a voltage of 0. In this way, the present invention controls the conduction state of a single transistor through different power supply voltages, thereby avoiding the problem of leakage to the high-voltage side power supply due to the low-voltage side power supply being powered on first during level conversion.

[0014] Hereinafter, the technical solutions according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0015] Figure 1 1 is a circuit diagram showing a signal level conversion circuit 100 according to an embodiment of the present disclosure. Figure 1 The circuit 100 includes an input terminal 102, a voltage regulating module 104, a transistor 106, and an output terminal 108. The input terminal 102 is electrically coupled to a first power supply voltage VCC_L, and the output terminal 108 is electrically coupled to a second power supply voltage VCC_H, which is greater than the first power supply voltage VCC_L.

[0016] The voltage regulating module 104 is electrically coupled to the second power supply voltage VCC_H and is configured to perform voltage regulation based on the second power supply voltage VCC_H to output a control voltage from a control node, the control voltage being lower than the first power supply voltage VCC_L.

[0017] In some embodiments, the voltage regulation module 104 is configured to divide the second power supply voltage VCC_H to output a control voltage from the control node. This ensures that the control voltage received by the transistor is always lower than the first power supply voltage VCC_L, thereby preventing leakage through the transistor to the high-voltage side when the low-voltage side is powered on first, effectively improving the reliability of the application chip.

[0018] In some embodiments, the voltage regulation module 104 includes a first resistor R1 and a second resistor R2. The first resistor R1 is electrically coupled between the second power supply voltage VCC_H and a control node, and the second resistor R2 is electrically coupled between the control node and ground. In this manner, the second power supply voltage is divided by the first resistor and the second resistor.

[0019] In some embodiments, the resistance values of the first resistor R1 and the second resistor R2 satisfy the following formula: the amplitude of the first power supply voltage VCC_L > the amplitude of the second power supply voltage VCC_H × the resistance value of the second resistor R2 / the sum of the resistance values of the first resistor R1 and the second resistor R2. In this way, because the second level enables the low-voltage power supply to power up, the resistance values of the resistors can be set to ensure that the second level corresponding to the first power supply voltage is greater than the control voltage. This ensures that the transistor is in the off state when the low-voltage side is powered up first, thereby preventing leakage from the low-voltage side to the high-voltage side.

[0020] Transistor 106 includes a first conduction terminal 1062 electrically coupled to input 102, a second conduction terminal 1064 electrically coupled to output 108, and a control terminal 1066 electrically coupled to a control node of voltage regulation module 104. Transistor 106 is configured to be powered on at first conduction terminal 1062 before second conduction terminal 1064, to be turned on when first conduction terminal 1062 is at a first level such that second conduction terminal 1064 is at the first level, and to be turned off when first conduction terminal 1062 is at a second level corresponding to the first power supply voltage such that second conduction terminal 1064 is at a third level corresponding to the second power supply voltage, the third level being greater than the second level, and the second level being greater than the first level.

[0021] In some embodiments, transistor 106 is configured to operate in a saturation region when first conduction terminal 1062 is at a low level, and to operate in a cutoff region when first conduction terminal 1062 is at a high level corresponding to a first power supply voltage. In this way, the operating state of the transistor is controlled by different levels.

[0022] In some embodiments, the input terminal 102 is further electrically coupled to a transmitting terminal of the first chip and configured to cause the first conductive terminal 1062 to be at a low level when the transmitting terminal transmits a low level signal, and to cause the first conductive terminal 1062 to be at a high level corresponding to the first power supply voltage VCC_L when the transmitting terminal transmits a first high level signal. Furthermore, the output terminal 108 is further electrically coupled to a receiving terminal of the second chip and configured to cause the receiving terminal to receive a low level signal when the transmitting terminal transmits a low level signal, and to cause the receiving terminal to receive a second high level signal when the transmitting terminal transmits a first high level signal, wherein the voltage of the second high level signal is greater than the voltage of the first high level signal.

[0023] In a specific application scenario, the input terminal 102 is electrically coupled to a signal transmitting terminal (low voltage side) of a chip SOC, and the output terminal 108 is electrically coupled to a signal receiving terminal (high voltage side) of a peripheral chip.

[0024] In some embodiments, transistor 106 is configured to turn on based on a control voltage at control terminal 1066 when first conduction terminal 1062 is at a first level, thereby pulling second conduction terminal 1064 down to the first level. Furthermore, transistor 106 is configured to turn off based on a control voltage at control terminal 1066 when first conduction terminal 1062 is at a second level corresponding to first power supply voltage VCC_L, thereby pulling second conduction terminal 1064 up to a third level corresponding to second power supply voltage VCC_H. In this manner, when the level at the first conduction terminal is less than the control voltage, the transistor turns on, and the second conduction terminal outputs a level corresponding to the first conduction terminal. When the level at the first conduction terminal is greater than the control voltage, the transistor turns off, and the second conduction terminal outputs a level corresponding to the second power supply voltage. This prevents leakage from the low-voltage side to the high-voltage side when powered on first, while enabling the output of a third level based on the second power supply voltage, completing voltage conversion between signals of different levels. This allows the high-voltage power supply to be controlled by the level of the low-voltage power supply, preventing the high-voltage side from powering on before the low-voltage side, effectively controlling the power-up timing of the high and low voltage sides.

[0025] In some embodiments, transistor 106 may include a bipolar junction transistor. In some embodiments, transistor 106 may include a base B electrically coupled to a control node, an emitter E electrically coupled to an input terminal, and a collector C electrically coupled to an output terminal.

[0026] In some embodiments, the input terminal 102 includes a third resistor R3, and the first conduction terminal 1062 is electrically coupled to the first power supply voltage VCC_L via the third resistor R3. Furthermore, the output terminal 108 includes a fourth resistor R4, and the second conduction terminal 1064 is electrically coupled to the second power supply voltage VCC_H via the fourth resistor R4. In this way, the third and fourth resistors, respectively, control the voltage levels of the input and output terminals when they are cleared, thereby protecting circuit safety.

[0027] In a specific scenario, when input terminal 102 receives a signal from a chip SOC, a GPIO (general purpose input / output) pin of the chip SOC can be configured as a pull-up resistor to replace the third resistor R3. When output terminal 108 outputs a signal from the chip SOC, a GPIO (general purpose input / output) pin of the chip SOC can be configured as a pull-up resistor to replace the fourth resistor R4.

[0028] Figure 2 FIG. 1 is a schematic diagram showing parameters of the signal level conversion circuit 100 according to an embodiment of the present disclosure. Figure 2 In a specific scenario, the first power supply voltage is 1.8V and the second power supply voltage is 3.3V.

[0029] In this scenario, the resistance values of the first resistor R1 and the second resistor R2 should satisfy the following condition: first power supply voltage 1.8V > second power supply voltage 3.3V × resistance value of second resistor R2 / (resistance value of first resistor R1 + resistance value of second resistor R2). If the resistance values of the first resistor R1 and the second resistor R2 do not meet this condition, then when the first conduction terminal is at the second voltage level (the voltage of the second voltage level is the first power supply voltage 1.8V), the control voltage of the input transistor is still greater than the first power supply voltage, and therefore the transistor cannot be turned off.

[0030] In some embodiments, the first resistor R1 and the second resistor R2 have equal resistance values of 100 kΩ, and the third resistor R3 and the fourth resistor R4 have equal resistance values of 47 kΩ. In this circuit, the second power supply voltage 3.3 V is divided by the first resistor R1 and the second resistor R2 to obtain a control voltage = 3.3 V × 100 kΩ / (100 kΩ + 100 kΩ) = 1.65 V. This means that the voltage at the base B of the input transistor 106 is 1.65 V. When the input terminal TX is at the second level, the voltage at the emitter E of the input transistor 106 is 1.8 V. When the input terminal TX is at the first level, the voltage at the emitter E of the input transistor 106 is 0 V.

[0031] When the voltage at the emitter E of the transistor 106 is 1.8 V, the voltage at the emitter E of the transistor 106 is greater than the voltage at the base B, and the transistor is in the off state. Therefore, the output terminal RX is pulled up to the second power supply voltage of 3.3 V by the fourth resistor R4. When the voltage at the emitter E of the transistor 106 is 0 V, the voltage at the emitter E of the transistor 106 is less than the voltage at the base B, and the transistor is in the on state. Therefore, the output terminal RX is pulled down to 0 V by the first level received by the input terminal TX.

[0032] From this, we can see that when the input level of the input terminal TX is 0V, the output level of the output terminal RX is 0V. When the input level of the input terminal TX is 1.8V, the output level of the output terminal RX is 3.3V. The level of the output terminal RX follows the level of the input terminal TX.

[0033] In another aspect of the present invention, Figure 3 1 is a block diagram showing a structure of an electronic device according to an embodiment of the present disclosure. Figure 3 The electronic device 200 includes an application processor 202, a peripheral device 204, and the signal level conversion circuit 100 of the above embodiment. The application processor 202 includes a transmitting end, the peripheral device 204 includes a receiving end, the input end is electrically coupled to the transmitting end, and the output end is electrically coupled to the receiving end.

[0034] In summary, the present invention provides a signal level conversion circuit and electronic device. When the level signal on the low-voltage side is at a first level of 0, the transistor is controlled to be turned on so that the output level of the high-voltage side is consistent with the output level of the low-voltage side, both being the first level. When the low-voltage side is at a second level of the first power supply voltage, the transistor is controlled to be turned off so that the output voltage of the high-voltage side is at a third level of the second power supply voltage, that is, the output level of the low-voltage side is converted to the output level of the high-voltage side. The present invention only controls the level of the output terminal to change with the level of the input terminal by turning the transistor on and off, effectively reducing circuit complexity and reducing the difficulty of circuit manufacturing and integration. In addition, because the control voltage used to control the on-off of the transistor is always lower than the voltage on the low-voltage side, the low-voltage side is prevented from being powered on first and leaking to the high-voltage side. At the same time, the power-on timing of the low-voltage and high-voltage sides is limited, effectively improving the reliability of the application chip.

[0035] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A signal level conversion circuit, characterized in that: include: an input terminal electrically coupled to a first supply voltage; an output terminal electrically coupled to a second power supply voltage, the second power supply voltage being greater than the first power supply voltage; a voltage regulating module electrically coupled to the second power supply voltage and configured to perform voltage regulation based on the second power supply voltage to output a control voltage from a control node, the control voltage being less than the first power supply voltage; a transistor including a first conduction terminal electrically coupled to the input terminal, a second conduction terminal electrically coupled to the output terminal, and a control terminal electrically coupled to the control node of the voltage regulation module, and configured to be powered on at the first conduction terminal before the second conduction terminal, to be turned on when the first conduction terminal is at a first level so that the second conduction terminal is at the first level, and to be turned off when the first conduction terminal is at a second level corresponding to the first power supply voltage so that the second conduction terminal is at a third level corresponding to the second power supply voltage, the third level being greater than the second level, and the second level being greater than the first level.

2. The circuit according to claim 1, wherein: The transistor is configured to operate in a saturation region when the first conduction terminal is at a low level, and to operate in a cutoff region when the first conduction terminal is at a high level corresponding to the first power supply voltage.

3. The circuit according to claim 1, wherein: The input end is further electrically coupled to a transmitting end of the first chip and is configured to cause the first conduction terminal to be at a low level when the transmitting end sends a low level signal, and to cause the first conduction terminal to be at a high level corresponding to the first power supply voltage when the transmitting end sends a first high level signal.

4. The circuit according to claim 3, characterized in that The output end is further electrically coupled to a receiving end of the second chip, and is configured to enable the receiving end to receive the low-level signal when the transmitting end sends the low-level signal, and to enable the receiving end to receive a second high-level signal when the transmitting end sends the first high-level signal, wherein the voltage of the second high-level signal is greater than the voltage of the first high-level signal.

5. The circuit according to claim 1, wherein: The transistors are configured as: When the first conduction terminal is at the first electrical level, the first conduction terminal is turned on according to the control voltage at the control terminal, so that the second conduction terminal is pulled down to the first electrical level; as well as When the first conduction terminal is at the second level corresponding to the first power supply voltage, the first conduction terminal is turned off according to the control voltage at the control terminal, so that the second conduction terminal is pulled high to the third level corresponding to the second power supply voltage.

6. The circuit according to claim 1, wherein: The transistor comprises a bipolar junction transistor and includes a base electrically coupled to the control node, an emitter electrically coupled to the input terminal, and a collector electrically coupled to the output terminal.

7. The circuit according to claim 1, characterized in that The voltage regulation module is configured to: The second power supply voltage is divided to output the control voltage from the control node.

8. The circuit according to claim 7, characterized in that The voltage regulation module includes: a first resistor electrically coupled between the second supply voltage and the control node; and A second resistor is electrically coupled between the control node and ground.

9. The circuit according to claim 8, characterized in that The resistance values of the first resistor and the second resistor satisfy the following formula: The amplitude of the first power supply voltage>the amplitude of the second power supply voltage×the resistance value of the second resistor / the sum of the resistance values of the first resistor and the second resistor.

10. The circuit according to claim 1, wherein: the input terminal comprising a third resistor, the first conduction terminal being electrically coupled to the first supply voltage via the third resistor; The output terminal includes a fourth resistor, and the second conduction terminal is electrically coupled to the second supply voltage via the fourth resistor.

11. An electronic device, characterized in that: include: Application processor, including the transmitter; peripheral devices, including a receiving end; and The signal level conversion circuit according to any one of claims 1 to 10, wherein the input terminal is electrically coupled to the transmitting terminal, and the output terminal is electrically coupled to the receiving terminal.

Images