Charge pump and phase-locked loop circuit
By introducing an adaptive adjustment circuit into the phase-locked loop circuit, the charge and discharge current of the charge pump is adjusted, the current mismatch problem is solved, the low spurious output is achieved, and the working efficiency and stability of the phase-locked loop are improved.
Patent Information
- Application Number
- CN202410167328.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-05
- Publication Date
- 2025-08-12
AI Technical Summary
The charge pumps in the existing phase-locked loop circuits have a problem of charge and discharge current mismatch, resulting in large spurious output signals, affecting working stability and efficiency.
An adaptive adjustment circuit is introduced to adjust the current of the charge and discharge branch through the output voltage signal of the charge pump, ensuring current matching, eliminating current mismatch, and achieving low spurious output.
It effectively eliminates the current mismatch problem in the charge pump, improves the working stability and efficiency of the phase-locked loop, and reduces signal spurs.
Smart Images
Figure CN120474545A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a charge pump and a phase-locked loop circuit including the charge pump. Background Art
[0002] Phase-locked loop (PLL) circuits are found in a variety of high-frequency applications, ranging from simple clock cleanup circuits to local oscillators used in high-performance radio communication links and ultrafast switching frequency synthesizers in vector network analyzers. Figure 1 It is a typical charge pump phase-locked loop structure. Its working principle is as follows: the oscillation signal generated by the voltage-controlled oscillator (VCO) passes through the frequency divider ( / N), and the frequency is divided by N times. The phase and frequency are compared with the reference clock through the phase frequency detector (PFD). A pull-up signal up or a pull-down signal down is generated according to the possible phase error. The corresponding current is generated by the charge pump (CP), and converted into a voltage change through the loop filter (LPF). It is used to drive the control voltage of the voltage-controlled oscillator to increase or decrease, thereby realizing negative feedback regulation to achieve a stable output frequency-doubled clock signal. Summary of the Invention
[0003] In view of this, the present invention provides a charge pump and a phase-locked loop circuit including the charge pump.
[0004] The present invention provides a charge pump for a phase-locked loop circuit, which can output a voltage signal based on a discharge current and a charging current. The charge pump includes: a current source, connected to a first power supply voltage, for providing a reference current for a first charge and discharge branch and a second charge and discharge branch; the first charge and discharge branch, one end of which is grounded and controlled by a pull-down pulse signal to output a discharge current; the second charge and discharge branch, which is connected between the first charge and discharge branch and the second power supply voltage, and controlled by a pull-up pulse signal to output a charging current; a loop filter, connected to the first charge and discharge branch and the second charge and discharge branch, whose voltage output end constitutes the output end of the charge pump and is used to output an output voltage signal of the charge pump according to the charging current or the discharging current; an adaptive adjustment circuit, connected between the output end of the charge pump and the second charge and discharge branch, and used to output a second power supply voltage to the second charge and discharge branch according to the output voltage signal of the charge pump, so as to adjust the size of the output voltage signal of the charge pump and output it.
[0005] Optionally, the first charge and discharge branch includes a discharge circuit and a first branch switch, the discharge circuit is connected to a current source, the first branch switch is connected between the ground and the discharge circuit, and is controlled by a pull-down pulse signal to discharge the discharge circuit; the second charge and discharge branch includes a charging circuit and a second branch switch, the charging circuit is connected to the current source, the second branch switch is connected between the second power supply voltage and the charging circuit, and is controlled by a pull-up pulse signal to charge the charging circuit.
[0006] Optionally, the discharge circuit includes a first NMOS tube, a second NMOS tube, and a third NMOS tube with a common gate, the drain of the first NMOS tube is connected to the current source and the gate of the first NMOS tube, and the drains of the second NMOS tube and the third NMOS tube are connected to the charging circuit; the first branch switch includes a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube with grounded sources, the drain of the fourth NMOS tube is connected to the source of the first NMOS tube, the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the fifth NMOS tube is connected to the source of the second NMOS tube, the gate of the sixth NMOS tube receives a pull-down pulse signal, and the drain of the sixth NMOS tube is connected to the source of the third NMOS tube.
[0007] Optionally, the charging circuit includes a first PMOS tube and a second PMOS with a common gate, the drain of the first PMOS tube is connected to the drain of the second NMOS tube and the gate of the first PMOS tube, and the drain of the second PMOS tube is connected to the drain of the third NMOS tube; the second branch switch includes a third PMOS tube and a fourth PMOS tube, the sources of the third PMOS tube and the fourth PMOS tube are connected to the second power supply voltage, the drain of the third PMOS tube is connected to the source of the first PMOS tube, the gate of the third PMOS tube is grounded, the gate of the fourth PMOS tube receives a pull-up pulse signal, and the drain of the fourth PMOS tube is connected to the source of the second PMOS tube.
[0008] Optionally, the charge pump also includes: a first selection circuit, the first selection circuit includes a first switching tube and a second switching tube; the first switching tube is connected to the output end of the charge pump, and is used to be turned on or off according to the control signal to output the output voltage signal of the charge pump to the voltage-controlled oscillator; the second switching tube is connected between the output end of the charge pump and the adaptive regulation circuit, and is used to be turned on or off according to the control signal to input the output voltage signal of the charge pump to the adaptive regulation circuit.
[0009] Optionally, the adaptive regulation circuit includes: a boost circuit, which is used to output a reference voltage; a power switch, which is connected to the boost circuit and whose output voltage changes with the voltage of the controlled end; a comparison circuit, which is connected to the boost circuit and the power switch and receives the output voltage signal of the charge pump, and is used to feedback-regulate the voltage of the output end of the power switch according to the voltage of the output end of the power switch and the output voltage signal of the charge pump; a second selection circuit, one end of which is connected to the first power supply voltage and the other end of which is connected to the output end of the power switch, and is used to selectively output the first power supply voltage or the voltage of the output end of the power switch as the second power supply voltage according to the control signal.
[0010] Optionally, the comparison circuit includes: a voltage sampling circuit, including a first sampling resistor and a second sampling resistor, the first end of the first sampling resistor is connected to the output end of the power switch, the second end of the first sampling resistor and the first end of the second sampling resistor are commonly connected to form a signal output end of the voltage sampling circuit, and the second end of the second sampling resistor is grounded; a comparator, whose non-phase input end receives the output voltage signal of the charge pump, whose inverting input end is connected to the output end of the voltage sampling circuit, and whose output end outputs a comparison voltage to the controlled end of the power switch.
[0011] Optionally, the second selection circuit includes a third switching tube and a fourth switching tube, one end of the third switching tube is connected to the first power supply voltage, and the other end serves as an output end, so as to output the first power supply voltage as the second power supply voltage in the on state, and one end of the fourth switching tube is connected to the output end of the power switch, and the other end serves as an output end, so as to output the output voltage of the output end of the power switch as the second power supply voltage in the on state.
[0012] Optionally, the charge pump includes three control stages; in the first control stage, the first switch tube and the third switch tube are turned on, the second switch tube and the fourth switch tube are turned off, and the loop of the charge pump is pre-locked; in the second control stage, the second switch tube and the third switch tube are turned on, and the first switch tube and the fourth switch tube are turned off, so as to introduce the output voltage signal of the charge pump into the comparison circuit, and the comparison circuit feedback adjusts the voltage of the output end of the power switch according to the voltage of the output end of the power switch and the output voltage signal of the charge pump; in the third control stage, the first switch tube and the fourth switch tube are turned on, and the second switch tube and the third switch tube are turned off, so that the adaptive adjustment circuit uses the voltage of the output end of the power switch as the second power supply voltage, and outputs it to the second charge and discharge branch to adjust the output voltage signal of the charge pump and output it.
[0013] The present invention also provides a phase-locked loop circuit, comprising: a phase frequency detector, which outputs a pull-up pulse signal and a pull-down pulse signal based on the phase difference and frequency difference between a reference clock signal and a feedback clock signal; a charge pump, which is connected to the phase frequency detector, outputs a corresponding charging current or discharging current based on the pull-up pulse signal or the pull-down pulse signal, and outputs an output voltage signal of the charge pump based on the charging current or the discharge current; a voltage-controlled oscillator, which is connected to the charge pump, and outputs a clock signal based on the output voltage signal of the charge pump; and a frequency divider, one end of which is connected to the voltage-controlled oscillator and the other end of which is connected to the phase frequency detector, so as to divide the clock signal output by the voltage-controlled oscillator and output a feedback clock signal to the phase frequency detector.
[0014] Compared with the prior art, the present invention has at least the following outstanding advantages:
[0015] In the present application, the output voltage signal of the charge pump is introduced into the adaptive regulation circuit, and the adaptive regulation circuit outputs a second power supply voltage in a certain proportion to the output voltage signal value of the charge pump to the second charge and discharge branch to regulate the charging current and the discharging current, thereby eliminating the current mismatch problem of the charge and discharge circuit in the charge pump, thereby achieving the requirement of low output spuriousness of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a typical charge pump phase-locked loop structure in the prior art;
[0017] Figure 2 This is a common structural diagram of a charge pump;
[0018] Figure 3 yes Figure 2 The waveform of the key node of loop locking when the charge pump current is mismatched is shown;
[0019] Figure 4 This is a schematic diagram of the circuit structure of a charge pump provided by this application;
[0020] Figure 5 This is a schematic diagram of the circuit structure of another charge pump provided by the present application;
[0021] Figure 6 This is a circuit diagram of another charge pump provided by the present application;
[0022] Figure 7 It is a structural diagram of the adaptive regulation circuit provided by this application;
[0023] Figure 8 This is a schematic diagram of the specific structure of the adaptive regulation circuit provided by this application;
[0024] Figure 9 This is a schematic diagram of the control signal of the switch tube in the charge pump provided by this application. DETAILED DESCRIPTION
[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0026] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways than those described herein, and those skilled in the art may make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0027] Figure 2This is a common structural diagram of a charge pump. When the loop is locked, the up and down signals should be pulses of equal width, so as not to change the output voltage Vcont. Figure 2 In the circuit, the CP current is mainly determined by M3 and M5. Specifically, it can be expressed as follows:
[0028]
[0029]
[0030] from Figure 2 It can be seen that the output voltage Vcont is uncertain, especially for different output frequencies, Vcont varies greatly. When Vcont changes, it will affect the Vds of M3 and M5, thereby causing a mismatch in the pull-up and pull-down currents. Figure 3 Shown Figure 2 The waveform of the key node of loop lock when the charge pump current is mismatched is shown in the figure. As shown in the figure, when Vcont is low, the current of M5 is greater than the current of M3. As can be seen from the figure, due to the current mismatch, the pulse widths of the up and down signals are not equal, which ultimately causes the Vcont node to jitter and causes spurious output signals.
[0031] Based on the above technical problems, the present application provides a structural diagram of a charge pump, such as Figure 4 As shown, the charge pump can output a voltage signal based on the discharge current and the charge current, wherein the charge pump includes: a current source 10 connected to the first power supply voltage AVDD, for providing a reference current for the first charge and discharge branch 21 and the second charge and discharge branch 22;
[0032] The first charge and discharge branch 21 has one end grounded and is controlled by the pull-down pulse signal down to output a discharge current I down The second charge and discharge branch 22 is connected between the first charge and discharge branch 21 and the second power supply voltage AVDD2, and is controlled by the pull-up pulse signal up to output the charging current I up ;
[0033] The loop filter 40 is connected to the first charge and discharge branch 21 and the second charge and discharge branch 22, and its voltage output terminal constitutes the output terminal of the charge pump, which is used to generate a voltage output according to the charging current I up Or discharge current I down Output voltage signal Vcont of the charge pump;
[0034] The adaptive regulation circuit 30 is connected between the output terminal of the charge pump and the second charge-discharge branch 22, and is used to output the second power supply voltage AVDD2 to the second charge-discharge branch 22 according to the output voltage signal Vcont of the charge pump, so as to adjust the magnitude of the output voltage signal Vcont of the charge pump and output it.
[0035] In the embodiment of the present application, the output voltage signal Vcont of the charge pump is introduced into the adaptive regulation circuit 30, and the adaptive regulation circuit 30 outputs a second power supply voltage AVDD2 proportional to the Vcont value to the second charge and discharge branch 22 according to the Vcont value to regulate the charging current and the discharging current, thereby eliminating the current mismatch problem of the charge and discharge circuit in the charge pump, thereby achieving the requirement of low spurious output of the charge pump.
[0036] Optionally, in some embodiments, Figure 5 As shown, the first charge and discharge branch 21 includes a discharge circuit 211 and a first branch switch 213. The discharge circuit 211 is connected to the current source 10. The first branch switch 213 is connected between the ground and the discharge circuit 211 and is controlled by the pull-down pulse signal down to discharge the discharge circuit 211.
[0037] Further optional, such as Figure 6 As shown, the discharge circuit 211 includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 with a common gate. The drain of the first NMOS transistor N1 is connected to the current source 10 and the gate of the first NMOS transistor N1, and the drains of the second NMOS transistor N2 and the third NMOS transistor N3 are connected to the charging circuit 222. That is, the discharge circuit 211 adopts a current mirror structure to copy the reference current output by the current source 10 to the discharge circuit 211; the first branch switch 213 includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6 with their sources grounded. The drain of the fourth NMOS transistor N4 is connected to the gate of the first NMOS transistor N1. The gate of the fourth NMOS transistor N4 is connected to the source of the first NMOS transistor N1, the gate of the fifth NMOS transistor N5 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the source of the second NMOS transistor N2, the gate of the sixth NMOS transistor N6 receives the pull-down pulse signal down, and the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3. The fourth NMOS transistor N4 and the fifth NMOS transistor N5 are both normally-on switches to ensure the symmetry of the first charge and discharge branch 21. The sixth NMOS transistor N6 is a control switch that controls whether the discharge circuit 211 is turned on or off through the pull-down pulse signal down.
[0038] Continue to refer Figure 5 The second charge and discharge branch 22 includes a charging circuit 222 and a second branch switch 224. The charging circuit 222 is connected to the current source 10. The second branch switch 224 is connected between the second power supply voltage AVDD2 and the charging circuit 222 and is controlled by the pull-up pulse signal up to charge the charging circuit 222.
[0039] Further optional, such as Figure 6As shown, the charging circuit 222 includes a first PMOS transistor P1 and a second PMOS transistor P2 with a common gate. The drain of the first PMOS transistor P1 is connected to the drain of the second NMOS transistor N2 and the gate of the first PMOS transistor P1, and the drain of the second PMOS transistor P2 is connected to the drain of the third NMOS transistor N3. That is, the charging circuit 222 adopts a current mirror structure to copy the reference current output by the current source 10 to the charging circuit 222; the second branch switch 224 includes a third PMOS transistor and a fourth PMOS transistor. The third PMOS transistor P3 and the fourth PMOS transistor The source of the S transistor P4 is connected to the second power supply voltage AVDD2, the drain of the third PMOS transistor P3 is connected to the source of the first PMOS transistor P1, the gate of the third PMOS transistor P3 is grounded, the gate of the fourth PMOS transistor P4 receives the pull-up pulse signal up, and the drain of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2. The third PMOS transistor P3 is a normally-on switch to ensure the symmetry of the second charge and discharge branch 22. The fourth PMOS transistor P4 is a control switch that controls whether the charging circuit 222 is turned on or off via the pull-up pulse signal up.
[0040] In some embodiments, as Figure 5 and Figure 6 As shown, the charge pump also includes:
[0041] A first selection circuit 50, the first selection circuit 50 includes a first switch tube S1 and a second switch tube S2;
[0042] The first switch tube S1 is connected to the output end of the charge pump and is used to be turned on or off according to the control signal to control the output signal Vcont of the charge pump to the voltage controlled oscillator;
[0043] The second switch S2 is connected between the output terminal of the charge pump and the adaptive regulation circuit 30 , and is configured to be turned on or off according to the control signal to input the output voltage signal Vcont of the charge pump to the adaptive regulation circuit 30 .
[0044] In an embodiment of the present application, a first selection circuit 50 is provided to input the output voltage signal Vcont of the charge pump to the adaptive regulation circuit 30 at a specific stage, so that the adaptive regulation circuit 30 feedback-regulates the output of the charge pump to eliminate the current mismatch problem of the charge pump, thereby achieving the requirement of low output spuriousness of the charge pump.
[0045] In some embodiments, in conjunction with reference Figure 6 and Figure 7 , the adaptive adjustment circuit 30 includes:
[0046] The boost circuit 31 is used to output a reference voltage VH. It can be understood that the reference voltage VH and the first power supply voltage AVDD have a certain proportional relationship, for example, VH is twice AVDD.
[0047] The power switch 32 is connected to the boost circuit 31, and the voltage at its output terminal changes with the voltage at the controlled terminal. Optionally, the power switch 32 may be an NMOS transistor or a PMOS transistor. In the embodiment of the present application, the power switch 32 is an NMOS transistor, that is, the voltage at its output terminal changes in a positive correlation with the voltage at the controlled terminal.
[0048] The comparison circuit 33 is connected to the boost circuit 31 and the power switch 32 and receives the output voltage signal Vcont of the charge pump. The comparison circuit 33 is used to feedback-regulate the voltage at the output end of the power switch 32 based on the voltage at the output end of the power switch 32 and the output voltage signal Vcont of the charge pump.
[0049] The second selection circuit 34 has one end connected to the first power supply voltage AVDD and the other end connected to the output end of the power switch 32, and is used to selectively output the first power supply voltage AVDD or the voltage at the output end of the power switch 32 as the second power supply voltage AVDD2 according to the control signal.
[0050] Specifically, such as Figure 8 As shown, the comparison circuit 33 includes:
[0051] The voltage sampling circuit 331 includes a first sampling resistor R1 and a second sampling resistor R2. The first end of the first sampling resistor R1 is connected to the output end of the power switch 32. The second end of the first sampling resistor R1 and the first end of the second sampling resistor R2 are connected together to form a signal output end of the voltage sampling circuit 331. The second end of the second sampling resistor R2 is grounded.
[0052] The comparator 332 has a non-inverting input terminal receiving the output voltage signal Vcont of the charge pump, an inverting input terminal connected to the output terminal of the voltage sampling circuit 331 , and an output terminal outputting a comparison voltage to the power switch 32 .
[0053] In the embodiment of the present application, the comparator 332 compares the charge pump output voltage signal Vcont with the voltage at the output end of the power switch 32, and feeds back the comparison voltage to the controlled end of the power switch 32 to further adjust the voltage at the output end of the power switch 32. The adjusted voltage at the output end of the power switch 32 is output as the second power supply voltage AVDD2 at a specific stage. In the circuit design, the voltage value of the second power supply voltage AVDD2 should be twice the charge pump output voltage signal Vcont, thereby ensuring that the Vds of the second PMOS transistor P2 and the third NMOS transistor N3 are the same. On this basis, by designing the MOS transistor size of the current mirror in the charge pump, the λ coefficient is ensured to be the same, thereby eliminating the current mismatch problem of the charge pump and achieving the requirement of low spurious output of the charge pump.
[0054] In some embodiments, as Figure 8 As shown, the second selection circuit 34 includes a third switch S3 and a fourth switch S4. One end of the third switch S3 is connected to the first power supply voltage AVDD, and the other end serves as an output end. When in the on state, the first power supply voltage AVDD is output as the second power supply voltage AVDD2. One end of the fourth switch S4 is connected to the output end of the power switch 32, and the other end serves as an output end. When in the on state, the output voltage of the output end of the power switch 32 is output as the second power supply voltage AVDD2. In other embodiments, the second selection circuit 34 can also be a two-to-one data selector, whose first input end is connected to the first power supply voltage AVDD, whose second input end is connected to the output end of the power switch 32, and whose control end receives a data selection signal to output the first power supply voltage AVDD or the output voltage of the power switch 32 as the second power supply voltage AVDD2. In this application, the second selection circuit 34 can be designed according to actual conditions and is not limited here.
[0055] See also Figure 6 、 Figure 8 and Figure 9 , Figure 9 This is a schematic diagram of the control signal of the switch tube in the charge pump; the charge pump includes three control stages;
[0056] In the first control phase T1, the first switch S1 and the third switch S3 are turned on, the second switch S2 and the fourth switch S4 are turned off, and the loop of the charge pump is pre-locked. At this time, the output frequency is stable.
[0057] In the second control phase T2, the second switch S2 and the third switch S3 are turned on, and the first switch S1 and the fourth switch S4 are turned off, so that the output voltage signal Vcont of the charge pump is introduced into the comparison circuit 33. The comparison circuit 33 then adjusts the voltage at the output end of the power switch 32 by feedback based on the voltage at the output end of the power switch 32 and the output voltage signal Vcont of the charge pump.
[0058] In the third control stage T3, the first switch tube S1 and the fourth switch tube S4 are turned on, and the second switch tube S2 and the third switch tube S3 are turned off, so that the adaptive regulation circuit 30 uses the voltage at the output end of the power switch 32 as the second power supply voltage AVDD2. At this time, the second power supply voltage AVDD2 is twice the value of the output voltage signal Vcont of the charge pump. The second power supply voltage AVDD2 is output to the second charge and discharge branch 22 to regulate the charging current and discharging current of the charge pump, and further regulates and outputs the output voltage signal Vcont of the charge pump.
[0059] In the embodiment of the present application, the voltage value of the second power supply voltage AVDD2 should be twice the value of the output voltage signal Vcont of the charge pump, so as to ensure that the Vds of the second PMOS transistor P2 and the third NMOS transistor N3 are the same. On this basis, by designing the size of the MOS transistor of the current mirror in the charge pump, the λ coefficient is ensured to be the same. At this time, the adaptive regulation circuit 30 serves as the power supply for the charging and discharging branch, regulates and outputs the output voltage signal Vcont of the charge pump, thereby eliminating the current mismatch problem of the charge pump, thereby achieving the requirement of low spurious output of the charge pump.
[0060] The present application also provides a phase-locked loop, comprising:
[0061] The phase frequency detector outputs a pull-up pulse signal and a pull-down pulse signal based on the phase difference and frequency difference between the reference clock signal and the feedback clock signal; the charge pump is connected to the phase frequency detector, and an adaptive adjustment circuit is provided in the charge pump. Based on the pull-up pulse signal or the pull-down pulse signal, the charge pump outputs a corresponding charging current or discharging current, and outputs an output voltage signal of the charge pump based on the charging current or the discharging current; the voltage-controlled oscillator is connected to the charge pump, and outputs a clock signal based on the output voltage signal of the charge pump; the frequency divider is connected to the voltage-controlled oscillator at one end and to the phase frequency detector at the other end, so as to divide the clock signal output by the voltage-controlled oscillator and output the feedback clock signal to the phase frequency detector.
[0062] The phase-locked loop of the present application sets an adaptive regulation circuit in a charge pump and introduces the output voltage signal of the charge pump into the adaptive regulation circuit to regulate the charging current and discharging current of the charge pump through the adaptive regulation circuit, thereby eliminating the current mismatch problem of the charging and discharging circuits in the charge pump, thereby achieving the low-spurious output requirement of the charge pump and improving the working efficiency of the phase-locked loop.
[0063] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A charge pump for a phase-locked loop circuit, capable of outputting a voltage signal based on a discharge current and a charge current, characterized in that: The charge pump comprises: a current source connected to the first power supply voltage and configured to provide a reference current for the first charge-discharge branch and the second charge-discharge branch; The first charge and discharge branch has one end grounded and is controlled by a pull-down pulse signal to output the discharge current; The second charge and discharge branch is connected between the first charge and discharge branch and the second power supply voltage, and is controlled by the pull-up pulse signal to output the charging current; a loop filter, connected to the first charge-discharge branch and the second charge-discharge branch, wherein a voltage output end of the loop filter constitutes an output end of the charge pump and is configured to output an output voltage signal of the charge pump according to the charging current or the discharging current; An adaptive regulation circuit is connected between the output end of the charge pump and the second charge and discharge branch, and is used to output the second power supply voltage to the second charge and discharge branch according to the output voltage signal of the charge pump, so as to adjust the size of the output voltage signal of the charge pump and output it.
2. The charge pump according to claim 1, wherein: The first charge-discharge branch includes a discharge circuit and a first branch switch, the discharge circuit is connected to the current source, the first branch switch is connected between the ground and the discharge circuit, and is controlled by the pull-down pulse signal to discharge the discharge circuit; The second charge and discharge branch includes a charging circuit and a second branch switch. The charging circuit is connected to the current source. The second branch switch is connected between the second power supply voltage and the charging circuit and is controlled by the pull-up pulse signal to charge the charging circuit.
3. The charge pump according to claim 2, wherein: The discharge circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor with a common gate, the drain of the first NMOS transistor is connected to the current source and the gate of the first NMOS transistor, and the drains of the second NMOS transistor and the third NMOS transistor are connected to the charging circuit; The first branch switch includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor with their sources grounded. The drain of the fourth NMOS transistor is connected to the source of the first NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the source of the second NMOS transistor, the gate of the sixth NMOS transistor receives the pull-down pulse signal, and the drain of the sixth NMOS transistor is connected to the source of the third NMOS transistor.
4. The charge pump according to claim 3, wherein: The charging circuit includes a first PMOS transistor and a second PMOS transistor with a common gate, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor; The second branch switch includes a third PMOS transistor and a fourth PMOS transistor, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the second power supply voltage, the drain of the third PMOS transistor is connected to the source of the first PMOS transistor, the gate of the third PMOS transistor is grounded, the gate of the fourth PMOS transistor receives a pull-up pulse signal, and the drain of the fourth PMOS transistor is connected to the source of the second PMOS transistor.
5. The charge pump according to claim 1, wherein: The charge pump further comprises: A first selection circuit, the first selection circuit comprising a first switching tube and a second switching tube; The first switch tube is connected to the output end of the charge pump, and is used to be turned on or off according to a control signal to output the output voltage signal of the charge pump to the voltage-controlled oscillator; The second switch tube is connected between the output end of the charge pump and the adaptive regulation circuit, and is used to be turned on or off according to a control signal to input the output voltage signal of the charge pump to the adaptive regulation circuit.
6. The charge pump according to any one of claims 1 to 5, wherein: The adaptive regulation circuit comprises: A boost circuit, the boost circuit being used to output a reference voltage; a power switch connected to the boost circuit, wherein the voltage at the output end thereof varies with the voltage at the controlled end; a comparator circuit connected to the boost circuit and the power switch and receiving an output voltage signal of the charge pump, and configured to feedback-regulate the voltage at the output end of the power switch according to the voltage at the output end of the power switch and the output voltage signal of the charge pump; A second selection circuit has one end connected to the first power supply voltage and the other end connected to the output end of the power switch, and is used to selectively output the first power supply voltage or the voltage of the output end of the power switch as the second power supply voltage according to a control signal.
7. The charge pump according to claim 6, wherein: The comparison circuit comprises: a voltage sampling circuit, comprising a first sampling resistor and a second sampling resistor, wherein a first end of the first sampling resistor is connected to the output end of the power switch, a second end of the first sampling resistor and a first end of the second sampling resistor are connected together to form a signal output end of the voltage sampling circuit, and a second end of the second sampling resistor is grounded; A comparator has a non-inverting input terminal receiving the output voltage signal of the charge pump, an inverting input terminal connected to the output terminal of the voltage sampling circuit, and an output terminal outputting a comparison voltage to the controlled terminal of the power switch.
8. The charge pump according to claim 6, wherein: The second selection circuit includes a third switching tube and a fourth switching tube. One end of the third switching tube is connected to the first power supply voltage, and the other end serves as an output end, so as to output the first power supply voltage as the second power supply voltage when in the on state. One end of the fourth switching tube is connected to the output end of the power switch, and the other end serves as an output end, so as to output the output voltage of the output end of the power switch as the second power supply voltage when in the on state.
9. The charge pump according to claim 8, wherein: The charge pump includes three control stages; In a first control phase, the first switch tube and the third switch tube are turned on, the second switch tube and the fourth switch tube are turned off, and the loop of the charge pump is pre-locked; In a second control phase, the second switch tube and the third switch tube are turned on, and the first switch tube and the fourth switch tube are turned off, so that the output voltage signal of the charge pump is introduced into the comparison circuit, and the comparison circuit feedback-adjusts the voltage at the output end of the power switch according to the voltage at the output end of the power switch and the output voltage signal of the charge pump; In the third control stage, the first switch tube and the fourth switch tube are turned on, and the second switch tube and the third switch tube are turned off, so that the adaptive regulation circuit uses the voltage at the output end of the power switch as the second power supply voltage and outputs it to the second charge and discharge branch to regulate and output the output voltage signal of the charge pump.
10. A phase-locked loop circuit, characterized in that: include: A phase frequency detector outputs a pull-up pulse signal and a pull-down pulse signal based on a phase difference and a frequency difference between a reference clock signal and a feedback clock signal; The charge pump according to any one of claims 1 to 9, connected to the phase and frequency detector, outputting a corresponding charging current or discharging current based on the pull-up pulse signal or the pull-down pulse signal, and outputting an output voltage signal of the charge pump based on the charging current or the discharge current; a voltage-controlled oscillator connected to the charge pump and outputting a clock signal based on an output voltage signal of the charge pump; A frequency divider is connected to the voltage controlled oscillator at one end and to the phase frequency detector at the other end, so as to divide the frequency of the clock signal output by the voltage controlled oscillator and then output the feedback clock signal to the phase frequency detector.