Integrated charge injection suppression type gate voltage bootstrap circuit
Through the integrated charge injection suppression type gate voltage bootloader circuit, the PMOS and NMOS gate voltage bootloader circuits are integrated, and channel charges are cancelled out, solving the sampling nonlinearity and charge injection problems in analog-to-digital converters, achieving high-precision sampling and retention.
Patent Information
- Application Number
- CN202510551150.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-12
AI Technical Summary
In existing analog-to-digital converters, the single MOS tube on-resistance changes with the input signal, the sampling is nonlinear. The NMOS gate voltage bootloader circuit has a problem of channel charge injection, and the separate PMOS and NMOS gate voltage bootloader circuits occupy a large chip area and have high power consumption.
The PMOS and NMOS gate voltage bootloader circuits are integrated into an integrated circuit. The channel charges of the NMOS and PMOS switch tubes are cancelled out from each other, and the same signal is used to control the pump piezoelectric capacitors to achieve the integration of NMOS and PMOS switch tubes, reducing chip area and power consumption.
While reducing chip area and power consumption, the sampling linearity is improved, the channel charge injection problem is solved, and the performance of the analog-to-digital converter is improved.
Smart Images
Figure CN120474550A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of analog integrated circuits, and in particular relates to an integrated charge injection suppression type gate voltage bootstrap circuit. Background Art
[0002] In an analog-to-digital converter (ADC), the sampling accuracy of the sample-and-hold circuit directly determines the overall performance of the converter. The simplest sampling switch structure is a single MOS transistor. Its on-resistance varies with the input signal, affecting sampling linearity and making it unsuitable for high-precision ADCs.
[0003] To address the sampling nonlinearity issue caused by the on-resistance of a single MOS transistor varying with the input signal, a paper has proposed an NMOS gate voltage bootstrap circuit. This circuit maintains the gate-source voltage of the NMOS transistor at a constant voltage through a pumping capacitor, improving the problem of the switch transistor's on-resistance varying with input signal amplitude and enhancing sampling linearity. However, this NMOS gate voltage bootstrap circuit suffers from the problem of channel charge being injected into the sampling capacitor after the field-effect transistor is turned off, causing errors in the sampled voltage.
[0004] To address the charge injection issue in NMOS gate voltage bootstrap switches, a paper has proposed a separate, high-performance gate voltage bootstrap switch structure. This structure, which utilizes a PMOS gate voltage bootstrap circuit and an NMOS gate voltage bootstrap circuit to form a complementary structure, can alleviate the channel charge injection problem. However, this separate PMOS and NMOS gate voltage bootstrap circuits occupy a large chip area and also increase the power consumption of the sampling circuit module.
[0005] To address the issues with the separate complementary structure, a technology has been developed that adds a CMOS transmission gate to a separate high-performance gate-voltage bootstrap switch, simply splicing the original separate PMOS and NMOS gate-voltage bootstrap circuits. However, this technology does not substantially improve the original separate high-performance gate-voltage bootstrap switch and does not address the large chip area and high power consumption issues of the separate structure. Summary of the Invention
[0006] To address the aforementioned problems or deficiencies, the present invention provides an integrated charge injection suppression gate voltage bootstrap circuit. This circuit uses the same signal to control the gate of the PMOS transistor that charges the pumping capacitor. This further integrates the pumping circuit in the PMOS gate voltage bootstrap circuit with the pumping circuit in the NMOS gate voltage bootstrap circuit, integrating the PMOS and NMOS transistors as switching transistors into a single circuit. The core of the present invention is to address the charge injection problem on the sampling capacitor by offsetting the negative channel charge injected by the NMOS switching transistor with the positive channel charge injected by the PMOS switching transistor. However, the integration of this single circuit allows the present invention to significantly reduce chip area and power consumption while effectively suppressing charge injection.
[0007] An integrated charge injection suppression gate voltage bootstrap circuit, as shown in the attached Figure 3 As shown, it consists of three parts: the pump circuit of the switch gate, the NMOS switch gate voltage control circuit, and the PMOS switch gate voltage control circuit. The clock control signal '1' represents a high level, and its voltage value is the power supply voltage V DD ; '0' means the clock signal is low level, the voltage value is the power ground V SS .
[0008] The pumping circuit of the switch gate includes PMOS transistors M1, M2, M7, NMOS transistors M3, M4, M5, M6, and capacitor C down and C boost .
[0009] Specifically: the source and substrate of M1 are connected to the power supply voltage, the gate of M1 is connected to the gate of M2, the gate of M3, the gate of MN, the gate of M8, the drain of M10, and the drain of M9, and the drain of M1 is connected to the drain of M3, C down The source of M2 is connected to the power supply voltage, the drain of M2 is connected to the substrate of M2, C boost The upper plate, source of M9 and substrate are connected; the substrate of M3 is connected to the power ground V SS , the source of M3 and C boost The lower plate of M5, the drain of M8 are connected; the drain of M4 is connected to the substrate of M4, the source of M6, the source and substrate of M12, the gate of M4 is connected to the drain and substrate of M6, the drain of M7, and the source of M4 is connected to the power ground V SS The gate of M5 is connected to the clock signal CLKN, and the source and substrate of M5 are connected to the power ground V SS ; The gate of M6 and the gate of M7 are connected to the clock signal CLK, and the source and substrate of M7 are connected to the power supply voltage.
[0010] The NMOS switch gate voltage control circuit includes a PMOS transistor M9 and NMOS transistors M8, M10, M11, and MN.
[0011] Specifically: The substrate of M8 is connected to the power ground V SS , the source of M8 is connected to the input signal V IN The gate of M9 is connected to the clock signal CLKN; the gate of M10 is connected to the power supply voltage, and the substrate of M10 is connected to the power ground V SS , the source of M10 is connected to the drain of M11; the gate of M11 is connected to CLKN, and the substrate and source of M11 are connected to the power ground V SS MN's source is connected to the input signal V IN MN's substrate is connected to M8's drain, and MN's drain serves as the entire circuit's signal output terminal V OUT ;
[0012] The PMOS switch gate voltage control circuit includes PMOS transistors M13, M14, MP, and an NMOS transistor M12.
[0013] Specifically: the gate of M12 is connected to the clock signal CLK, the drain of M12 is connected to the gate of MP and the drain of M13; the gate of M13 is connected to the power ground V SS , the substrate of M13 is connected to the power supply voltage, the source of M13 is connected to the drain of M14; the gate of M14 is connected to the clock signal CLK, the source and substrate of M14 are connected to the power supply voltage; the source of MP is connected to the input signal V IN , the substrate of MP is connected to the drain of M3, and the drain of MP serves as the signal output terminal V of the entire circuit OUT .
[0014] Furthermore, MN is an NMOS switch tube, MP is a PMOS switch tube; M2, M5, C boost The pump circuit that forms the gate of the NMOS switch tube MN, M1, M4, C down The pumping circuit of the gate of the PMOS switch MP is formed; the function of the isolation transistors M9 and M12 is to conduct when the circuit is in the follower stage and transmit the pumping voltage to the gate terminals of MN and MP respectively, so that the absolute value of the gate-source voltage of the switch tube is kept at a constant voltage V DD When the circuit is in the hold phase, it is turned off to isolate the capacitor plate voltage from the switch tube gate voltage, providing conditions for the switch tube to be turned off; M8 and M3 transmit the input signal to the corresponding capacitor plate when the circuit is in the follow phase to achieve the pumping function; MN's reset tubes M10 and M11 connect MN's gate voltage to the power ground V when the circuit is in the hold phase. SS, thereby achieving the purpose of turning off the switch tube MN. Similarly, the reset tubes M13 and M14 of MP also pull the gate of MP to V during the holding phase. DD , turn off the switch tube MP.
[0015] Furthermore, the NMOS transistors M4, M6, M12, and MN use DNW transistors because current CMOS processes use P-type substrates. Ordinary NMOS transistors are fabricated directly on the P-type substrate, so their substrates are connected to the entire P-type substrate. To prevent leakage during operation, the P-type substrate needs to be connected to the power ground. In the present invention, however, the substrates of the NMOS transistors M4, M6, M12, and MN are connected to the drain or source. Their substrate voltage changes with changes in the drain or source voltage, which in turn changes the potential of the connected P-type substrate, affecting the performance of other MOS transistors. In contrast, the DNW transistors implant an N-well on the P-type substrate, and then implant a P-well within the N-well. The NMOS transistors are fabricated within this P-well, isolating the NMOS transistor substrate from the entire P-type substrate and preventing changes in the NMOS transistor substrate potential from affecting the potential of the entire P-type substrate.
[0016] The specific working process of the above-mentioned integrated charge injection suppression gate voltage bootstrap circuit is as follows:
[0017] 1) When CLK=0, CLKN=1, see attached Figure 4 , the working state of the MOS tube in the gate voltage bootstrap circuit:
[0018] Isolation tubes M9 and M12 are turned off, and reset tubes M10 and M11 are turned on to pull the MN gate voltage to ground V SS At this time, M8, MN, and M3 are turned off, M1 and M2 are turned on to charge the upper plates of the two capacitors respectively; reset tubes M13 and M14 are turned on to pull the gate of MP to V DD Thus, the MP tube is turned off, and the clock CLKN controls M5 to turn on the capacitor C boost Pull the lower plate to ground V SS , the clock CLK controls M6 to turn off and M7 to turn on, so that the gate voltage of M4 V G is pulled to the supply voltage V DD At this time, M4 is turned on and the capacitor C down Pull the lower plate to ground V SS ; Switches MN and MP are turned off, and the circuit is in the hold phase; M1, M2, M4, and M5 are turned on, and the two capacitors are in the charging state, and the stored voltage is V DD .
[0019] (2) When CLK=1, CLKN=0, see attached Figure 5 , the working state of the MOS tube in the gate voltage bootstrap circuit:
[0020] The clock CLKN controls M5 to turn off, the clock CLK controls M6 to turn on and M7 to turn off. At this time, the gate voltage of M4 is V G and drain voltage V4 are equal through the connection of M6, and V G =V4=0V, M4 is turned off because the gate voltage becomes low; the isolation tube M12 is turned on to transmit the voltage of V4 to the gate of MP, and because the reset tubes M13 and M14 are turned off, the gate voltage of MP is low and turned on; the isolation tube M9 is turned on to transmit the voltage of V1 to the gate of MN, and the reset tubes M10 and M11 are turned off, so the gate voltage of MN is raised to a high level and turned on. At this time, M1 and M2 are turned off, and M3 and M8 are turned on, making C down The upper plate is made of V DD becomes V IN , C boost The lower plate changes from 0V to V IN ; The two switch tubes MN and MP are turned off, and the circuit is in the following stage; M1, M2, M4, and M5 are all turned off, and the capacitor is in the pumping state;, because C down The upper plate is made of V DD becomes V IN , capacitor C boost The lower plate changes from 0V to V IN , and then according to the law of conservation of charge, it can be deduced that C down The lower plate changes from 0 to V IN -V DD , C boost The upper plate is made of V DD becomes V DD +V IN After this process, the absolute values of the gate-source voltages of the two switching tubes MN and MP are both V DD .
[0021] In the present invention, M6 and M7 play a key role in the integration of the PMOS gate voltage bootstrap circuit and the NMOS gate voltage bootstrap circuit. In order to realize the integration of the PMOS and NMOS gate voltage bootstrap circuits, the MOS tubes for charging and discharging the capacitors in the pump circuits of the two gate voltage bootstrap circuits are connected in parallel, as shown in the attached figure. Figure 3 The gates of the two PMOS transistors M1 and M2 are controlled by the gate voltage of the NMOS switch transistor. The gates of the two NMOS transistors M4 and M5 are connected to the clock signal CLKN. The NMOS transistor M3 is added between the plates of the two capacitors as the input signal V IN Transmitted to capacitor C downThe path of the upper plate; ideally, this parallel connection can achieve the integration of the gate voltage bootstrap circuit while ensuring the normal operation of the pump circuit. However, in the actual verification process, it was found that the gate of M4 cannot be directly controlled by CLKN like M5. The reason is that when CLK = 1, the entire circuit is in the follow-up stage, that is, the capacitor C down In the pump pressure state, V4=V IN -V DD For negative voltage, if the gate of M4 is connected to CLKN=0, then the gate voltage of M4 (P terminal) is higher than the drain voltage (N terminal), and the PN junction formed by the gate and drain will leak, resulting in the voltage of V4 unable to be pumped down, thereby causing the PMOS switch tube to malfunction.
[0022] The solution of the present invention is to use M6 and M7 to form the M4 gate voltage V G When CLK=0, the circuit is in the holding stage, the capacitor is in the charging state, and M7 is turned on so that V G Close to V DD , M4 is turned on due to the gate voltage becoming high level, so that V4=0 can work normally when the capacitor is in the charging state. When CLK=1, that is, CLKN=0, the whole circuit is in the following stage, the capacitor is in the pumping state, and M6 is turned on so that the gate voltage of M4 V G The optimized parallel structure ensures that the pumping circuit of the switch gate can work properly. boost and C down The value of and the relationship between the two capacitors will not have a significant impact, similar to the split-gate bootstrap circuit.
[0023] In summary, the present invention realizes the use of NMOS and PMOS gate voltage bootstrap switches in the same circuit, which ensures that the absolute value of the gate-source voltage of the two switches is kept at V DD , thereby reducing the nonlinearity caused by on-resistance and maintaining the characteristics of traditional gate-voltage bootstrap circuits. Furthermore, the circuit also achieves the goal of suppressing charge injection by using both NMOS and PMOS switches in the same circuit. By adjusting the size of the two switches, an integrated NMOS and PMOS gate-voltage bootstrap switch circuit can be implemented to mitigate the impact of charge injection on sampling linearity while balancing chip area and power consumption, thus resolving the large area and high power consumption issues of separate high-performance gate-voltage bootstrap switches. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a diagram showing changes in NMOS and PMOS switch tubes in an existing complementary gate voltage bootstrap circuit when the circuit is in the follow and hold stages;
[0025] Figure 2 This is a diagram showing the changes of the NMOS switch tube in the traditional gate voltage bootstrap circuit when the circuit is in the follow and hold stages;
[0026] Figure 3 It is a structural schematic diagram of the present invention;
[0027] Figure 4 Schematic diagram of the working state of each tube when the gate voltage bootstrap circuit of the present invention is in the holding stage (CLK=0);
[0028] Figure 5 Schematic diagram of the working state of each tube when the gate voltage bootstrap circuit of the present invention is in the following stage (CLK=1);
[0029] Figure 6 The simulation results of the input signal and output signal of this embodiment;
[0030] Figure 7 The output signal is subjected to FFT simulation results for this embodiment;
[0031] Figure 8 This is a simulated spectrum diagram of the output signal of this embodiment. DETAILED DESCRIPTION
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0033] As attached Figure 1 As shown, in the existing complementary gate voltage bootstrap switch circuit, NMOS and PMOS are used as switch tubes, and the charge injected into the sampling capacitor can be expressed as:
[0034] Q=C GDn,on V DD +C GDn,off V OUT -C GDp,on V DD -C GDp,off (V DD -V OUT )
[0035] Among them C GDn,on and C GDn,off are the gate-drain parasitic capacitances of the NMOS switch when it is turned on and off, respectively, C GDp,on and C GDp,off They are the gate-drain parasitic capacitances when the PMOS switch is turned on and off respectively.
[0036] By setting the size of NMOS and PMOS switch tubes, C GDn,on =C GDp,on, so the charge injected into the sampling capacitor can be reduced to:
[0037] Q np =C GDn,off V OUT -C GDp,off (V DD -V OUT )
[0038] For the structure with only NMOS as the switch tube, as shown in the attached Figure 2 As shown, the charge injected into the sampling capacitor is:
[0039] Q n =C GDn,on V DD +C GDn,off V OUT
[0040] Therefore, using both NMOS and PMOS as the switch structure can greatly reduce the charge injected from the switch channel to the sampling capacitor, thereby improving the linearity of sampling.
[0041] In this embodiment, the integrated charge injection suppression type gate voltage bootstrap circuit is composed of three parts: a pumping circuit for the gate of the switch tube, a gate voltage control circuit for the NMOS switch tube, and a gate voltage control circuit for the PMOS switch tube. The specific structure is shown in the attached figure. Figure 3 As shown. Where: V1 is the capacitor C boost The voltage of the upper plate, V2 is the capacitance C boost The voltage of the lower plate, V3 is the capacitor C down The voltage of the upper plate, V4 is the drain voltage of M4, V out is the output voltage of the entire circuit.
[0042] The working process of the integrated charge suppression gate voltage bootstrap circuit is as follows:
[0043] 1) When CLK=0, CLKN=1, the working state of the MOS tube in the gate voltage bootstrap circuit is as shown in the attached figure. Figure 4 shown.
[0044] Isolation tubes M9 and M12 are turned off, and reset tubes M10 and M11 are turned on to pull the MN gate voltage to the power ground V SS At this time, M8, MN, and M3 are turned off, and M1 and M2 are turned on to charge the upper plates of the two capacitors respectively. Reset tubes M13 and M14 are turned on to pull the gate of MP to V DD The MP tube is turned off, and the clock CLKN controls M5 to turn on the capacitor C boost Pull the lower plate to ground V SS , the clock CLK controls M6 to turn off and M7 to turn on, so that the gate voltage of M4 V Gis pulled to the supply voltage V DD At this time, M4 is turned on and the capacitor C down Pull the lower plate to the power ground V SS ; Switches MN and MP are turned off, and the circuit is in the hold phase; M1, M2, M4, and M5 are turned on, and the two capacitors are in the charging state, and the stored voltage is V DD .
[0045] Specific working principle: When CLK=0, CLKN=1, the circuit is in the holding stage.
[0046] At this time, the isolation tubes M9 and M12 are turned off, and the reset tubes M10 and M11 are turned on, making the gate voltage of MN 0V, so M8 and the switch tube MN are turned off; and because the gates of M1, M2 and M3 are connected to the gate of the switch tube MN, M3 is turned off and M1 and M2 are turned on, and the two capacitors C down and C boost The upper plate is charged to V DD For the PMOS switch, M13 and M14 are turned on to pull the gate voltage of MP to V DD , the switch MP is turned off. In the gate voltage control circuit of M4, because CLK=0, M7 is turned on and M6 is turned off. At this time, the gate voltage of M4 is pulled to V DD , the gate voltage of M5 is also V DD , so M4 and M5 respectively down and C boost Pull the lower plate to ground V SS After the working state conversion of the above MOS tube is completed, the voltage difference between the upper and lower plates of the two capacitors reaches V DD value.
[0047] (2) When CLK=1, CLKN=0, the working state of the MOS tube in the gate voltage bootstrap circuit is as shown in the attached figure. Figure 5 shown.
[0048] The clock CLKN controls M5 to turn off, the clock CLK controls M6 to turn on and M7 to turn off. At this time, the gate voltage of M4 is V G and drain voltage V4 are equal through the connection of M6, and V G =V4=0V, M4 is turned off because the gate voltage becomes low; isolation transistor M12 is turned on to transmit the voltage of V4 to the gate of MP, and because reset transistors M13 and M14 are turned off, the gate voltage of MP is low and turned on. Isolation transistor M9 is turned on to transmit the voltage of V1 to the gate of MN, reset transistors M10 and M11 are turned off, so the gate voltage of MN is raised to a high level and turned on. At this time, M1 and M2 are turned off, and M3 and M8 are turned on, making C down The upper plate is made of V DD becomes V IN, C boost The lower plate changes from 0V to V IN The circuit is in the following stage, M1, M2, M4, and M5 are all turned off, and the capacitor is in the pumping state. According to the charge conservation theorem and the change in the plate voltage of the capacitor mentioned above, C down The lower plate changes from 0 to V IN -V DD , C boost The upper plate is made of V DD becomes V DD +V IN After this process, the gate-source voltages of the two switching tubes MN and MP are both V DD .
[0049] Specific working principle: When CLK=1, CLKN=0, the circuit is in the following stage.
[0050] In the gate voltage control circuit of M4, M6 is turned on and M7 is turned off, so that the gate of M4 V G It is connected to the drain V4, and the voltage value of V4 remains at 0V, so the gate voltage of M4 becomes low and is turned off, and the gate of M5 is also low and turned off. CLK controls the isolation tube M12 to turn on, and the voltage 0V of V4 is transmitted to the gate of the switch tube MP through the isolation tube M12. Because the reset tubes M13 and M14 are turned off, the gate voltage of MP becomes low and turns on. CLKN controls the reset tube M11 to turn off, and the isolation tube M9 turns on and increases the voltage V1 to V DD Transmitted to the gate end of the switch tube MN, at this time the gate voltage of M1 and M2 becomes high and is turned off, the gate voltage of MN, M3 and M8 becomes high and is turned on, and M8 converts the input signal V IN Transfer to C boost At the same time, because M3 is turned on, C down The upper plate and C boost The lower plates are connected, and V2=V3=V IN According to the principle of conservation of capacitance charge, the voltage of V4 changes from 0V to V IN -V DD , the voltage of V1 is V DD Change to V DD +V IN The voltage V4 is transmitted to the gate of the switch tube MP through the isolation tube M12, and the voltage V1 is transmitted to the gate of the switch tube MN through the isolation tube M9. The sources of the two switch tubes are connected to the output voltage V IN , after calculation, it can be obtained that the absolute value of the gate-source voltage of NMOS and PMOS switch tubes is V DD .
[0051] In this embodiment, the power supply voltage V DDThe voltage is 5V, the frequency of the sampling clock CLK is 25M, the input range of the input signal VIN is 0-5V, and the test load capacitance used is 5pF. This is to test the circuit's suppression of the channel charge injection effect and the effectiveness of the circuit. Figure 6 The simulation results of the input signal and output signal of this embodiment; Figure 7 The output signal is subjected to FFT simulation results for this embodiment; Figure 8 This is a simulated spectrum diagram of the output signal of this embodiment.
[0052] From the above embodiments, it can be seen that the present invention realizes the use of NMOS and PMOS gate voltage bootstrap switches in the same circuit, which ensures that the gate-source voltage of the two switches is kept at V DD , thereby reducing the nonlinearity caused by on-resistance and maintaining the characteristics of traditional gate voltage bootstrap circuits. Furthermore, the circuit also achieves the goal of suppressing charge injection by using both NMOS and PMOS as bootstrap switches. By adjusting the size of the two switching transistors, an integrated NMOS and PMOS gate voltage bootstrap switch circuit can be implemented to mitigate the impact of charge injection on sampling linearity while balancing chip area and power consumption.
Claims
1. An integrated charge injection suppression gate voltage bootstrap circuit, characterized in that: It consists of three parts: the pump voltage circuit of the switch tube gate, the NMOS switch tube gate voltage control circuit and the PMOS switch tube gate voltage control circuit; The pumping circuit of the switch gate includes PMOS transistors M1, M2, M7, NMOS transistors M3, M4, M5, M6, and capacitor C down and C boost ; Specifically: the source and substrate of M1 are connected to the power supply voltage, the gate of M1 is connected to the gate of M2, the gate of M3, the gate of MN, the gate of M8, the drain of M10, and the drain of M9, and the drain of M1 is connected to the drain of M3, C down The source of M2 is connected to the power supply voltage, the drain of M2 is connected to the substrate of M2, C boost The upper plate, source of M9 and substrate are connected; the substrate of M3 is connected to the power ground V SS , the source of M3 and C boost The lower plate of M5, the drain of M8 are connected; the drain of M4 is connected to the substrate of M4, the source of M6, the source and substrate of M12, the gate of M4 is connected to the drain and substrate of M6, the drain of M7, and the source of M4 is connected to the power ground V SS The gate of M5 is connected to the clock signal CLKN, and the source and substrate of M5 are connected to the power ground V SS The gate of M6 and the gate of M7 are connected to the clock signal CLK, and the source and substrate of M7 are connected to the power supply voltage; The NMOS switch gate voltage control circuit includes a PMOS transistor M9 and NMOS transistors M8, M10, M11, and MN; Specifically: The substrate of M8 is connected to the power ground V SS , the source of M8 is connected to the input signal V IN The gate of M9 is connected to the clock signal CLKN; the gate of M10 is connected to the power supply voltage, and the substrate of M10 is connected to the power ground V SS , the source of M10 is connected to the drain of M11; the gate of M11 is connected to CLKN, and the substrate and source of M11 are connected to the power ground V SS MN's source is connected to the input signal V IN MN's substrate is connected to M8's drain, and MN's drain serves as the entire circuit's signal output terminal V OUT ; The PMOS switch gate voltage control circuit includes PMOS transistors M13, M14, MP, and an NMOS transistor M12; Specifically: the gate of M12 is connected to the clock signal CLK, the drain of M12 is connected to the gate of MP and the drain of M13; the gate of M13 is connected to the power ground V SS , the substrate of M13 is connected to the power supply voltage, the source of M13 is connected to the drain of M14; the gate of M14 is connected to the clock signal CLK, the source and substrate of M14 are connected to the power supply voltage; the source of MP is connected to the input signal V IN , the substrate of MP is connected to the drain of M3, and the drain of MP serves as the signal output terminal V of the entire circuit OUT .
2. The integrated charge injection suppression gate voltage bootstrap circuit according to claim 1, characterized in that: Among them, MN is NMOS switch tube, MP is PMOS switch tube; M2, M5, C boost The pump circuit that forms the gate of the NMOS switch tube MN, M1, M4, C down The pumping circuit of the gate of the PMOS switch MP is formed; the function of the isolation transistors M9 and M12 is to conduct when the circuit is in the follower stage and transmit the pumping voltage to the gate terminals of MN and MP respectively, so that the absolute value of the gate-source voltage of the switch tube is kept at a constant voltage V DD ; When the circuit is in the holding stage, it is turned off to isolate the capacitor plate voltage from the switch tube gate voltage, providing conditions for the switch tube to be turned off; M8 and M3 transmit the input signal to the corresponding capacitor plate when the circuit is in the following stage to achieve the pumping function; MN's reset tubes M10 and M11 connect the MN gate voltage to the power ground V when the circuit is in the holding stage SS , thereby achieving the purpose of turning off the switch tube MN; similarly, the reset tubes M13 and M14 of MP also pull the gate of MP to V during the holding phase. DD , turn off the switch tube MP.
3. The integrated charge injection suppression gate voltage bootstrap circuit according to claim 1, wherein: The NMOS transistors M4, M6, M12 and MN use DNW transistors.
4. The integrated charge injection suppression gate voltage bootstrap circuit according to claim 1, wherein: The specific working process is as follows: 1) When CLK=0, CLKN=1, the working state of the MOS tube in the gate voltage bootstrap circuit: Isolation tubes M9 and M12 are turned off, and reset tubes M10 and M11 are turned on to pull the MN gate voltage to ground V SS At this time, M8, MN, and M3 are turned off, M1 and M2 are turned on to charge the upper plates of the two capacitors respectively; reset tubes M13 and M14 are turned on to pull the gate of MP to V DD Thus, the MP tube is turned off, and the clock CLKN controls M5 to turn on the capacitor C boost Pull the lower plate to ground V SS , the clock CLK controls M6 to turn off and M7 to turn on, so that the gate voltage of M4 V G is pulled to the supply voltage V DD At this time, M4 is turned on and the capacitor C down Pull the lower plate to ground V SS ; Switches MN and MP are turned off, and the circuit is in the hold phase; M1, M2, M4, and M5 are turned on, and the two capacitors are in the charging state, and the stored voltage is V DD ; (2) When CLK=1, CLKN=0, the working state of the MOS tube in the gate voltage bootstrap circuit is: The clock CLKN controls M5 to turn off, the clock CLK controls M6 to turn on and M7 to turn off. At this time, the gate voltage of M4 is V G and drain voltage V4 are equal through the connection of M6, and V G =V4=0V, M4 is turned off because the gate voltage becomes low; the isolation tube M12 is turned on to transmit the voltage of V4 to the gate of MP, and because the reset tubes M13 and M14 are turned off, the gate voltage of MP is low and turned on; the isolation tube M9 is turned on to transmit the voltage of V1 to the gate of MN, and the reset tubes M10 and M11 are turned off, so the gate voltage of MN is raised to a high level and turned on. At this time, M1 and M2 are turned off, and M3 and M8 are turned on, making C down The upper plate is made of V DD becomes V IN , C boost The lower plate changes from 0V to V IN ; The two switch tubes MN and MP are turned off, and the circuit is in the following stage; M1, M2, M4, and M5 are all turned off, and the capacitor is in the pumping state;, because C down The upper plate is made of V DD becomes V IN , capacitor C boost The lower plate changes from 0V to V IN , and then according to the law of conservation of charge, it can be deduced that C down The lower plate changes from 0 to V IN -V DD , C boost The upper plate is made of V DD becomes V DD +V IN After this process, the absolute values of the gate-source voltages of the two switching tubes MN and MP are both V DD .