Sectional integration switched capacitor integrator
Through the switching capacitor integrator with segmented integral, the integration stage is divided into two segments, and the segmented integration is performed using timing control signals and two-stage amplifiers, which solves the performance degradation of Sigma-Delta analog-to-digital converter caused by integration leakage in the prior art, and achieves performance improvement.
Patent Information
- Application Number
- CN202510617017.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-14
- Publication Date
- 2025-08-12
AI Technical Summary
The prior art is difficult to reduce the integration leakage of the integrator without increasing power consumption and losing the establishment speed, resulting in a degradation of the Sigma-Delta analog-to-digital converter performance.
A switching capacitor integrator with segmented integration is used to divide the integration stage into two segments, use two-stage amplifiers and two sets of switching components, and use timing control signals to turn on and off to achieve segmented integration of the input signal.
Without increasing power consumption and losing establishment speed, the integration leakage is effectively reduced and the performance of Sigma-Delta analog-to-digital converter is improved.
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Figure CN120474556A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a segmented integrated switched capacitor integrator. Background Art
[0002] The Sigma-Delta analog-to-digital converter (ADC) is a high-precision ADC capable of achieving resolutions exceeding 13 bits. Its performance depends on the design of its various components, with the integrator being a key element. To meet the high-precision requirements of the Sigma-Delta ADC, the switched capacitor integrator must exhibit high precision and low noise. This is typically achieved using high-quality capacitors, operational amplifiers, and optimized circuit design. However, with the increasing popularity of mobile devices and the Internet of Things (IoT), Sigma-Delta ADCs must also meet low power requirements without sacrificing speed.
[0003] Switched-capacitor integrators utilize low-power design techniques to reduce the power consumption of the entire analog-to-digital converter. However, since the stability of switched-capacitor integrators can adversely affect the Sigma-Delta ADC's output, such as drift and increased noise, integrator stability is crucial to the performance of the Sigma-Delta ADC. The limited DC gain of the integrator's op amp reduces the gain and introduces integral leakage. To reduce integral leakage and improve integrator performance, it is necessary to increase the op amp gain without sacrificing settling speed or increasing power consumption, but this is difficult to achieve. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to overcome the defect in the prior art that it is difficult to reduce the integral leakage of the integrator without increasing power consumption and losing the settling speed, resulting in a decrease in the performance of the Sigma-Delta analog-to-digital converter, and to provide a segmented integrated switched capacitor integrator.
[0005] The present invention solves the above technical problems through the following technical solutions:
[0006] In a first aspect, the present invention provides a switched capacitor integrator with segmented integration, characterized in that the switched capacitor integrator comprises: a sampling circuit and an integration circuit, the sampling circuit and the integration circuit are electrically connected, the sampling circuit comprises a sampling capacitor and a first switch component; the integration circuit comprises a first-stage amplifier, a second-stage amplifier, a first integration capacitor C i1 , the second integrating capacitor C i2 and a second switch component; the first integral capacitor C i1 and the second integrating capacitor C i2 are respectively connected to the input end of the first stage amplifier, and the output end of the first stage amplifier is connected to the negative input end of the second stage amplifier;
[0007] The first switch component and the second switch component are configured to be turned on and off according to a timing control signal, wherein the timing control signal comprises at least a two-phase non-overlapping clock signal;
[0008] The sampling circuit is used to collect the original signal into the sampling capacitor and output an input signal to the integration circuit according to the original signal;
[0009] The integration circuit is used to transfer and integrate the input signal to the first integration capacitor C under different working states corresponding to the timing control signal. i1 and the second integrating capacitor C i2 .
[0010] Preferably, the first switch assembly includes a first switch φ s , the second switch φ s , the first switch φ i and the second switch φ i , the first switch φ s and the first switch φ i connected to the negative electrode of the sampling capacitor, the second switch φ s and the second switch φ i connected to the positive electrode of the sampling capacitor;
[0011] The second switch assembly includes a third switch φ s , the fourth switch φ s , the first switch φ i1 , the second switch φ i1 , the third switch φ i1 , the first switch φ s +φ i2 , the second switch φ s +φ i2 , the third switch φ s +φ i2 , the first switch φ i2 and the first switch φ ix ,
[0012] The first switch φ s +φ i2 and the first switch φ i1 Connected to the negative input terminal of the first stage amplifier, the second switch φs+φ i2 and the second switch φ i1 connected to the positive input terminal of the first stage amplifier, the third switch φ i1 and the third switch φ s +φ i2One end of the switch is connected to the output end of the first stage amplifier, and the third switch φ i1 and the third switch φ s +φ i2 The other end of the first switch φ is connected in series to the negative input terminal of the second stage amplifier. i2 and the first switch φ ix connected to the output terminal of the second stage amplifier; the first switch φ i1 Connected to the first integrating capacitor C i1 The positive electrode of the third switch φ s and the third switch φ i1 Connected to the first integrating capacitor C i1 The negative electrode of the second switch φi, the first switch φ i1 and the second switch φ s +φ i2 Connected to the second integrating capacitor C i2 The positive electrode of the fourth switch φ s and the first switch φ i2 Connected to the second integrating capacitor C i2 The negative electrode;
[0013] The first switch component and the second switch component are respectively s , Φ i , Φ i1 , Φ i2 and Φ ix To conduct and disconnect, where Φ s and Φ i is a two-phase non-overlapping clock signal, Φ i1 and Φ i2 For non-overlapping clock signals.
[0014] Preferably, when the timing control signal Φ s When the first switch φ in the first switch component is high, s and the second switch φ s conduction.
[0015] Preferably, when the timing control signal Φ s When the level is high, the third switch φ in the second switch component s , the fourth switch φ s , the first switch φs+φ i2 The second switch φ s +φ i2 and the third switch φ s +φ i2 conduction.
[0016] Preferably, when the timing control signal Φ i1 When the first switch φ in the first switch component is high, i and the second switch φ i conduction.
[0017] Preferably, when the timing control signal Φ i1 When the first switch φ in the second switch component is high, i1 The second switch φ i1 , the third switch φ i1 and the first switch φ ix conduction.
[0018] Preferably, when the timing control signal Φ i2 When the first switch φ in the first switch component is high, i and the second switch φ i conduction.
[0019] Preferably, when the timing control signal Φ i2 When the first switch φ in the second switch component is high, s +φ i2 The second switch φ s +φ i2 , the third switch φ s +φ i2 and the first switch φ i2 The first switch φ is turned on. ix The on state lasts for a set period of time and then turns off.
[0020] Preferably, the second stage amplifier is only i1 Works at low level.
[0021] Preferably, the first-stage amplifier is a large-bandwidth amplifier, and the first-stage amplifier and the second-stage amplifier are cascaded to form a two-stage operational amplifier with high gain.
[0022] The positive progress of the present invention is that: a switched capacitor integrator with segmented integration is provided, wherein the integration stage is divided into a first integration stage and a second integration stage based on an integration circuit composed of a first-stage amplifier, a second-stage amplifier, a first integrating capacitor, and a second integrating capacitor; the first switching component and the second switching component are turned on or off according to a timing control signal, thereby transferring and integrating the input signal to the first integrating capacitor C i1 and the second integrating capacitor C i2 Without increasing power consumption and sacrificing settling speed, the problem of difficulty in reducing the integral leakage of the integrator, which leads to performance degradation of the Sigma-Delta analog-to-digital converter, is completely solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Schematic diagram of a switched capacitor integrator with segmented integration according to embodiment 1 of the present invention.
[0024] Figure 2 This is a first circuit structure diagram of a switched capacitor integrator with segmented integration according to embodiment 2 of the present invention.
[0025] Figure 3 Schematic diagram of timing control signals of a switched capacitor integrator with segmented integration according to embodiment 2 of the present invention.
[0026] Figure 4 This is a second circuit structure diagram of the switched capacitor integrator with segmented integration according to the second embodiment of the present invention.
[0027] Figure 5 This is a third circuit structure diagram of the switched capacitor integrator with segmented integration according to the second embodiment of the present invention.
[0028] Figure 6 This is a fourth circuit structure diagram of the switched capacitor integrator with segmented integration according to the second embodiment of the present invention.
[0029] Figure 7 Schematic diagram of a traditional switched capacitor integrator according to embodiment 2 of the present invention. DETAILED DESCRIPTION
[0030] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.
[0031] Example 1
[0032] like Figure 1 As shown, this embodiment provides a schematic diagram of a segmented integration. The switched capacitor integrator includes: a sampling circuit 10 and an integration circuit 20. The sampling circuit 10 and the integration circuit 20 are electrically connected. The sampling circuit 10 includes a sampling capacitor 11 and a first switch component 12; the integration circuit 20 includes a first-stage amplifier 21, a second-stage amplifier 22, a first integration capacitor C i1 23. Second integrating capacitor C i2 24 and the second switch component 25; the first integral capacitor C i1 23 and the second integrating capacitor C i2 24 are respectively connected to the input end of the first stage amplifier 21, and the output end of the first stage amplifier 21 is connected to the negative input end of the second stage amplifier 22;
[0033] The first switch component 12 and the second switch component 25 are used to be turned on and off according to a timing control signal, and the timing control signal includes at least two-phase non-overlapping clock signals;
[0034] The sampling circuit 10 is used to collect the original signal into the sampling capacitor and output the input signal to the integration circuit 20 according to the original signal;
[0035] The integration circuit 20 is used to transfer and integrate the input signal to the first integration capacitor C under different working states corresponding to the timing control signals. i1 and the second integrating capacitor C i2 .
[0036] In this embodiment, an integration circuit consisting of a first-stage amplifier and a second-stage amplifier divides the integration phase into two stages, employing two op amps with different performance advantages for segmented integration. During the first stage of integration, a high-bandwidth but relatively low-gain op amp is used to quickly approach the desired voltage. During the second stage of integration, a high-gain but relatively slow op amp is used to achieve the desired voltage. This switched capacitor integrator improves integrator performance without increasing power consumption, while simplifying the circuit design and making it easy to implement.
[0037] This embodiment provides a switched capacitor integrator with segmented integration. The integration circuit composed of a first-stage amplifier, a second-stage amplifier, a first integrating capacitor, and a second integrating capacitor divides the integration phase into a first integration segment and a second integration segment. The first switch component and the second switch component are turned on or off according to a timing control signal to transfer and integrate the input signal to the first integrating capacitor C. i1 and the second integrating capacitor C i2 Without increasing power consumption and sacrificing settling speed, the problem of difficulty in reducing the integral leakage of the integrator, which leads to performance degradation of the Sigma-Delta analog-to-digital converter, is completely solved.
[0038] Example 2
[0039] On the basis of Example 1, Figure 2 As shown, this embodiment provides a first circuit structure diagram of a switched capacitor integrator with segmented integration. Figure 1 The schematic diagram of the switched capacitor integrator with segmented integration is shown as Figure 2 The same electronic components in the first circuit structure diagram of the segmented integrated switched capacitor integrator are denoted by the same reference numerals.
[0040] The first switch assembly 12 includes a first switch φ s , the second switch φ s , the first switch φ i and the second switch φ i , the first switch φ s and the first switch φ i Connected to the sampling capacitor The negative pole of the second switch φ s and the second switch φ i Connected to the sampling capacitor The positive electrode;
[0041] The second switch assembly 25 includes a third switch φ s , the fourth switch φ s , the first switch φ i1 , the second switch φ i1 , the third switch φ i1 , the first switch φ s +φ i2 , the second switch φ s +φ i2 , the third switch φ s +φ i2 , the first switch φ i2 and the first switch φ ix ,
[0042] The first switch φ s +φ i2 and the first switch φ i1 Connected to the negative input terminal of the first stage amplifier A1, the second switch φ s +φ i2 and the second switch φ i1 Connected to the positive input terminal of the first stage amplifier A1, the third switch φ i1 and the third switch φ s +φ i2 One end of the third switch is connected to the output end of the first stage amplifier A1, i1 and the third switch φ s +φ i2 The other end is connected in series to the negative input terminal of the second stage amplifier A2, and the first switch φ i2 and the first switch φ ix Connected to the output terminal of the second stage amplifier A2; the first switch φ i1 Connected to the first integrating capacitor C i1 The positive pole of the third switch φ s and the third switch φ i1 Connected to the first integrating capacitor C i1 The negative electrode of the second switch φi, the first switch φ i1 and the second switch φ s +φ i2 Connected to the second integrating capacitor C i2 The positive pole of the fourth switch φ s and the first switch φ i2 Connected to the second integrating capacitor C i2 The negative electrode;
[0043] The first switch component 12 and the second switch component 25 are respectively controlled by the timing control signal Φ s , Φ i , Φ i1 , Φ i2 and Φ ix To conduct and disconnect, where Φ s and Φ i is a two-phase non-overlapping clock signal, Φ i1 and Φ i2 For non-overlapping clock signals.
[0044] In this embodiment, Figure 2 As shown, C L represents the load capacitance, φ s The switch is represented by Φ s The sampling phase timing clock controls the switch, φ i The switch is represented by Φ i , the switching of the timing clock controlled by the integral phase, φ i1 The switch is represented by Φ i1 The first integral phase timing clock controls the switch. The switch is represented by Φ i2 The switch of the second integral phase is controlled by the timing clock, φ ix The switch is represented by Φ ix The switch is controlled by the phase timing clock. When the corresponding timing control signal is high, the switch is turned on. This means that when Φ i1 The timing clock control signal is valid when it is low.
[0045] like Figure 3 As shown, when the timing control signal Φ s When it is high, the first switch φs, the second switch φs, the third switch φs, and the fourth switch φs can be controlled to be turned on, and the other switches in the first switch component and the second switch component are turned off. Figure 3 As shown, when the timing control signal Φ i When the timing control signal Φ is high, i1 and Φ ix When it is also at a high level, that is, in the first integration stage, the first switch φ in the first switch component and the second switch component is controlled. i , the second switch φ i , the first switch φ i1 , the second switch φ i1 , the third switch φ i1 and the first switch φ ix The first switch component and the other switches in the second switch component are turned off, and the second stage amplifier A222 is turned off. i When the timing control signal Φ is high,ix When the level is high, the first switch φ in the first switch component and the second switch component is controlled. i , the second switch φ i and the first switch φ ix is turned on, and the other switches in the first switch component and the second switch component are controlled to be turned off. i When the timing control signal Φ is high, i2 When it is high, that is, in the second integration stage, the first switch φ in the first switch component and the second switch component is controlled. i , the second switch φ i , the first switch φ i2 , the first switch φ s +φ i2 , the second switch φ s +φ i2 and the third switch φ s +φ i2 On, the first switch φ ix The on state lasts for a set period of time and then turns off.
[0046] Figure 4 The second circuit structure diagram of the switched capacitor integrator with segmented integration, when the timing control signal Φ s When the first switch φ in the first switch assembly is high, s and the second switch φ s The third switch φ in the second switch assembly is turned on. s , the fourth switch φ s , the first switch φ s +φ i2 , the second switch φ s +φ i2 and the third switch φ s +φ i2 conduction.
[0047] In this embodiment, when the timing control signal Φ s When it is high, Figure 2 The first switch φ in the first switch assembly s and the second switch φ s is turned on while the other switches are turned off, and Figure 2 The third switch φ in the second switch assembly s , the fourth switch φ s , the first switch φ s +φ i2 , the second switch φ s +φ i2 and the third switch φ s +φ i2 When the switch is turned on and the other switches are turned off, the circuit structure obtained by the equivalent change Figure 4In the sampling phase Φ s During this period, the sampling circuit 10 collects the original signal into the sampling capacitor .
[0048] Figure 5 The third circuit structure diagram of the switched capacitor integrator with segmented integration, when the timing control signal Φ i1 When the first switch φ in the first switch assembly is high, i and the second switch φ i The first switch φ in the second switch assembly is turned on. i1 , the second switch φ i1 , the third switch φ i1 and the first switch φ ix is turned on, and the second stage amplifier A222 is turned off.
[0049] In this embodiment, when the timing control signal Φ i1 When it is high, Figure 2 The first switch φ in the first switch assembly i and the second switch φ i is turned on while the other switches are turned off, and Figure 2 The first switch φ in the second switch assembly i1 , the second switch φ i1 , the third switch φ i1 and the first switch φ ix When the other switches are turned on and the second-stage amplifier A222 is turned off, the circuit structure obtained by the equivalent change is Figure 5 .
[0050] In the first integral phase Φ i1 During this period, the second stage op amp A2 of the two-stage op amp is turned off, and the first stage op amp A1 is working, which will Most of the charge is transferred to the first integrating capacitor C i1 However, due to the limited gain of the first-stage operational amplifier A1, the sampling capacitor There is still a small amount of residual charge.
[0051] Figure 6 The fourth circuit structure diagram of the switched capacitor integrator with segmented integration, when the timing control signal Φ i2 When the first switch φ in the first switch assembly is high, i and the second switch φ i The first switch φ in the second switch assembly is turned on. s +φ i2 , the second switch φ s +φ i2 , the third switch φ s +φ i2 and the first switch φ i2On, the first switch φ ix The on state lasts for a set period of time and then turns off.
[0052] In this embodiment, when the timing control signal Φ i2 When it is high, Figure 2 The first switch φ in the first switch assembly i and the second switch φ i is turned on while the other switches are turned off, and Figure 2 The first switch φ in the second switch assembly s +φ i2 , the second switch φ s +φ i2 , the third switch φ s +φ i2 and the first switch φ i2 is turned on while the other switches are turned off, and the first switch φ ix The conduction state lasts for a set period of time and then turns off. The circuit structure obtained by the equivalent change Figure 6 .
[0053] In the second integral phase Φ i2 During this period, operational amplifiers A1 and A2 are cascaded to form a two-stage operational amplifier to complete the charge integration operation, and the sampling capacitor The small amount of residual charge is transferred to the second integrating capacitor C i2 In general, this integration stage is equivalent to a traditional integrator using two-stage op amps, but the charge transfer time is determined by the second-stage amplifier A2. i2 The negative electrode is connected by the first switch φ ix Control the grounded switch so that when the first integral phase switches to the second integral phase, the node voltage The node voltage can be quickly lowered to speed up the integration. and node voltage The relationship is as follows, and Indicates the capacitance value of the corresponding capacitor.
[0054]
[0055] In the output sampling stage, that is, the next sampling stage Φ s During this period, the operational amplifiers A1 and A2 are cascaded to form a two-stage operational amplifier and then continue to perform the charge integration operation, and the second integral capacitor C i2 The residual charge obtained by upsampling is transferred to the first integrating capacitor C i1 Although the first integrating capacitor C i1 and the second integrating capacitor C i2 The charge on the remain unchanged, .
[0056] The following calculation formula is used to theoretically verify that the performance of the switched capacitor integrator with segmented integration in this embodiment is significantly improved compared to the traditional switched capacitor integrator:
[0057] like Figure 7 As shown in the figure, it is a typical traditional switched capacitor integrator, which consists of three parts: switch, capacitor and operational amplifier. The sampling switch and the integration switch are controlled by a two-phase clock signal to control the charging and discharging process of the capacitor, thereby realizing the integration processing of the input signal.
[0058] Figure 7 China A v Represents the finite DC gain of the op amp, V in Indicates the input voltage, V out Indicates the output voltage, V x Represents the voltage at the negative input terminal of the operational amplifier, C s Represents the sampling capacitor, C i Indicates the integrating capacitor, C L represents the load capacitance, Figure 7 The line graph in the lower left corner shows the timing control signal diagram, φ s The switch is represented by φ s The sampling phase timing clock controls the switch, φ i The switch is represented by Φ i The timing clock of the integral phase controls the switch, φ s Switch and φ i The switch is turned on when the corresponding timing control signal is high. According to the principle of charge conservation:
[0059] (1)
[0060] In the formula, [n-1] represents the n-1th cycle, [n] represents the nth cycle, Represents the charge on the sampling capacitor Cs, Represents the amount of charge on the integrating capacitor Ci.
[0061] From formula (1), the charge on the integrating capacitor can be expressed as:
[0062] (2)
[0063] because , ,and ,
[0064] Where, Indicates the output voltage V out , and represents the capacitance of the corresponding capacitor, then formula (2) can be simplified as:
[0065] (3)
[0066] According to formula (3), we can know that: , represents the charge transfer error term, assuming ,but .
[0067] Therefore, it can be seen that the limited DC gain of the op amp will reduce the gain of the integrator and introduce integration leakage. To reduce integration leakage and improve integrator performance, the op amp gain needs to be increased without sacrificing settling speed. However, this is difficult to achieve with a typical traditional switched capacitor integrator without increasing power consumption.
[0068] like Figure 4-6 As shown, according to the charge conservation theorem:
[0069]
[0070] Where [n-1] represents the n-1th phase (sampling phase ), [nt] represents the ntth phase (the first integral phase Φ i1 ), [n] represents the nth phase (the second integral phase Φ i2 ), Represents the sampling capacitor C s The amount of charge on Represents the first integrating capacitor C i1 The amount of charge on Represents the second integrating capacitor C i2 The amount of charge on .
[0071] because , so we have:
[0072] (4)
[0073] Similar to the traditional integrator, we can get:
[0074] (5)
[0075] According to formula (5), the charge transfer error is:
[0076] (6)
[0077] Depend on Figure 6 Middle Φ i2 The second section of the integration circuit can obtain the sampling capacitor C s The charge on is:
[0078] (7)
[0079] Where, Indicates the capacitance value of the corresponding capacitor, represents the finite DC gain of the first-stage op amp, Represents the finite DC gain of the second-stage op amp.
[0080] Depend on Figure 5 and Figure 6 Φ i1 , Φ i2 The total integrated charge of the integral phase circuit can be obtained and the sampling capacitor at the ntth phase The amount of charge on They are:
[0081] (8)
[0082] (9)
[0083] According to formula (9), the node voltage can be obtained for:
[0084] (10)
[0085] According to equations (8) and (10), the total integrated charge can be obtained for:
[0086] (11)
[0087] Therefore, according to equations (6) and (11), the charge transfer error term of the integrator circuit can be obtained as:
[0088] (12)
[0089] Assuming finite DC gain of the op amp and , then , it can be seen that compared with the traditional integrator, the equivalent DC gain of the switched capacitor integrator op amp of the segmented integration in the present invention is The larger the value, the smaller the integral error, which can improve the performance of the integrator without increasing power consumption and make the circuit design simple and easy to implement.
[0090] This embodiment provides a switched capacitor integrator with segmented integration, which uses an integration circuit to divide the integration stage into two stages, and adopts two first-stage amplifiers and second-stage amplifiers with different performance advantages to perform segmented integration. This improves the performance of the integrator without increasing power consumption or sacrificing settling speed, and makes the circuit design simple and easy to implement.
[0091] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.
Claims
1. A switched capacitor integrator with segmented integration, characterized in that: The switch capacitor integrator includes: a sampling circuit and an integration circuit, the sampling circuit and the integration circuit are electrically connected, the sampling circuit includes a sampling capacitor and a first switch component; the integration circuit includes a first stage amplifier, a second stage amplifier, a first integration capacitor C i1 , the second integrating capacitor C i2 and a second switch component; the first integral capacitor C i1 and the second integrating capacitor C i2 are respectively connected to the input end of the first stage amplifier, and the output end of the first stage amplifier is connected to the negative input end of the second stage amplifier; The first switch component and the second switch component are configured to be turned on and off according to a timing control signal, wherein the timing control signal comprises at least a two-phase non-overlapping clock signal; The sampling circuit is used to collect the original signal into the sampling capacitor and output an input signal to the integration circuit according to the original signal; The integration circuit is used to transfer and integrate the input signal to the first integration capacitor C under different working states corresponding to the timing control signal. i1 and the second integrating capacitor C i2 .
2. The switched capacitor integrator with segmented integration as claimed in claim 1, wherein: The first switch assembly includes a first switch φ s , the second switch φ s , the first switch φ i and the second switch φ i , the first switch φ s and the first switch φ i connected to the negative electrode of the sampling capacitor, the second switch φ s and the second switch φ i connected to the positive electrode of the sampling capacitor; The second switch assembly includes a third switch φ s , the fourth switch φ s , the first switch φ i1 , the second switch φ i1 , the third switch φ i1 , the first switch φ s +φ i2 , the second switch φ s +φ i2 , the third switch φ s +φ i2 , the first switch φ i2 and the first switch φ ix , The first switch φ s +φ i2 and the first switch φ i1 connected to the negative input terminal of the first stage amplifier, the second switch φ s +φ i2 and the second switch φ i1 connected to the positive input terminal of the first stage amplifier, the third switch φ i1 and the third switch φ s +φ i2 One end of the switch is connected to the output end of the first stage amplifier, and the third switch φ i1 and the third switch φ s +φ i2 The other end of the first switch φ is connected in series to the negative input terminal of the second stage amplifier. i2 and the first switch φ ix connected to the output terminal of the second stage amplifier; the first switch φ i1 Connected to the first integrating capacitor C i1 The positive electrode of the third switch φ s and the third switch φ i1 Connected to the first integrating capacitor C i1 The negative electrode of the second switch φ i , the first switch φ i1 and the second switch φ s +φ i2 Connected to the second integrating capacitor C i2 The positive electrode of the fourth switch φ s and the first switch φ i2 Connected to the second integrating capacitor C i2 The negative electrode; The first switch component and the second switch component are respectively s , Φ i , Φ i1 , Φ i2 and Φ ix To conduct and disconnect, where Φ s and Φ i is a two-phase non-overlapping clock signal, Φ i1 and Φ i2 For non-overlapping clock signals.
3. The switched capacitor integrator with segmented integration as claimed in claim 2, wherein: When the timing control signal Φ s When the first switch φ in the first switch component is high, s and the second switch φ s conduction.
4. The switched capacitor integrator with segmented integration as claimed in claim 3, wherein: When the timing control signal Φ s When the level is high, the third switch φ in the second switch component s , the fourth switch φ s , the first switch φs+φ i2 , the second switch φs+φ i2 and the third switch φs+φ i2 conduction.
5. The switched capacitor integrator with segmented integration as claimed in claim 2, wherein: When the timing control signal Φ i1 When the level is high, the first switch φi and the second switch φi in the first switch component are turned on.
6. The switched capacitor integrator with segmented integration as claimed in claim 5, wherein: When the timing control signal Φ i1 When the first switch φ in the second switch component is high, i1 The second switch φ i1 , the third switch φ i1 and the first switch φ ix conduction.
7. The switched capacitor integrator with segmented integration as claimed in claim 2, wherein: When the timing control signal Φ i2 When the level is high, the first switch φi and the second switch φi in the first switch component are turned on.
8. The switched capacitor integrator with segmented integration as claimed in claim 7, wherein: When the timing control signal Φ i2 When the first switch φ in the second switch component is high, s +φ i2 The second switch φ s +φ i2 , the third switch φ s +φ i2 and the first switch φ i2 The first switch φ is turned on. ix The on state lasts for a set period of time and then turns off.
9. The switched capacitor integrator with segmented integration as claimed in claim 2, wherein: The second stage amplifier is only activated when the timing control signal Φ i1 Works at low level.
10. The switched capacitor integrator with segmented integration as claimed in claim 1, wherein: The first-stage amplifier is a large-bandwidth amplifier, and the first-stage amplifier and the second-stage amplifier are cascaded to form a two-stage operational amplifier with high gain.