Compression method and compression device of test data, computer readable storage medium and electronic equipment

Abstract

The invention discloses a compression method and compression device of test data, a computer readable storage medium and electronic equipment, and the compression method of the test data comprises the following steps: S100, obtaining corresponding test data based on a to-be-tested chip, and initializing the test data to obtain a plurality of pieces of test vector data which are arranged in sequence; s200, combining continuous and repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data; and S300, storing the compressed test vector data in a vector memory.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of integrated circuit testing, and more particularly, to a test data compression method, a compression device, a computer-readable storage medium, and an electronic device. Background Art

[0002] A system-on-chip (SoC) is an integrated circuit that combines all necessary components onto a single chip. High fault coverage is a crucial requirement for its testing. Achieving this high fault coverage requires a large amount of test data, often referred to as vectors. The input or output responses of each pin on the chip under test are grouped together as test data. As the complexity of modern SoCs increases, achieving maximum test coverage requires an increasing number of test vectors.

[0003] The hardware memory of integrated circuit test equipment, such as automated testers (ATE), is often limited to a certain value. Requirement of maximum test hardware memory subsequently increases hardware or software costs, thereby increasing test costs. A proven technique is to optimize the test vector data stored in the hardware memory. Test data compression involves compressing the test input or output responses so that the entire test data (pattern) can be stored in the ATE hardware memory. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method for compressing test data, comprising the following steps:

[0005] S100: Acquire corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence;

[0006] S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data;

[0007] S300: Storing the compressed test vector data in a vector memory.

[0008] In some embodiments, step S100: acquiring corresponding test data based on the chip under test and initializing the test data to obtain a plurality of test vector data arranged in sequence includes the following steps:

[0009] S110: Acquire corresponding test data based on the chip under test, the test data including a plurality of initial test vector data arranged in sequence, each initial test vector data including period data and vector data, the period data indicating the execution time of the initial test vector data, and the vector data including input or output data corresponding to each pin of the chip under test;

[0010] S120: Perform an initialization operation on each initial test vector data to obtain a plurality of test vector data arranged in sequence, wherein the initialization operation includes defining the first-level sequencer data of the initial test vector data as R1, indicating execution once, and each test vector data after initialization includes the first-level sequencer data, period data and vector data.

[0011] In some embodiments, step S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of multiple test vector data to obtain compressed test vector data comprises the following steps:

[0012] S210: performing a first level of processing on the plurality of test vector data sequentially arranged after initialization, so as to merge and compress the continuously repeated test vector data in the plurality of test vector data;

[0013] S220: Performing a second level of processing on the plurality of test vector data that have undergone the first level of processing, so as to merge and compress two consecutively repeated adjacent test vector data in the plurality of test vector data that have undergone the first level of processing.

[0014] In some embodiments, step S210: performing the first level processing on the plurality of test vector data sequentially arranged after initialization to merge and compress the continuously repeated test vector data in the plurality of test vector data includes the following steps:

[0015] S211: Taking the first row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the first row of test vector data until the i-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and 2≤i≤n, and n is the number of rows of multiple test vector data arranged in sequence after initialization, merge the first row of test vector data to the i-1th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Ri-1, indicating that the operation is repeated i-1 times;

[0016] S212: Taking the i-th row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the i-th row of test vector data until the j-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and i+1≤j≤n, merge the i-th row of test vector data to the j-1-th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Rj-i, indicating that the execution is repeated j times;

[0017] S213: starting with the jth row of test vector data and sequentially referring to step S212, the process continues until n rows of test vector data have been traversed.

[0018] S214: The test vector data that have been merged and compressed are renumbered in sequence, where m is the number of rows of the test vector data that have been merged and compressed, and 1≤m≤n.

[0019] In some embodiments, step S220: performing the second level processing on the plurality of test vector data after the first level processing, merging and compressing two consecutively repeated adjacent test vector data in the plurality of test vector data after the first level processing, includes the following steps:

[0020] S221: Taking the 1st and 2nd rows of test vector data as references, sequentially compare the subsequent two consecutive rows of test vector data with the 1st and 2nd rows of test vector data; if the 3rd and 4th rows of test vector data are respectively the same as the 1st and 2nd rows of test vector data, then continue to compare the subsequent two rows of test vector data with the 1st and 2nd rows of test vector data until the kth and k+1th rows of test vector data that are different from the 1st and 2nd rows of test vector data are found, where k is a positive integer and 5≤k≤m-1;

[0021] S222: If the third and fourth rows of test vector data are different from the first and second rows of test vector data, then refer to step S211 to compare the subsequent two consecutive rows of test vector data with the second and third rows of test vector data based on the second and third rows of test vector data;

[0022] S223: Merge two consecutive lines of test vector data that are repeated p times into two consecutive lines of test vector data, and assign the second-level sequencer data to the two consecutive lines of test vector data as Lp, indicating that the loop is executed p times, where

[0023] S224: The test vector data that have been merged and compressed are renumbered in sequence, where q is the number of rows of the test vector data that have been merged and compressed, and 1≤q≤m.

[0024] In some embodiments, the compression method further comprises the following steps:

[0025] S230: Referring to step S220, the next level of processing is performed sequentially until the t-th level of processing, wherein,

[0026] s is the number of rows of the test vector data after the t-1th level of processing.

[0027] In some embodiments, step S300: storing the compressed test vector data in the vector memory includes the following steps:

[0028] The compressed test vector data is written into the vector memory row by row, and each row of test vector data stores one storage row space in the vector. Each storage row space includes a vector data storage unit and a control data storage unit. The vector data storage unit is used to store the vector data of the corresponding row test vector data, and the control data storage unit is used to store the vector data period data and sequencer data of each level of the corresponding row test vector data.

[0029] Some embodiments of the present disclosure provide a test data compression device, wherein:

[0030] An initialization module is configured to obtain corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence;

[0031] a merging and compressing module configured to merge consecutively repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data;

[0032] The storage module is configured to store the compressed test vector data in the vector memory.

[0033] Some embodiments of the present disclosure provide a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the compression method as described in the aforementioned embodiments is implemented.

[0034] Some embodiments of the present disclosure provide an electronic device, comprising: one or more processors; a storage device for storing one or more programs, which, when executed by the one or more processors, enables the one or more processors to implement the compression method described in the aforementioned embodiments.

[0035] According to the technical solution of the embodiment of the present disclosure, by effectively analyzing the vector data in the test vector data, the test vector data is merged and compressed by adopting the method of vector data reuse, the test vector data is quickly optimized, the memory occupied by the test vector data is reduced, the storage cost is saved, and thus the test cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 A flowchart of a method for compressing test data provided in some embodiments of the present disclosure;

[0038] Figure 2 for Figure 1 Specific flow chart of step S100;

[0039] Figure 3 for Figure 1 Specific flow chart of step S200;

[0040] Figure 4 for Figure 3 Specific flow chart of step S210;

[0041] Figure 5 for Figure 3 Specific flow chart of step S220;

[0042] Figure 6 A schematic diagram of the storage structure of a vector memory provided in some embodiments of the present disclosure;

[0043] Figure 7 A structural block diagram of a test data compression device provided in some embodiments of the present disclosure.

[0044] In the drawings, the same or similar structures are marked with the same or similar reference numerals. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present disclosure, rather than all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present disclosure without creative effort are intended to fall within the scope of protection of the present disclosure.

[0046] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a," "an," "the," and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include plural forms, and unless the context clearly indicates otherwise, "a plurality" generally includes at least two.

[0047] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0048] It should be understood that although the terms "first," "second," "third," etc. may be used to describe structures in the embodiments of the present disclosure, these structures should not be limited to these terms. These terms are merely used to distinguish different structures. For example, a first component may also be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the embodiments of the present disclosure.

[0049] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0050] It should also be noted that the terms "include," "comprises," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a product or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such product or device. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the product or device comprising the element.

[0051] In the related art, system-on-chip (SoC) consists of highly complex blocks, requiring high fault coverage testing. To achieve maximum test coverage, the number of patterns to be tested must increase significantly. It is quite difficult to fit all patterns into the tester hardware memory without exceeding memory limitations.

[0052] In order to overcome the above problems, the present disclosure provides a test data compression method, including the following steps: S100: obtaining corresponding test data based on the chip to be tested and initializing the test data to obtain multiple test vector data arranged in sequence; S200: merging continuously repeated test vector data and / or test vector data groups based on comparing multiple test vector data to obtain compressed test vector data; S300: storing the compressed test vector data in a vector memory.

[0053] In the present disclosure, by effectively analyzing the vector data in the test vector data, the test vector data is merged and compressed by adopting the method of vector data reuse, the test vector data is quickly optimized, the memory occupied by the test vector data is reduced, the storage cost is saved, and thus the test cost is reduced.

[0054] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0055] Figure 1 Flowchart of a method for compressing test data provided by some embodiments of the present disclosure. Figure 1 As shown, some embodiments of the present disclosure provide a method for compressing test data, the compression method comprising the following steps:

[0056] S100: Acquire corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence;

[0057] S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data;

[0058] S300: Storing the compressed test vector data in a vector memory.

[0059] The test vector data memory optimization method proposed in the present disclosure is achieved by analyzing the vector data in the test vector data without considering the test case. In the test data of each pin, there may be a large amount of duplicate data. By effectively analyzing the vector data, these duplicate data can be optimized using sequencing instructions. Through multi-level analysis of the test vector data and optimization through sequencer-controlled vector data reuse, the memory occupied by the test vector data is reduced, storage costs are saved, and thus the test cost is reduced.

[0060] Figure 2 for Figure 1 In some embodiments, the step S100 of obtaining corresponding test data based on the chip under test and initializing the test data to obtain a plurality of test vector data arranged in sequence includes the following steps:

[0061] S110: Acquire corresponding test data based on the chip under test, the test data including a plurality of initial test vector data arranged in sequence, each initial test vector data including period data and vector data, the period data indicating the execution time of the initial test vector data, and the vector data including input or output data corresponding to each pin of the chip under test;

[0062] In step S110, the chip structures of different system-on-chip (SoC) are different, and the number of pins is also different, which requires a specific large amount of test data. The test data includes a plurality of initial test vector data arranged in sequence, for example, a plurality of initial test vector data arranged in the order of execution. The period data in the initial test vector data represents the execution time of the initial test vector data, for example, represented by WFT_1, WFT_2, WFT_3..., WFT_1, for example, represents 1μs, WFT_2, for example, represents 2μs, WFT_3, for example, represents 3μs... The vector data in the initial test vector data includes the input or output data corresponding to each pin of the chip to be tested. The pins of the chip to be tested include input pins and / or output pins. When the input signal of the input pin is high, it is represented by 1, and when it is low, it is represented by 0. When the output signal of the output pin is high, it is represented by H, and when it is low, it is represented by L. The vector data in the initial test vector data is a data string composed of multiple references to the corresponding input or output levels.

[0063] By introducing test data into the chip for chip testing, the chip test result is determined by comparing the actual output of the output pin of the chip to be tested with the level of the output pin of the vector data in the initial test vector data, and the chip is graded.

[0064] S120: Perform an initialization operation on each initial test vector data to obtain a plurality of test vector data arranged in sequence, wherein the initialization operation includes defining the first-level sequencer data of the initial test vector data as R1, indicating execution once, and each test vector data after initialization includes the first-level sequencer data, period data and vector data.

[0065] In step S120, the first-level sequencer data of each initial test vector data is defined through an initialization operation, so that each test vector data includes the first-level sequencer data, period data and vector data, and the first-level sequencer data is used for compression and merging of subsequent test vector data.

[0066] Figure 3 for Figure 1 In some embodiments, as shown in FIG. Figure 3 As shown, step S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of multiple test vector data to obtain compressed test vector data includes the following steps:

[0067] S210: performing a first level of processing on the plurality of test vector data sequentially arranged after initialization, so as to merge and compress the continuously repeated test vector data in the plurality of test vector data;

[0068] S220: Performing a second level of processing on the plurality of test vector data that have undergone the first level of processing, so as to merge and compress two consecutively repeated adjacent test vector data in the plurality of test vector data that have undergone the first level of processing.

[0069] Hierarchical compression processing is performed on multiple test vector data arranged in sequence after initialization, vector data is reused, the memory occupied by the test vector data is reduced, storage costs are saved, and thus test costs are reduced.

[0070] Figure 4 for Figure 3 In some embodiments, as shown in FIG. Figure 4 As shown, step S210: performing the first level processing on the plurality of test vector data sequentially arranged after initialization to merge and compress the continuously repeated test vector data in the plurality of test vector data includes the following steps:

[0071] S211: Taking the first row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the first row of test vector data until the i-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and 2≤i≤n, and n is the number of rows of multiple test vector data arranged in sequence after initialization, merge the first row of test vector data to the i-1th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Ri-1, indicating that the operation is repeated i-1 times;

[0072] In step S211, the test vector data of the first row is used as a reference to compare the test vector data of the second row with the test vector data of the first row. If the two are different, that is, the first-level sequencer data, period data and vector data are not exactly the same, then step S212 is performed. If the two are exactly the same, that is, the first-level sequencer data, period data and vector data are exactly the same, then the test vector data of the third row is compared with the test vector data of the first row. If the two are different, then step S212 is performed. If the two are exactly the same, then the test vector data of the fourth row is compared with the test vector data of the first row, until the test vector data of the i-th row that is not exactly the same as the test vector data of the first row is found. For example, the test vector data of the second to fourth rows are exactly the same as the test vector data of the first row, and the test vector data of the fifth row is not exactly the same as the test vector data of the first row.

[0073] At this time, the identical test vector data from the 1st row to the 4th row are merged into one row of test vector data, and the first-level sequencer data of the row is modified to R4, indicating execution 4 times.

[0074] S212: Taking the i-th row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the i-th row of test vector data until the j-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and i+1≤j≤n, merge the i-th row of test vector data to the j-1-th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Rj-i, indicating that the execution is repeated j times;

[0075] In step S212, for example, taking the 5th row of test vector data as a reference, the 6th row of test vector data is compared with the 5th row of test vector data. If the two are different, that is, the first-level sequencer data, cycle data and vector data are not exactly the same, then step S212 is performed. If the two are exactly the same, that is, the first-level sequencer data, cycle data and vector data are exactly the same, then the 7th row of test vector data is compared with the 1st row of test vector data. If the two are different, then step S212 is performed. If the two are exactly the same, then the 8th row of test vector data is compared with the 5th row of test vector data until the jth row of test vector data that is not exactly the same as the 5th row of test vector data is found. For example, the 6th to 7th row of test vector data is exactly the same as the 5th row of test vector data, and the 8th row of test vector data is not exactly the same as the 8th row of test vector data.

[0076] At this time, the identical test vector data from the 5th row to the 7th row are merged into one row of test vector data, and the first-level sequencer data of this row is modified to R3, indicating execution 3 times.

[0077] S213: starting with the jth row of test vector data and sequentially referring to step S212, the process continues until n rows of test vector data have been traversed.

[0078] Using an operation similar to step S212, all rows of test vector data are traversed, the continuously repeated test vector data in the multiple test vector data are merged and compressed, and the number of repetitions of the continuously repeated test vector data is recorded based on the first-level sequencer data.

[0079] S214: The test vector data that have been merged and compressed are renumbered in sequence, where m is the number of rows of the test vector data that have been merged and compressed, and 1≤m≤n.

[0080] The test vector data that has been merged and compressed are renumbered in sequence to facilitate subsequent merging and compression processing.

[0081] Figure 5 for Figure 3 In some embodiments, as shown in FIG. Figure 5As shown, step S220: performing the second level processing on the plurality of test vector data that have undergone the first level processing, merging and compressing two consecutively repeated adjacent test vector data in the plurality of test vector data that have undergone the first level processing, includes the following steps:

[0082] S221: Taking the 1st and 2nd rows of test vector data as references, sequentially compare the subsequent two consecutive rows of test vector data with the 1st and 2nd rows of test vector data; if the 3rd and 4th rows of test vector data are respectively the same as the 1st and 2nd rows of test vector data, then continue to compare the subsequent two rows of test vector data with the 1st and 2nd rows of test vector data until the kth and k+1th rows of test vector data that are different from the 1st and 2nd rows of test vector data are found, where k is a positive integer and 5≤k≤m-1;

[0083] S222: If the third and fourth rows of test vector data are different from the first and second rows of test vector data, then refer to step S211 to compare the subsequent two consecutive rows of test vector data with the second and third rows of test vector data based on the second and third rows of test vector data;

[0084] S223: Merge two consecutive lines of test vector data that are repeated p times into two consecutive lines of test vector data, and assign the second-level sequencer data to the two consecutive lines of test vector data as Lp, indicating that the loop is executed p times, where

[0085] S224: The test vector data that have been merged and compressed are renumbered in sequence, where q is the number of rows of the test vector data that have been merged and compressed, and 1≤q≤m.

[0086] Specifically, with the test vector data in the first and second rows as the benchmark, the subsequent vector data is searched for pairs of test vector data identical to the test vector data in the first and second rows, and alternate rows are not allowed. If the test vector data in the third and fourth rows are different from the test vector data in the first and second rows, then with the test vector data in the second and third rows as the benchmark, the subsequent vector data is searched for pairs of test vector data identical to the test vector data in the second and third rows.

[0087] If the test vector data in rows 3 and 4 are identical to the test vector data in rows 1 and 2, respectively, then the comparison continues with the next two rows of test vector data, i.e., rows 5 and 6, and rows 1 and 2. If the test vector data in rows 5 and 6 are different from the test vector data in rows 1 and 2, then the test vector data in rows 5 and 6 is used as a reference to search for a pair of test vector data identical to the test vector data in rows 5 and 6 in the subsequent vector data.

[0088] If the test vector data in the 7th and 8th rows are different from the test vector data in the 5th and 6th rows, the test vector data in the 6th and 7th rows are used as a reference to search for paired test vector data identical to the test vector data in the 6th and 7th rows in subsequent vector data.

[0089] The test vector data that are repeated in pairs are searched in sequence and merged and compressed, and the second-level sequencer data is assigned to record the number of loop repetitions.

[0090] In some embodiments, as Figure 3 As shown, the compression method further includes the following steps:

[0091] S230: Referring to step S220, the next level of processing is performed sequentially until the t-th level of processing, wherein,

[0092] s is the number of rows of the test vector data after the t-1th level of processing.

[0093] Specifically, after executing the second level processing, the renumbered test vector data will be subjected to the third level processing, and the subsequent three consecutive lines of test vector data will be compared with the 1st to 3rd lines of test vector data in sequence based on the 1st to 3rd lines of test vector data. Referring to step S220, the test vector data repeated in consecutive groups (three lines in a group) will be searched in sequence and merged and compressed, and the third level sequencer data will be assigned to record the number of loop repetitions.

[0094] After the third level of processing is completed, the renumbered test vector data is subjected to the fourth level of processing, and the next level of processing is performed in sequence until the tth level of processing.

[0095] In some embodiments, it can generally be set that the compression of the test data is completed after the third level processing is performed.

[0096] In some embodiments, step S300: storing the compressed test vector data in the vector memory includes the following steps:

[0097] The compressed test vector data is written into the vector memory row by row, and each row of test vector data stores one storage row space in the vector. Each storage row space includes a vector data storage unit and a control data storage unit. The vector data storage unit is used to store the vector data of the corresponding row test vector data, and the control data storage unit is used to store the vector data period data and sequencer data of each level of the corresponding row test vector data.

[0098] Figure 6 A schematic diagram of the storage structure of a vector memory provided in some embodiments of the present disclosure, such as Figure 6As shown, the vector memory includes multiple storage row spaces, each of which may correspond to a row of test vector data. Each storage row space has, for example, 64 bytes.

[0099] Each storage row space, for example, includes a vector data storage unit and a control data storage unit. The vector data storage unit is used to store vector data corresponding to the row test vector data. The vector data storage unit, for example, has 7 storage units, each storage unit has 8 bytes, and each byte corresponds to the data of a pin of the chip under test. The control data storage unit is used to store the vector data cycle data and sequencer data of each level corresponding to the row test vector data. The control data storage unit, for example, has 8 bytes, of which 1 byte corresponds to the cycle data and the other 7 bytes correspond to the sequencer data of the first to seventh levels, respectively.

[0100] The following uses a specific example to introduce the specific implementation of the test data compression method in the present disclosure.

[0101] The initial test data is as follows:

[0102] Multiple initial test vector data are arranged in row order as shown below. Each initial test vector includes periodic data WFT_1, WFT_2, or WFT_3. The vector data includes input or output data corresponding to each pin of the chip under test. The pins of the chip under test include input pins and / or output pins. The input signal of the input pin is represented by 1 when it is at a high level and by 0 when it is at a low level. The output signal of the output pin is represented by H when it is at a high level and by L when it is at a low level. The vector data in the initial test vector data is a data string consisting of multiple references to the corresponding input or output levels.

[0103]

[0104] The multiple test vector data after initialization in step S120 are as follows:

[0105]

[0106] The first-level sequencer data of the initial test vector data is defined as R1, which means it is executed once. Each test vector data after initialization includes the first-level sequencer data, cycle data and vector data. In some embodiments, R1 may not be presented.

[0107] The multiple test vector data after the first-level processing in step S210 are as follows:

[0108]

[0109] R1, R2 and R3 in the first-level sequencer data represent execution 1, 2 and 3 times respectively.

[0110] The multiple test vector data after the second-level processing in step S220 are as follows:

[0111]

[0112] The L2 loop in the second level sequencer data is executed twice.

[0113] Figure 7 A structural block diagram of a test data compression device provided in some embodiments of the present disclosure, such as Figure 7 As shown, some embodiments of the present disclosure provide a test data compression device 100 , which includes an initialization module 10 , a merging and compression module 20 , and a storage module 30 .

[0114] The initialization module 10 is configured to obtain corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence;

[0115] The merging and compression module 20 is configured to merge consecutively repeated test vector data and / or test vector data groups based on comparison of multiple test vector data to obtain compressed test vector data;

[0116] The storage module 30 is configured to store the compressed test vector data in the vector memory.

[0117] Some embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer program instructions, which, when called and executed by a processor, implement the steps of the test data compression method described in any of the above embodiments.

[0118] Some embodiments of the present disclosure provide an electronic device, comprising: one or more processors and a storage device, the storage device being used to store one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors implement the compression method described in the aforementioned embodiments.

[0119] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A method for compressing test data, characterized in that: The following steps are involved: S100: Acquire corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence; S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data; S300: Storing the compressed test vector data in a vector memory.

2. The test data compression method according to claim 1, characterized in that: Step S100: Acquiring corresponding test data based on the chip to be tested and initializing the test data to obtain a plurality of test vector data arranged in sequence includes the following steps: S110: Acquire corresponding test data based on the chip under test, the test data including a plurality of initial test vector data arranged in sequence, each initial test vector data including period data and vector data, the period data indicating the execution time of the initial test vector data, and the vector data including input or output data corresponding to each pin of the chip under test; S120: Perform an initialization operation on each initial test vector data to obtain a plurality of test vector data arranged in sequence, wherein the initialization operation includes defining the first-level sequencer data of the initial test vector data as R1, indicating execution once, and each test vector data after initialization includes the first-level sequencer data, period data and vector data.

3. The test data compression method according to claim 2, characterized in that: Step S200: merging consecutively repeated test vector data and / or test vector data groups based on comparison of multiple test vector data to obtain compressed test vector data includes the following steps: S210: performing a first level of processing on the plurality of test vector data sequentially arranged after initialization, so as to merge and compress the continuously repeated test vector data in the plurality of test vector data; S220: Performing a second level of processing on the plurality of test vector data that have undergone the first level of processing, so as to merge and compress two consecutively repeated adjacent test vector data in the plurality of test vector data that have undergone the first level of processing.

4. The test data compression method according to claim 3, characterized in that: Step S210: performing a first level of processing on the plurality of test vector data sequentially arranged after initialization to merge and compress the continuously repeated test vector data in the plurality of test vector data, including the following steps: S211: Taking the first row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the first row of test vector data until the i-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and 2≤i≤n, and n is the number of rows of multiple test vector data arranged in sequence after initialization, merge the first row of test vector data to the i-1th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Ri-1, indicating that the operation is repeated i-1 times; S212: Taking the i-th row of test vector data as a reference, sequentially compare the subsequent rows of test vector data with the i-th row of test vector data until the j-th row of test vector data that is different from the first row of test vector data is found, where i is a positive integer and i+1≤j≤n, merge the i-th row of test vector data to the j-1-th row of test vector data into one row of test vector data, and modify the first-level sequencer data of the row to Rj-i, indicating that the execution is repeated j times; S213: starting with the jth row of test vector data and sequentially referring to step S212, and continuing until n rows of test vector data have been traversed; S214: The test vector data that have been merged and compressed are renumbered in sequence, where m is the number of rows of the test vector data that have been merged and compressed, and 1≤m≤n.

5. The test data compression method according to claim 3, characterized in that: Step S220: performing a second level of processing on the plurality of test vector data that have undergone the first level of processing, merging and compressing two consecutively repeated adjacent test vector data in the plurality of test vector data that have undergone the first level of processing, including the following steps: S221: Taking the 1st and 2nd rows of test vector data as references, sequentially compare the subsequent two consecutive rows of test vector data with the 1st and 2nd rows of test vector data; if the 3rd and 4th rows of test vector data are respectively the same as the 1st and 2nd rows of test vector data, then continue to compare the subsequent two rows of test vector data with the 1st and 2nd rows of test vector data until the kth and k+1th rows of test vector data that are different from the 1st and 2nd rows of test vector data are found, where k is a positive integer and 5≤k≤m-1; S222: If the third and fourth rows of test vector data are different from the first and second rows of test vector data, then refer to step S211 to compare the subsequent two consecutive rows of test vector data with the second and third rows of test vector data based on the second and third rows of test vector data; S223: Merge two consecutive lines of test vector data that are repeated p times into two consecutive lines of test vector data, and assign the second-level sequencer data to the two consecutive lines of test vector data as Lp, indicating that the loop is executed p times, where S224: The test vector data that have been merged and compressed are renumbered in sequence, where q is the number of rows of the test vector data that have been merged and compressed, and 1≤q≤m.

6. The test data compression method according to any one of claims 3 to 5, characterized in that: The compression method further comprises the following steps: S230: Referring to step S220, the next level of processing is performed sequentially until the t-th level of processing, wherein, s is the number of rows of the test vector data after the t-1th level of processing.

7. The test data compression method according to claim 6, characterized in that: Step S300: Storing the compressed test vector data in the vector memory includes the following steps: The compressed test vector data is written into the vector memory row by row, and each row of test vector data stores one storage row space in the vector. Each storage row space includes a vector data storage unit and a control data storage unit. The vector data storage unit is used to store the vector data of the corresponding row test vector data, and the control data storage unit is used to store the vector data period data and sequencer data of each level of the corresponding row test vector data.

8. A test data compression device, characterized in that: The compression device: An initialization module is configured to obtain corresponding test data based on the chip to be tested and initialize the test data to obtain a plurality of test vector data arranged in sequence; a merging and compressing module configured to merge consecutively repeated test vector data and / or test vector data groups based on comparison of a plurality of test vector data to obtain compressed test vector data; The storage module is configured to store the compressed test vector data in the vector memory.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the compression method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the one or more processors to implement the compression method according to any one of claims 1 to 7.

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