Method for realizing assembly line optimization of FPGA of LDPC decoder
By changing the update order of the check matrix layer, avoiding RAM read and write conflicts, and adopting pipeline update strategy, the problems of hardware resource occupation and decoding delay in the implementation of LDPC decoder FPGA are solved, and the system throughput and decoding performance are improved.
Patent Information
- Application Number
- CN202510545653.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-12
AI Technical Summary
In the existing LDPC decoder FPGA implementation, there is a problem of excessive hardware resource occupation or excessive decoding delay, especially when the DVB-S2 standard LDPC code is long, which affects the system throughput and efficiency.
By changing the update order of each layer of the check matrix, avoiding RAM read and write conflicts between adjacent and sub-adjacent layers, and using pipeline update strategy, optimizing the efficiency of DVB-S2 standard FPGA implementation.
It significantly reduces the probability of RAM read and write conflicts, optimizes the efficiency of DVB-S2 standard FPGA implementation, and improves the system throughput and decoding performance.
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of LDPC decoders, and in particular to a pipeline optimization method for FPGA implementation of LDPC decoders. Background Art
[0002] Channel coding refers to methods used in wireless high-speed data transmission to increase data redundancy and correct errors in order to fully utilize channel capacity and improve spectrum efficiency. LDPC (Low-Density Parity-Check) codes, due to their excellent error correction capabilities and efficient iterative decoding algorithms, are considered the most widely used error-correcting code scheme in high-speed communications. The DVB-S2 standard significantly improves data transmission efficiency and service support capabilities, achieving performance close to the Shannon limit.
[0003] FPGAs (Field-Programmable Gate Arrays) are commonly used in LDPC code applications to increase system parallelism. However, due to the complexity of the LDPC decoding algorithm, FPGA implementation is particularly complex.
[0004] To facilitate the transmission of parity check matrix node information in the minimum-sum algorithm, several current LDPC decoder architectures offer significant room for optimization. Fully parallel architectures leverage FPGA parallel processing, resulting in the fastest node update speeds. However, as LDPC code lengths increase, hardware implementation complexity increases dramatically. For DVB-S2 standard LDPC codes with lengths up to 64,800 bytes, the hardware complexity and FPGA resource usage become unacceptable. Serial architectures share a single node processing unit during parity check matrix node updates, but for most coding systems, node updates are too slow, resulting in excessive iterative decoding delays and a significant impact on system throughput. Summary of the Invention
[0005] The present invention aims to overcome the shortcomings of the prior art and provide a pipeline optimization method for FPGA implementation of an LDPC decoder. By changing the layer update order of DVB-S2, the probability of RAM (Random Access Memory) read / write conflicts is reduced, thereby optimizing the efficiency of the DVB-S2 standard FPGA implementation.
[0006] The present invention adopts the following technical solutions to achieve the above-mentioned purpose. The present invention provides a pipeline optimization method for an LDPC decoder FPGA, comprising:
[0007] S1, traverse all check matrix layers and select one layer as the starting layer;
[0008] S2. Calculate the delays of the remaining check matrix layers relative to the starting layer, and select the check matrix layer with the lowest delay relative to the starting layer as the second layer.
[0009] S3. Determine whether the selected second layer and the starting layer have the same nodes. If there are no same nodes, the delay between the second layer and the starting layer is:
[0010]
[0011] If there are the same nodes, the delay between the second layer and the starting layer is:
[0012]
[0013] In the formula, k(1) represents the starting layer number, k(2) represents the second layer number, l is the first identical conflicting node, T p is the update period, m represents the number of nodes before the conflict node l, and n represents the number of nodes after the conflict node l;
[0014] If the number of layers with the lowest delay from the starting layer is not 1, a layer is randomly selected from all the layers with the lowest delay as the second layer;
[0015] S4, select 3 to q ldpc Layer, calculate the idle time of the current layer to be determined, the starting layer and the second layer in turn, let the sequence number of the current layer to be determined be k(a), 3≤a≤q ldpc ,q ldpc Indicates the maximum number of layers of the check matrix;
[0016] S5. Determine whether the current layer has the same nodes as the starting layer and the second layer;
[0017] If the current layer and the starting layer do not have the same nodes, the current layer and the starting layer are delayed:
[0018]
[0019] If the current layer and the starting layer have the same nodes, the current layer and the starting layer will be delayed:
[0020]
[0021] If the current layer and the second layer do not have the same nodes, the delay between the current layer and the second layer is:
[0022]
[0023] If the current layer and the second layer have the same nodes, the delay between the current layer and the second layer is:
[0024]
[0025] Where m is the number of nodes before the conflict node l, n is the number of nodes after the conflict node l, and d c is the row weight of the check matrix;
[0026] The maximum idle time among the current layer, the starting layer, and the second layer is selected as the actual delay in the following way:
[0027]
[0028] The layer with the lowest latency is selected as the current layer. If the number of layers with the lowest latency compared to the previous layer is not 1, a layer is randomly selected from all the layers with the lowest latency as the current layer.
[0029] S6. After all layers are selected, the delay of each layer is added up in sequence to obtain the final total idle time of this starting layer selection, in the following manner:
[0030]
[0031] S7. Compare the total idle time of all starting layer selections, and find the starting layer selection with an idle time of 0 and the layer sequence generated by it.
[0032] The beneficial effects of the present invention are:
[0033] This invention avoids RAM read / write conflicts between adjacent and sub-adjacent layers by changing the update order of the parity check matrix. When using a pipeline to update the parity check matrix, this minimizes pipeline idle periods, minimizes decoding latency, and improves system throughput when decoding multiple frames continuously. By changing the DVB-S2 layer update order, the probability of RAM read / write conflicts is reduced, optimizing the efficiency of FPGA implementations of the DVB-S2 standard. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 This is a flow chart of the parallel strategy for DVB-S2 standard LDPC decoding provided by an embodiment of the present invention;
[0035] Figure 2 This is a flow chart of message update of an LDPC layered decoding pipeline provided by an embodiment of the present invention;
[0036] Figure 3 This is a flow chart of message update for a LDPC layered decoding pipeline without delay provided by an embodiment of the present invention;
[0037] Figure 4 This is a flow chart of message update of an LDPC layered decoding pipeline with delay provided by an embodiment of the present invention;
[0038] Figure 5 Schematic diagram of calculating idle time of LDPC layered decoding pipeline provided by an embodiment of the present invention;
[0039] Figure 6 This is a flow chart of a pipeline optimization method for implementing an LDPC decoder FPGA according to an embodiment of the present invention. DETAILED DESCRIPTION
[0040] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0041] The primary decoding method for LDPC codes in the DVB-S2 standard is the partially parallel layered min-sum algorithm. In the check node update and variable node update steps of the min-sum decoding algorithm, the nodes of the entire parity check matrix must be updated. However, in hardware implementations, using a flooding update (i.e., a fully parallel structure) reduces decoding time but requires excessive hardware resources, making it unacceptable.
[0042] If a serial update strategy is adopted, although hardware resources are less occupied, the decoding delay is too long, which will seriously affect the throughput of the decoder. Therefore, the present invention takes advantage of the fact that the DVB-S2 standard LDPC parity check matrix can perform quasi-cyclic transformations and uses a decoding scheme similar to QC-LDPC, namely a partially parallel layered minimum sum decoding scheme, and uses a partially parallel, that is, block parallel strategy to perform decoding iterative updates. The specific update process is as follows: Figure 1 As shown, the parity check matrix is divided into submatrices based on the selected degree of parallelism. The present invention has a degree of parallelism of 360. All submatrices are square, and only one submatrix is read or written per clock cycle. The submatrices in each row of the parity check matrix are called a layer. Layers are updated serially, and submatrices within each layer are also updated serially, while submatrices within each layer are updated in parallel. According to the layered minimum-sum decoding algorithm, messages are passed between layers. This update strategy can improve decoding convergence speed while maintaining acceptable hardware resources.
[0043] The present invention adopts a partially parallel layered decoding strategy, in which the updating principle of each layer is as follows: Figure 2 As shown. The pipeline update process of each layer in the figure is roughly divided into three parts. The old part represents reading the RAM information updated last time, the new part represents writing the RAM information after the current update is completed, and the middle part is the clock required for the update calculation. The row weight of the DVB-S2 check matrix is 4, so the present invention takes the row weight equal to 4 as an example. Each clock reads a message from the RAM. The bit width of the message is determined by the input soft information bit width and the specific decoder architecture. It takes 4 cycles to read the message of one layer. pAfter a cycle of update calculation, it takes another four cycles to write to RAM, thus completing the message update of one layer. According to this structure, all layers of the check matrix are updated in sequence, and one iteration of LDPC decoding can be achieved.
[0044] In order to reduce the iterative decoding delay and improve the system throughput, a pipeline update structure is adopted in the actual implementation process. The update process of two adjacent layers is as follows: Figure 3 As shown, Figure 3 In the figure, orange represents the update process of the previous layer, green represents the update process of the next layer, and the gray clock represents that the two adjacent layers contain the same variable nodes. In this case, Figure 3 There is a problem with the delay-free pipeline update method shown in . The variable node marked in gray reads the information in the RAM before the previous layer has completed the update and the update result has not been written. Obviously, the data in the RAM at this time is not the latest posterior probability information. This delay-free pipeline update method will inevitably cause conflicts in information reading and writing. Although it reduces the decoding delay, it will significantly reduce the LDPC decoding performance, and the decoding performance curve will not meet the DVB-S2 standard results. To solve this problem, it is necessary to introduce pipeline delay, such as Figure 4 The delayed pipeline structure in Figure 1 is shown. Idle time is inserted into the pipeline to stagger repeated nodes between adjacent layers. This ensures that the node information for the next layer is read from RAM only after the previous layer's node is updated and written to RAM. This ensures the correctness of the pipeline's iterative updates and maintains lossless LDPC decoding performance, meeting the DVB-S2 standard bit error rate performance curve.
[0045] Aiming at the LDPC parity check matrix of the DVB-S2 standard, the present invention proposes a pipeline idle time optimization algorithm. For the LDPC decoder of the DVB-S2 standard, the algorithm can completely eliminate the decoding pipeline idle time, significantly reduce the decoding delay, and realize multi-frame continuous decoding. The algorithm also has a certain inspiration for the LDPC decoding schemes of other standards besides DVB-S2.
[0046] First of all, this optimization algorithm is based on the following two principles:
[0047] (1) For an LDPC check matrix, rearranging the rows of the check matrix does not change the code defined by the matrix. The rows of the check matrix can be changed arbitrarily before decoding.
[0048] (2) For the LDPC check matrix, rearranging the columns of the check matrix will not change the error correction performance of the code, but will only lead to an appropriate rearrangement of the codeword sequence.
[0049] Therefore, although the compressed parity check matrix of the DVB-S2 standard does not conform to the QC-LDPC quasi-cyclic structure in its decompressed form, it can be converted to a quasi-cyclic structure by permuting the parity check matrix's rows and columns. This permutation only partially changes the order of the check bits in the parity check matrix. This parity check matrix, converted to a QC-LDPC quasi-cyclic structure, can be decoded using an FPGA architecture using a partially parallel hierarchical min-sum algorithm.
[0050] Based on the above principles, the present invention further proposes an optimization method for eliminating pipeline idle time for the DVB-S2 standard and provides an algorithm for calculating the update order for non-idle layers. By changing the update order of each parity check matrix layer, RAM read / write conflicts between adjacent and sub-adjacent layers are avoided. When the parity check matrix is updated using a pipeline, the idle period is minimized, minimizing decoding latency and improving system throughput when decoding multiple frames continuously.
[0051] After a comprehensive analysis of the FPGA development board's hardware resources and decoding efficiency, a partially parallel minimum-sum algorithm was ultimately chosen for decoding the DVB-S2 standard's LDPC codes. However, the implementation of this partially parallel minimum-sum algorithm involves layered updates of variable and check nodes. In a layered update pipeline structure, if two adjacent layers are connected to the same variable node, read-write conflicts may occur during RAM reads and writes. This prevents the next layer from reading the latest node information, resulting in reduced decoding performance. This paper proposes a pipeline optimization method for FPGA implementation of an LDPC decoder. This method is optimized for the DVB-S2 standard's LDPC codes. By changing the DVB-S2 layer update order, the probability of read-write conflicts can be reduced, and RAM read-write conflicts can even be completely eliminated, significantly improving the efficiency of the DVB-S2 standard's FPGA implementation.
[0052] Specifically, such as Figure 5 As shown, taking the DVB-S2 standard LDPC code check matrix with code rate 1 / 2 as an example, the number of layers of the DVB-S2 LDPC check matrix with code rate 1 / 2 is q ldpc , each line is repeated c The same is 4, the pipeline read and write RAM cycle of each layer is 4, and the update cycle is T p is 4, m is the number of nodes before the conflict node l, and n is the number of nodes after the conflict node l.
[0053] like Figure 6 As shown, the LDPC decoder FPGA implementation pipeline optimization method provided by the present invention is as follows:
[0054] S1, traverse all check matrix layers and select one layer as the starting layer;
[0055] S2. Calculate the idle time, i.e., delay, of the remaining check matrix layers relative to the starting layer, and select the check matrix layer with the lowest delay relative to the starting layer as the second layer.
[0056] S3. Determine whether the selected second layer and the starting layer have the same nodes. If there are no same nodes, the delay between the second layer and the starting layer is:
[0057]
[0058] If there are the same nodes, the delay between the second layer and the starting layer is:
[0059]
[0060] In the formula, k(1) represents the starting layer number, k(2) represents the second layer number, l is the first identical conflicting node, T p For the update cycle;
[0061] If the number of layers with the lowest delay from the starting layer is not 1, a layer is randomly selected from all the layers with the lowest delay as the second layer;
[0062] S4, select 3 to q ldpc Layer, calculate the idle time of the current layer to be determined, the starting layer and the second layer in turn, let the sequence number of the current layer to be determined be k(a), 3≤a≤q ldpc ,q ldpc Indicates the maximum number of layers of the check matrix;
[0063] S5. Determine whether the current layer has the same nodes as the starting layer and the second layer;
[0064] If the current layer and the starting layer do not have the same nodes, the current layer and the starting layer are delayed:
[0065]
[0066] If the current layer and the starting layer have the same nodes, the current layer and the starting layer will be delayed:
[0067]
[0068] If the current layer and the second layer do not have the same nodes, the delay between the current layer and the second layer is:
[0069]
[0070] If the current layer and the second layer have the same nodes, the delay between the current layer and the second layer is:
[0071]
[0072] Where, d cis the row weight of the check matrix;
[0073] The maximum idle time among the current layer, the starting layer, and the second layer is selected as the actual delay in the following way:
[0074]
[0075] The layer with the lowest latency is selected as the current layer. If the number of layers with the lowest latency compared to the previous layer is not 1, a layer is randomly selected from all the layers with the lowest latency as the current layer.
[0076] S6. After all layers are selected, the delay of each layer is added up in sequence to obtain the final total idle time of this starting layer selection, in the following manner:
[0077]
[0078] Where D(i) represents the total idle time, i represents the starting layer number, and D j Indicates the delay between the starting layer and the second layer;
[0079] S7. Compare the total idle time of all starting layer selections, and find the starting layer selection with an idle time of 0 and the layer sequence generated by it.
[0080] Targeting the DVB-S2 standard, the method described above specifically calculates the layer update sequence that minimizes idle periods. By changing the update order of each parity check matrix layer, RAM read / write conflicts between adjacent and sub-adjacent layers are avoided. When using a pipeline to update the parity check matrix, the pipeline idle period is minimized, minimizing decoding latency and improving system throughput when decoding multiple frames continuously. By changing the DVB-S2 layer update sequence, the probability of RAM read / write conflicts is reduced, optimizing the efficiency of FPGA implementations of the DVB-S2 standard.
[0081] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.
Claims
1. A pipeline optimization method for LDPC decoder FPGA implementation, characterized in that: include: S1, traverse all check matrix layers and select one layer as the starting layer; S2. Calculate the delays of the remaining check matrix layers relative to the starting layer, and select the check matrix layer with the lowest delay relative to the starting layer as the second layer. S3. Determine whether the selected second layer and the starting layer have the same nodes. If there are no same nodes, the delay between the second layer and the starting layer is 0. If there are same nodes, calculate the delay between the second layer and the starting layer. If the number of layers with the lowest delay from the starting layer is not 1, a layer is randomly selected from all the layers with the lowest delay as the second layer.
2. The LDPC decoder FPGA pipeline optimization method according to claim 1, characterized in that: The delay between the second layer and the starting layer is calculated as follows: In the formula, k(1) represents the starting layer number, k(2) represents the second layer number, l is the first identical conflicting node, T p is the update period, m is the number of nodes before the conflict node l, n is the number of nodes after the conflict node l, Indicates the delay between the second layer and the starting layer.
3. The LDPC decoder FPGA implementation pipeline optimization method according to claim 1, characterized in that: The optimization method also includes: S4, select 3 to q ldpc Layer, calculate the idle time of the current layer to be determined, the starting layer and the second layer in turn, let the sequence number of the current layer to be determined be k(a), 3≤a≤q ldpc ,q ldpc Indicates the maximum number of layers of the check matrix; S5. Determine whether the current layer has the same nodes as the starting layer and the second layer; If the current layer and the starting layer have no common nodes, the delay between the current layer and the starting layer is 0; If the current layer and the starting layer have the same nodes, calculate the delay between the current layer and the starting layer: If the current layer and the second layer have no common nodes, the delay between the current layer and the second layer is 0; If the current layer and the second layer have the same nodes, calculate the delay between the current layer and the second layer; Select the maximum value among the idle time of the current layer, the starting layer, and the second layer as the actual delay; The layer with the lowest delay is selected as the current layer. If the number of layers with the lowest delay compared to the previous layer is not 1, a layer is randomly selected from all the layers with the lowest delay as the current layer.
4. The LDPC decoder FPGA pipeline optimization method according to claim 3, characterized in that: The delay between the current layer and the starting layer is calculated as follows: Where, Indicates the delay between the current layer and the starting layer.
5. The LDPC decoder FPGA pipeline optimization method according to claim 4, characterized in that: The delay between the current layer and the second layer is calculated as follows: Where, Indicates the delay between the current layer and the second layer, d c Represents the row weight of the check matrix.
6. The LDPC decoder FPGA implementation pipeline optimization method according to claim 5, characterized in that: The actual delay is calculated as follows: Where D k(α) Indicates the actual delay.
7. The LDPC decoder FPGA implementation pipeline optimization method according to claim 1, characterized in that: The optimization method also includes: S6. After all layers are selected, the delay of each layer is added up in sequence to obtain the final total idle time of this starting layer selection, in the following manner: Where D(i) represents the total idle time, i represents the starting layer number, and D j Indicates the delay between the starting layer and the second layer; S7. Compare the total idle time of all starting layer selections, and find the starting layer selection with an idle time of 0 and the layer sequence generated by it.