A high-voltage radiation-resistant silicon carbide MOSFET structure and a method for manufacturing the same

Abstract

This invention discloses a high-voltage radiation-resistant silicon carbide MOSFET structure and its fabrication method, belonging to the field of semiconductor device technology, comprising: a drain metal; and SiCP located on the drain metal. + / N + Network; located in P + / N + N on the Internet ‑ Drift region; located in N ‑ The N-type carrier storage layer on the drift region; the MOS structure, interlayer dielectric, and source metal layer located on the N-type carrier storage layer; the SiCP + / N + In the network, P + Network than N + The network is deeper; the N-type carrier storage layer contains multiple periodically repeating back-to-back bench-shaped P-wells, and the P-well region contains N... + Trap region and P1 + Region; source metal and P1 + District, N + The well regions are interconnected. This invention systematically solves the reliability problem of traditional silicon carbide MOSFETs under high-voltage irradiation environments through structural innovation and synergistic process optimization, providing a technical solution for the design of power devices in extreme environments.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a high-voltage anti-radiation silicon carbide MOSFET structure and a preparation method thereof. BACKGROUND

[0002] In aviation, aerospace and military equipment, power semiconductor devices are mainly used in power supply and distribution subsystems, which are core components. Power semiconductor devices using Si material have gradually reached their theoretical limits, and it is difficult to further realize high frequency, high power density and miniaturization of power converters at the current research level. Silicon carbide (SiC) power devices have advantages such as high breakdown field strength and high thermal conductivity, and are widely used in extreme environments such as high voltage, high temperature and strong radiation. However, in the irradiation environment (such as space particle radiation, nuclear radiation, etc.), traditional silicon carbide MOSFETs face the following technical challenges:

[0003] High-energy particle bombardment can cause transient charge deposition inside the device, resulting in backside avalanche breakdown of the N - / N + junction interface, or causing gate dielectric layer breakdown (single event gate punch-through), causing device failure. The holes generated by irradiation are difficult to extract quickly and are easy to accumulate near the gate to form a strong electric field, inducing avalanche multiplication effect, further reducing the anti-radiation capability of the device. The existing anti-radiation structure usually needs complex process adjustment, which is not compatible with the mainstream preparation process, resulting in high cost and low yield. SUMMARY

[0004] The purpose of the present application is to provide a high-voltage anti-radiation silicon carbide MOSFET structure and a preparation method thereof to solve the above problems.

[0005] To achieve the above purpose, the present application provides a high-voltage anti-radiation silicon carbide MOSFET structure, comprising:

[0006] a drain metal;

[0007] a SiC P + / N + network located on the drain metal;

[0008] an N + / N + network located on the P - drift region;

[0009] an N-type carrier storage layer located on the N - drift region;

[0010] a MOS structure, an interlayer dielectric and a source metal layer located on the N-type carrier storage layer;

[0011] The SiC P + / N + The P + The network is deeper than the N + The network is deeper than the N - The drift region and the N + The N - / N + The junction forms a shielding protection to inhibit the backside avalanche breakdown caused by single particle irradiation.

[0012] The N-type carrier storage layer is provided with a plurality of periodically repeated back-to-back bench type P-wells, and the P-well region is provided with N + The well region and the P1 + The N + The channel region is formed between the N-well region boundary and the P-well boundary.

[0013] The MOS structure includes polycrystalline silicon, and a thin layer of silicon dioxide is provided between the polycrystalline silicon and the silicon carbide semiconductor as a gate dielectric, and the polycrystalline silicon, the gate dielectric and the silicon carbide semiconductor together form a MOS structure.

[0014] The channel region is located below the polycrystalline silicon of the MOS structure.

[0015] The source metal is connected to the P1 + region, the N + well region.

[0016] An interlayer medium is provided between the source metal and the MOS structure.

[0017] The adjacent back-to-back bench type P-wells form a JFET structure with a lower width and an upper width to increase the area of the hole extraction path in an instant of single particle irradiation.

[0018] Preferably, in the high-voltage anti-radiation silicon carbide MOSFET structure, a relatively thin P2 + region is provided on the surface of the JFET structure, the P2 + region in each sub-cell is connected to the P2 + electrode region through a P2 + main channel and is short-circuited with the source metal, and the grounded P2 + region is used to form a shielding protection for the gate dielectric to avoid single particle gate penetration, and at the same time, as an additional hole extraction channel, to improve the single particle irradiation resistance of the device.

[0019] A preparation method of the high-voltage anti-radiation silicon carbide MOSFET structure, the preparation method is compatible with the existing mainstream process, by adding a mask to define the P2 + region pattern, and adding one step of self-aligned ion implantation process and one step of P2 +The zone ion implantation process adds a mask to define the back P+ network and a two-step back ion implantation process, which specifically comprises:

[0020] S1. A mask is used to define the bottom pattern of the back-to-back bench type P well on the surface of the silicon carbide MOSFET epitaxial wafer, and the high-energy ion implantation is used to form the bottom of the P well;

[0021] S2. Polysilicon is deposited and etched to form the self-aligned mask pattern of the back of the back-to-back bench type P well, and ion implantation is used to form the "chair back" morphology;

[0022] S3. Continue to deposit polysilicon and etch to form the self-aligned mask pattern of the N + well region, and ion implantation is used to form the N + well region and the channel region;

[0023] S4. A mask is used to define the P2 + zone pattern, and ion implantation is used to form the P2 + zone;

[0024] S5. After completing the front process, the wafer is thinned and the substrate is removed, and N ions are implanted on the back to form N + ;

[0025] S6. A mask is used to define the back P + network, and SiC is etched and ion implanted to form the back P + network, and the remaining processes are consistent with mainstream processes.

[0026] Preferably, in the preparation method of the high-voltage radiation-resistant silicon carbide MOSFET structure, the self-aligned mask pattern is formed by LPCVD deposition of polysilicon and anisotropic etching in steps S2 and S3.

[0027] Preferably, in the preparation method of the high-voltage radiation-resistant silicon carbide MOSFET structure, the two-step back ion implantation process is used to form the back N + and P + networks, respectively.

[0028] Preferably, in the preparation method of the high-voltage radiation-resistant silicon carbide MOSFET structure, the back-to-back bench type P well is formed by two ion implantation processes to form the bottom and "chair back" structure.

[0029] Therefore, by using the high-voltage radiation-resistant silicon carbide MOSFET structure and its preparation method, the following beneficial effects are obtained: the P + network is deeper than the N + network, and the N - drift region and the N + network interface form a charge shielding layer, which weakens the N- / N + The electric field reconstruction and enhancement of the junction effectively suppresses the occurrence of backside avalanche breakdown. The adjacent P-well forms a JFET structure with a narrow lower part and a wide upper part, expands the extraction path area of the hole at the moment of single particle irradiation, shortens the charge discharge time, and reduces the electric field distortion caused by charge accumulation. The P2 + region forms a low-potential shielding layer on the surface of the JFET structure to avoid single particle gate penetration. The P2 + region is short-circuited with the source metal, providing an additional low-resistance path for the holes generated by irradiation, significantly improving the charge extraction efficiency and suppressing the single particle effect caused by abnormal charge accumulation. The channel region is located below the polysilicon, combined with the gate dielectric (silicon dioxide layer) and the polysilicon gate, forming a high-efficiency carrier regulation channel, which maintains a low on-resistance under high voltage while improving the stability of carrier transmission in the irradiation environment. The preparation method only needs to add 2 mask plates, 1 step of self-aligned ion implantation, 1 step of P2 + region implantation and 2 steps of backside implantation process, which is highly compatible with the existing mainstream SiC MOSFET process, without the need for large-scale adjustment of the production line, reducing the process complexity and manufacturing cost. Through multiple shielding and charge extraction mechanisms, the single particle effect threshold of the device in a strong irradiation environment is significantly improved, and it can withstand higher dose of particle bombardment while maintaining normal operation. N - The design of the drift region and the N-type carrier storage layer maintains high breakdown voltage while reducing conduction loss, suitable for high-voltage power device scenarios. Through structural innovation and process optimization, the reliability problem of traditional silicon carbide MOSFET in high-voltage irradiation environment is systematically solved, providing an efficient and low-cost technical solution for the design of power devices in extreme environments.

[0030] The technical solutions of the present application will be further described in detail below through the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0031] Fig. 1 is a schematic diagram of the overall structure of a high-voltage anti-radiation silicon carbide MOSFET structure of the present application;

[0032] Fig. 2 is a schematic diagram of the longitudinal cross-sectional structure of a high-voltage anti-radiation silicon carbide MOSFET structure of the present application;

[0033] Fig. 3 is a schematic diagram of the transverse cross-sectional structure of a high-voltage anti-radiation silicon carbide MOSFET structure of the present application. DETAILED DESCRIPTION

[0034] For better understanding the above technical solutions, the above technical solutions will be explained in detail below by combining with the drawings in the specification and specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0035] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. "Multiple" generally includes at least two.

[0036] It should also be noted that the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that the products or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such products or devices. Without more limitations, the element defined by the sentence "including a" does not exclude the presence of other identical elements in the product or device including the element.

[0037] Embodiment 1

[0038] As Figs. 1-3 shown, a high-voltage radiation-resistant silicon carbide MOSFET structure is provided, comprising: a drain metal 1; a SiC P + / N + network 2 on the P + / N + network; an N - drift region 3; an N-type carrier storage layer 4 on the N - drift region 3; a MOS structure 5, an interlayer dielectric 6 and a source metal layer 7 on the N-type carrier storage layer 4;

[0039] Wherein, in the SiC P + / N + network, the P + network is deeper than the N + network, for shielding protection against backside avalanche breakdown caused by single particle irradiation; the N - network interface of the N + drift region 3 and the N - / N + junction forms a shielding protection to inhibit backside avalanche breakdown caused by single particle irradiation; a plurality of periodically repeated back-to-back bench type P traps 41 are provided in the N-type carrier storage layer 4, and N +The well region 42 and P1 + The N + The channel region 44 is formed between the well region 42 boundary and the P well boundary; the MOS structure 5 comprises a polysilicon 51, and a thin layer of silicon dioxide is arranged between the polysilicon 51 and the silicon carbide semiconductor as a gate dielectric, and the polysilicon 51, the gate dielectric, and the silicon carbide semiconductor together form the MOS structure 5; the channel region 44 is located below the polysilicon 51 of the MOS structure 5; the source metal 7 is connected to the P1 + The N + The well region 42; an interlayer dielectric 6 is arranged between the source metal 7 and the MOS structure 5; the adjacent back-to-back plate bench type P well 41 forms a JFET structure with a lower width and an upper width, so as to increase the area of the hole extraction path in the single particle irradiation moment.

[0040] Specifically, the JFET structure surface is provided with a relatively thin P2 + The region 45, the P2 + The region 45 in each sub-cell is connected through the P2 + The main road is connected to the P2 + The electrode region and the source metal 7 are short-circuited, and the P2 + The region 45 is used for shielding protection of the gate dielectric, avoiding single particle gate penetration phenomenon, and simultaneously serving as an additional hole extraction channel to improve the single particle irradiation resistance of the device.

[0041] The embodiment illustrates the core structure of the high-voltage anti-radiation silicon carbide MOSFET through the combination of specific structures and functional modules, and highlights the synergistic effect of each layer structure in the anti-radiation scene. + The network deeper structure is in the N - The drift region 3 and the N + The network interface forms a charge shielding layer, when the high-energy particle irradiation causes the N - / N + The junction generates a transient current, the P + The network weakens the interface electric field through the electric field shielding, avoids the backside avalanche breakdown caused by the electric field reconstruction and enhancement, and improves the single particle irradiation resistance of the device in the irradiation environment. The lower width and upper width JFET structure formed by the adjacent P well expands the lateral extraction path area of the hole in the single particle irradiation moment (the path width gradually narrows from top to bottom, forming a funnel-like diffusion channel), shortens the charge discharge time, reduces the abnormal rise of the drift region electric field caused by the charge accumulation, and suppresses the single particle effect. The P2 + The region 45 forms a potential barrier on the JFET structure surface, suppresses the aggregation of a large number of holes to form a strong electric field in the gate dielectric (silicon dioxide layer) and further cause the gate dielectric to break down, reduces the probability of single particle gate penetration, and prolongs the gate life. P2 +The zone 45 is shorted with the source metal 7 to form a low resistance path, providing a "second discharge path" for the irradiation generated holes, compared with the traditional structure which only relies on the single channel of the source metal, the charge extraction efficiency is improved, and the peak value of the body electric field is effectively reduced. The channel zone is accurately located below the polysilicon gate, and the efficient opening and closing of the carrier (electron) is realized through the electric field regulation of the gate dielectric (silicon dioxide layer), the low on-resistance is maintained under high voltage working condition, and the channel conductance degradation caused by irradiation is avoided.

[0042] Embodiment 2

[0043] A preparation method of a high-voltage anti-radiation silicon carbide MOSFET structure is provided, which is compatible with the existing mainstream process. By adding a mask to define the P2 + zone pattern, and adding a self-aligned ion implantation process and a P2 + ion implantation process, a back P + network and a two-step back ion implantation process are realized, specifically including:

[0044] S1, using a mask to define the back-to-back bench type P well bottom pattern 41 on the surface of the silicon carbide MOSFET epitaxial wafer, and forming the P well bottom by high-energy ion implantation;

[0045] S2, depositing polysilicon and etching to form a self-aligned mask pattern of the back-to-back bench type P well "chair back", and forming the "chair back" morphology by ion implantation;

[0046] S3, continuing to deposit polysilicon and etch to form a self-aligned mask pattern of the N + well region 42, and forming the N + well region 42 and the channel region 44 by ion implantation;

[0047] S4, using a mask to define the P2 + zone 45 pattern, and forming the P2 + zone 45 by ion implantation;

[0048] S5, after completing the front process, thinning the wafer and removing the substrate, and implanting N ions on the back to form N + ;

[0049] S6, using a mask to define the back P+ network, etching SiC and ion implantation to form the back P+ network, and the remaining process is consistent with the mainstream process.

[0050] Specifically, in steps S2 and S3, the self-aligned mask pattern is formed by LPCVD deposition of polysilicon and anisotropic etching.

[0051] The two-step back ion implantation process is used to form the back N + and P +Network.

[0052] The back-to-back plate bench type P well 41 is formed by twice ion implantation processes to form a bottom and a "chair back" structure.

[0053] The embodiment explicitly compatible with the existing mainstream process preparation process, through the limitation of key process steps, solves the process adaptability problem of the anti-radiation structure in the engineering production. Only 2 masks and 3 additional ion implantation processes are added, without reconfiguring the existing production line equipment or introducing special processes, and the compatibility with the commercial SiC MOSFET process is more than 90%, reducing the research and manufacturing cost. In step S2, the P well "chair back" structure is formed by polysilicon mask self-alignment, avoiding the overlay error of the traditional photolithography process, ensuring the symmetry of the back-to-back P well, and improving the consistency of the JFET structure. In step S3, the N + The self-aligned etching of the well region makes the channel length deviate from the design value by less than 5%, ensuring the stability of the threshold voltage of the device and reducing the yield loss caused by process fluctuation. The first back N ion implantation forms an N + layer, which is an ohmic contact layer of the drain metal, reducing the contact resistance; the second step defines a P + network through a mask, and a deep junction P + region is formed by high-energy Al ion implantation, accurately controlling the depth difference of the P + / N + network, ensuring the effectiveness of the shielding effect. Wafer thinning exposes the back surface after removing the substrate, facilitating the back ion implantation and metallization process, while maintaining the mechanical strength and heat dissipation performance of the device, meeting the thermal management requirements in high-voltage scenarios.

[0054] Therefore, the high-voltage anti-radiation silicon carbide MOSFET structure and its preparation method have the following beneficial effects: P + The network depth is greater than the N + network, and the N - drift region and the N + network interface forms a charge shielding layer, weakening the electric field reconstruction and enhancement of the N - / N + junction under single particle irradiation, effectively inhibiting the occurrence of back avalanche breakdown. The adjacent P well forms a JFET structure with a narrow lower part and a wide upper part, which expands the extraction path area of the hole under single particle irradiation, shortens the charge discharge time, and reduces the electric field distortion caused by charge accumulation. The P2 + region forms a low potential shielding layer on the surface of the JFET structure, inhibiting the formation of a strong electric field in the gate dielectric (silicon dioxide layer) due to the accumulation of a large number of holes, and avoiding single particle gate wear. P2 +The zone is short-circuited with a source metal, which provides an additional low-resistance path for the holes generated by irradiation, significantly improves the charge extraction efficiency, and suppresses the single event effect formed by abnormal aggregation of charges. The channel zone is located below the polysilicon, combined with the gate dielectric (silicon dioxide layer) and the polysilicon gate, to form a high-efficiency carrier regulation channel, which maintains a low on-resistance under high voltage while improving the stability of carrier transmission in an irradiation environment. The preparation method only needs to add 2 mask plates, 1 step of self-aligned ion implantation, 1 step of P2 + zone implantation and 2 steps of backside implantation process, which is highly compatible with the existing mainstream SiC MOSFET process, without the need for large-scale adjustment of the production line, reducing the process complexity and manufacturing cost. Through multiple shielding and charge extraction mechanisms, the single event effect threshold of the device in a strong irradiation environment is significantly improved, and the device can withstand higher doses of particle bombardment while maintaining normal operation. - The design of the drift zone and the N-type carrier storage layer maintains a high breakdown voltage while reducing the on-resistance loss, which is suitable for high-voltage power device scenarios. Through structural innovation and process optimization, the present application systematically solves the reliability problem of traditional silicon carbide MOSFETs in a high-voltage irradiation environment, providing an efficient and low-cost technical solution for the design of power devices in extreme environments.

[0055] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application and not to limit it, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand: it can still modify or equivalently replace the technical solutions of the present application, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A high voltage radiation hard silicon carbide MOSFET structure, characterized by, Comprise: Drain metal; SiC P located on the drain metal + / N + network; located at the P + / N + N - drift region N-type carrier storage layer on the drift region - N-type carrier storage layer on the drift region MOS structure, interlayer dielectric and source metal layer on the N-type carrier storage layer; Wherein, the SiC P + / N + Network, P + Network than N + Network is deeper, for N - Drift region and N + Network interface N - / N + The junction forms a shield protection, inhibiting the backside avalanche breakdown caused by single particle irradiation; The N-type carrier storage layer is provided with a plurality of periodically repeated back-to-back bench type P-wells, the P-well is provided with N + well region and P1 + region, the N + well region and the P-well boundary form a channel region; The MOS structure comprises polysilicon, thin layer of silicon dioxide as gate dielectric between polysilicon and silicon carbide semiconductor, and the polysilicon, gate dielectric and silicon carbide semiconductor together form MOS structure; The channel region is below the polysilicon of the MOS structure; The source metal layer is connected with the P1 + region, N + well region The source metal layer and the MOS structure are provided with interlayer dielectric therebetween; Adjacent back-to-back bench-type P-well forms lower narrow and upper wide JFET structure to increase the area of hole extraction path in single particle irradiation moment.

2. The high voltage radiation resistant silicon carbide MOSFET structure of claim 1, wherein, The JFET structure surface is provided with a relatively thin P2 + region, the P2 + region in each sub-cell is connected to the P2 + main road through P2 + electrode region and is short-circuited with the source metal layer, the grounded P2 + region is used for shielding protection to the gate medium to avoid the single particle gate penetration phenomenon, and simultaneously serves as an additional hole extraction channel to improve the single particle irradiation resistance of the device.

3. A method of fabricating a high-voltage radiation-hardened silicon carbide MOSFET structure as claimed in any one of claims 1-2, characterized in that, The preparation method is compatible with the existing mainstream process, a mask plate is added to define P2 + region pattern, and a self-aligned ion implantation process and a P2 + region ion implantation process, a mask plate is added to define the back P+ network, and a two-step back ion implantation process is added, specifically including: S1, define the bottom pattern of the back-to-back bench-type P-well on the surface of the silicon carbide MOSFET epitaxial wafer by mask, and form the bottom of the P-well by high-energy ion implantation; S2, deposit polysilicon and etch to form the self-aligned mask pattern of the back-to-back bench-type P-well "backrest", and form the "backrest" morphology by ion implantation; S3, continue to deposit polysilicon and etch to form N + Self-aligned mask pattern for well region, formed by ion implantation + Well region and channel region; S4, define P2 using a mask + region, formed by ion implantation P2 + region; S5, after the front side process is completed, the wafer is thinned and the substrate is removed, N ions are implanted on the back side to form N + ; S6, using mask three define back P + Network, etching SiC and ion implantation to form back P + Network, the rest of the process is consistent with mainstream process.

4. The method of claim 3, wherein the high-voltage radiation-hardened silicon carbide MOSFET structure is formed by the steps of: In steps S2 and S3, the self-aligned mask pattern is formed by depositing polysilicon by LPCVD and anisotropic etching.

5. The method of claim 3, wherein the high-voltage radiation-hardened silicon carbide MOSFET structure is formed by the steps of: The two-step backside ion implantation process is used to form backside N + and P + networks, respectively.

6. The method of fabricating a high voltage radiation hard silicon carbide MOSFET structure of claim 3, wherein, The back-to-back bench-type P-well forms the bottom and "backrest" structure by two ion implantation processes.

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