A super junction metal oxide semiconductor field effect transistor and a manufacturing method thereof

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a super-junction metal oxide semiconductor field effect transistor which is composed of a drain, a semiconductor epitaxial layer, a source and a gate, wherein the semiconductor epitaxial layer specifically comprises two P well layers, two P+ layers, two N well layers, an N substrate layer and an N drift layer, the inside of the N drift layer is formed with a beam waist N-layer through ion implantation; the beam waist N-layer is composed of an upper half area and a lower half area, wherein the cross-section profile of the beam waist N-layer is in the shape of thick at the upper and lower ends and thin in the middle. The gradient doped N-layer with the beam waist shape in the cross-section is formed in the inside of the N drift layer, the electric field distribution is optimized, the longitudinal electric field support capability is enhanced in the middle thin and narrow area, the breakdown voltage is improved, the lateral conduction path is expanded in the thick and large area at the two ends, the specific on-resistance is significantly reduced, and thus high voltage resistance and low on-loss are simultaneously realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a super junction metal oxide semiconductor field effect transistor and a manufacturing method thereof. BACKGROUND

[0002] In the prior art super junction MOSFET, the traditional planar or columnar doping structure is limited by the uneven electric field distribution, and there is an inherent contradiction between the on-resistance and the withstand voltage performance. At the same time, the electric field concentration at the top of the drift region easily causes local breakdown, the resistance of the longitudinal conduction path at the bottom is high, and the charge imbalance also causes switch oscillation and dynamic stability to decrease, which restricts the reliability of the device in high-voltage application scenarios.

[0003] The prior art discloses a super junction metal oxide semiconductor field effect transistor structure (CN202434527U), which comprises a semiconductor base layer, a plurality of source semiconductor grooves buried in the semiconductor base layer, a base layer and a groove formed at the upper end and the lower end of each source semiconductor groove, a first connecting layer and a second connecting layer formed on the top surface of the base layer, at least one additional doping layer combined around each source semiconductor groove to form a super junction, and at least one gate connected between the top end of the semiconductor base layer and the base layer, the first connecting layer and the base layer of each source semiconductor groove. The present application solves the three core problems of the super junction MOSFET in the comparative document (CN202434527U): the contradiction between the breakdown voltage and the on-resistance caused by the uneven electric field distribution of the traditional planar / columnar doping structure; the local breakdown risk caused by the electric field concentration at the top of the drift region; and the dynamic oscillation and the high resistance of the longitudinal conduction path caused by the charge imbalance during the switching process. SUMMARY

[0004] The present application provides a super junction metal oxide semiconductor field effect transistor and a manufacturing method thereof to solve the existing technical problems, and solves the problem of dynamic oscillation and high resistance of the longitudinal conduction path caused by the charge imbalance during the switching process.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a super junction metal oxide semiconductor field effect transistor is composed of a drain, a semiconductor epitaxial layer, a source and a gate, wherein the semiconductor epitaxial layer specifically includes two P well layers, two P+ layers, two N well layers, an N substrate layer and an N drift layer, and the inside of the N drift layer is formed with a beam waist N- layer by ion implantation.

[0006] The beam waist N- layer is composed of an upper half region and a lower half region, and the cross-sectional profile of the beam waist N- layer is in the shape of thick at both ends and thin in the middle.

[0007] Further, the top of the upper half area of the beam-waisted N-layer is formed with a confinement P-layer by ion implantation, which is located between two P-well layers.

[0008] Further, the top of the upper half area of the beam-waisted N-layer is provided with a high-resistance medium, which is located between two P-well layers and is in ohmic contact with the gate.

[0009] Further, the lower half area of the beam-waisted N-layer is provided with two groups of high-doped N+ layers, each of which is in contact with the N-substrate layer.

[0010] Further, the left and right sides of each group of high-doped N+ layers are provided with side P-block layers, which are in contact with the high-doped N+ layers.

[0011] Further, the upper half area of the beam-waisted N-layer is also a heavily doped upper region.

[0012] Further, the upper half area of the beam-waisted N-layer is formed with a confinement N-layer by ion implantation, which has a doping concentration of 0.4-0.7 times that of the beam-waisted N-layer.

[0013] Further, the lower half area of the beam-waisted N-layer is formed with a suppression P-layer by ion implantation, which is horizontally aligned with the confinement N-layer and is in contact with the N-substrate layer.

[0014] A manufacturing method of a super-junction metal-oxide-semiconductor field-effect transistor, comprising:

[0015] S1, growing a low-doped N-drift layer on the surface of an N-substrate layer by epitaxy;

[0016] S2, etching a beam-waisted groove with a narrow middle and wide upper and lower portions in the middle area of the N-drift layer by a multi-step mask etching process;

[0017] S3, forming a beam-waisted N-layer with a gradient change in doping concentration in the groove by epitaxial filling or inclined ion implantation process, ensuring that its cross section is thick at both ends and thin in the middle;

[0018] S4, injecting a confinement N-layer in the upper half area of the beam-waisted N-layer, controlling its doping concentration to be 0.4-0.7 times the background concentration of the beam-waisted N-layer;

[0019] S5, injecting a suppression P-layer in the corresponding position of the lower half area of the beam-waisted N-layer, so that it is horizontally aligned with the confinement N-layer and in contact with the N-substrate;

[0020] S6, forming symmetrical P-well layers, N-well layers and P+ layers by photolithography and ion implantation;

[0021] S7, depositing a gate dielectric layer and forming a gate structure forming a source electrode on the front surface of the device and a drain electrode on the back surface.

[0022] The super-junction metal oxide semiconductor field effect transistor and the manufacturing method thereof have the following advantages compared with the prior art:

[0023] 1. The gradient-doped N-layer with a beam waist shape in cross-section is formed in the N drift layer, the electric field distribution is optimized, the longitudinal electric field support capability is enhanced in the middle narrow area, and the breakdown voltage is improved; the lateral conduction path is expanded in the two end thick areas, and the specific on-resistance is significantly reduced, thereby simultaneously achieving high voltage resistance and low on-resistance loss.

[0024] 2. The light-doped constraint N-layer is injected in the upper half of the beam waist N-layer, and the suppression P-layer is horizontally injected in the lower half, thereby forming a vertical charge compensation structure. The design effectively suppresses the electric field oscillation and charge imbalance problem in the switching process, improves the dynamic stability, reduces the leakage current, and enhances the gate control response speed.

[0025] 3. The constraint P-layer or high-resistance dielectric is added to the top of the beam waist structure to address the risk of electric field concentration, the P-type area is formed by ion implantation to directly suppress the electric field peak value between P-well layers, and the dielectric material is used to realize electric field homogenization and form an ohmic contact with the gate to avoid carrier recombination loss. Both of them significantly reduce the local breakdown probability and prolong the service life of the device.

[0026] 4. The high-doped N+ layer and the lateral P-block layer are arranged at the bottom of the beam waist N-layer, the N+ layer is directly connected to the N substrate to shorten the longitudinal current path and reduce the on-resistance, and the N+ layer is wrapped by the P-block layer to form local charge balance, enhance the bottom voltage resistance, suppress the longitudinal punch-through breakdown, and improve the current expansion uniformity.

[0027] 5. The beam waist groove is formed by multi-step mask etching in the manufacturing method, the gradient doping is realized by epitaxial filling or inclined ion implantation, and the geometric morphology and concentration distribution of the beam waist N-layer are accurately controlled. The process is compatible with the existing semiconductor process, and the self-aligned injection of the constraint layer and the suppression layer ensures the position accuracy of the vertical charge compensation structure and improves the production feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of example one in the present application;

[0029] Figure 2 is a schematic diagram of example two in the present application;

[0030] Figure 3 is a schematic diagram of example three in the present application;

[0031] Figure 4 is a schematic diagram of Example Four in the present application;

[0032] Figure 5 is a schematic diagram of Example Five in the present application;

[0033] Figure 6 is a schematic diagram of Example Six in the present application.

[0034] In the figure: 1, drain; 2, source; 3, gate; 4, P well layer; 5, P+ layer; 6, N well layer; 7, N substrate layer; 8, N drift layer; 9, beam waist N- layer; 10, constraint P- layer; 11, high resistance medium; 12, side P- block layer; 13, high doped N+ layer; 14, heavily doped upper region; 15, suppression P- layer; 16, constraint N- layer. DETAILED DESCRIPTION

[0035] In order to make the technical scheme of the present application clearer, the present application is further described in detail below in combination with the drawings and specific examples.

[0036] As shown in Figures 1-6 , a manufacturing method of a super-junction metal oxide semiconductor field effect transistor comprises the following steps:

[0037] Step one, growing a low-doped N drift layer 8 on the surface of the N substrate layer 7 by epitaxy process; the epitaxial growth of the low-doped N drift layer 8 on the N substrate layer 7 ensures that the drift region has a uniform thickness and a controllable doping concentration, laying a foundation for the subsequent formation of a super-junction structure, and the low-doped characteristic is conducive to improving the breakdown voltage of the device.

[0038] Step two, etching a beam waist-shaped groove with a narrow middle and wide upper and lower parts in the middle region of the N drift layer 8 by a multi-step mask etching process; the multi-step mask etching is used to form a beam waist-shaped groove in the middle of the N drift layer 8, and through accurate control of the etching depth and the side wall angle, a unique three-dimensional structure of "narrow middle and wide upper and lower parts" is realized, providing a geometric basis for optimizing the electric field distribution.

[0039] Step three, forming a beam waist N- layer 9 with a gradient change in doping concentration in the groove by epitaxial filling or inclined ion implantation process, so as to ensure that the cross section is thick at both ends and thin in the middle; the gradient-doped beam waist N- layer 9 is formed by epitaxial filling or inclined ion implantation, and the cross section design of thick at both ends and thin in the middle can simultaneously reduce the on-resistance and enhance the withstand voltage capability, and the inclined implantation process can accurately control the concentration gradient.

[0040] Step 4: Implant a confined N-layer 16 in the upper half of the waist N-layer 9, controlling its doping concentration to be 0.4–0.7 times the background concentration of the waist N-layer; Implant the confined N-layer 16 (concentration 0.4–0.7 times the background concentration) in the upper half of the waist N-layer 9. This lightly doped layer can suppress electric field peaks and optimize charge balance, improve the dynamic stability of the device, and avoid switching oscillations.

[0041] Step 5: Implant a suppression P-layer 15 at the corresponding position in the lower half of the waist N-layer 9, aligning it horizontally with the constraint N-layer 16 and contacting the N substrate 7; align and implant the suppression P-layer 15 in the lower half of the waist N-layer 9, aligning it horizontally with the constraint N-layer 16 and contacting the substrate, forming a vertical charge compensation structure, which significantly enhances the longitudinal withstand voltage capability and reduces leakage current.

[0042] Step 6: Form symmetrical P-well layer 4, N-well layer 6 and P+ layer 5 through photolithography and ion implantation; The strict symmetry design ensures uniform current distribution, avoids local overheating, and improves device reliability.

[0043] Step 7: Deposit the gate dielectric layer and form the gate 3 structure. The source 2 is formed on the front side of the device, and the drain 1 is formed on the back side. Depositing the gate dielectric and forming the gate 3 structure, combined with the ohmic contact process of the front source 2 and the back drain 1, ensures low contact resistance and high gate control efficiency, ultimately achieving high-performance device integration.

[0044] Example 1

[0045] like Figure 1 As shown, a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) consists of a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer specifically includes two P-well layers 4, two P+ layers 5, two N-well layers 6, an N-substrate layer 7, and an N-drift layer 8. The key feature is that a waisted N-layer 9 is formed inside the N-drift layer 8 through ion implantation. The waisted N-layer 9 consists of an upper half and a lower half, with a cross-sectional profile that is thicker at both ends and thinner in the middle. The "waisted" N-layer 9 (thicker at both ends and thinner in the middle) is designed inside the N-drift layer 8. Traditional superjunction MOSFETs exhibit uneven electric field distribution under high voltage, leading to limited breakdown voltage and high on-resistance. The waisted structure optimizes the electric field distribution of the N-drift layer 8, improving the breakdown voltage while reducing the on-resistance, thus enhancing the device's withstand voltage capability.

[0046] Example 2

[0047] like Figure 2As shown, a constrained P-layer 10 is formed on the top of the upper half of the waist N-layer 9 via ion implantation. This constrained P-layer 10 is located between the two P-well layers 4. The electric field at the top of the waist N-layer 9 structure is prone to concentration, potentially leading to localized breakdown. The constrained P-layer 10 suppresses the peak electric field at the top, improving device reliability, and the process is simple (achieved through ion implantation).

[0048] Example 3

[0049] like Figure 3 As shown, a high-resistivity dielectric 11 is provided at the top of the upper half of the N-layer 9, between the two P-well layers 4, and this high-resistivity dielectric 11 is in ohmic contact with the gate 3. The high-resistivity dielectric 11 replaces the confined P-layer, making ohmic contact with the gate 3. The P-type injection layer may introduce carrier recombination, affecting the switching speed. The high-resistivity dielectric 11 both homogenizes the electric field and avoids carrier loss, improving switching efficiency and the control capability of the gate 3.

[0050] Example 4

[0051] like Figure 4 As shown, the lower half of the waist N-layer 9 has two sets of highly doped N+ layers 13, each of which is in contact with the N-substrate layer 7. Each set of highly doped N+ layers 13 has side P-block layers 12 on both sides, which are in contact with the highly doped N+ layers 13. The waist N-layer 9 has a highly doped N+ layer 13 and side P-block layers 12 on both sides. The bottom of the device has a high on-path resistance and is prone to longitudinal breakdown under high voltage. The N+ layer 13 reduces the on-resistance, and the side P-block layers 12 enhance the longitudinal breakdown voltage and optimize current spread capability.

[0052] Example 5

[0053] like Figure 5 As shown, the upper half of the waist N-layer 9 is also a heavily doped upper region 14. Designing the upper half of the waist N-layer 9 as a heavily doped upper region 14 is beneficial because the narrow region in the middle of the waist structure can easily become a conduction bottleneck, limiting current capability. The heavily doped upper region 14 reduces channel resistance, increases saturation current, and enhances device conduction performance.

[0054] Example 6

[0055] like Figure 6As shown, the upper half of the beam waist N-layer 9 is formed with a confinement N-layer 16 by ion implantation, the doping concentration of the confinement N-layer 16 being 0.4-0.7 times that of the doping concentration of the beam waist N-layer 9. The lower half of the beam waist N-layer 9 is formed with a suppression P-layer 15 by ion implantation, the suppression P-layer 15 being horizontally aligned with the confinement N-layer 16, and the suppression P-layer 15 being in contact with the N-substrate layer 7. The upper half of the beam waist N-layer 9 is implanted with the confinement N-layer 16 (concentration 0.4-0.7 times), and the lower half is implanted with the suppression P-layer 15 in alignment. When the drift region charge is unbalanced, the voltage resistance decreases, and the switching process is prone to oscillation. The confinement N-layer 16 and the suppression P-layer 15 form vertical charge balance, significantly improving the breakdown voltage stability and suppressing dynamic oscillation.

[0056] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A super-junction metal oxide semiconductor field effect transistor, which is composed of a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer specifically comprises two P-well layers (4), two P+ layers (5), two N-well layers (6), an N substrate layer (7) and an N drift layer (8), characterized in that: The inside of the N drift layer (8) is formed with a beam waist N-layer (9) by ion implantation; The beam waist N-layer (9) is composed of an upper half region and a lower half region, wherein the cross-sectional profile of the beam waist N-layer (9) is thick at both ends and thin in the middle; The top of the upper half region of the beam waist N-layer (9) is formed with a confinement P-layer (10) by ion implantation, which is located between the two P well layers (4).

2. A super-junction metal oxide semiconductor field effect transistor, which is composed of a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer specifically comprises two P-well layers (4), two P+ layers (5), two N-well layers (6), an N substrate layer (7) and an N drift layer (8), characterized in that: The inside of the N drift layer (8) is formed with a beam waist N-layer (9) by ion implantation; The beam waist N-layer (9) is composed of an upper half region and a lower half region, wherein the cross-sectional profile of the beam waist N-layer (9) is thick at both ends and thin in the middle; The lower half region of the beam waist N-layer (9) is provided with two groups of high-doped N+ layers (13), and each group of the high-doped N+ layers (13) is in contact with the N substrate layer (7); Each group of the high-doped N+ layers (13) is provided with a side P-block layer (12) on the left and right sides, which is in contact with the high-doped N+ layer (13).

3. A super-junction metal oxide semiconductor field effect transistor, which is composed of a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer specifically comprises two P-well layers (4), two P+ layers (5), two N-well layers (6), an N substrate layer (7) and an N drift layer (8), characterized in that: The inside of the N drift layer (8) is formed with a beam waist N-layer (9) by ion implantation; The beam waist N-layer (9) is composed of an upper half region and a lower half region, wherein the cross-sectional profile of the beam waist N-layer (9) is thick at both ends and thin in the middle; The upper half region of the beam waist N-layer (9) is formed with a confinement N-layer (16) by ion implantation, and the doping concentration of the confinement N-layer (16) is 0.4-0.7 times that of the beam waist N-layer (9); The lower half region of the beam waist N-layer (9) is formed with a suppression P-layer (15) by ion implantation, which is horizontally aligned with the confinement N-layer (16) and is in contact with the N substrate layer (7).

4. A method of manufacturing a super junction metal oxide semiconductor field effect transistor, characterized by, The super junction metal oxide semiconductor field effect transistor of claim 3, the method for manufacturing the super junction metal oxide semiconductor field effect transistor, comprising: S1, growing a low-doped N drift layer (8) on the surface of the N substrate layer (7) by epitaxy process; S2, using a multi-step mask etching process to etch a beam waist shaped groove in the middle region of the N drift layer (8), which is narrow in the middle and wide at both ends; S3, forming a beam waist N-layer (9) with a gradient change in doping concentration in the groove by epitaxial filling or inclined ion implantation process, ensuring that its cross section is thick at both ends and thin in the middle; S4, injecting a confinement N-layer (16) in the upper half region of the beam waist N-layer (9), and controlling its doping concentration to be 0.4-0.7 times the background concentration of the beam waist N-layer; S5, injecting a suppression P-layer (15) in the corresponding position of the lower half region of the beam waist N-layer (9), so that it is horizontally aligned with the confinement N-layer (16) and contacts the N substrate layer (7); S6, forming symmetrical P well layer (4), N well layer (6) and P+ layer (5) by photolithography and ion implantation; S7, depositing a gate dielectric layer and forming a gate (3) structure to form a source (2) on the front surface of the device and a drain (1) on the back surface.

Images