An integrated N-PolySi / N-SiC heterojunction SiC MOSFET and its preparation method

Abstract

The present invention discloses an integrated N-PolySi / N-SiC heterojunction SiC MOSFET and a preparation method thereof, relating to the technical field of power semiconductor devices. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention forms a shallow trench by etching the surface of an n-SiC drift region, and forms a shallow-grooved N-PolySi / N-SiC heterojunction structure between the n-SiC drift region by depositing a Schottky contact electrode of N-PolySi covering the shallow trench, thereby reducing the Schottky barrier height, improving the device's surge current resistance, reducing the on-state voltage drop in the third quadrant, and reducing losses. A shallow trench is also provided in the JFET region, so that the gate oxide layer thickness in the area directly above the JFET region is increased, thereby reducing the gate oxide electric field above the JFET region and improving the device's avalanche resistance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to an integrated N-PolySi / N-SiC heterojunction SiC MOSFET (SiC Metal Oxide Semiconductor Field Effect Transistor) and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) offers advantages such as a wide bandgap, a strong critical breakdown electric field, high thermal conductivity, and excellent radiation resistance, making it an ideal material for power semiconductor devices. Compared to silicon (Si), SiC-based power semiconductor devices offer higher breakdown voltage, lower on-state voltage drop, higher operating frequencies, smaller size, and more reliable high-temperature stability, making them more suitable for power electronics circuits.

[0003] SiC MOSFETs, with their high power density, fast switching speed, and excellent thermal conductivity, are gradually becoming a key advantage in high-power systems. Key power applications include photovoltaic panels, grid inverters, UPS (uninterruptible power supply), and railway traction drives.

[0004] In power electronics, the body diode of SiC MOSFETs often operates in the third quadrant as a freewheeling diode. However, due to the high bandgap of SiC material (3.26eV), the turn-on voltage of the SiC diode is approximately 2.7V. This higher turn-on voltage increases the conduction losses of the SiC MOSFET's body diode when used for freewheeling. Furthermore, double-click degradation may occur when the body diode is in conduction mode.

[0005] Currently, to reduce the forward voltage drop of the SiC MOSFET body diode, Schottky diodes can be used as freewheeling diodes. These can be classified into two types: external and internally integrated Schottky diodes. External integration introduces additional area, increasing module manufacturing costs and limiting the development of miniaturization, lightweighting, and high-density high-power electronic devices. Therefore, internal integration has become the mainstream development direction.

[0006] However, the Schottky metal of the current integrated SiC Schottky diode is usually Ni (nickel) or Ti (titanium) metal, which has a high barrier height. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides an integrated N-PolySi / N-SiC heterojunction SiC MOSFET and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0008] The present invention provides an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, comprising:

[0009] The drain and n + -SiC substrate and n-SiC drift region;

[0010] The upper surface of the n-SiC drift region is provided with a plurality of grooves arranged at intervals, and a Pwell region is provided inside the n-SiC drift region on both sides of the groove, and a JFET region is provided between the two Pwell regions near the edges of both sides of the device;

[0011] An N+ region and a P+ region are provided in the Pwell region, wherein the N+ region and the P+ region are adjacent to each other, the N+ region is close to the JFET region, and the P+ region is far away from the JFET region;

[0012] A gate oxide layer is provided inside the trench of the JFET region, the upper surface of the n-SiC drift region, the upper surface of the Pwell region, and part of the upper surface of the N+ region;

[0013] A gate is provided on the gate oxide layer, and an isolation dielectric is provided on the top and sidewalls of the gate;

[0014] Ohmic contact electrodes are provided on the upper surface of the P+ region and part of the upper surface of the N+ region; a Schottky contact electrode is provided on the n-SiC drift region between the two ohmic contact electrodes near the middle of the device, and the Schottky contact electrode covers the trench; the material of the Schottky contact electrode is N-PolySi; the ohmic contact electrode and the Schottky contact electrode are connected by an interconnect metal;

[0015] A passivation layer is provided on a portion of the upper surface of the interconnection metal close to both sides of the device.

[0016] In one embodiment of the present invention, the n + -The doping concentration of the SiC substrate is 5×10 18 cm -3 -2×10 19 cm -3 , thickness is 150-180μm.

[0017] In one embodiment of the present invention, the doping concentration of the n-SiC drift region is 5×10 15 cm -3-2×10 16 cm -3 , thickness is 6.6-33μm.

[0018] In one embodiment of the present invention, the groove is a trapezoidal groove, the top width of the trapezoidal groove is 1.0 μm-2.0 μm, the minimum width of the bottom is 0.8 μm, and the vertical depth is 0.2 μm-0.3 μm.

[0019] In one embodiment of the present invention, the width of the Pwell region is 2.0 μm-5.0 μm, and the doping concentration is 5×10 18 cm -3 -1×10 19 cm -3 .

[0020] In one embodiment of the present invention, the material of the gate oxide layer is SiO2, wherein the thickness of the gate oxide layer above the n-SiC drift region, the Pwell region and part of the N+ region is 30-50 nm, and the thickness of the gate oxide layer above the trench is 0.23 μm-0.35 μm.

[0021] In one embodiment of the present invention, the gate is made of N-PolySi with a thickness of 0.3-0.5 μm, and the isolation dielectric is made of SiO 2 with a thickness of 0.8-1.0 μm.

[0022] In one embodiment of the present invention, the material of the ohmic contact electrode is Ti / Ni / Ti laminated metal with a thickness of 10-1000 nm, and the material of the interconnect metal is Al with a thickness of 4 μm.

[0023] In one embodiment of the present invention, the Schottky contact electrode has a thickness of 300-500 nm, and an N-PolySi / n-SiC heterojunction is formed between the Schottky contact electrode and the n-SiC drift region.

[0024] The present invention provides a method for preparing an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, which is applicable to the integrated N-PolySi / N-SiC heterojunction SiC MOSFET described in any of the above embodiments. The preparation method comprises:

[0025] Step 1: Get n + -SiC substrate, in the n + -Preparing an n-SiC drift region on the upper surface of the SiC substrate;

[0026] Step 2: etching a plurality of spaced-apart trenches on the upper surface of the n-SiC drift region;

[0027] Step 3: forming a Pwell region inside the n-SiC drift region on both sides of the trench by an ion implantation process. A JFET region is formed between the two Pwell regions near the edges of the device. Adjacent N+ and P+ regions are formed in the Pwell region by an ion implantation process.

[0028] Step 4: preparing SiO2 on the device surface by a high-temperature thermal oxidation process to form a gate oxide layer, and depositing N-PolySi on the upper surface of the gate oxide layer in the JFET region to form a gate;

[0029] Step 5: depositing an isolation dielectric on the gate surface, etching away the gate oxide layer outside the gate region, and forming an ohmic contact electrode on the upper surface of the P+ region and a portion of the upper surface of the N+ region;

[0030] Step 6: depositing N-PolySi on the n-SiC drift region between the two ohmic contact electrodes near the middle of the device to form a Schottky contact electrode, wherein the Schottky contact electrode covers the trench, and an N-PolySi / n-SiC heterojunction is formed between the Schottky contact electrode and the n-SiC drift region;

[0031] Step 7: preparing Al metal above the ohmic contact electrode, the Schottky contact electrode and the isolation dielectric to form an interconnect metal connecting the ohmic contact electrode and the Schottky contact electrode;

[0032] Step 8: depositing a passivation layer on the upper surface of the interconnect metal near both sides of the device;

[0033] Step 9: Place the + -The back side of the SiC substrate is thinned to 150-180 μm;

[0034] Step 10: After thinning + -A drain electrode is prepared on the back side of the SiC substrate.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention forms a shallow trench by etching the surface of the n-SiC drift region. A Schottky contact electrode of N-PolySi is deposited covering the shallow trench, forming a shallow-grooved N-PolySi / N-SiC heterojunction structure between the electrode and the n-SiC drift region. This reduces the Schottky barrier height, improves the device's surge current capability, reduces the on-state voltage drop in the third quadrant, and minimizes losses.

[0037] 2. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention also has a shallow trench in the JFET region, which increases the thickness of the gate oxide layer in the area directly above the JFET region, thereby reducing the gate oxide electric field above the JFET region and improving the avalanche resistance of the device.

[0038] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 1 is a schematic structural diagram of an integrated N-PolySi / N-SiC heterojunction SiC MOSFET provided by an embodiment of the present invention;

[0040] Figure 2 This is a schematic structural diagram of the completion of step 1 of the preparation method provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic structural diagram of the completion of step 2 of the preparation method provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic structural diagram of the completion of step 3 of the preparation method provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic structural diagram of the completion of step 4 of the preparation method provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic structural diagram of the completion of step 5 of the preparation method provided in an embodiment of the present invention;

[0045] Figure 7 This is a schematic structural diagram of the completion of step 6 of the preparation method provided in an embodiment of the present invention;

[0046] Figure 8 This is a schematic structural diagram of the completion of step 7 of the preparation method provided in an embodiment of the present invention;

[0047] Figure 9 This is a schematic structural diagram of the completion of step 8 of the preparation method provided in an embodiment of the present invention;

[0048] Figure 10 This is a schematic structural diagram of the completion of step 9 of the preparation method provided in an embodiment of the present invention;

[0049] Figure 111 is an IV curve diagram of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention and a traditional SiC MOSFET;

[0050] Figure 12 It is a schematic diagram of the gate oxide electric field distribution of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention and the traditional SiC MOSFET in blocking mode.

[0051] Icon: 1-n + -SiC substrate; 2-n-SiC drift region; 3-trench; 4-Pwell region; 5-N+ region; 6-P+ region; 7-gate oxide layer; 8-gate; 9-isolation dielectric; 10-ohmic contact electrode; 11-Schottky contact electrode; 12-interconnect metal; 13-passivation layer; 14-drain. DETAILED DESCRIPTION

[0052] To further illustrate the technical means and effects adopted by the present invention to achieve the predetermined objectives of the invention, an integrated N-PolySi / N-SiC heterojunction SiC MOSFET and its preparation method proposed in accordance with the present invention are described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0054] In the first aspect, the embodiment of the present invention provides an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, see Figure 1 , Figure 1 FIG is a schematic structural diagram of an integrated N-PolySi / N-SiC heterojunction SiC MOSFET provided by an embodiment of the present invention, such as Figure 1 As shown, the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the embodiment of the present invention includes: a drain 14, an n + - SiC substrate 1 and n-SiC drift region 2 .

[0055] Optionally, n + -The doping concentration of SiC substrate 1 is 5×10 18 cm -3 -2×10 19 cm -3, with a thickness of 150μm-180μm. The doping concentration of the n-SiC drift region 2 is 5×10 15 cm -3 -2×10 16 cm -3 The drain electrode 14 is made of Ni / Ag (nickel / silver) laminated metal with a thickness of 10nm-1000nm. + -SiC substrate 1 is in ohmic contact.

[0056] In this embodiment, a plurality of trenches 3 arranged at intervals are provided on the upper surface of the n-SiC drift region 2, and Pwell regions 4 are provided inside the n-SiC drift region 2 on both sides of the trenches 3. The JFET region is located between the two Pwell regions 4 near the edges of the device. Figure 1 From left to right, the JFET region is located between the first and second Pwell regions 4, and the JFET region is located between the third and fourth Pwell regions 4. The JFET region is a junction field effect transistor region, and the Pwell region is a P-well injection region.

[0057] Optionally, the trench 3 is a trapezoidal trench with a top width of 1.0 μm-2.0 μm, a minimum bottom width of 0.8 μm, and a vertical depth of 0.2 μm-0.3 μm, that is, the trench 3 is a shallow trench. The width of the Pwell region 4 is 2.0 μm-5.0 μm, and the doping concentration is 5×10 18 cm -3 -1×10 19 cm -3 .

[0058] In this embodiment, an N+ region 5 and a P+ region 6 are provided in the Pwell region 4, wherein the N+ region 5 and the P+ region 6 are adjacent to each other, the N+ region 5 is close to the JFET region, and the P+ region 6 is far away from the JFET region; a gate oxide layer 7 is provided inside the trench 3 of the JFET region, the upper surface of the n-SiC drift region 2, the upper surface of the Pwell region 4, and part of the upper surface of the N+ region 5.

[0059] Optionally, the material of the gate oxide layer 7 is SiO2, wherein the thickness of the gate oxide layer 7 above the n-SiC drift region 2, the Pwell region 4 and part of the N+ region 5 is 30nm-50nm, and the thickness of the gate oxide layer 7 above the trench 3 is 0.23μm-0.35μm.

[0060] In this embodiment, a gate electrode 8 is provided on the gate oxide layer 7 , and an isolation dielectric 9 is provided on the top and sidewalls of the gate electrode 8 .

[0061] Optionally, the gate 8 is made of N-PolySi with a thickness of 0.3 μm-0.5 μm, and the isolation dielectric 9 is made of SiO 2 with a thickness of 0.8 μm-1.0 μm.

[0062] In this embodiment, ohmic contact electrodes 10 are provided on the upper surface of the P+ region 6 and part of the upper surface of the N+ region 5. A Schottky contact electrode 11 is provided on the n-SiC drift region 2 between the two ohmic contact electrodes 10 near the middle of the device. The Schottky contact electrode 11 covers the trench 3. The material of the Schottky contact electrode 11 is N-PolySi.

[0063] Optionally, the ohmic contact electrode 10 is made of a Ti / Ni / Ti laminated metal with a thickness of 10 nm to 1000 nm, and the Schottky contact electrode 11 has a thickness of 300 nm to 500 nm. In this embodiment, the Schottky contact electrode 11 covers the trench 3, forming a shallow trench-type N-PolySi / n-SiC heterojunction with the n-SiC drift region 2.

[0064] In this embodiment, the ohmic contact electrode 10 and the Schottky contact electrode 11 are connected via an interconnect metal 12. That is, the interconnect metal 12 is located above the ohmic contact electrode 10, the isolation dielectric 9, and the Schottky contact electrode 11. A passivation layer 13 is provided on the upper surface of the interconnect metal 12 near both sides of the device to provide insulation and protection.

[0065] Optionally, the interconnection metal 12 is made of Al with a thickness of 4 μm, and the passivation layer 13 is made of SiN (silicon nitride) and PI (polyimide).

[0066] The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention is etched into a shallow trench on the surface of the n-SiC drift region. A Schottky contact electrode of N-PolySi is deposited covering the shallow trench, forming a shallow-grooved N-PolySi / N-SiC heterojunction structure between the electrode and the n-SiC drift region. This reduces the Schottky barrier height, improves the device's surge current resistance, reduces the on-state voltage drop in the third quadrant, and minimizes losses. Furthermore, a shallow trench is also provided in the JFET region, increasing the thickness of the gate oxide layer directly above the JFET region, thereby reducing the gate oxide electric field above the JFET region and improving the device's avalanche resistance.

[0067] In a second aspect, an embodiment of the present invention provides a method for preparing an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, which is applicable to the integrated N-PolySi / N-SiC heterojunction SiC MOSFET provided in the first aspect, and the preparation method comprises the following steps:

[0068] Step 1: Get n+ -SiC substrate 1, in n + -Prepare n-SiC drift region 2 on the upper surface of SiC substrate 1, such as Figure 2 shown.

[0069] In this embodiment, n + -The doping concentration of SiC substrate 1 is 5×10 18 cm -3 -2×10 19 cm -3 , with a thickness of 350 μm. The doping concentration of the n-SiC drift region 2 is 5×10 15 cm -3 -2×10 16 cm -3 , thickness is 6.6μm-33μm.

[0070] Step 2: Etch a plurality of trenches 3 arranged at intervals on the upper surface of the n-SiC drift region 2, such as Figure 3 shown.

[0071] In this embodiment, the groove 3 is a trapezoidal groove, the top width of the trapezoidal groove is 1.0 μm-2.0 μm, the minimum width of the bottom is 0.8 μm, and the vertical depth is 0.2 μm-0.3 μm.

[0072] Step 3: Pwell region 4 is formed inside the n-SiC drift region 2 on both sides of the trench 3 by ion implantation. The JFET region is located between the two Pwell regions 4 near the edges of the device. Adjacent N+ region 5 and P+ region 6 are formed in the Pwell region 4 by ion implantation. Figure 4 shown.

[0073] In this embodiment, the Pwell region 4 may be formed by front Al ion implantation, the N+ region 5 may be formed by front N ion implantation using a self-aligned process, and then the P+ region 6 may be formed by Al ion implantation.

[0074] Step 4: Prepare SiO2 on the device surface by high temperature thermal oxidation process to form gate oxide layer 7, and deposit N-PolySi on the upper surface of gate oxide layer 7 in JFET region to form gate 8, as shown in FIG. Figure 5 shown.

[0075] In this embodiment, the thickness of the gate oxide layer 7 above the n-SiC drift region 2, the Pwell region 4, and part of the N+ region 5 is 30 nm to 50 nm, and the thickness of the gate oxide layer 7 above the trench 3 is 0.23 μm to 0.35 μm. The thickness of the gate 8 is 0.3 μm to 0.5 μm.

[0076] Step 5: Deposit an isolation dielectric 9 on the surface of the gate 8, etch away the gate oxide layer 7 outside the gate 8 area, and prepare an ohmic contact electrode 10 on the upper surface of the P+ region 6 and part of the upper surface of the N+ region 5, as shown in FIG. Figure 6 shown.

[0077] In this embodiment, the isolation dielectric 9 is made of SiO 2 with a thickness of 0.8 μm-1.0 μm, and the ohmic contact electrode 10 is made of Ti / Ni / Ti laminated metal with a thickness of 10 nm-1000 nm.

[0078] Step 6: N-PolySi is deposited on the n-SiC drift region 2 between the two ohmic contact electrodes 10 near the middle of the device to form a Schottky contact electrode 11. The Schottky contact electrode 11 covers the trench 3, and an N-PolySi / n-SiC heterojunction is formed between the Schottky contact electrode 11 and the n-SiC drift region 2. Figure 7 shown.

[0079] In this embodiment, the thickness of the Schottky contact electrode 11 is 300 nm-500 nm.

[0080] Step 7: Al metal is prepared on the ohmic contact electrode 10, the Schottky contact electrode 11 and the isolation dielectric 9 to form an interconnection metal 12 connecting the ohmic contact electrode 10 and the Schottky contact electrode 11, as shown in FIG. Figure 8 shown.

[0081] In this embodiment, the interconnection metal 12 is made of Al and has a thickness of 4 μm.

[0082] Step 8: Deposit a passivation layer 13 on the upper surface of the interconnection metal 12 near both sides of the device, such as Figure 9 shown.

[0083] In this embodiment, the passivation layer 13 is made of SiN and PI, and performs insulation and protection functions.

[0084] Step 9: Place the + - The back side of the SiC substrate 1 is thinned to 150 μm-180 μm, such as Figure 10 shown.

[0085] Step 10: After thinning + - A drain electrode 14 is prepared on the back side of the SiC substrate 1 to obtain an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, such as Figure 1 shown.

[0086] In this embodiment, the drain electrode 14 is made of Ni / Ag laminated metal with a thickness of 10nm-1000nm. + -SiC substrate 1 is in ohmic contact.

[0087] For the specific content of the preparation method of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET and the corresponding beneficial effects, please refer to the relevant content of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET provided in the first aspect, which will not be repeated here.

[0088] Furthermore, by comparing the performance of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention with that of a traditional SiC MOSFET, the effect of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention is described.

[0089] See Figure 11 , Figure 11 The IV curves of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention and a conventional SiC MOSFET are shown. As can be seen from the figure, the bipolar turn-on voltage of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention is low. Therefore, at a conduction current of 100A, the forward voltage drops of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET and the conventional SiC MOSFET are 1.5V and 3.6V, respectively. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention significantly reduces the forward voltage drop, resulting in greatly reduced conduction losses.

[0090] See Figure 12 , Figure 12 It is a schematic diagram of the gate oxide electric field distribution of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention and the traditional SiC MOSFET in blocking mode.

[0091] As can be seen from the figure, the gate oxide electric field of the integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention is reduced to 3MV / cm, improving reliability. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET of the present invention adopts a shallow-trench N-PolySi / N-SiC heterojunction structure, which reduces the Schottky barrier height, improves the device's surge current resistance, reduces the on-state voltage drop in the third quadrant, and reduces losses. At the same time, because the JFET region also has a shallow trench, the gate oxide layer thickness in the area directly above the JFET region is increased, thereby reducing the gate oxide electric field above the JFET from the original 4MV / cm to below 3MV / cm, improving the device's avalanche resistance and reliability.

[0092] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0093] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0094] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An integrated N-PolySi / N-SiC heterojunction SiC MOSFET, characterized in that: include: The drain (14) and n + -SiC substrate (1) and n-SiC drift region (2); The upper surface of the n-SiC drift region (2) is provided with a plurality of grooves (3) arranged at intervals, and Pwell regions (4) are provided inside the n-SiC drift region (2) on both sides of the grooves (3), and a JFET region is provided between the two Pwell regions (4) close to the edges of both sides of the device; An N+ region (5) and a P+ region (6) are provided in the Pwell region (4), wherein the N+ region (5) and the P+ region (6) are adjacently provided, the N+ region (5) is close to the JFET region, and the P+ region (6) is far away from the JFET region; A gate oxide layer (7) is provided inside the trench (3) of the JFET region, the upper surface of the n-SiC drift region (2), the upper surface of the Pwell region (4), and part of the upper surface of the N+ region (5); A gate electrode (8) is provided on the gate oxide layer (7), and an isolation dielectric (9) is provided on the top and sidewalls of the gate electrode (8); An ohmic contact electrode (10) is provided on the upper surface of the P+ region (6) and a portion of the upper surface of the N+ region (5); a Schottky contact electrode (11) is provided on the n-SiC drift region (2) between the two ohmic contact electrodes (10) near the middle of the device, and the Schottky contact electrode (11) covers the groove (3); the material of the Schottky contact electrode (11) is N-PolySi; the ohmic contact electrode (10) and the Schottky contact electrode (11) are connected via an interconnection metal (12); A passivation layer (13) is provided on a portion of the upper surface of the interconnection metal (12) close to both sides of the device.

2. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The n + -The doping concentration of the SiC substrate (1) is 5×10 18 cm -3 -2×10 19 cm -3 , thickness is 150μm-180μm.

3. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The doping concentration of the n-SiC drift region (2) is 5×10 15 cm -3 -2×10 16 cm -3 , thickness is 6.6μm-33μm.

4. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The groove (3) is a trapezoidal groove, the top surface width of the trapezoidal groove is 1.0 μm-2.0 μm, the minimum width of the bottom is 0.8 μm, and the vertical depth is 0.2 μm-0.3 μm.

5. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The width of the Pwell region (4) is 2.0 μm-5.0 μm, and the doping concentration is 5×10 18 cm -3 -1×10 19 cm -3 .

6. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The material of the gate oxide layer (7) is SiO2, wherein the thickness of the gate oxide layer (7) above the n-SiC drift region (2), the Pwell region (4) and part of the N+ region (5) is 30nm-50nm, and the thickness of the gate oxide layer (7) above the trench (3) is 0.23μm-0.35μm.

7. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The gate (8) is made of N-PolySi with a thickness of 0.3 μm-0.5 μm, and the isolation medium (9) is made of SiO2 with a thickness of 0.8 μm-1.0 μm.

8. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The material of the ohmic contact electrode (10) is Ti / Ni / Ti laminated metal with a thickness of 10 nm-1000 nm, and the material of the interconnection metal (12) is Al with a thickness of 4 μm.

9. The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to claim 1, wherein: The Schottky contact electrode (11) has a thickness of 300 nm to 500 nm, and an N-PolySi / n-SiC heterojunction is formed between the Schottky contact electrode (11) and the n-SiC drift region (2).

10. A method for preparing an integrated N-PolySi / N-SiC heterojunction SiC MOSFET, characterized in that: The integrated N-PolySi / N-SiC heterojunction SiC MOSFET according to any one of claims 1 to 9, wherein the preparation method comprises: Step 1: Get n + -SiC substrate, in the n + -Preparing an n-SiC drift region on the upper surface of the SiC substrate; Step 2: etching a plurality of spaced-apart trenches on the upper surface of the n-SiC drift region; Step 3: forming a Pwell region inside the n-SiC drift region on both sides of the trench by an ion implantation process. A JFET region is formed between the two Pwell regions near the edges of the device. Adjacent N+ and P+ regions are formed in the Pwell region by an ion implantation process. Step 4: preparing SiO2 on the device surface by a high-temperature thermal oxidation process to form a gate oxide layer, and depositing N-PolySi on the upper surface of the gate oxide layer in the JFET region to form a gate; Step 5: depositing an isolation dielectric on the gate surface, etching away the gate oxide layer outside the gate region, and forming an ohmic contact electrode on the upper surface of the P+ region and a portion of the upper surface of the N+ region; Step 6: depositing N-PolySi on the n-SiC drift region between the two ohmic contact electrodes near the middle of the device to form a Schottky contact electrode, wherein the Schottky contact electrode covers the trench, and an N-PolySi / n-SiC heterojunction is formed between the Schottky contact electrode and the n-SiC drift region; Step 7: preparing Al metal above the ohmic contact electrode, the Schottky contact electrode and the isolation dielectric to form an interconnect metal connecting the ohmic contact electrode and the Schottky contact electrode; Step 8: depositing a passivation layer on the upper surface of the interconnect metal near both sides of the device; Step 9: Place the + -The back side of the SiC substrate is thinned to 150μm-180μm; Step 10: After thinning + -A drain electrode is prepared on the back side of the SiC substrate.

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