Compound semiconductor and method for manufacturing same

Abstract

The compound semiconductor has a crystal structure containing a first element and a second element. The compound semiconductor contains, in a crystal structure, a third element that causes the compound semiconductor to have a first conductivity type by being substituted with the first element, and a fourth element that causes the compound semiconductor to have the first conductivity type by being substituted with the second element.

Description

Technical Field

[0001] This specification discloses technologies related to compound semiconductors and methods for manufacturing the same. Background Art

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device using compound semiconductors. In Patent Document 1, impurities are ion-implanted into a predetermined region of a semiconductor layer to form a semiconductor device having multiple semiconductor regions within the semiconductor layer. Specifically, nitrogen is ion-implanted as an impurity into a SiC semiconductor layer to form n-type semiconductor regions.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-136894 Summary of the Invention

[0006] If nitrogen is ion-implanted into a SiC semiconductor layer as described in Patent Document 1, the carbon (carbon vacancies) in the SiC crystal are replaced with nitrogen, and the SiC semiconductor layer becomes n-type. In order to increase the impurity concentration (n-type impurity concentration) of the SiC semiconductor layer, it is necessary to increase the nitrogen concentration during ion implantation. However, if the nitrogen concentration of the ion implantation is increased, crystal defects are generated during ion implantation, which may cause degradation of the characteristics of the semiconductor device. Therefore, a technology is needed to suppress the degradation of the characteristics of the semiconductor device while adjusting the impurity concentration of the compound semiconductor. The purpose of this specification is to provide a technology for adjusting the impurity concentration of a compound semiconductor.

[0007] The compound semiconductor device disclosed in this specification has a crystal structure containing a first element and a second element. The compound semiconductor includes within the crystal structure a third element that partially replaces the first element to convert the compound semiconductor to the first conductivity type, and a fourth element that partially replaces the second element to convert the compound semiconductor to the first conductivity type.

[0008] In the compound semiconductors described above, both the first and second elements that constitute the compound semiconductor's crystal structure are partially replaced with impurity elements (third and fourth elements). Therefore, when the impurity concentration of the compound semiconductor is the same, for example, compared to a compound semiconductor in which only the lattice sites of the first element are replaced by the third element, the number of atomic vacancies (substitution sites) of the first element is reduced, thereby suppressing the shortage of atomic vacancies of the first element. The impurity concentration of the third element ion-implanted into the compound semiconductor can be reduced, and crystal defects in the compound semiconductor can be suppressed. As a result, the degradation of the characteristics of semiconductor devices using the compound semiconductor can be suppressed.

[0009] The manufacturing method disclosed in this specification relates to a method for manufacturing a compound semiconductor. This manufacturing method comprises: a film formation step of forming a growth layer having a crystal structure containing a first element and a second element, and containing as an impurity a third element that partially substitutes for the first element and changes the compound semiconductor to the first conductivity type; an ion implantation step of implanting a fourth element that partially substitutes for the second element and changes the compound semiconductor to the first conductivity type into the growth layer formed by the film formation step; and an annealing step of heating the growth layer after the fourth element has been implanted, thereby forming the compound semiconductor.

[0010] Another manufacturing method disclosed in this specification relates to a method for manufacturing a compound semiconductor. This manufacturing method comprises: a first ion implantation step of implanting a third element, which partially replaces the first element and converts the compound semiconductor to the first conductivity type, into a predetermined region of a semiconductor substrate having a crystal structure containing a first element and a second element; a second ion implantation step of implanting a fourth element, which partially replaces the second element and converts the compound semiconductor to the first conductivity type, into the predetermined region into which the third element has been implanted; and an annealing step of heating the semiconductor substrate after the implantation of the third and fourth elements to form the compound semiconductor.

[0011] According to the above-described manufacturing method, the compound semiconductor can be made conductive by replacing the lattice site of the first element with the third element, and the compound semiconductor can be made conductive by replacing the lattice site of the second element with the fourth element. This can reduce the concentration of impurities ion-implanted into the compound semiconductor, and suppress crystal defects in the compound semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a semiconductor device.

[0013] Figure 2 The crystal structure of a compound semiconductor constituting a semiconductor device is shown.

[0014] Figure 3 The crystal structure of conventional compound semiconductors constituting semiconductor devices is shown.

[0015] Figure 4 A method for manufacturing a compound semiconductor according to the first embodiment will be described.

[0016] Figure 5 A method for manufacturing a compound semiconductor according to a second embodiment will be described. DETAILED DESCRIPTION

[0017] In the compound semiconductor of one example disclosed in this specification, the doping concentration ratio of the third element to the fourth element in the crystal structure may be 1:9 to 9:1.

[0018] According to this configuration, it is possible to suppress atomic vacancy shortages for both the first element and the second element.

[0019] In the compound semiconductor of one example disclosed in this specification, the first element may be Si, and the second element may be C.

[0020] According to this configuration, crystal defects can be suppressed in a high-breakdown voltage SiC semiconductor, and a semiconductor device having high breakdown voltage and excellent electrical characteristics (eg, low on-resistance) can be realized.

[0021] In the semiconductor device disclosed in this specification, a semiconductor region composed of one of the aforementioned compound semiconductors may be provided in a portion of the semiconductor substrate. In other words, a semiconductor region not composed of one of the aforementioned compound semiconductors may be provided in the semiconductor substrate.

[0022] This configuration allows, for example, the semiconductor region composed of the compound semiconductor described above to be provided only in specific regions within the semiconductor substrate, avoiding high-concentration impurity regions such as those in contact with electrodes. For example, when forming high-concentration impurity regions, it is not necessary to substitute multiple substitution sites with impurity elements, thereby reducing the manufacturing cost (and time) of the semiconductor device.

[0023] (Semiconductor Device)

[0024] Reference Figure 1 Semiconductor device 10 will be described. Semiconductor device 10 is a vertical semiconductor device comprising a semiconductor substrate 14, a source electrode 12 and a gate electrode 4 provided on the surface of semiconductor substrate 14, and a drain electrode 28 provided on the back surface of semiconductor substrate 14. Semiconductor substrate 14 is made of SiC, an example of a compound semiconductor. In semiconductor device 10, source region 8, body region 6, drift region 23, p-type column region 22, n-type column region 24, and drain region 26 are formed by ion implantation of n-type and p-type impurities into n-type semiconductor substrate 14. Drift region 23 is formed by regions of semiconductor substrate 14 where source region 8, body region 6, p-type column region 22, and drain region 26 are not formed. In other words, n-type column region 24 is part of drift region 23.

[0025] P-type body regions 6 are dispersedly provided on the surface of the semiconductor substrate 14. In addition, n-type body regions 6 are provided on the surface of the body regions 6. +The source region 8 is separated from the drift region 23 by the body region 6. The source electrode 12 is electrically connected to the source region 8. Furthermore, the gate electrode 4 is provided on the surface of the body region 6, which separates the source region 8 from the drift region 23, via the gate insulating film 2. The semiconductor device 10 is a planar gate MOSFET. Furthermore, the source region 8 and the body region 6 are formed by ion implanting n-type or p-type impurities into the semiconductor substrate 14 from the surface of the semiconductor substrate 14.

[0026] On the back surface of the semiconductor substrate 14, n + The drain region 26 is formed by ion implanting n-type impurities into the semiconductor substrate 14 from the back surface of the semiconductor substrate 14 .

[0027] A p-type column region 22 is formed below the body region 6. The p-type column region 22 extends in the thickness direction of the semiconductor substrate 14 (i.e., in the direction connecting the front and back surfaces). An n-type column region 24, into which no impurities are introduced, is formed between the p-type column regions 22 and 22. The p-type column region 22 and the n-type column region 24 form a superjunction structure 20. The superjunction structure 20 is formed in the middle portion of the thickness direction of the semiconductor substrate 14, i.e., between the body region 6 and the drain region 26. The p-type column region 22 is formed by ion implanting p-type impurities into the semiconductor substrate 14 from the surface. Although details will be described later, in the n-type column region 24 (drift region 23), some silicon (Si) vacancies are replaced by phosphorus (P), and some carbon (C) vacancies are replaced by nitrogen (N).

[0028] In the semiconductor device 10, if a voltage exceeding the threshold voltage is applied to the gate electrode 4, an inversion layer (path) can be formed on the surface of the body region 6 opposite to the gate electrode 4. Electrons supplied from the source electrode 12 to the source region 8 can be supplied to the drift region 23 through the inversion layer. The electrons supplied to the drift region 23 move toward the drain region 26 and are discharged from the drain electrode 28. In other words, the semiconductor device 10 is turned on. If the application of voltage to the gate electrode 4 is stopped (that is, if the voltage applied to the gate electrode 4 is lower than the threshold voltage), the inversion layer formed on the body region 6 disappears, and the supply of electrons from the source region 8 to the drift region 23 stops. In other words, the semiconductor device 10 is turned off. The semiconductor device 10 is a normally-off MOSFET (metal oxide semiconductor field effect transistor) that is turned on when a voltage exceeding the threshold voltage is applied to the gate electrode 4.

[0029] As described above, the semiconductor device 10 has a superjunction structure 20 formed in the semiconductor substrate 14. Therefore, when the semiconductor device 10 is disconnected, a depletion layer extends from the interface between the p-type column region 22 and the n-type column region 24 into the p-type column region 22, and at the same time, the depletion layer also extends into the n-type column region 24. In the semiconductor device 10, by controlling the length (width direction) of the p-type column region 22 perpendicular to the thickness direction, the depletion layer 20 is formed. Figure 1 The length and impurity concentration of the p-type column region 22 and the n-type column region 24 in the width direction are controlled to ensure charge balance between the p-type column region 22 and the n-type column region 24. Semiconductor device 10 can achieve nearly complete depletion of the semiconductor substrate 14 (i.e., the portion where the superjunction structure 20 is formed) while semiconductor device 10 is off. Consequently, semiconductor device 10 has a high withstand voltage.

[0030] (Crystal structure of n-type column region)

[0031] Reference Figure 2 and Figure 3 , the crystal structure of the n-type column region 24 (drift region 23) will be described. Figure 2 A portion of the crystal structure of the n-type column region 24 of the semiconductor device 10 is shown. Figure 3 FIG. 4 shows a portion of the crystal structure of the n-type column region of a conventional semiconductor device. Figure 2 and Figure 3 In the figure, (a) shows a state where the substitution site is substituted with an n-type impurity, and (b) shows a state where no n-type impurity is introduced.

[0032] like Figure 2 As shown, in the semiconductor device 10 , silicon vacancies are substituted with phosphorus, and carbon vacancies are substituted with nitrogen. Figure 2 In the example, three silicon vacancies are replaced with phosphorus, and two carbon vacancies are replaced with nitrogen. Phosphorus substitution for silicon vacancies converts n-type column region 24 to n-type. Nitrogen substitution for carbon vacancies also converts n-type column region 24 to n-type.

[0033] Furthermore, in the semiconductor device 10, the concentration of phosphorus in the n-type column region 24 (atoms / cm -3 ) and nitrogen concentration (atoms / cm -3 ) is adjusted so that the ratio (i.e., doping concentration ratio) becomes 1:9 to 9:1. In addition, a semiconductor region (n-type column region 24) in which silicon vacancies are replaced by phosphorus and carbon vacancies are replaced by nitrogen is provided in a portion of the semiconductor substrate 14. In other words, the crystal structure ( Figure 2 The crystal structure shown in (a) exists only in the n-type column region 24 , and does not exist in the source region 8 , the body region 6 , the p-type column region 22 , and the drain region 26 , for example.

[0034] like Figure 3 As shown, in conventional semiconductor devices, only carbon vacancies are replaced by nitrogen, and silicon vacancies are not replaced. Figure 3 In the conventional semiconductor device, the n-type column region is converted to n-type by replacing carbon vacancies with nitrogen.

[0035] As described above, in both semiconductor device 10 and conventional semiconductor devices, vacancies at five locations are replaced with impurities (phosphorus and nitrogen). Therefore, the impurity concentrations in the n-type column regions of semiconductor device 10 and conventional semiconductor devices are approximately the same. However, semiconductor device 10 replaces carbon vacancies at two locations with nitrogen, whereas conventional semiconductor devices replace carbon vacancies at five locations with nitrogen. Therefore, in the case of conventional semiconductor devices, when nitrogen ions are implanted into the SiC semiconductor, carbon vacancies tend to become insufficient, and therefore the nitrogen doping concentration (usage amount) needs to be increased compared to semiconductor device 10. As a result, crystal defects are more likely to occur in the SiC semiconductor in conventional semiconductor devices. In other words, crystal defects are less likely to occur in the SiC semiconductor (in the n-type column region 24) in semiconductor device 10 than in conventional semiconductor devices.

[0036] Other advantages of the semiconductor device 10 are described. As described above, the semiconductor device 10 is less likely to produce crystal defects in the SiC semiconductor than conventional semiconductor devices. As a result, the semiconductor device 10 can suppress the occurrence of electrical characteristic degradation such as an increase in on-resistance. That is, the semiconductor device 10 can adjust the impurity concentration in the semiconductor substrate 14 (p-type column region 22) while suppressing specific degradation of the device. In addition, nitrogen has a higher ionization energy than phosphorus. Therefore, the beam current of nitrogen ion implantation is lower than that of phosphorus ion implantation, and the ion implantation time is longer. If the ion implantation time is longer, the replacement cycle of the components (consumable components) of the manufacturing device (ion implantation device) is shortened. As a result, the manufacturing cost of the semiconductor device increases. The semiconductor device 10 can extend the replacement cycle of the components of the manufacturing device and can also reduce the manufacturing cost.

[0037] (Method for Manufacturing Semiconductor Device: First Embodiment)

[0038] Reference Figure 4 The following describes a method for manufacturing semiconductor device 10. As described above, source region 8, body region 6, drain region 26, and p-type column region 22 are formed by ion implanting n-type or p-type impurities into semiconductor substrate 14. These ion implantation techniques are well known, so their description will be omitted. The following describes only the method for fabricating n-type column region 24 (drift region 23).

[0039] First, silicon source gas, carbon source gas, and nitrogen source gas are supplied onto the substrate to epitaxially grow a SiC growth layer containing nitrogen as an impurity on the substrate (film formation process: step S2). Supplying the nitrogen source gas forms an n-type SiC growth layer in which carbon vacancies are replaced by nitrogen.

[0040] Next, phosphorus is ion-implanted into the SiC growth layer as an impurity (ion implantation step: step S4). The concentration of the nitrogen source gas and the phosphorus concentration (doping concentration) are adjusted so that the concentration of phosphorus to nitrogen in the SiC growth layer is 1:9 to 9:1.

[0041] Next, the substrate and the SiC growth layer are heated and annealed (annealing process: step S6). In the annealing process, the substrate and the SiC growth layer are heated at a temperature that activates phosphorus and nitrogen. By performing the annealing process, silicon vacancies are replaced by phosphorus, forming a silicon vacancy with Figure 2 (a) shows an n-type semiconductor (n-type SiC semiconductor) with a crystal structure.

[0042] According to the above manufacturing method, compared to, for example, an n-type SiC semiconductor in which only carbon vacancies are replaced by nitrogen, a carbon vacancy deficiency can be suppressed. Therefore, the doping concentration during ion implantation can be suppressed, and the generation of crystal defects in the n-type column region 24 (drift region 23) can be suppressed. Furthermore, in this embodiment, carbon is an example of a first element, silicon is an example of a second element, nitrogen is an example of a third element, and phosphorus is an example of a fourth element. Furthermore, in the technology disclosed in this specification, the first element, the second element, the third element, and the fourth element are different elements.

[0043] Furthermore, as a modification of this embodiment, silicon source gas, carbon source gas, and phosphorus source gas may be used in the film forming process, and nitrogen may be ion-implanted in the ion implantation process. In this case, by performing the annealing process, a film having Figure 2 (a) shows an n-type semiconductor (n-type SiC semiconductor) having a crystal structure. In this modification, silicon is an example of the first element, carbon is an example of the second element, phosphorus is an example of the third element, and nitrogen is an example of the fourth element.

[0044] (Method for Manufacturing a Semiconductor Device: Second Embodiment)

[0045] Reference Figure 5 A description will be given of another method for manufacturing the semiconductor device 10. In this embodiment, only the method for manufacturing the n-type column region 24 (drift region 23) will be described.

[0046] First, an i-type SiC substrate (semiconductor substrate) is prepared, and nitrogen is ion-implanted into the SiC substrate as an impurity (first ion implantation step: step S12). Next, phosphorus is ion-implanted into the SiC substrate as an impurity (second ion implantation step: step S14). In the second ion implantation step, phosphorus is ion-implanted into the same area as the area where nitrogen was implanted in the first ion implantation step. Furthermore, in the first and second ion implantation steps, the nitrogen and phosphorus concentrations (doping concentrations) are adjusted to a ratio of 1:9 to 9:1.

[0047] Next, the SiC substrate is annealed (annealing process: step S16). In the annealing process, the SiC substrate is heated at a temperature at which phosphorus and nitrogen are activated. By performing the annealing process, silicon vacancies are replaced by phosphorus and carbon vacancies are replaced by nitrogen, thereby forming a SiC substrate having Figure 2 (a) shows an n-type semiconductor (n-type SiC semiconductor) with a crystal structure.

[0048] In this manufacturing method, for example, compared to an n-type SiC semiconductor in which only carbon vacancies are replaced by nitrogen, the lack of carbon vacancies can be suppressed. Therefore, in this manufacturing method, the doping concentration during ion implantation can be suppressed, and the generation of crystal defects in the n-type column region 24 (drift region 23) can be suppressed. In this embodiment, carbon is an example of a first element, silicon is an example of a second element, nitrogen is an example of a third element, and phosphorus is an example of a fourth element.

[0049] Furthermore, in this embodiment, the order of step S12 and step S14 is arbitrary, and step S12 may be performed after step S14. In this case, step S14 is the first ion implantation process, step S12 is the second ion implantation process, silicon is an example of the first element, carbon is an example of the second element, phosphorus is an example of the third element, and nitrogen is an example of the fourth element.

[0050] Furthermore, an n-type or p-type SiC substrate may be used instead of an i-type SiC substrate in step S12. When an n-type SiC substrate is used in step S12, a SiC substrate having an impurity concentration lower than the target impurity concentration (the impurity concentration of the n-type column region 24) is used.

[0051] Furthermore, in the above embodiment, compound semiconductors such as gallium nitride (GaN) and gallium arsenide (GaAs) can also be used instead of SiC. In other words, in the technology disclosed in this specification, the type of compound semiconductor is arbitrary as long as it has two or more substitution sites.

[0052] In the above embodiments, a semiconductor device in which the crystal structure of an n-type column region is replaced by two impurities that convert a compound semiconductor to n-type. However, the technology disclosed in this specification can also be applied to a semiconductor device in which the crystal structure of a p-type column region is replaced by two impurities that convert a compound semiconductor to p-type. Alternatively, the technology can also be applied to a semiconductor device in which the crystal structure of an n-type column region is replaced by two impurities that convert a compound semiconductor to n-type, and the crystal structure of a p-type column region is replaced by two impurities that convert a compound semiconductor to p-type.

[0053] Furthermore, when both the n-type column region and the p-type column region are substituted with two types of impurities, the method described in the first embodiment may be used to manufacture both the n-type column region and the p-type column region. Alternatively, the method described in the second embodiment may be used to manufacture both the n-type column region and the p-type column region. Alternatively, one of the n-type column region and the p-type column region may be manufactured using the method described in the first embodiment, and the other may be manufactured using the method described in the second embodiment.

[0054] Furthermore, the technology disclosed in this specification can also be applied to semiconductor regions other than the n-type column region and the p-type column region (eg, the body region).

[0055] In the above embodiments, a planar-gate MOSFET is described. However, the technology disclosed in this specification is applicable to a variety of semiconductor devices, including, for example, trench-gate MOSFETs, planar-gate or trench-gate IGBTs (insulated-gate bipolar transistors), and the like. Furthermore, it is also applicable to semiconductor devices that do not have a superjunction structure.

[0056] The specific examples of the present invention have been described in detail above, but these examples are merely illustrative and do not limit the scope of the patent claims. The technology described in the scope of the patent claims includes various modifications and changes to the specific examples illustrated above. In addition, the technical elements described in this specification or the drawings are technical elements that exert technical usefulness alone or through various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings is a technology that achieves multiple purposes at the same time. As long as one of the purposes is achieved, it itself has technical usefulness.

Claims

1. A compound semiconductor having a crystal structure containing a first element and a second element, wherein: The crystal structure contains a third element that partially replaces the first element to change the compound semiconductor to the first conductivity type, and a fourth element that partially replaces the second element to change the compound semiconductor to the first conductivity type.

2. The compound semiconductor according to claim 1, wherein In the crystal structure, a doping concentration ratio of the third element to the fourth element is 1:9 to 9:

1.

3. The compound semiconductor according to claim 1, wherein The first element is Si, and the second element is C.

4. A semiconductor device, wherein: The semiconductor region composed of the compound semiconductor according to any one of claims 1 to 3 is provided in a portion of a semiconductor substrate.

5. A manufacturing method, which is a method for manufacturing a compound semiconductor, comprising: a film forming step of forming a growth layer having a crystal structure including a first element and a second element and containing, as an impurity, a third element that can partially substitute for the first element and change the compound semiconductor to the first conductivity type; an ion implantation step of implanting a fourth element, which can partially replace the second element and change the compound semiconductor to the first conductivity type, into the growth layer formed by the film formation step; and An annealing step is performed to form the compound semiconductor by heating the growth layer after the ion implantation step.

6. A manufacturing method, which is a method for manufacturing a compound semiconductor, comprising: a first ion implantation step of implanting, into a predetermined area of a semiconductor substrate having a crystal structure containing a first element and a second element, a third element that can partially replace the first element and change the compound semiconductor to the first conductivity type; a second ion implantation step of implanting a fourth element that partially replaces the second element and changes the compound semiconductor to the first conductivity type into the predetermined range where the third element was implanted in the first ion implantation step; and An annealing step is performed by heating the semiconductor substrate after the second ion implantation step to form the compound semiconductor.

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