Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: forming a substrate, a fin part located on the substrate, and a cover layer located on the fin part; and processing the fin part and the cover layer by adopting an oxygen plasma enhanced atomic layer deposition process to form a gate oxide layer with a first gate oxide part and a second gate oxide part, and the thickness of the first gate oxide part is greater than that of the second gate oxide part. The method has the advantages that the gate oxide layer is formed by the oxygen plasma enhanced atomic layer deposition process, the problem of electrical drift caused by doped atom diffusion due to high temperature can be reduced, the gate oxide layer is not formed by directly oxidizing the fin part, and the consumption of the fin part can be reduced. The thickness of the first gate oxide part formed on the top surface of the fin part is large, and the protection effect on the fin part can be effectively enhanced through the first gate oxide part. The thickness of the second gate oxide parts formed on the surfaces of the side walls of the fin parts is small, so that the distance between the adjacent fin parts is large, a material filling window of the gate layer is enlarged, and the performance of the device structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the gradual advancement of semiconductor process technology, semiconductor process nodes continue to shrink in line with Moore's Law. To adapt to this shrinking process node, the channel length of MOSFETs needs to be continuously shortened. This shortening of the channel length has the benefits of increasing chip die density and increasing the switching speed of MOSFETs.

[0003] However, as the device channel length shortens, the distance between the device source and drain also shortens. As a result, the gate's ability to control the channel deteriorates, making subthreshold leakage (SCE) more likely to occur, increasing the transistor's channel leakage current.

[0004] To meet the requirements of device scaling down, overcome the short-channel effect of transistors, and suppress leakage current, semiconductor processes have gradually begun to transition from planar transistors to more efficient three-dimensional transistors, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate can control the ultra-thin body (fin) from at least two sides. Compared with planar transistors, the gate has stronger control over the channel and can effectively suppress the short-channel effect. Furthermore, compared with other devices, FinFETs have better compatibility with existing integrated circuit manufacturing.

[0005] However, the prior art FinFETs still have many problems. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the device structure.

[0007] To solve the above problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate having a fin; a gate oxide layer located on the surface of the fin, the gate oxide layer comprising a first gate oxide portion and a second gate oxide portion, the first gate oxide portion being located on the top surface of the fin, the second gate oxide portion being located on the sidewall surface of the fin, and the thickness of the first gate oxide portion being greater than the thickness of the second gate oxide portion.

[0008] Optionally, the thickness of the first gate oxide portion is 1 nanometer to 5 nanometers.

[0009] Optionally, the thickness of the second gate oxide portion is 1 nanometer to 5 nanometers.

[0010] Optionally, the material of the gate oxide layer includes silicon oxide.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing an initial substrate; forming an initial capping layer on the top surface of the initial substrate; etching the initial capping layer and the initial substrate so that the initial substrate forms a substrate and a fin located on the substrate, and the initial capping layer forms a capping layer located on the top surface of the fin; processing the fin and the capping layer using an oxygen plasma enhanced atomic layer deposition process to form a gate oxide layer on the surface of the fin, the gate oxide layer comprising a first gate oxide portion and a second gate oxide portion, the first gate oxide portion being formed on the top surface of the fin, a portion of the first gate oxide portion being formed by oxidation of the capping layer, the second gate oxide portion being formed on the sidewall surface of the fin, and the thickness of the first gate oxide portion being greater than the thickness of the second gate oxide portion.

[0012] Optionally, the oxygen plasma enhanced atomic layer deposition process has an oxidation rate for the cap layer that is greater than an oxidation rate for the fin.

[0013] Optionally, the material of the cap layer includes: polysilicon or amorphous silicon.

[0014] Optionally, the thickness of the cover layer is 1 nanometer to 5 nanometers.

[0015] Optionally, the thickness of the first gate oxide portion is 1 nanometer to 5 nanometers.

[0016] Optionally, the thickness of the second gate oxide portion is 1 nanometer to 5 nanometers.

[0017] Optionally, the material of the gate oxide layer includes silicon oxide.

[0018] Optionally, the process of forming the initial capping layer on the top surface of the initial substrate includes: a chemical vapor deposition process.

[0019] Optionally, the method for etching the initial cap layer and the initial substrate includes: forming a mask layer on the top surface of the initial cap layer; forming a photoresist layer on the top surface of the mask layer; exposing and developing the photoresist layer to expose a portion of the top surface of the mask layer; etching the mask layer using the photoresist layer as a mask until the top surface of the initial cap layer is exposed; removing the photoresist layer, and etching the initial cap layer and the initial substrate using the mask layer as a mask to form the substrate, the fin and the cap layer; after forming the substrate, the fin and the cap layer, removing the mask layer.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the semiconductor structure of the present invention, the first gate oxide region located on the top surface of the fin is relatively thick. During the subsequent formation of the gate layer, the thick first gate oxide region effectively enhances the protection of the fin, thereby improving the performance of the device structure. Furthermore, the second gate oxide region located on the sidewalls of the fin is relatively thin, thereby increasing the spacing between adjacent fins and thereby increasing the filling of the material forming the gate layer, thereby improving the performance of the device structure.

[0022] In the method for forming a semiconductor structure of the technical solution of the present invention, a low-temperature oxygen plasma enhanced atomic layer deposition process is used to form the gate oxide layer, which can reduce the electrical drift problem caused by the diffusion of dopant atoms caused by high temperature. Moreover, the gate oxide layer is not formed by directly oxidizing the fin itself, which can reduce the consumption of the fin to improve the performance of the device structure. The thickness of the first gate oxide portion formed on the top surface of the fin is relatively large. In the subsequent process of forming the gate layer, the use of the first gate oxide portion with a larger thickness can effectively enhance the protection of the fin to improve the performance of the device structure. In addition, the thickness of the second gate oxide portion formed on the sidewall surface of the fin is relatively small, so that the distance between adjacent fins is larger, thereby increasing the filling window of the material forming the gate layer to improve the performance of the device structure.

[0023] Furthermore, the capping layer has a thickness of 1 to 5 nanometers, with the thickness of the capping layer being perpendicular to the top surface of the fin. When the capping layer is less than 1 nanometer thick, the thickness of the first gate oxide formed after oxidation of the capping layer is also relatively small, thereby weakening the protective ability of the first gate oxide for the fin. When the capping layer is greater than 5 nanometers thick, the capping layer is too thick to guarantee that it will be fully oxidized during the oxidation process. If the capping layer is not fully oxidized, the capping layer remaining on the fin will not be made of single-crystal silicon, thereby affecting the performance of the device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural diagram of a semiconductor structure;

[0025] Figures 2 to 5 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background art, the prior art FinFETs still have many problems, which will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 It is a structural diagram of a semiconductor structure.

[0028] Please refer to Figure 1 Currently, the industry generally uses thermal oxidation to grow the gate oxide layer 101 on the fin 100. This involves directly oxidizing the surface of the fin 100 using O2 or a mixture of H2 and O2 at high temperatures. The gate oxide layer 101 formed by thermal oxidation has excellent thermal stability and interface state. However, high temperatures can cause dopant atoms to diffuse, leading to electrical drift. Furthermore, direct oxidation of the fin 100 by thermal oxidation can cause unnecessary wear and tear on the fin 100.

[0029] In addition, during the gate patterning process, a plasma etching process is required. During this process, the top of the fin 100 will be bombarded by directional plasma, making it vulnerable to damage. Therefore, by thickening the gate oxide layer 101 formed on the top of the fin 100, its protective effect can be enhanced. On the other hand, due to electrical properties and the gate material filling process window, if the gate oxide layer 101 on the sidewalls of the fin 100 is thick, the spacing between adjacent fins 100 will be reduced, which in turn affects the filling of the gate material. Therefore, the gate oxide layer 101 on the sidewalls of the fin 100 cannot be thickened. However, the gate oxide layer 101 formed on the fin 100 by thermal oxidation is of uniform thickness, making it difficult to achieve this morphology.

[0030] On this basis, the present invention provides a semiconductor structure and a method for forming the same, which uses a low-temperature oxygen plasma enhanced atomic layer deposition process to form the gate oxide layer, which can reduce the electrical drift problem caused by the diffusion of dopant atoms due to high temperature, and the gate oxide layer is not formed by directly oxidizing the fin itself, which can reduce the consumption of the fin to improve the performance of the device structure. The thickness of the first gate oxide portion formed on the top surface of the fin is relatively large. In the subsequent process of forming the gate layer, the use of the first gate oxide portion with a larger thickness can effectively enhance the protection of the fin to improve the performance of the device structure. In addition, the thickness of the second gate oxide portion formed on the sidewall surface of the fin is relatively small, so that the distance between adjacent fins is larger, thereby increasing the filling window of the material forming the gate layer to improve the performance of the device structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 2 to 5 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 2 , providing an initial substrate 200.

[0034] In this embodiment, the material of the initial substrate 200 is single crystal silicon.

[0035] In other embodiments, the material of the initial substrate may also be germanium, silicon germanium, or silicon carbide; or the substrate may also be other materials, such as III-V compounds such as gallium arsenide.

[0036] Please refer to Figure 3 , forming an initial capping layer 201 on the top surface of the initial substrate 200 .

[0037] The initial capping layer 201 is a basic material layer for subsequent oxidation to form a gate oxide layer. The initial capping layer 201 is a semiconductor material, and the initial capping layer 201 needs to have an oxidation rate faster than that of single crystal silicon to ensure that the gate oxide layer subsequently formed on the top surface of the fin has a greater thickness than the side wall surface.

[0038] The material of the initial cap layer 201 includes polycrystalline silicon or amorphous silicon. Since the gaps between polycrystalline silicon and amorphous silicon are larger than those between single crystal silicon, oxygen plasma can penetrate deeper into the polycrystalline silicon at the same energy, thus having a faster oxidation rate.

[0039] In this embodiment, the material of the initial capping layer 201 is amorphous silicon.

[0040] In this embodiment, the process of forming the initial capping layer 201 on the top surface of the initial substrate 200 adopts a chemical vapor deposition process.

[0041] Please refer to Figure 4 The initial capping layer 201 and the initial substrate 200 are etched so that the initial substrate 200 forms a substrate 202 and a fin 203 located on the substrate 202 , and the initial capping layer 201 forms a capping layer 204 located on the top surface of the fin 203 .

[0042] The method for etching the initial cap layer 201 and the initial substrate 200 includes: forming a mask layer (not shown) on the top surface of the initial cap layer 201; forming a photoresist layer (not shown) on the top surface of the mask layer; exposing and developing the photoresist layer to expose a portion of the top surface of the mask layer; etching the mask layer using the photoresist layer as a mask until the top surface of the initial cap layer 201 is exposed; removing the photoresist layer, and etching the initial cap layer 201 and the initial substrate 200 using the mask layer as a mask to form the substrate 202, the fin 203 and the cap layer 204; after forming the substrate 202, the fin 203 and the cap layer 204, removing the mask layer.

[0043] Since the cap layer 204 is formed by etching the initial cap layer 201 , the material of the cap layer 204 is the same as that of the initial cap layer 201 ; and the fin 203 is formed by etching the initial substrate 200 , the material of the fin 203 is the same as that of the initial substrate 200 .

[0044] In this embodiment, the cap layer 204 is made of amorphous silicon.

[0045] In other embodiments, when the material of the initial capping layer is polysilicon, the material of the corresponding capping layer is also polysilicon.

[0046] In this embodiment, the material of the fin 203 is single crystal silicon,

[0047] In other embodiments, when the initial substrate is made of a III-V compound such as germanium, silicon germanium, silicon carbide, or gallium arsenide, the corresponding fin is also made of a III-V compound such as silicon germanium, silicon carbide, or gallium arsenide.

[0048] In this embodiment, the capping layer 204 has a thickness of 1 to 5 nanometers, wherein the thickness of the capping layer 204 is perpendicular to the top surface of the fin 203. When the capping layer 204 is less than 1 nanometer thick, the thickness of the first gate oxide formed after the capping layer 204 is subsequently oxidized is also relatively small, thereby weakening the first gate oxide's ability to protect the fin 203. When the capping layer 204 is greater than 5 nanometers thick, the capping layer 204 is too thick, and there is no guarantee that the capping layer 204 will be fully oxidized during the subsequent oxidation process. If the capping layer 204 is not fully oxidized, the capping layer 204 remaining on the fin 203 will not be made of single crystal silicon, which may affect the performance of the device structure.

[0049] It should be noted that the capping layer 204 is formed by etching the initial capping layer 201 . During this process, the thickness of the initial capping layer 201 will be partially consumed during the etching process. Therefore, the thickness of the deposited initial capping layer 201 is greater than the thickness of the capping layer 204 .

[0050] Please refer to Figure 5 The fin 203 and the cap layer 204 are processed by an oxygen plasma enhanced atomic layer deposition process to form a gate oxide layer 205 on the surface of the fin 203. The gate oxide layer 205 includes a first gate oxide portion 2051 and a second gate oxide portion 2052. The first gate oxide portion 2051 is formed on the top surface of the fin 203, and a portion of the first gate oxide portion 2051 is formed by oxidation of the cap layer 204. The second gate oxide portion 2052 is formed on the sidewall surface of the fin 203, and the thickness of the first gate oxide portion 2051 is greater than the thickness of the second gate oxide portion 2052.

[0051] The gate oxide layer 205 is formed using a low-temperature oxygen plasma enhanced atomic layer deposition process, which can reduce the electrical drift problem caused by the diffusion of dopant atoms caused by high temperature. In addition, the gate oxide layer 205 is not formed by directly oxidizing the fin 203 itself, which can reduce the consumption of the fin 203, thereby improving the performance of the device structure. The first gate oxide portion 2051 formed on the top surface of the fin 203 has a large thickness. In the subsequent process of forming the gate layer, the thick first gate oxide portion 2051 can effectively enhance the protection of the fin 203, thereby improving the performance of the device structure. In addition, the second gate oxide portion 2052 formed on the sidewall surface of the fin 203 has a small thickness, which makes the distance between adjacent fins 203 larger, thereby increasing the filling window of the material forming the gate layer, thereby improving the performance of the device structure.

[0052] It should be noted that the thickness of the first gate oxide portion 2051 is perpendicular to the top surface of the fin 203, while the thickness of the second gate oxide portion 2052 is perpendicular to the sidewall surfaces of the fin 203. Directional oxygen plasma bombarding the cap layer 204 on the top surface of the fin 203 using the oxygen plasma enhanced atomic layer deposition process can easily and completely oxidize the amorphous silicon cap layer 204. The first gate oxide portion 2051 is composed of: the material deposited by the oxygen plasma enhanced atomic layer deposition process itself; the material after oxidation of the cap layer 204; the second gate oxide portion 2052 is composed of: the material deposited by the oxygen plasma enhanced atomic layer deposition process itself; and a small amount of the material after oxidation of the fin 203. Because the oxidation rate of the amorphous silicon cap layer 204 is greater than that of the single crystal silicon fin 203, the thickness of the first gate oxide portion 2051 is greater than that of the second gate oxide portion 2052.

[0053] In this embodiment, the thickness of the first gate oxide portion 2051 is 1 nm to 5 nm.

[0054] In this embodiment, the thickness of the second gate oxide portion 2052 is 1 nm to 5 nm.

[0055] In this embodiment, the gate oxide layer 205 is made of silicon oxide.

[0056] Accordingly, a semiconductor structure is also provided in the embodiment of the present invention, please continue to refer to Figure 5 , comprising: a substrate 202 having a fin 203 thereon; a gate oxide layer 205 located on a surface of the fin 203, the gate oxide layer 205 comprising a first gate oxide portion 2051 and a second gate oxide portion 2052, the first gate oxide portion 2051 being located on a top surface of the fin 203, the second gate oxide portion 2052 being located on a sidewall surface of the fin 203, and the thickness of the first gate oxide portion 2051 being greater than the thickness of the second gate oxide portion 2052.

[0057] The first gate oxide portion 2051 located on the top surface of the fin 203 has a relatively large thickness. During the subsequent formation of the gate layer, the thick first gate oxide portion 2051 can effectively enhance the protection of the fin 203, thereby improving the performance of the device structure. In addition, the second gate oxide portion 2052 located on the sidewall surface of the fin 203 has a relatively small thickness, thereby increasing the spacing between adjacent fins 203 and increasing the filling of the material forming the gate layer, thereby improving the performance of the device structure.

[0058] In this embodiment, the thickness of the first gate oxide portion 2051 is 1 nm to 5 nm.

[0059] In this embodiment, the thickness of the second gate oxide portion 2052 is 1 nm to 5 nm.

[0060] In this embodiment, the gate oxide layer 205 is made of silicon oxide.

[0061] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a fin thereon; A gate oxide layer is located on the surface of the fin, and the gate oxide layer includes a first gate oxide portion and a second gate oxide portion, the first gate oxide portion is located on the top surface of the fin, the second gate oxide portion is located on the sidewall surface of the fin, and the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

2. The semiconductor structure according to claim 1, wherein: The thickness of the first gate oxide portion is 1 nanometer to 5 nanometers.

3. The semiconductor structure according to claim 1, wherein: The thickness of the second gate oxide portion is 1 nanometer to 5 nanometers.

4. The semiconductor structure according to claim 1, wherein: The material of the gate oxide layer includes silicon oxide.

5. A method for forming a semiconductor structure, characterized in that: include: providing an initial substrate; forming an initial capping layer on a top surface of the initial substrate; Etching the initial capping layer and the initial substrate so that the initial substrate forms a substrate and a fin located on the substrate, and the initial capping layer forms a capping layer located on a top surface of the fin; The fin and the cap layer are processed by an oxygen plasma enhanced atomic layer deposition process to form a gate oxide layer on the surface of the fin, wherein the gate oxide layer includes a first gate oxide portion and a second gate oxide portion, wherein the first gate oxide portion is formed on the top surface of the fin, and a portion of the first gate oxide portion is formed by oxidation of the cap layer, and the second gate oxide portion is formed on the side wall surface of the fin, and the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

6. The method for forming a semiconductor structure according to claim 5, wherein: The oxygen plasma enhanced atomic layer deposition process has an oxidation rate for the cap layer that is greater than an oxidation rate for the fin.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the cap layer includes: polysilicon or amorphous silicon.

8. The method for forming a semiconductor structure according to claim 5, wherein: The thickness of the cover layer is 1 nanometer to 5 nanometers.

9. The method for forming a semiconductor structure according to claim 5, wherein: The thickness of the first gate oxide portion is 1 nanometer to 5 nanometers.

10. The method for forming a semiconductor structure according to claim 5, wherein: The thickness of the second gate oxide portion is 1 nanometer to 5 nanometers.

11. The method for forming a semiconductor structure according to claim 5, wherein: The material of the gate oxide layer includes silicon oxide.

12. The method for forming a semiconductor structure according to claim 5, wherein: The process of forming the initial capping layer on the top surface of the initial substrate includes: a chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 5, wherein: The method for etching the initial cap layer and the initial substrate includes: forming a mask layer on the top surface of the initial cap layer; forming a photoresist layer on the top surface of the mask layer; exposing and developing the photoresist layer to expose a portion of the top surface of the mask layer; etching the mask layer using the photoresist layer as a mask until the top surface of the initial cap layer is exposed; removing the photoresist layer, and etching the initial cap layer and the initial substrate using the mask layer as a mask to form the substrate, the fin and the cap layer; after forming the substrate, the fin and the cap layer, removing the mask layer.

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