Semiconductor device

Abstract

The invention provides a semiconductor device, which prevents the contact resistance between an alloy layer formed on a semiconductor layer and a metal layer formed on the alloy layer from deteriorating, and reduces the adhesion strength between the alloy layer and a metal film. A semiconductor device is provided with: a semiconductor substrate (10); an alloy layer (20) containing, as a main component, constituent elements of the semiconductor substrate (10); and an upper metal layer (30) formed on the alloy layer (20). A plurality of minute regions (31) containing an inert gas are discretely disposed at the interface between the alloy layer (20) and the upper metal layer (30). 90% or more of the plurality of minute regions (31) have an arc shape in which the opening is widest.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] For example, Patent Document 1 below discloses a technique for forming a silicide layer on a semiconductor substrate by using a metal, such as Co, which forms a silicide with a high metal composition during an initial silicide reaction as a barrier metal to suppress the formation of voids caused by Ar gas being drawn into the silicide film. This technique prevents deterioration in the contact resistance between the silicide film and the electrode formed thereon.

[0003] Furthermore, for example, the following Non-Patent Document 1 reports a phenomenon in which inert gas elements contained in a metal film aggregate by heat treatment to form voids.

[0004] Patent Document 2 below discloses a technique for forming a recessed portion in the shape of a keyhole (a shape in which the entrance is narrower than the internal space) on the surface of an electrode in cross-section, thereby increasing the bonding strength between the electrode and an upper electrode thereon by an anchoring effect.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2001-223178

[0006] Patent Document 2: International Publication No. 2021 / 246241

[0007] Non-patent literature 1: Peter Hatton, et al., "Inert gas bubble formation inmagnetron sputtered thin-film CdTe solar cells", Proc. Of the royal soc. A, vol. 476, issue 2239

[0008] The technology of Patent Document 1 forms a uniform and dense silicide film at the contact portion between the semiconductor substrate and the electrode, thereby improving the adhesion strength between the semiconductor substrate and the electrode. However, if the adhesion strength between the semiconductor substrate and the electrode is too high, damage caused by external stress can easily spread to the active cells of the semiconductor substrate, causing serious accidents such as short circuit damage. Summary of the Invention

[0009] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to prevent the deterioration of the contact resistance between the alloy layer formed on the semiconductor layer and the metal layer thereon, and to relax the adhesion strength between the alloy layer and the metal film.

[0010] The semiconductor device involved in the present disclosure comprises: a semiconductor substrate; an alloy layer, which contains the constituent elements of the above-mentioned semiconductor substrate as a main component; and an upper metal layer, which is formed on the above-mentioned alloy layer, and a plurality of tiny regions containing inert gas are discretely arranged at the interface between the above-mentioned alloy layer and the above-mentioned upper metal layer, and more than 90% of the multiple tiny regions have an arc shape with the widest opening.

[0011] According to the present disclosure, it is possible to prevent the deterioration of the contact resistance between the alloy layer formed on the semiconductor layer and the metal layer thereon (upper metal layer) and to relax the adhesion strength between the alloy layer and the metal film. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing the basic structure of a contact portion of the semiconductor device according to the first embodiment.

[0013] Figure 2 (a) to (c) are diagrams for explaining a method for forming a contact portion of the semiconductor device according to the first embodiment.

[0014] Figure 3 (a) to (c) are diagrams for explaining a method for forming a contact portion of the semiconductor device according to the first embodiment.

[0015] Figure 4 This is a diagram showing a specific example of the contact portion of the semiconductor device according to the first embodiment.

[0016] Figure 5 This is a diagram showing an atomic number comparison image of a contact portion of the semiconductor device according to the first embodiment.

[0017] Figure 6 This figure shows an atomic number comparison image of a conventional contact portion without a micro region.

[0018] Figure 7 yes Figure 5 A magnified view of a small area in the atomic number contrast image.

[0019] Figure 8 This is a diagram showing an elemental map image of Si in the contact portion of the semiconductor device according to the first embodiment.

[0020] Figure 9 This is a diagram showing an elemental map image of Ar in the contact portion of the semiconductor device according to the first embodiment.

[0021] Figure 10 This is a diagram showing an EDX spectrum of a contact portion of the semiconductor device according to the first embodiment.

[0022] Figure 11This is a diagram showing the structure of a contact portion of the semiconductor device according to the first embodiment.

[0023] Description of Reference Numerals

[0024] 10…semiconductor substrate; 20…alloy layer; 21…metal film; 30…upper metal layer; 31…micro region; 40…upper metal layer; 41…lower metal layer; 42…upper metal layer; 50…interlayer insulating film. DETAILED DESCRIPTION

[0025] <Implementation Method 1>

[0026] Figure 1 FIG. 1 is a diagram showing the basic structure of the contact portion of the semiconductor device according to the first embodiment. Figure 1 As shown, the “contact portion” in this embodiment refers to a portion where the semiconductor substrate 10 and the upper metal layer 30 are connected via the alloy layer 20 .

[0027] The semiconductor substrate 10 includes, for example, Si, SiC, or a compound containing Ga as a constituent element. The alloy layer 20 is formed on the upper surface of the semiconductor substrate 10 and is composed of an alloy containing the constituent elements of the semiconductor substrate 10 as a main component. When the semiconductor substrate 10 is a wide-bandgap semiconductor such as SiC or GaN, a semiconductor device can be obtained that operates better at high voltages, high currents, and high temperatures than when using silicon.

[0028] An n-type layer or p-type layer containing a donor or an acceptor as a dopant may be selectively formed on the surface of the semiconductor substrate 10. The alloy layer 20 may be in contact with the n-type layer or the p-type layer, or both, formed on the semiconductor substrate 10. Furthermore, the alloy layer 20 may be formed by alloying the surface of the n-type layer or the p-type layer, or both, formed on the semiconductor substrate 10.

[0029] The alloy layer 20 is formed by depositing a metal film (equivalent to the "metal film 21" described later) on the semiconductor substrate 10 using, for example, sputtering or chemical vapor deposition (CVD), and then alloying the metal film and the semiconductor substrate 10 by chemical reaction through heat treatment. Therefore, the alloy layer 20 mainly contains the constituent elements of the semiconductor substrate 10 and the constituent elements of the metal film before alloying. The metal film before alloying can be considered to contain, for example, Ti, Ni, Co, etc. as its main component. When the semiconductor substrate 10 is Si or SiC, the alloy layer 20 is preferably a silicide compound.

[0030] The upper metal layer 30 is formed on the alloy layer 20. The upper metal layer 30 is composed of, for example, Ti, Ni, W, Cu, Al, or an alloy containing one or more of these (e.g., TiN), and is formed, for example, by sputtering or CVD. Above the upper metal layer 30, another upper metal layer composed of a different composition from the upper metal layer 30 may be provided. Furthermore, a stacked structure may be formed in which a metal composed of a different composition or a metal of the same type as the upper metal layer 30 is further stacked on the upper metal layer 30.

[0031] A plurality of tiny regions 31 containing an inert gas are discretely formed at the interface between the alloy layer 20 and the upper metal layer 30. The tiny regions 31 have a shape that erodes the alloy layer 20, i.e., a shape that enters the alloy layer 20 side from the interface between the alloy layer 20 and the upper metal layer 30. In addition, the tiny regions 31 are in the shape of an arc with the widest opening when viewed in cross section. By discretely forming tiny regions 31 of this shape between the alloy layer 20 and the upper metal layer 30, the contact resistance between the alloy layer 20 and the upper metal layer 30 can be prevented from deteriorating, and the adhesion strength between the alloy layer 20 and the upper metal layer 30 can be relaxed. The inert gas can be Ar, N2, or other rare gas elements.

[0032] Here, as Figure 1 As shown, the depth of the microregion 31 is defined as t1, the width of the microregion 31 is defined as w1, and the thickness of the alloy layer 20 is defined as t2. The thickness t2 of the alloy layer 20 is preferably, for example, greater than 10 nm and less than 50 nm. The depth t1 of the microregion 31 is preferably, for example, greater than 5 nm and less than t2. The width w1 of the microregion 31 is preferably, for example, greater than 5 nm and less than 100 nm. Preferably, at least 90% of the microregions 31 have an arc shape with the widest opening when viewed in cross-section.

[0033] In the semiconductor device, the upper metal layer 30 is used as an electrode electrically connected to the semiconductor substrate 10 via the alloy layer 20. For example, when the semiconductor device is a semiconductor device for power control (so-called power device), the adhesion strength of the electrode may become an important design parameter in stress tests such as power cycle (P / C) tests and heat cycle (H / C) tests.

[0034] If the adhesion strength of the upper metal layer 30, which serves as an electrode, is too low, the upper metal layer 30 will peel off during the stress test, reducing the life of the semiconductor device. However, if the adhesion strength of the upper metal layer 30 is too high, the damage during the stress test will not extend to the interface between the upper metal layer 30 and the alloy layer 20, but will extend to the interior of the semiconductor substrate 10. The damage inside the semiconductor substrate 10 sometimes causes the semiconductor device to short-circuit. For example, if a semiconductor device with a voltage of several hundred to several thousand volts is short-circuited, it will cause significant damage to the entire system equipped with the semiconductor device.

[0035] By applying the contact structure of Embodiment 1 to the electrodes of a semiconductor device, the adhesion strength of the electrodes can be controlled. By controlling the adhesion strength of the electrodes within a desired range, damage can be prevented at the interface between the alloy layer 20 and the upper metal layer 30 without compromising the life of the device during stress testing, thereby suppressing short circuits in the semiconductor device.

[0036] Conventionally, the problem has been that the contact resistance of the upper metal layer 30 deteriorates due to the formation of voids in the alloy layer 20. Since it is difficult to control the composition, shape, and size of the voids, it has been considered that the voids should be completely eliminated.

[0037] The inventors of the technology disclosed herein have succeeded in discretely arranging minute regions 31 , which are different from voids, at the interface between the alloy layer 20 and the upper metal layer 30 through detailed analysis of semiconductor manufacturing processes.

[0038] As more preferable parameters for controlling the adhesion strength without degrading the contact resistance of the upper metal layer 30, the thickness t2 of the alloy layer 20 is preferably 30 nm or greater, the width w1 of the microregion 31 is less than 100 nm, and the depth t1 of the microregion 31 is less than t2. Furthermore, the occupancy rate of the microregion 31 at the interface between the alloy layer 20 and the upper metal layer 30 is preferably less than 50%. The atomic concentration of the inert gas in the microregion 31 is preferably 0.5 wt% or greater and less than 20.0 wt%, and the atomic density of the constituent elements of the alloy layer 20 in the microregion 31 is preferably 80.0 wt% or greater.

[0039] The atomic concentration of the micro region 31 can be a value quantitatively evaluated by a general elemental analysis method such as EDX (Energy dispersive X-ray spectroscopy). In elemental analysis, when the evaluation region is small, such as on the order of nm, it is conceivable that a value including regions other than the evaluation target will be output. However, as will be shown later, Figure 8 、 Figure 10 In that way, there is no problem as long as the elements in the micro area 31 can be detected.

[0040] If the width w1 of the microregion 31 is too wide, the actual thickness of the alloy layer 20 is reduced, resulting in poor contact resistance. Furthermore, if the depth t1 of the microregion 31 is too large, the upper metal layer 30 and the semiconductor substrate 10 cannot achieve good ohmic contact, which also results in poor contact resistance. Furthermore, if the occupancy rate of the microregion 31 is too high, similar to the case where the width w1 of the microregion 31 is too wide, the actual thickness of the alloy layer 20 is reduced, resulting in poor contact resistance.

[0041] Furthermore, if the microregions 31 are not formed at the interface between the alloy layer 20 and the upper metal layer 30, the adhesion strength of the upper metal layer 30 becomes high, and damage is likely to propagate toward the semiconductor substrate 10 during a stress test. Furthermore, even if the microregions 31 are in the shape of a keyhole, such as the recessed portion disclosed in Patent Document 2, the adhesion strength of the upper metal layer 30 becomes excessively high due to the anchoring effect, and damage is likely to propagate toward the semiconductor substrate 10 during a stress test. Therefore, it is important to control the width, depth, density, shape, and position of the microregions 31 within a preferred range.

[0042] Figure 2 (a) to (c) show the method for manufacturing the semiconductor device according to the first embodiment, and particularly the method for forming a contact portion.

[0043] First, if Figure 2 As shown in (a), a metal film 21 that becomes the material of the alloy layer 20 is formed on the semiconductor substrate 10 by using a sputtering method or a CVD method. Then, by performing a heat treatment, the semiconductor substrate 10 and the metal film 21 chemically react to form the alloy layer 20. At this time, by using the following method, Figure 2 As shown in (b), micro regions 31 can be formed on the surface of the alloy layer 20 .

[0044] Here, the case of forming the metal film 21 by sputtering is described. Generally, the sputtering method is a film forming method in which an inert gas is filled into a chamber at a certain ratio, the inert gas is converted into plasma, and the plasma is caused to collide with the target metal, physically cutting the bonds between the atoms of the target metal, thereby ionizing (activating) the metal atoms and depositing them on the semiconductor substrate 10. The metal film 21 deposited on the semiconductor substrate 10 contains not only the desired metal ions, but also a trace amount of inert gas ions converted into plasma. In existing manufacturing methods, the content of these inert gas ions is small, and they evaporate and disappear during the heat treatment used to alloy the metal film 21, or they are not condensed but are absorbed into the alloy layer 20.

[0045] In this embodiment, by increasing the concentration of the inert gas contained in the metal film 21 before alloying, as shown in FIG. Figure 2As shown in (b), a micro region 31 is formed on the surface of the alloy layer 20. In the micro region 31, the mass percentage concentration of the atoms constituting the alloy layer 20 is low, and the content of the inert gas is high. In other words, the micro region 31 is a rough area where the atomic density is reduced due to the condensation of the inert gas during the heat treatment.

[0046] Then, if Figure 2 As shown in (c), a metal film is deposited on the alloy layer 20 including the minute region 31 to deposit the upper metal layer 30. After the upper metal layer 30 is formed, heat treatment may be performed.

[0047] The alloying of the metal film 21 and the heat treatment for forming the micro region 31 can also be performed after the deposition of the upper metal layer 30. That is, first, as shown in FIG. Figure 3 As shown in (a), a metal film 21 serving as a material for an alloy layer 20 is formed on a semiconductor substrate 10. Next, as shown in FIG. Figure 3 As shown in (b), an upper metal layer 30 is formed on the metal film 21. Then, a heat treatment may be performed, such as Figure 3 As shown in (c), the semiconductor substrate 10 and the metal film 21 are chemically reacted to form the alloy layer 20 , and the micro regions 31 are formed on the surface of the alloy layer 20 .

[0048] The microregions 31 are similar to voids in that they are formed by the aggregation of inert gas elements contained in the metal film 21 before alloying through heat treatment. However, the width, depth, density, position, atomic density, etc. of the microregions 31 are controlled and they are not complete voids.

[0049] The metal film 21 before alloying can also be deposited using CVD. However, unlike sputtering, the inert gas is not absorbed into the metal film 21. Therefore, after the metal film 21 is deposited, it is necessary to introduce the inert gas into the metal film 21 by, for example, ion implantation. Even if the inert gas is introduced after the metal film 21 is deposited, the inert gas will condense and form the microregions 31 if heat treatment is performed.

[0050] Next, a method for controlling the parameters of the micro region 31 will be described. Since the micro region 31 is formed by agglomeration of inert gas atoms, controlling the parameters of the micro region 31 requires controlling the amount of inert gas contained in the metal film 21 before alloying.

[0051] For example, when forming a metal film 21 by sputtering, in order to control the amount of inert gas captured by the metal film 21, it is sufficient to adjust the pressure in the chamber, adjust the plasma density, adjust the voltage at which the active species are introduced into the semiconductor substrate 10, etc. The pressure in the chamber can be adjusted by the flow rate of the inert gas, and it is preferred to adjust the flow rate of the inert gas, for example, within the range of 1 sccm to 100 sccm. The plasma density can be adjusted by a DC bias as one of its adjustment parameters, and it is preferred to adjust the DC bias, for example, within the range of 1 kW to 50 kW. The voltage at which the active species are introduced can be adjusted by an AC bias, and it is preferred to adjust the AC bias, for example, within the range of 1 W to 1 kW. The temperature during film formation is preferably adjusted, for example, within the range of room temperature to 500°C.

[0052] Furthermore, since the thicker the metal film 21 before alloying, the greater the amount of inert gas atoms condensed at the interface, the thicker the metal film 21 is. However, if the metal film 21 is too thick, the resulting alloy layer 20 also becomes thicker, and the alloy layer 20 is formed deeper than the n-type layer or p-type layer of the surface portion of the semiconductor substrate 10, resulting in increased contact resistance. Therefore, the thickness t2 of the alloy layer 20 is preferably, for example, not less than 30 nm and not more than 50 nm.

[0053] Furthermore, the heat treatment conditions after depositing the pre-alloyed metal film 21 may also be important parameters. For example, if the heat treatment is performed at a high temperature and for a long time, the condensation of the inert gas is accelerated, causing the micro-regions 31 to become larger. This, in turn, increases the width and depth of the micro-regions 31, making it impossible to obtain the desired shape. Heat treatment conditions are preferably in the range of 700°C to 900°C and for a time of 10 seconds to 120 seconds.

[0054] By adjusting the above parameters, the parameters of the micro region 31 can be controlled.

[0055] The metal film 21 before alloying can also be deposited using CVD. However, unlike sputtering, no inert gas is introduced during the deposition of the metal film 21. Therefore, after depositing the metal film 21, an inert gas must be introduced, for example, by ion implantation. Even when an inert gas is introduced after depositing the metal film 21, heat treatment causes the inert gas to condense, forming microregions 31.

[0056] Figure 4This is a specific example of the contact portion of the semiconductor device involved in Embodiment 1, schematically showing a cross-section of the emitter (or source) contact of a semiconductor device for power conversion. An interlayer insulating film 50 is formed on a semiconductor substrate 10. A contact hole is formed in the interlayer insulating film 50, reaching the semiconductor substrate 10, and an alloy layer 20 is formed on the surface portion of the semiconductor substrate 10 exposed at the bottom of the contact hole. An upper metal layer 30 is formed on the alloy layer 20, and a micro region 31 is formed at the interface between the alloy layer 20 and the upper metal layer 30. In addition, an upper metal layer 40 is formed on the upper metal layer 30, serving as a contact plug embedded in the contact hole.

[0057] The semiconductor substrate 10 is made of, for example, Si, SiC, or a compound containing Ga. The alloy layer 20 is made of, for example, a silicide compound or an alloy primarily containing the elements of the semiconductor substrate 10. The interlayer insulating film 50 is, for example, a TEOS film, a BPSG film, a thermal oxide film, or a stacked film thereof, and is provided to ensure insulation from the gate electrode (not shown).

[0058] The bottom width of the contact hole formed in the interlayer insulating film 50 ( Figure 4 The bottom width of the contact hole (shown) is, for example, on the submicron scale of 0.2 μm or more and 1.0 μm or less, and the aspect ratio thereof to the thickness of the interlayer insulating film 50 (i.e., the thickness of the interlayer insulating film / the bottom width of the contact hole) is, for example, 1.5 or more. Furthermore, although not shown in the figure, an n-type or p-type emitter layer is selectively formed on the surface portion of the semiconductor substrate 10 at the bottom of the contact hole, and the alloy layer 20 is in contact with the emitter layer.

[0059] Figure 5 Is a Figure 4 Atomic number contrast image of the contact portion of the semiconductor device according to the first embodiment of the structure obtained by cross-sectional TEM. In the atomic number contrast image, the lower the atomic density, the darker the black. Therefore, the micro region 31 is represented as a local dark black region. Figure 5 It can be confirmed that the micro regions 31 are discretely formed. Figure 6 , as a comparative example, an atomic number comparison image of a conventional contact portion without a micro region is shown.

[0060] Figure 7 It will Figure 5 The atomic number comparison image of the micro region 31 is magnified and the size is marked. By adjusting the inert gas elements contained in the metal film 21 before alloying and the heat treatment conditions, a micro region 31 with a reduced atomic concentration of 35nm in width and 10nm in depth was successfully formed. Figure 7 The dimensions of the upper metal layer 30 shown are merely an example.

[0061] Figure 8 and Figure 9 Indicates that Figure 4 Elemental map image of the contact portion of the semiconductor device according to the first embodiment of the structure. Figure 8 is the elemental diagram image of Si, Figure 9 is an elemental image of Ar. The upper metal layer 30 does not contain Si, while the alloy layer 20 and the semiconductor substrate 10 contain Si. Figure 8 In the elemental map image of Si shown, the upper metal layer 30 is depicted with dark contrast. At the boundary between the alloy layer 20 and the upper metal layer 30 (the area surrounded by the white dashed line), a small region 31 where the Si atomic concentration is reduced is locally depicted with dark contrast. Furthermore, bright contrast appears in the portion of the upper metal layer 40 that does not contain Si, but this is confirmed to be caused by background noise from the EDX spectrum.

[0062] On the other hand, Figure 9 In the Ar elemental image shown, a small area 31 where the atomic concentration of Ar increases is locally depicted with bright contrast at the boundary between the alloy layer 20 and the upper metal layer 30 (the area surrounded by the white dotted line). Figure 9 In the figure, it can be confirmed that the bright contrast of the upper metal layer 40 is background noise.

[0063] Figure 10 Yes Figure 8 and Figure 9 The graph shows the raw data of the elemental mapping image, namely the EDX spectrum. The dashed line represents the spectrum of the alloy layer 20 in the portion excluding the microregion 31, while the solid line represents the spectrum of the alloy layer 20 in the portion including the microregion 31. In the portion including the microregion 31, the peak intensity of Si, a constituent element of the alloy layer 20, is approximately 3.1% lower than in the portion not including the microregion 31. Furthermore, Ar, an inert gas element, is significantly detected in the portion including the microregion 31.

[0064] from Figure 8 、 Figure 9 as well as Figure 10 It can be confirmed that the minute region 31 is a region where the concentration of the constituent elements of the alloy layer 20 is low and the atomic concentration of the inert gas is high.

[0065] <Implementation Method 2>

[0066] In the second embodiment, the minute region 31 described in the first embodiment is applied to an electrode formed on the interlayer insulating film 50 .

[0067] Figure 11FIG. 1 is a diagram showing the basic structure of the contact portion of the semiconductor device according to the second embodiment. Figure 11 As shown, the "contact portion" in this embodiment refers to a portion where the lower metal layer 41 formed on the interlayer insulating film 50 is connected to the upper metal layer 42 thereon. The interlayer insulating film 50 is, for example, an oxide film.

[0068] In the contact portion of the semiconductor device according to the second embodiment, a microregion 31 is formed at the interface between the lower metal layer 41 and the upper metal layer 42. Microregion 31 has a shape that erodes the lower metal layer 41, that is, a shape that intrudes from the interface between the lower metal layer 41 and the upper metal layer 42 toward the lower metal layer 41. Preferably, 90% or more of the microregions 31 have an arc shape with the widest opening when viewed in cross-section.

[0069] Furthermore, microregions 31 are arc-shaped, with the opening at its widest point when viewed in cross-section. The width, depth, density, shape, and position of microregions 31 are the same as those in Embodiment 1. However, lower metal layer 41, in which microregions 31 are formed, is formed on interlayer insulating film 50 and is not alloyed with semiconductor substrate 10. Therefore, lower metal layer 41 does not contain any constituent elements of semiconductor substrate 10, and neither do microregions 31. The atomic concentration of the constituent elements of lower metal layer 41 in microregions 31 is preferably 80.0 wt% or greater.

[0070] The micro region 31 can be formed by heat treating the lower metal layer 41 that has been exposed to an inert gas. Figure 2 (a) to (c) and Figure 3 By adjusting the inert gas element contained in the lower metal layer 41 and the conditions of the heat treatment, the width, depth, density, shape, position, etc. of the micro region 31 can be controlled.

[0071] In the second embodiment, the contact resistance between the lower metal layer 41 and the upper metal layer 42 formed on the interlayer insulating film 50 can be prevented from deteriorating, and the adhesion strength therebetween can be relaxed. Even if the electrode on the interlayer insulating film 50 peels off during a stress test, by adjusting the adhesion strength to an appropriate level, the damage can be suppressed from spreading into the interior of the semiconductor substrate 10 without compromising the life of the stress test.

[0072] Furthermore, the various embodiments may be freely combined, or the various embodiments may be appropriately modified or omitted.

[0073] <Note>

[0074] Hereinafter, various aspects of the present disclosure are collectively described as supplementary notes.

[0075] (Note 1)

[0076] A semiconductor device, wherein:

[0077] have:

[0078] semiconductor substrates;

[0079] an alloy layer containing, as a main component, the constituent elements of the semiconductor substrate; and

[0080] The upper metal layer is formed on the alloy layer.

[0081] A plurality of micro regions containing an inert gas are discretely arranged at the interface between the alloy layer and the upper metal layer.

[0082] More than 90% of the plurality of micro regions have an arc shape with the widest opening.

[0083] (Note 2)

[0084] The semiconductor device according to Supplementary Note 1, wherein:

[0085] The atomic concentration of the constituent elements of the alloy layer in the minute region is 80 wt % or more.

[0086] (Note 3)

[0087] The semiconductor device according to Supplementary Note 1 or 2, wherein:

[0088] The thickness of the alloy layer is greater than 30 nm.

[0089] The width of the above-mentioned tiny area is less than 100nm.

[0090] The depth of the micro region is smaller than the thickness of the alloy layer.

[0091] (Note 4)

[0092] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0093] The occupancy rate of the micro region at the interface between the alloy layer and the upper metal layer is less than 50%.

[0094] (Note 5)

[0095] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0096] Also features:

[0097] an interlayer insulating film formed on the semiconductor substrate; and

[0098] a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate;

[0099] The alloy layer and the upper metal layer are formed on the semiconductor substrate at the bottom of the contact hole.

[0100] The contact hole has a bottom width of 0.2 μm or more and 1.0 μm or less.

[0101] (Note 6)

[0102] The semiconductor device according to Supplementary Note 5, wherein:

[0103] An aspect ratio of the bottom width of the contact hole to the thickness of the interlayer insulating film is 1.5 or greater.

[0104] (Note 7)

[0105] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0106] The atomic concentration of the inert gas in the minute region is greater than or equal to 0.5 wt % and less than 20.0 wt %.

[0107] (Note 8)

[0108] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0109] The above-mentioned inert gas is Ar or N2.

[0110] (Note 9)

[0111] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein:

[0112] The semiconductor substrate is made of Si, SiC, or a compound containing Ga.

[0113] (Note 10)

[0114] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein:

[0115] The semiconductor substrate is made of Si or SiC.

[0116] The alloy layer is a silicide compound containing Ti or Ni.

[0117] (Note 11)

[0118] The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein:

[0119] The upper metal layer is composed of a metal containing Ti, W, or Al as a main component, or a stacked structure of a plurality of metals containing Ti, W, or Al as a main component.

[0120] (Note 12)

[0121] A semiconductor device, wherein:

[0122] have:

[0123] lower metal layer; and

[0124] An upper metal layer is formed on the lower metal layer.

[0125] A plurality of micro regions containing an inert gas are discretely arranged at the interface between the lower metal layer and the upper metal layer.

[0126] More than 90% of the plurality of micro regions have an arc shape with the widest opening.

[0127] (Note 13)

[0128] The semiconductor device according to Supplementary Note 12, wherein:

[0129] The atomic concentration of the constituent elements of the lower metal layer in the minute region is 80 wt % or more.

Claims

1. A semiconductor device, wherein: have: semiconductor substrates; an alloy layer containing, as a main component, the constituent elements of the semiconductor substrate; and an upper metal layer formed on the alloy layer, A plurality of micro regions containing an inert gas are discretely arranged at the interface between the alloy layer and the upper metal layer. More than 90% of the plurality of micro regions have an arc shape with the widest opening.

2. The semiconductor device according to claim 1, wherein The atomic concentration of the constituent elements of the alloy layer in the minute region is 80 wt % or more.

3. The semiconductor device according to claim 1 or 2, wherein The thickness of the alloy layer is greater than 30 nm, The width of the micro region is less than 100 nm, The depth of the micro region is smaller than the thickness of the alloy layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein The occupancy rate of the minute region at the interface between the alloy layer and the upper metal layer is less than 50%.

5. The semiconductor device according to any one of claims 1 to 4, wherein Also features: an interlayer insulating film formed on the semiconductor substrate; and a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate; The alloy layer and the upper metal layer are formed on the semiconductor substrate at the bottom of the contact hole, The bottom width of the contact hole is, for example, not less than 0.2 μm and not more than 1.0 μm. The semiconductor device according to claim 5 , wherein: An aspect ratio of the bottom width of the contact hole to the thickness of the interlayer insulating film is 1.5 or greater.

7. The semiconductor device according to any one of claims 1 to 6, wherein The atomic concentration of the inert gas in the minute region is greater than or equal to 0.5 wt % and less than 20.0 wt %.

8. The semiconductor device according to any one of claims 1 to 7, wherein The inert gas is Ar or N2.

9. The semiconductor device according to any one of claims 1 to 8, wherein The semiconductor substrate is made of Si, SiC, or a compound containing Ga.

10. The semiconductor device according to any one of claims 1 to 8, wherein The semiconductor substrate is made of Si or SiC, The alloy layer is a silicide compound containing Ti or Ni.

11. The semiconductor device according to any one of claims 1 to 10, wherein The upper metal layer is composed of a metal mainly composed of Ti, W, or Al, or a stacked structure of a plurality of metals mainly composed of Ti, W, or Al.

12. A semiconductor device, wherein: have: lower metal layer; and an upper metal layer formed on the lower metal layer, A plurality of micro regions containing an inert gas are discretely arranged at the interface between the lower metal layer and the upper metal layer. More than 90% of the plurality of micro regions have an arc shape with the widest opening.

13. The semiconductor device according to claim 12, wherein The atomic concentration of the constituent elements of the lower metal layer in the minute region is 80 wt % or more.

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