Sigma trench and manufacturing method of semiconductor device thereof

Abstract

The invention provides a manufacturing method of a sigma trench and a semiconductor device thereof, and the manufacturing method of the sigma trench comprises the steps: providing a substrate, forming a gate structure on the substrate, and forming source and drain regions in the substrate at two sides of the gate structure; anisotropic dry etching is carried out, and a first groove is formed in the source drain region; performing an isotropic chemical reaction, raising the temperature after the reaction is finished to sublimate a reaction product, forming a second groove in the first groove, enabling the top of the side wall of the second groove to be located at the bottom of the gate structure, and forming an undercut at the bottom of the gate structure; and performing wet etching, and forming a sigma groove in the second groove. According to the Sigma trench formed by the three steps of anisotropic dry etching, isotropic chemical reaction and wet etching, the top of the side wall of the Sigma trench is located at the bottom of the gate structure, and the undercut is formed at the bottom of the gate structure, so that the linear distance between the source region and the drain region is shortened, the resistance is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a sigma trench and a method for manufacturing a semiconductor device. Background Art

[0002] With the increasing integration density and shrinking critical dimensions of CMOS technology, the stress-stretching method used in traditional CMOS processes can no longer meet the device's PMOS drive current requirements. As critical dimensions reach 28nm and below, germanium-silicon (GeSi) epitaxial growth technology is required to increase the compressive stress of the PMOS, thereby improving the device's overall response speed.

[0003] In silicon-germanium epitaxial growth technology, sigma trenches are first formed in the source and drain regions of a PMOS device, followed by the formation of an epitaxial layer within the sigma trenches. The morphology of the sigma trenches is a key factor influencing PMOS device performance. To further improve PMOS performance, those skilled in the art must address the challenges of etching away the silicon on both sides of the sigma trenches and reducing the resistance between the source and drain regions. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a sigma trench and a semiconductor device thereof, wherein the top of the sigma trench sidewall is located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure, thereby reducing the resistance between the source and drain regions and improving device performance.

[0005] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a sigma groove is provided, comprising the following steps:

[0006] Providing a substrate, wherein a gate structure is formed on the substrate, and source and drain regions are formed in the substrate on both sides of the gate structure;

[0007] performing anisotropic dry etching to form a first trench in the source / drain region;

[0008] Performing an isotropic chemical reaction, and after the reaction is completed, increasing the temperature to allow the reaction product to sublime, thereby forming a second trench in the first trench, wherein the top of the sidewall of the second trench is located at the bottom of the gate structure, thereby forming an undercut at the bottom of the gate structure; and

[0009] Performing wet etching to form a sigma trench in the second trench.

[0010] Optionally, the isotropic chemical reaction is performed alternately with the step of increasing the temperature after the reaction is completed to allow the reaction product to sublime.

[0011] Optionally, the reaction gases of the isotropic chemical reaction include NF3 and H2, NF3 and HF, or NF3 and NH3.

[0012] Optionally, the volume ratio of NF3 and H2 is 7:8, and the total reaction time is 15 s.

[0013] Optionally, the etching gas used in the anisotropic dry etching includes HBr, CF4, O2, C l2 , NF3 or a combination thereof; the etching solution used in the wet etching includes TMAH or ammonia water.

[0014] Optionally, both the first groove and the second groove are U-shaped grooves.

[0015] Optionally, a gate oxide layer is formed on the substrate, and the substrate includes a first region and a second region, and a gate structure is formed on the substrate in at least the first region; the gate structure includes a gate and a gate mask layer formed in sequence on the gate oxide layer, and side walls formed on the side walls of the gate and the gate mask layer.

[0016] Optionally, before performing the anisotropic dry etching, the manufacturing method further includes: forming a hard mask layer, wherein the hard mask layer covers the second region;

[0017] After performing the wet etching, the manufacturing method further includes: removing the hard mask layer.

[0018] Optionally, in the isotropic chemical reaction, the substrate has a high etching selectivity relative to the hard mask layer, the gate oxide layer, the sidewall spacer, and the gate mask layer.

[0019] To solve the above technical problem, according to a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0020] Fabricating a sigma groove using the above-mentioned method for fabricating a sigma groove; and

[0021] Silicon-germanium epitaxial growth is performed in the sigma trench to form a silicon-germanium epitaxial layer.

[0022] In summary, in the method for making a sigma trench provided by the present invention, the substrate is first subjected to anisotropic dry etching to form a first trench in the source and drain regions, and then an isotropic chemical reaction is performed. After the reaction is completed, the temperature is increased to allow the reaction product to sublime, forming a second trench in the first trench. The top of the sidewall of the second trench is located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure. Subsequently, wet etching is performed to form a sigma trench in the second trench. The sigma trench thus formed has a top of its sidewall located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure. Compared with the sigma trench formed in the prior art, the top of the sidewall of the sigma trench formed in the present invention extends to both sides of the trench, shortening the straight-line distance between the source and drain regions. At the same time, the present invention uses three steps of anisotropic dry etching, isotropic chemical reaction, and wet etching to form a sigma trench. The method is simple and saves process time.

[0023] In the method for manufacturing a semiconductor device provided by the present invention, germanium-silicon epitaxial growth is performed in the sigma trench manufactured by the above-mentioned manufacturing method to form a germanium-silicon epitaxial layer. Since the top of the side wall of the sigma trench expands toward both sides of the trench, the straight-line distance between the source and drain regions becomes shorter, the resistance is reduced, and the hole mobility is increased, thereby improving the performance of the device.

[0024] Furthermore, the reaction gases of the isotropic chemical reaction include NF3 and H2, the volume ratio of NF3 and H2 is 7:8, and the total reaction time is 15 seconds. A 9nm undercut can be formed, and the bottom of the formed second groove is smooth and has low roughness, which is convenient for subsequent wet etching to form a sigma groove with better morphology.

[0025] Furthermore, during the isotropic chemical reaction, the substrate has a high etch selectivity relative to the hard mask layer, thereby ensuring the integrity of the hard mask layer in the second region and preventing impacts on subsequent processes. Simultaneously, the substrate also has a high etch selectivity relative to the gate oxide layer, thereby ensuring the integrity of the gate oxide layer and preventing impacts on device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a flow chart of a method for manufacturing a sigma trench provided by one embodiment of the present invention.

[0027] Figures 2 to 5 1 is a schematic structural diagram of each step of a method for manufacturing a sigma trench provided by an embodiment of the present invention.

[0028] Figure 6 It is a schematic structural diagram of a semiconductor device provided by one embodiment of the present invention.

[0029] Description of reference numerals:

[0030] 10 - substrate; 11 - gate oxide layer; 20 - gate structure; 21 - gate; 22 - gate mask layer; 23 - sidewall; 30 - hard mask layer; 41 - first trench; 42 - second trench; 43 - sigma trench; 50 - silicon germanium epitaxial layer. DETAILED DESCRIPTION

[0031] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0032] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0033] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a sigma groove according to an embodiment of the present invention. Figure 1 As shown, the method for making a sigma groove includes the following steps:

[0034] S1: providing a substrate, wherein a gate structure is formed on the substrate, and source and drain regions are formed in the substrate on both sides of the gate structure;

[0035] S2: performing anisotropic dry etching to form a first trench in the source and drain region;

[0036] S3: performing an isotropic chemical reaction, and after the reaction is completed, increasing the temperature to allow the reaction product to sublime, thereby forming a second trench in the first trench, wherein the top of the sidewall of the second trench is located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure; and

[0037] S5: performing wet etching to form a sigma trench in the second trench.

[0038] Figures 2 to 5 This is a schematic diagram of the various steps of the method for making a sigma groove according to an embodiment of the present invention. Figure 1 and Figures 2 to 5 The method for manufacturing the sigma trench provided in the embodiment of the present invention is described in detail.

[0039] In step S1, please refer to Figure 2 As shown, a substrate 10 is provided, a gate structure 20 is formed on the substrate 10 , and source and drain regions are formed in the substrate 10 on both sides of the gate structure 20 .

[0040] In this embodiment, the substrate 10 may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or may be silicon-on-insulator or germanium-on-insulator. Alternatively, the substrate 10 may be made of other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate 10 is preferably made of silicon.

[0041] In one embodiment of the present invention, the substrate 10 includes a first region I and a second region II. The first region I is, for example, a PMOS region, and the second region II is, for example, an NMOS region, but is not limited thereto. A gate structure 20 is formed on the substrate 10 within at least the first region I. In this embodiment, the gate structures 20 are formed on the substrate 10 within both the first region I and the second region II. Isolation structures (not shown) are formed within the substrate 10 between adjacent gate structures 20. Source and drain regions (not shown) are also formed within the substrate 10 on both sides of the gate structures 20.

[0042] In one embodiment of the present invention, a gate oxide layer 11 is formed on the substrate 10, and the gate structure 20 includes a gate 21 formed on the gate oxide layer 11, a gate mask layer 22 formed on the gate 21, and sidewall spacers 23 formed on the sidewalls of the gate 21 and the gate mask layer 22. Exemplarily, the gate oxide layer 11 is made of silicon oxide, the gate 21 is made of polysilicon, the gate mask layer 22 is made of silicon nitride, and the sidewall spacers 23 are made of silicon nitride. Of course, the sidewall spacers 23 may also be a stacked structure consisting of one or more layers of silicon oxide and silicon nitride.

[0043] In step S2, please refer to Figure 3 As shown, anisotropic dry etching is performed to form a first trench 41 in the source and drain region.

[0044] In one embodiment of the present invention, the substrate 10 includes a first region I and a second region II. Therefore, before performing anisotropic dry etching, a hard mask layer 30 needs to be formed. The hard mask layer 30 covers the region that does not need to be etched. In this embodiment, the hard mask layer 30 covers the second region II.

[0045] Exemplarily, a hard mask material layer is first formed, the hard mask material layer covering the gate structure 20 and the substrate 10 on both sides of the gate structure 20, then a photoresist layer is formed on the hard mask material layer, the photoresist layer is patterned to form a patterned photoresist layer, the patterned photoresist layer exposes the first region I, then the patterned photoresist layer is used as a mask to etch the hard mask material layer until the gate structure 20 and the substrate 10 in the first region I are exposed to form a hard mask layer 30, and then the patterned photoresist layer is removed.

[0046] Then, the source and drain electrodes are etched using the hard mask layer 30 as a mask and the exposed gate mask layer 22 and the sidewall spacer 23 as masks, that is, the substrate 10 on both sides of the gate structure 20 is etched to form a first trench 41 .

[0047] The etching is anisotropic dry etching, and the etching gas includes HBr, CF4, O2, Cl2, NF3, or a combination thereof. The first trench 41 formed is a U-shaped trench. In this embodiment, the top cross-sectional dimensions of the first trench 41 can be the same as the dimensions of the source and drain regions exposed on both sides of the gate structure 20.

[0048] Exemplarily, the material of the hard mask layer 30 is Barc or silicon nitride, and the hard mask material layer can be formed by spin coating or chemical vapor deposition process.

[0049] In step S3, please refer to Figure 4 As shown, an isotropic chemical reaction is carried out. After the reaction is completed, the temperature is increased to allow the reaction product to sublime, forming a second trench 42 in the first trench 41. The top of the sidewall of the second trench 42 is located at the bottom of the gate structure 20, forming an undercut at the bottom of the gate structure 20.

[0050] In this embodiment, a reaction gas is introduced into the reaction chamber, and a readily sublimable product is generated by the reaction between the reaction gas and the substrate 10 (i.e., silicon). After the reaction is complete, the chamber temperature is raised to allow the reaction product to sublime, thereby achieving isotropic etching and forming a second trench 42 within the first trench 41. Specifically, in this step, the sidewalls and bottom of the first trench 41 are etched at the same rate, thereby etching the silicon at the top of the sidewalls of the first trench 41. As a result, the top of the sidewalls of the ultimately formed second trench 42 is located at the bottom of the gate structure 20, forming an undercut at the bottom of the gate structure 20. The second trench 42 is also a U-shaped trench.

[0051] It should be noted that the top of the sidewall of the second trench 42 is located at the bottom of the sidewall 23 of the gate structure 20 .

[0052] In one embodiment of the present invention, the isotropic chemical reaction comprises reactant gases (NF3 and H2) in a volume ratio of 7:8. The reactant gases react with silicon to form a product that is easily sublimated. After the chemical reaction is complete, the chamber temperature is raised to allow the reaction product to sublime. Exemplarily, the chamber temperature may be raised to between 150°C and 190°C, but is not limited thereto. It is noteworthy that the etching selectivity of the reactant gases to silicon can be adjusted by adjusting the atomic ratio of H and F.

[0053] In some embodiments, the reaction gases of the isotropic chemical reaction include NF3 and HF, or NF3 and NH3.

[0054] In the isotropic chemical reaction, the substrate 10 has a high etching selectivity relative to the hard mask layer 30, the gate oxide layer 11, the spacer 23, and the gate mask layer 22. Exemplarily, the high etching selectivity is 20-30:1.

[0055] The substrate 10 has a high etch selectivity relative to the hard mask layer 30, thereby ensuring the integrity of the hard mask layer 30 in the second region II and preventing it from affecting subsequent processes. Simultaneously, the substrate 10 also has a high etch selectivity relative to the gate oxide layer 11, thereby ensuring the integrity of the gate oxide layer 11 and preventing it from affecting device performance.

[0056] In some embodiments, the isotropic chemical reaction and the step of raising the chamber temperature after the chemical reaction to allow the reaction products to sublime are performed alternately. During the isotropic chemical reaction, a solid, easily sublimable product is produced. When the reaction temperature is lowered, the easily sublimable product is deposited on the structural surface of the substrate, forming a protective layer that prevents further progress of the isotropic chemical reaction. Therefore, the isotropic chemical reaction can be carried out for a period of time, and then the chamber temperature can be raised for a period of time to allow the reaction products to sublime. By repeating the above process multiple times, the second groove 42 can be better etched and formed.

[0057] When the reaction gases of the isotropic chemical reaction include NF3 and H2, the volume ratio of NF3 and H2 is 7:8, and the total reaction time is 15 seconds, a 9nm undercut can be formed, and the bottom of the formed second groove 42 is smooth and has low roughness, which is convenient for subsequent wet etching to form a sigma groove 43 with better morphology.

[0058] In step S4, please refer to Figure 5 As shown, wet etching is performed to form a sigma trench 43 in the second trench 42 .

[0059] The etching solution used in the wet etching includes TMAH (tetramethylammonium hydroxide) or ammonia water, and may also include NH4OH, NH3OH, KOH, NaOH, BTMH (benzyltrimethylammonium hydroxide) or a combination thereof.

[0060] The wet etching is directional etching, and the etching rate varies according to the crystal orientation of the substrate 10. For example, <100> and <110> Has a very high etch rate, for <111> The etching rate is very low, so that a sigma-shaped trench is formed by etching. After the sigma trench 43 is formed, the hard mask layer 30 is removed.

[0061] Since the top of the sidewall of the second trench 42 is already located at the bottom of the gate structure 20 in the isotropic chemical reaction step, an undercut is formed at the bottom of the gate structure 20. In this step, the sidewall and bottom of the second trench 42 are further etched, and the top of the sidewall of the sigma trench 43 finally formed is also located at the bottom of the gate structure 20.

[0062] Due to the isotropic chemical reaction performed in step S3, the silicon at the top of the sidewalls of the first trench 41 is etched. Compared with the prior art, the top of the sidewalls of the sigma trench 43 formed in the present invention expands toward both sides of the trench. That is, the cross-sectional dimensions of the top of the sigma trench 43 are increased, thereby shortening the linear distance between the source and drain regions. Furthermore, the present invention forms the sigma trench 43 using three steps: anisotropic dry etching, isotropic chemical reaction, and wet etching. This method is simple and saves process time.

[0063] Accordingly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising the following steps:

[0064] Fabricating a sigma groove using the above-mentioned method for fabricating a sigma groove; and

[0065] Silicon-germanium epitaxial growth is performed in the sigma trench to form a silicon-germanium epitaxial layer.

[0066] Please refer to Figure 6 As shown, silicon-germanium epitaxial growth is performed in the sigma trench 43 to form a silicon-germanium epitaxial layer 50. In this embodiment, the silicon-germanium epitaxial layer 50 is formed by a selective epitaxial process. Exemplarily, the selective epitaxial process can be an ultra-high vacuum chemical vapor deposition process (UHVCVD) or a molecular beam epitaxy process (MEB). In this embodiment, the silicon-germanium epitaxial layer 50 can be formed in the sigma trench 43 using an ultra-high vacuum chemical vapor deposition process. The reaction gases include SiH2Cl2, HCl, and GeH4, but are not limited thereto.

[0067] like Figure 6 As shown, the shape of the SiGe epitaxial layer 50 matches the shape of the sigma groove 43. Since the lattice constant of SiGe material is greater than that of silicon, the SiGe epitaxial layer 50 can generate compressive stress in the sigma groove 43, thereby increasing the driving current of the semiconductor device and thus improving the response speed of the semiconductor device.

[0068] In this embodiment, SiGe epitaxial growth is performed in the sigma trench 43 manufactured by the above-mentioned manufacturing method to form a SiGe epitaxial layer 50. Since the top of the sidewall of the sigma trench 43 expands toward both sides of the trench, the straight-line distance between the source and drain regions, i.e., the SiGe epitaxial layer 50, becomes shorter, the resistance is reduced, and the hole mobility is increased, thereby improving the performance of the device.

[0069] In summary, in the method for making a sigma trench provided by the present invention, the substrate is first subjected to anisotropic dry etching to form a first trench in the source and drain regions, and then an isotropic chemical reaction is performed. After the reaction is completed, the temperature is increased to allow the reaction product to sublime, forming a second trench in the first trench. The top of the sidewall of the second trench is located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure. Subsequently, wet etching is performed to form a sigma trench in the second trench. The sigma trench thus formed has a top of its sidewall located at the bottom of the gate structure, forming an undercut at the bottom of the gate structure. Compared with the sigma trench formed in the prior art, the top of the sidewall of the sigma trench formed in the present invention extends to both sides of the trench, shortening the straight-line distance between the source and drain regions. At the same time, the present invention uses three steps of anisotropic dry etching, isotropic chemical reaction, and wet etching to form a sigma trench. The method is simple and saves process time.

[0070] In the method for manufacturing a semiconductor device provided by the present invention, germanium-silicon epitaxial growth is performed in the sigma trench manufactured by the above-mentioned manufacturing method to form a germanium-silicon epitaxial layer. Since the top of the side wall of the sigma trench expands toward both sides of the trench, the straight-line distance between the source and drain regions becomes shorter, the resistance is reduced, and the hole mobility is increased, thereby improving the performance of the device.

[0071] Furthermore, the reaction gases of the isotropic chemical reaction include NF3 and H2, the volume ratio of NF3 and H2 is 7:8, and the total reaction time is 15 seconds. A 9nm undercut can be formed, and the bottom of the formed second groove is smooth and has low roughness, which is convenient for subsequent wet etching to form a sigma groove with better morphology.

[0072] Furthermore, during the isotropic chemical reaction, the substrate has a high etch selectivity relative to the hard mask layer, thereby ensuring the integrity of the hard mask layer in the second region and preventing impacts on subsequent processes. Simultaneously, the substrate also has a high etch selectivity relative to the gate oxide layer, thereby ensuring the integrity of the gate oxide layer and preventing impacts on device performance.

[0073] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a sigma groove, characterized in that: The following steps are involved: Providing a substrate, wherein a gate structure is formed on the substrate, and source and drain regions are formed in the substrate on both sides of the gate structure; performing anisotropic dry etching to form a first trench in the source / drain region; performing an isotropic chemical reaction, and after the reaction is completed, raising the temperature to allow the reaction product to sublime, thereby forming a second trench in the first trench, wherein the top of the sidewall of the second trench is located at the bottom of the gate structure, thereby forming an undercut at the bottom of the gate structure; as well as Performing wet etching to form a sigma trench in the second trench.

2. The method for manufacturing a sigma groove according to claim 1, wherein: The isotropic chemical reaction is alternately performed with a step of raising the temperature after the reaction is completed to allow the reaction product to sublime.

3. The method for manufacturing a sigma groove according to claim 1, wherein: The reaction gases of the isotropic chemical reaction include NF3 and H2, NF3 and HF, or NF3 and NH3.

4. The method for manufacturing a sigma groove according to claim 3, wherein: The volume ratio of NF3 and H2 was 7:8, and the total reaction time was 15 s.

5. The method for manufacturing a sigma groove according to claim 1, wherein: The etching gas used in the anisotropic dry etching includes HBr, CF4, O2, Cl2, NF3 or a combination thereof; the etching solution used in the wet etching includes TMAH or ammonia water.

6. The method for manufacturing a sigma groove according to claim 1, wherein: Both the first groove and the second groove are U-shaped grooves.

7. The method for manufacturing a sigma groove according to any one of claims 1 to 6, characterized in that: A gate oxide layer is formed on the substrate, and the substrate includes a first region and a second region, and a gate structure is formed on the substrate in at least the first region; the gate structure includes a gate and a gate mask layer formed in sequence on the gate oxide layer, and sidewalls formed on the sidewalls of the gate and the gate mask layer.

8. The method for manufacturing a sigma groove according to claim 7, wherein: Before performing anisotropic dry etching, the manufacturing method further includes: forming a hard mask layer, wherein the hard mask layer covers the second region; After performing the wet etching, the manufacturing method further includes: removing the hard mask layer.

9. The method for manufacturing a sigma groove according to claim 8, wherein: In the isotropic chemical reaction, the substrate has a high etching selectivity ratio relative to the hard mask layer, the gate oxide layer, the spacer, and the gate mask layer.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: The sigma groove is manufactured by the method for manufacturing the sigma groove according to any one of claims 1 to 9; as well as Silicon-germanium epitaxial growth is performed in the sigma trench to form a silicon-germanium epitaxial layer.

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