Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a first channel pattern on a first active fin; a second channel pattern on the second active fin; and a lower spacer between the first channel pattern and the second channel pattern, in which the lower spacer includes a first portion extending from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin in a vertical direction, and a second portion on the first portion, a width of the first portion in the second horizontal direction on an upper surface of the first portion is greater than a width of the second portion in the second horizontal direction on a lower surface of the second portion, and the first portion continuously extends in the first horizontal direction along the first active fin and the second active fin.

Description

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0019177 filed on February 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Embodiments of the inventive concept relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0003] Semiconductor devices may include integrated circuits that include metal oxide semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices have gradually decreased, the size reduction (scaling) of MOSFETs has also accelerated. This reduction in MOSFET size can degrade the operating characteristics of semiconductor devices. Therefore, various methods have been developed to create semiconductor devices with improved performance while overcoming the limitations imposed by the high integration density of semiconductor devices. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device having improved electrical performance and reliability.

[0005] Embodiments of the inventive concept also provide a method of fabricating a semiconductor device having improved electrical performance and reliability.

[0006] Problems to be solved by the inventive concept are not limited to the above-mentioned problems, and as those skilled in the art understand from the following description, other problems not mentioned can be solved by embodiments of the inventive concept.

[0007] According to one aspect of the inventive concept, a semiconductor device is provided, comprising: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern on the first active fin; a second channel pattern on the second active fin; and a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer comprises: a first portion extending in a third direction from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin, and a lower spacer on the first portion. a second portion of the active fin, the third direction being perpendicular to a plane defined by the first direction and the second direction; a first gate electrode on the first channel pattern and at least partially surrounding the first channel pattern; and a second gate electrode on the second channel pattern and at least partially surrounding the second channel pattern, wherein a width of the first portion in the second direction on an upper surface of the first portion is a first width, wherein a width of the second portion in the second direction on a lower surface of the second portion is a second width, wherein the first width is greater than the second width, and wherein the first portion extends continuously in the first direction along the first active fin and the second active fin.

[0008] According to another aspect of the inventive concept, a semiconductor device is provided, including: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern on the first active fin; a second channel pattern on the second active fin; a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer includes: a first portion extending from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin in a third direction, and a second portion on the first portion, the third direction being perpendicular to a plane defined by the first direction and the second direction; a first gate electrode on the first channel pattern and at least partially surrounding the first channel pattern; and a second gate electrode on the second channel pattern and at least partially surrounding the second channel pattern, wherein a width of the first portion in the second direction is a first width, wherein a width of the second portion in the second direction is a second width, wherein the first width is greater than the second width, and wherein the first portion is formed integrally with the second portion.

[0009] According to another aspect of the inventive concept, a semiconductor device is provided, comprising: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern on the first active fin, and a second channel pattern on the second active fin, wherein the first channel pattern and the second channel pattern include semiconductor patterns stacked in a third direction and spaced apart from each other, the third direction being perpendicular to a plane defined by the first and second directions; a first source / drain pattern positioned adjacent to the first channel pattern in the first direction and connected to the first channel pattern; a second source / drain pattern positioned adjacent to the second channel pattern in the first direction and connected to the second channel pattern; and a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer comprises: a first portion extending in the third direction from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin. a space between the fins, and a second portion on the first portion; a first gate electrode traversing the first channel pattern in the second direction; and a second gate electrode traversing the second channel pattern in the second direction, wherein the first channel pattern and the second channel pattern are spaced apart from each other in the second direction, with a first portion between the first channel pattern and the second channel pattern, wherein the first source / drain pattern and the second source / drain pattern are spaced apart from each other in the second direction, with a first portion between the first source / drain pattern and the second source / drain pattern, wherein the first gate electrode and the second gate electrode are spaced apart from each other in the second direction, with a second portion between the first gate electrode and the second gate electrode, wherein a width of the first portion in the second direction on an upper surface of the first portion is a first width, wherein a width of the second portion in the second direction on a lower surface of the second portion is a second width, wherein the first width is greater than the second width, and wherein the first portion extends continuously in the first direction along the first active fin and the second active fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a plan view illustrating a semiconductor device according to some embodiments.

[0012] Figures 2A to 2D Along the Figure 1 Cross-sectional views taken along line X1-X1', line X2-X2', line Y1-Y1' and line Y2-Y2'.

[0013] Figure 3A It shows Figure 2C An enlarged view of an example of region M1.

[0014] Figure 3B It shows Figure 2C FIG. 1 is an enlarged view of another example of the region M1 .

[0015] Figure 3C It shows Figure 2C FIG. 1 is an enlarged view of another example of the region M1 .

[0016] Figure 3D It shows Figure 2C FIG. 1 is an enlarged view of another example of the region M1 .

[0017] Figure 4A and Figure 4B Along the Figure 1 A cross-sectional view taken along line Y1-Y1' and line Y2-Y2'.

[0018] Figure 5 It shows Figure 4A An enlarged view of an example of region M2.

[0019] Figure 6 It is along Figure 1 A cross-sectional view taken along line Y1-Y1'.

[0020] Figure 7A It shows Figure 6 An enlarged view of an example of region M3.

[0021] Figure 7B It shows Figure 6 FIG. 1 is an enlarged view of another example of region M3 .

[0022] Figures 8A to 8C 、 Figures 9A to 9C 、 10A to 10C 、 Figures 11A to 11C 、 12A to 12C 、 13A to 13C 、 FIG. 14A to FIG. 14B 、 Figures 15A to 15C 、 16A to 16C 、 17A to 17C 、 18A to 18C 、 Figures 19A to 19B 、 20A to 20C 、 21A to 21D 、 FIG. 22A to FIG. 22B 、 Figures 23A to 23C as well as FIG. 24A to FIG. 24B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0023] Figures 25A to 25C 、 Figures 26A to 26C 、 Figures 27A to 27C 、 Figures 28A to 28C 、 Figures 29A to 29B 、 FIG. 30A to FIG. 30B 、 Figures 31A to 31B 、 Figure 32 as well as Figure 33is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, a semiconductor device according to the inventive concept is described with reference to the accompanying drawings. In the accompanying drawings, identical reference numerals are used for the same constituent elements, and their repeated descriptions are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms "first", "second", "upper", "lower", etc. can be used to describe various elements or components here, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first element or component discussed below can be named as the second element or component. Note that the aspects described with respect to one embodiment may be included in different embodiments, although not specifically described with respect to it. That is, all embodiments and / or features of the embodiments can be combined in any manner and / or combination.

[0025] Figure 1 is a plan view showing the semiconductor device 1 according to the embodiment. Figures 2A to 2D Along the Figure 1 Cross-sectional views taken along line X1-X1', line X2-X2', line Y1-Y1' and line Y2-Y2'.

[0026] In the following, reference is made to Figure 1 and Figures 2A to 2D A semiconductor device 1 including a field effect transistor having a fork-tab structure or a gate-all-around structure is described.

[0027] Reference Figure 1 and Figures 2A to 2D , the semiconductor device 1 may include a substrate 10 .

[0028] like Figure 2C As shown in FIG, the substrate 10 may include a first region 10_1, a second region 10_2, a third region 10_3, and a fourth region 10_4 spaced apart from each other in a second horizontal direction D2 intersecting the first horizontal direction D1.

[0029] In this specification, the first horizontal direction D1 is defined as a direction parallel to the upper surface of the substrate 10, the second horizontal direction D2 is defined as a direction intersecting the first horizontal direction D1 and parallel to the upper surface of the substrate 10, and the vertical direction (or third direction) D3 is defined as a direction perpendicular to the upper surface of the substrate 10 or perpendicular to a plane defined by the first horizontal direction D1 and the second horizontal direction D2.

[0030] The substrate 10 may include a semiconductor material such as Si or Ge or a compound semiconductor material such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms SiGe, SiC, GaAs, InAs, InGaAs, and InP used in this specification refer to materials including the elements included in each term and do not represent chemical formulas representing stoichiometric relationships.

[0031] like Figure 2C As shown in , in some embodiments, the first active fin FA1 may be disposed on the first region 10_1 of the substrate 10. The second active fin FA2 may be disposed on the second region 10_2 of the substrate 10. The third active fin FA3 may be disposed on the third region 10_3 of the substrate 10. The fourth active fin FA4 may be disposed on the fourth region 10_4 of the substrate 10.

[0032] The first to fourth active fins FA1 to FA4 may protrude from the substrate 10 in the vertical direction D3. The first to fourth active fins FA1 to FA4 may be integrally formed with the substrate 10, ie, they may form a unitary structure.

[0033] The first to fourth active fins FA1 to FA4 may extend parallel to each other in the first horizontal direction D1 and may be spaced apart from each other in the second horizontal direction D2.

[0034] The first trench TR1 may be located between the first active fin FA1 and the second active fin FA2. The second trench TR2 may be located between the third active fin FA3 and the fourth active fin FA4. The third trench TR3 may be located between the second active fin FA2 and the third active fin FA3.

[0035] The device isolation film 20 may be provided on the substrate 10. The device isolation film 20 may at least partially fill the third trench TR3. The device isolation film 20 may not be located in the first trench TR1 and the second trench TR2.

[0036] The device isolation film 20 may include an insulating material. The device isolation film 20 may include an oxide film, a nitride film, or a combination thereof.

[0037] The protection film 25 may be located between the device isolation film 20 and the first active fin FA1 , between the device isolation film 20 and the second active fin FA2 , between the device isolation film 20 and the third active fin FA3 , and between the device isolation film 20 and the fourth active fin FA4 .

[0038] The protective film 25 may extend from the sidewalls of the first active fin FA1 to the upper surface of the substrate 10. The protective film 25 may extend from the sidewalls of the second active fin FA2 to the upper surface of the substrate 10. The protective film 25 may extend from the sidewalls of the third active fin FA3 to the upper surface of the substrate 10. The protective film 25 may extend from the sidewalls of the fourth active fin FA4 to the upper surface of the substrate 10. The protective film 25 may extend in the first horizontal direction D1.

[0039] The protection film 25 may include an oxide film, a nitride film, or a combination thereof.

[0040] The first channel pattern CH1 may be disposed on the first active fin FA1. The second channel pattern CH2 may be disposed on the second active fin FA2. The third channel pattern CH3 may be disposed on the third active fin FA3. The fourth channel pattern CH4 may be disposed on the fourth active fin FA4.

[0041] The first channel pattern CH1 may be provided in plural. The plurality of first channel patterns CH1 may be separated from each other in the first horizontal direction D1. A pair of first channel patterns CH1 may be spaced apart from each other in the first horizontal direction D1 with the first source / drain pattern SD1 therebetween.

[0042] The second channel pattern CH2 may be provided in plural. The plurality of second channel patterns CH2 may be separated from each other in the first horizontal direction D1. A pair of second channel patterns CH2 may be spaced apart from each other in the first horizontal direction D1, with the second source / drain pattern SD2 between the pair of second channel patterns CH2.

[0043] The third channel pattern CH3 may be provided in plurality. The plurality of third channel patterns CH3 may be separated from each other in the first horizontal direction D1. A pair of third channel patterns CH3 may be spaced apart from each other in the first horizontal direction D1, with the third source / drain pattern SD3 between the pair of third channel patterns CH3.

[0044] The fourth channel pattern CH4 may be provided in plurality. The plurality of fourth channel patterns CH4 may be separated from each other in the first horizontal direction D1. A pair of fourth channel patterns CH4 may be spaced apart from each other in the first horizontal direction D1 with the fourth source / drain pattern SD4 therebetween.

[0045] The first to fourth channel patterns CH1 to CH4 may be spaced apart from each other in the second horizontal direction D2.

[0046] Each of the first to fourth channel patterns CH1 to CH4 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked. The first to third semiconductor patterns SP1 to SP3 may be spaced apart from each other in the vertical direction D3.

[0047] The first to third semiconductor patterns SP1 to SP3 may have nanostructures such as nanosheets, nanorods, or nanowires.

[0048] exist Figure 2A and Figure 2C , each of the first to fourth channel patterns CH1 to CH4 is shown as including three semiconductor patterns, but there is no limitation on the number of semiconductor patterns. That is, each of the first to fourth channel patterns CH1 to CH4 may include two or fewer semiconductor patterns, or may include four or more semiconductor patterns. This may vary depending on the design of the semiconductor device 1 to be manufactured.

[0049] Each of the first to third semiconductor patterns SP1 to SP3 may include silicon, germanium, or silicon-germanium. For example, each of the first to third semiconductor patterns SP1 to SP3 may include crystalline silicon.

[0050] The first source / drain pattern SD1 may be disposed on the first active fin FA1. The first source / drain pattern SD1 may be located in the first recess RS1 formed on the first active fin FA1. The first source / drain pattern SD1 may be an impurity region of a first conductive type (eg, N-type).

[0051] The first source / drain pattern SD1 may be provided in plurality. The plurality of first source / drain patterns SD1 may be spaced apart from each other in the first horizontal direction D1. The first channel pattern CH1 may be located between a pair of first source / drain patterns SD1.

[0052] The first channel pattern CH1 may physically and electrically connect the pair of first source / drain patterns SD1 to each other. In other words, the first to third semiconductor patterns SP1 to SP3 may physically and electrically connect the pair of first source / drain patterns SD1 to each other.

[0053] The second source / drain pattern SD2 may be disposed on the second active fin FA2. The second source / drain pattern SD2 may be located in the second recess RS2 formed on the second active fin FA2. The second source / drain pattern SD2 may be an impurity region of the first conductivity type.

[0054] The second source / drain pattern SD2 may be provided in plurality. The plurality of second source / drain patterns SD2 may be spaced apart from each other in the first horizontal direction D1. The second channel pattern CH2 may be located between a pair of second source / drain patterns SD2.

[0055] The second channel pattern CH2 may physically and electrically connect the pair of second source / drain patterns SD2 to each other. In other words, the first to third semiconductor patterns SP1 to SP3 may physically and electrically connect the pair of second source / drain patterns SD2 to each other.

[0056] The third source / drain pattern SD3 may be disposed on the third active fin FA3. The third source / drain pattern SD3 may be located in a third recess RS3 formed on the third active fin FA3. The third source / drain pattern SD3 may be an impurity region of a second conductivity type (eg, p-type) different from the first conductivity type.

[0057] The third source / drain pattern SD3 may be provided in plurality. The plurality of third source / drain patterns SD3 may be spaced apart from each other in the first horizontal direction D1. The third channel pattern CH3 may be located between a pair of third source / drain patterns SD3.

[0058] The third channel pattern CH3 may physically and electrically connect the pair of third source / drain patterns SD3 to each other. In other words, the first to third semiconductor patterns SP1 to SP3 may physically and electrically connect the pair of third source / drain patterns SD3 to each other.

[0059] The fourth source / drain pattern SD4 may be disposed on the fourth active fin FA4. The fourth source / drain pattern SD4 may be located in the fourth recess RS4 formed on the fourth active fin FA4. The fourth source / drain pattern SD4 may be an impurity region of the second conductivity type.

[0060] The fourth source / drain pattern SD4 may be provided in plurality. The plurality of fourth source / drain patterns SD4 may be spaced apart from each other in the first horizontal direction D1. The fourth channel pattern CH4 may be located between a pair of fourth source / drain patterns SD4.

[0061] The fourth channel pattern CH4 may physically and electrically connect the pair of fourth source / drain patterns SD4 to each other. In other words, the first to third semiconductor patterns SP1 to SP3 may physically and electrically connect the pair of fourth source / drain patterns SD4 to each other.

[0062] The first and second source / drain patterns SD1 and SD2 may be spaced apart from each other in the second horizontal direction D2. The third and fourth source / drain patterns SD3 and SD4 may be spaced apart from each other in the second horizontal direction D2.

[0063] The first to fourth source / drain patterns SD1 to SD4 may be epitaxial patterns formed by selective epitaxial growth (SEG). For example, the upper surface of each of the first to fourth source / drain patterns SD1 to SD4 may be taller than the upper surface of the third semiconductor pattern SP3 in the vertical direction D3 ( Figure 3A As another example, the upper surface of at least one of the first to fourth source / drain patterns SD1 to SD4 may be located at a position higher than the upper surface of the third semiconductor pattern SP3 ( Figure 3A At essentially the same height as SP3a in Figure 1.

[0064] In this specification, the term "substantially the same" may include not only mathematical equality but also a margin for errors in the process.

[0065] In one embodiment, each of the first through fourth source / drain patterns SD1 through SD4 may include the same semiconductor element as the substrate 10 (e.g., Si). In other embodiments, each of the first through fourth source / drain patterns SD1 through SD4 may include a semiconductor element having a larger lattice constant than the substrate 10 (e.g., SiGe). For example, when the first source / drain patterns SD1 include a semiconductor element having a larger lattice constant than the substrate 10, the pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 located between the pair of first source / drain patterns SD1. Similarly, the pair of second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2, the pair of third source / drain patterns SD3 may provide compressive stress to the third channel pattern CH3, and the pair of fourth source / drain patterns SD4 may provide compressive stress to the fourth channel pattern CH4.

[0066] The lower spacer 50 may be located between the first channel pattern CH1 and the second channel pattern CH2. The lower spacer 50 may be located between the third channel pattern CH3 and the fourth channel pattern CH4. The lower spacer 50 may be located between the first source / drain pattern SD1 and the second source / drain pattern SD2. The lower spacer 50 may be located between the third source / drain pattern SD3 and the fourth source / drain pattern SD4.

[0067] The lower partition 50 may include a first portion 51 and a second portion 53 on the first portion 51. The first portion 51 may be distinguished from the second portion 53, but is not limited thereto. For example, the first portion 51 may be integrally formed with the second portion 53, that is, the first portion 51 and the second portion 53 may form a unitary structure.

[0068] The first portion 51 of the lower spacer 50 may be located in the first trench TR1. The first portion 51 may be located in the second trench TR2. The first portion 51 may fill at least a portion of the first trench TR1. The first portion 51 may fill at least a portion of the second trench TR2. The first portion 51 may extend in the vertical direction D3 from the space between the first channel pattern CH1 and the second channel pattern CH2 to the space between the first active fin FA1 and the second active fin FA2. The first portion 51 may extend in the vertical direction D3 from the third channel pattern CH3 and the fourth channel pattern CH4 to the space between the third active fin FA3 and the fourth active fin FA4.

[0069] The first portion 51 may extend in the first horizontal direction D1. The first portion 51 may extend continuously along the first to fourth active fins FA1 to FA4 in the first horizontal direction D1, but the embodiment is not limited thereto. The length of the first portion 51 in the first horizontal direction D1 may be the same as the length of each of the first to fourth active fins FA1 to FA4 in the first horizontal direction D1, but the embodiment is not limited thereto.

[0070] The first and second channel patterns CH1 and CH2 may be spaced apart from each other in the second horizontal direction D2, with the first portion 51 between them. The third and fourth channel patterns CH3 and CH4 may be spaced apart from each other in the second horizontal direction D2, with the first portion 51 between them.

[0071] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be spaced apart from each other in the second horizontal direction D2, with the first portion 51 between the first source / drain pattern SD1 and the second source / drain pattern SD2. The third source / drain pattern SD3 and the fourth source / drain pattern SD4 may be spaced apart from each other in the second horizontal direction D2, with the first portion 51 between the third source / drain pattern SD3 and the fourth source / drain pattern SD4.

[0072] The second portion 53 may be disposed on the first portion 51. The second portion 53 may be in contact with the first portion 51.

[0073] The second portion 53 may overlap the first to fourth channel patterns CH1 to CH4 in the second horizontal direction D2. The second portion 53 may not overlap the first to fourth source / drain patterns SD1 to SD4 in the second horizontal direction D2.

[0074] The upper spacer 55 may be disposed on the first portion 51. The upper spacer 55 may contact the first portion 51. A vertical height of an upper surface of the upper spacer 55 in the D3 direction may be higher than a vertical height of an upper surface of the second portion 53 in the D3 direction.

[0075] The upper spacer 55 may overlap the first to fourth source / drain patterns SD1 to SD4 in the second horizontal direction D2. The upper spacer 55 may not overlap the first to fourth channel patterns CH1 to CH4 in the second horizontal direction D2.

[0076] The upper spacer 55 may overlap the second portion 53 in the first horizontal direction D1. A sidewall of the upper spacer 55 in the first horizontal direction D1 may contact a sidewall of the second portion 53 in the first horizontal direction D1.

[0077] The upper partition 55 can be distinguished from the first portion 51 and the second portion 53, but the embodiment is not limited thereto. As an example, the upper partition 55 can be integrally formed with at least one of the first portion 51 and the second portion 53, that is, the upper partition 55 and at least one of the first portion 51 and the second portion 53 can form a unitary structure.

[0078] The first portion 51 and the second portion 53 may be tapered in the vertical direction D3. The width of the first portion 51 in the second horizontal direction D2 may become narrower as the first portion 51 extends downward in the direction D3. The width of the second portion 53 in the second horizontal direction D2 may become narrower as the second portion 53 extends downward in the direction D3.

[0079] The first portion 51, the second portion 53, and the upper spacer 55 may include an insulating material. As an example, the first portion 51, the second portion 53, and the upper spacer 55 may include an oxide, a nitride, or a combination thereof. As an example, the first portion 51, the second portion 53, and the upper spacer 55 may include SiN, SiO2, SiBN, SiON, SiOCN, SiBCN, and / or SiOC.

[0080] At least two of the first portion 51, the second portion 53, and the upper divider 55 may comprise the same material. In other embodiments, the first portion 51, the second portion 53, and the upper divider 55 may comprise different materials.

[0081] The buried insulating pattern 61 may be located in the first trench TR1 and the second trench TR2. The buried insulating pattern 61 may be located between the first channel pattern CH1 and the first portion 51. The buried insulating pattern 61 may be located between the second channel pattern CH2 and the first portion 51. The buried insulating pattern 61 may be located between the third channel pattern CH3 and the first portion 51. The buried insulating pattern 61 may be located between the fourth channel pattern CH4 and the first portion 51.

[0082] The buried insulating pattern 61 may not be located between the first source / drain pattern SD1 and the first portion 51. The buried insulating pattern 61 may not be located between the second source / drain pattern SD2 and the first portion 51. The buried insulating pattern 61 may not be located between the third source / drain pattern SD3 and the first portion 51. The buried insulating pattern 61 may not be located between the fourth source / drain pattern SD4 and the first portion 51.

[0083] In the portion overlapping the first channel pattern CH1 in the second horizontal direction D2, the buried insulating pattern 61 may be on the sidewalls of the first portion 51 in the second horizontal direction D2 and at least partially cover the sidewalls of the first portion 51. In the portion overlapping the second channel pattern CH2 in the second horizontal direction D2, the buried insulating pattern 61 may be on the sidewalls of the first portion 51 in the second horizontal direction D2 and at least partially cover the sidewalls of the first portion 51. In the portion overlapping the third channel pattern CH3 in the second horizontal direction D2, the buried insulating pattern 61 may be on the sidewalls of the first portion 51 in the second horizontal direction D2 and at least partially cover the sidewalls of the first portion 51. In the portion overlapping the fourth channel pattern CH4 in the second horizontal direction D2, the buried insulating pattern 61 may be on the sidewalls of the first portion 51 in the second horizontal direction D2 and at least partially cover the sidewalls of the first portion 51.

[0084] In the portion overlapping the first source / drain pattern SD1 in the second horizontal direction D2, the buried insulating pattern 61 may be on a portion of the sidewall of the first portion 51 in the second horizontal direction D2 and at least partially cover the portion of the sidewall of the first portion 51. In the portion overlapping the second source / drain pattern SD2 in the second horizontal direction D2, the buried insulating pattern 61 may be on a portion of the sidewall of the first portion 51 in the second horizontal direction D2 and at least partially cover the portion of the sidewall of the first portion 51. In the portion overlapping the third source / drain pattern SD3 in the second horizontal direction D2, the buried insulating pattern 61 may be on a portion of the sidewall of the first portion 51 in the second horizontal direction D2 and at least partially cover the portion of the sidewall of the first portion 51. In the portion overlapping the fourth source / drain pattern SD4 in the second horizontal direction D2, the buried insulating pattern 61 may be on a portion of the sidewall of the first portion 51 in the second horizontal direction D2 and at least partially cover the portion of the sidewall of the first portion 51.

[0085] The buried insulating pattern 61 may extend from the sidewall of the first portion 51 to the lower surface of the first portion 51. The buried insulating pattern 61 may be on the lower surface of the first portion 51 and at least partially cover the lower surface of the first portion 51.

[0086] The buried insulating pattern 61 may include an oxide film, a nitride film, or a combination thereof. The buried insulating pattern 61 may include the same material as that of the protective film 25.

[0087] The first gate electrode 31 extending in the second horizontal direction D2 may be provided on the first active fin FA1 across the plurality of first channel patterns CH1. The first gate electrode 31 may be provided in plurality. The plurality of first gate electrodes 31 may be spaced apart from each other in the first horizontal direction D1.

[0088] The second gate electrode 32 extending in the second horizontal direction D2 may be provided on the second active fin FA2 across the plurality of second channel patterns CH2. The second gate electrode 32 may be provided in plurality. The plurality of second gate electrodes 32 may be spaced apart from each other in the first horizontal direction D1.

[0089] The first gate electrode 31 may be spaced apart from the second gate electrode 32 in the second horizontal direction D2 with the second portion 53 of the lower spacer 50 therebetween.

[0090] The third gate electrode 33 extending in the second horizontal direction D2 may be provided on the third active fin FA3 across the plurality of third channel patterns CH3. The third gate electrode 33 may be provided in plurality. The plurality of third gate electrodes 33 may be spaced apart from each other in the first horizontal direction D1.

[0091] The fourth gate electrode 34 extending in the second horizontal direction D2 may be provided on the fourth active fin FA4 across the plurality of fourth channel patterns CH4. The fourth gate electrode 34 may be provided in plurality. The plurality of fourth gate electrodes 34 may be spaced apart from each other in the first horizontal direction D1.

[0092] The third gate electrode 33 may be spaced apart from the fourth gate electrode 34 in the second horizontal direction D2 with the second portion 53 of the lower spacer 50 therebetween. The third gate electrode 33 may be electrically disconnected (open) from the fourth gate electrode 34.

[0093] The first and second gate electrodes 31 and 32 may include a first conductive type work function metal, but the embodiment is not limited thereto. The third and fourth gate electrodes 33 and 34 may include a second conductive type work function metal, but the embodiment is not limited thereto.

[0094] The second gate electrode 32 may be in contact with the third gate electrode 33. When the second gate electrode 32 includes a first conductive type work function metal, the third gate electrode 33 may include a second conductive type work function metal.

[0095] Each of the first gate electrode 31, the second gate electrode 32, the third gate electrode 33, and the fourth gate electrode 34 may include a single component or multiple components. Each of the first gate electrode 31, the second gate electrode 32, the third gate electrode 33, and the fourth gate electrode 34 may include a metal, a metal nitride, a metal carbide, or a combination thereof. For example, the metal may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd, but the embodiment is not limited thereto. As an example, the metal nitride may include TiN and / or TaN, but the embodiment is not limited thereto. For example, the metal carbide may be TiAlC, but the embodiment is not limited thereto.

[0096] The first gate electrode 31 may be located between the first active fin FA1 and the first semiconductor pattern SP1 of the first channel pattern CH1. The first gate electrode 31 may be located between the first semiconductor pattern SP1 of the first channel pattern CH1 and the second semiconductor pattern SP2 of the first channel pattern CH1. The first gate electrode 31 may be located between the second semiconductor pattern SP2 of the first channel pattern CH1 and the third semiconductor pattern SP3 of the first channel pattern CH1. The first gate electrode 31 may be disposed on the third semiconductor pattern SP3 of the first channel pattern CH1 and on the device isolation film 20.

[0097] The second gate electrode 32 may be located between the second active fin FA2 and the first semiconductor pattern SP1 of the second channel pattern CH2. The second gate electrode 32 may be located between the first semiconductor pattern SP1 of the second channel pattern CH2 and the second semiconductor pattern SP2 of the second channel pattern CH2. The second gate electrode 32 may be located between the second semiconductor pattern SP2 of the second channel pattern CH2 and the third semiconductor pattern SP3 of the second channel pattern CH2. The second gate electrode 32 may be disposed on the third semiconductor pattern SP3 of the second channel pattern CH2 and on the device isolation film 20.

[0098] The third gate electrode 33 may be located between the third active fin FA3 and the first semiconductor pattern SP1 of the third channel pattern CH3. The third gate electrode 33 may be located between the first semiconductor pattern SP1 of the third channel pattern CH3 and the second semiconductor pattern SP2 of the third channel pattern CH3. The third gate electrode 33 may be located between the second semiconductor pattern SP2 of the third channel pattern CH3 and the third semiconductor pattern SP3 of the third channel pattern CH3. The third gate electrode 33 may be disposed on the third semiconductor pattern SP3 of the third channel pattern CH3 and on the device isolation film 20.

[0099] The fourth gate electrode 34 may be located between the fourth active fin FA4 and the first semiconductor pattern SP1 of the fourth channel pattern CH4. The fourth gate electrode 34 may be located between the first semiconductor pattern SP1 of the fourth channel pattern CH4 and the second semiconductor pattern SP2 of the fourth channel pattern CH4. The fourth gate electrode 34 may be located between the second semiconductor pattern SP2 of the fourth channel pattern CH4 and the third semiconductor pattern SP3 of the fourth channel pattern CH4. The fourth gate electrode 34 may be disposed on the third semiconductor pattern SP3 of the fourth channel pattern CH4 and on the device isolation film 20.

[0100] An interlayer insulating layer 60 may be disposed on the first to fourth source / drain patterns SD1 to SD4. The interlayer insulating layer 60 may vertically overlap each of the first to fourth source / drain patterns SD1 to SD4 (e.g., in the D3 direction). The interlayer insulating layer 60 may extend in the second horizontal direction D2, but may be interrupted by the upper spacer 55. In other words, the interlayer insulating layer 60 may extend discontinuously in the second horizontal direction D2.

[0101] However, this corresponds to an embodiment only, and embodiments of the inventive concept are not limited thereto. By adjusting the thickness of the upper spacer 55 in the vertical direction D3, the interlayer insulating layer 60 can continuously extend in the second horizontal direction D2. This can vary depending on the design of the semiconductor device 1 to be manufactured.

[0102] As an example, the interlayer insulating layer 60 may include silicon oxide.

[0103] The gate dielectric film 41 may be located between the first gate electrode 31 and the first channel pattern CH1. The gate dielectric film 41 may also be located between the first gate electrode 31 and the second portion 53. The gate dielectric film 41 may be disposed on the upper surface, lower surface, and sidewalls in the second horizontal direction D2 of each of the first to third semiconductor patterns SP1 to SP3 included in the first channel pattern CH1. The gate dielectric film 41 may be disposed on and cover at least a portion of the sidewalls of the buried insulating pattern 61 in the second horizontal direction D2. The gate dielectric film 41 may also be disposed on the upper surface of the first active fin FA1 and the upper surface of the device isolation film 20. On the third semiconductor pattern SP3 of the first channel pattern CH1, the gate dielectric film 41 may be located on the lower surface of the first gate electrode 31 and on the sidewalls in the first horizontal direction D1.

[0104] The gate dielectric film 41 may be located between the second gate electrode 32 and the second channel pattern CH2. The gate dielectric film 41 may also be located between the second gate electrode 32 and the second portion 53. The gate dielectric film 41 may be disposed on the upper surface, lower surface, and sidewalls in the second horizontal direction D2 of each of the first to third semiconductor patterns SP1 to SP3 included in the second channel pattern CH2. The gate dielectric film 41 may also be disposed on the upper surface of the second active fin FA2 and the upper surface of the device isolation film 20. On the third semiconductor pattern SP3 on the second channel pattern CH2, the gate dielectric film 41 may also be located on the lower surface of the second gate electrode 32 and on the sidewalls in the first horizontal direction D1.

[0105] The gate dielectric film 41 may be located between the third gate electrode 33 and the third channel pattern CH3. The gate dielectric film 41 may also be located between the third gate electrode 33 and the second portion 53. The gate dielectric film 41 may be disposed on the upper surface, lower surface, and sidewalls in the second horizontal direction D2 of each of the first to third semiconductor patterns SP1 to SP3 included in the third channel pattern CH3. The gate dielectric film 41 may also be disposed on the upper surface of the third active fin FA3 and the upper surface of the device isolation film 20. On the third semiconductor pattern SP3 of the third channel pattern CH3, the gate dielectric film 41 may be located on the lower surface of the third gate electrode 33 and on the sidewalls in the first horizontal direction D1.

[0106] The gate dielectric film 41 may be located between the fourth gate electrode 34 and the fourth channel pattern CH4. The gate dielectric film 41 may also be located between the fourth gate electrode 34 and the second portion 53. The gate dielectric film 41 may be disposed on the upper surface, lower surface, and sidewalls in the second horizontal direction D2 of each of the first to third semiconductor patterns SP1 to SP3 included in the fourth channel pattern CH4. The gate dielectric film 41 may also be disposed on the upper surface of the fourth active fin FA4 and the upper surface of the device isolation film 20. On the third semiconductor pattern SP3 of the fourth channel pattern CH4, the gate dielectric film 41 may be located on the lower surface of the fourth gate electrode 34 and on the sidewalls in the first horizontal direction D1.

[0107] The gate dielectric film 41 may include multiple layers comprising a low-k dielectric material and a high-k dielectric material. For example, the low-k dielectric material may include, but is not limited to, SiO2, SiN, SiOCN, SiOC, SiON, or a combination thereof. For example, the high-k dielectric material may include, but is not limited to, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or a combination thereof.

[0108] On the third semiconductor pattern SP3 of each of the first to fourth channel patterns CH1 to CH4 , gate spacers GS may be disposed on both sidewalls of each of the first to fourth gate electrodes 31 , 32 , 33 , and 34 in the first horizontal direction D1 .

[0109] The gate spacer GS may contact the third semiconductor pattern SP3 of each of the first to fourth channel patterns CH1 to CH4, but the embodiment is not limited thereto. The vertical height of the upper surface of the gate spacer GS in the D3 direction may be substantially the same as the vertical height of the upper surface of each of the first to second gate electrodes 31, 32, third to fourth gate electrodes 33, and 34 in the D3 direction, but the embodiment is not limited thereto.

[0110] The gate spacer GS may be spaced apart from the first gate electrode 31 in the first horizontal direction D1, with the gate dielectric film 41 positioned between the gate spacer GS and the first gate electrode 31, but the embodiment is not limited thereto. The gate spacer GS may be spaced apart from the second gate electrode 32 in the first horizontal direction D1, with the gate dielectric film 41 positioned between the gate spacer GS and the second gate electrode 32, but the embodiment is not limited thereto. The gate spacer GS may be spaced apart from the third gate electrode 33 in the first horizontal direction D1, with the gate dielectric film 41 positioned between the gate spacer GS and the third gate electrode 33, but the embodiment is not limited thereto. The gate spacer GS may be spaced apart from the fourth gate electrode 34 in the first horizontal direction D1, with the gate dielectric film 41 positioned between the gate spacer GS and the fourth gate electrode 34, but the embodiment is not limited thereto.

[0111] The gate spacer GS may include SiCN, SiCON, and / or SiN. In another embodiment, the gate electrode GS may include a multilayer including at least two of SiCN, SiCON, and SiN, ie, SiCN and SiCON, SiCN and SiN, or SiCON and SiN.

[0112] The capping film 70 may be disposed on the first gate electrode 31, the second gate electrode 32, the third gate electrode 33, and the fourth gate electrode 34, on the interlayer insulating layer 60, and on the second portion 53. The capping film 70 may include an insulating material. For example, the capping film 70 may include SiON, SiCN, SiCON, and / or SiN, but the embodiment is not limited thereto.

[0113] Figure 3A It shows Figure 2C Hereinafter, reference will be made to the example of the region M1. Figure 3A The lower partition 50 is described in detail.

[0114] Reference Figure 2C and Figure 3A, the upper surface 51a of the first portion 51 of the lower spacer 50 may contact the lower surface 53b of the second portion 53. The vertical height of the upper surface 51a of the first portion 51 in the D3 direction may be substantially the same as the vertical height of the upper surface SP3a of the third semiconductor pattern SP3 in the D3 direction. The upper surface SP3a of the third semiconductor pattern SP3 may also be referred to as the upper surface CH1a of the first channel pattern CH1. Figure 3A , only the upper surface CH1 a of the first channel pattern CH1 is illustrated, but the upper surface SP3 a of the third semiconductor pattern SP3 may also be referred to as an upper surface of each of the first to fourth channel patterns CH1 to CH4 .

[0115] The vertical height of the upper surface 51a of the first portion 51 in the D3 direction may be substantially the same as the vertical height of the upper surface 61a of the buried insulating pattern 61 in the D3 direction. The vertical height of the upper surface 61a of the buried insulating pattern 61 in the D3 direction may be substantially the same as the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction.

[0116] The width of the first portion 51 in the second horizontal direction D2 may be a first width W1. The first width W1 may be a value measured at a specific point of the first portion 51. The width of the second portion 53 in the second horizontal direction D2 may be a second width W2. The second width W2 may be a value measured at a specific point of the second portion 53.

[0117] For example, the first width W1 may be about 10 nm to about 25 nm, but the embodiment is not limited thereto. For example, the second width W2 may be about 5 nm to about 15 nm, but the embodiment is not limited thereto.

[0118] For example, the second width W2 may be smaller than the first width W1. For example, when the second width W2 is about 15 nm, the first width W1 may be greater than 15 nm and less than 25 nm or equal to 25 nm.

[0119] However, this corresponds only to an embodiment, and the first width W1 may be smaller than the second width W2. For example, the minimum width of the first portion 51 in the second horizontal direction D2 may be smaller than the maximum width of the second portion 53 in the second horizontal direction D2.

[0120] The width of the upper surface 51a of the first portion 51 in the second horizontal direction D2 may be greater than the width of the lower surface 53b of the second portion 53 in the second horizontal direction D2. In other words, the width of the lower surface 53b of the second portion 53 in the second horizontal direction D2 may be smaller than the width of the upper surface 51a of the first portion 51 in the second horizontal direction D2.

[0121] The first portion 51 may be spaced apart from the first channel pattern CH1 in the second horizontal direction D2, with the buried insulating pattern 61 between the first portion 51 and the first channel pattern CH1. The buried insulating pattern 61 may contact the sidewall CH1t of the first channel pattern CH1 in the second horizontal direction D2. The buried insulating pattern 61 may contact the sidewall CH2t of the second channel pattern CH2 in the second horizontal direction D2. Figure 3A , although the buried insulating pattern 61 is shown only on the sidewall CH1t of the first channel pattern CH1 in the second horizontal direction D2, the buried insulating pattern 61 may also contact the sidewall of each of the third and fourth channel patterns CH3 and CH4 in the second horizontal direction D2.

[0122] The distance between the first portion 51 and the first channel pattern CH1 in the second horizontal direction D2 may be a third width W3. The third width W3 may be about 1 nm to about 5 nm, but the embodiment is not limited thereto. The third width W3 may be equal to the distance between the first portion 51 and each of the second to fourth channel patterns CH2 to CH4 in the second horizontal direction D2.

[0123] The first portion 51 may contact the inner wall 61 t of the buried insulating pattern 61. The first portion 51 may at least partially cover the inner wall 61 t of the buried insulating pattern 61.

[0124] Figure 3B It shows Figure 2C Hereinafter, reference will be made to the enlarged view of another example of the region M1. Figure 3B The lower separator 50 will be described in detail. Figures 1 to 3A The same description is given, and only the differences are described in detail.

[0125] Reference Figures 2C to 3B , the semiconductor device 1 may further include a channel dielectric film PTL located between the third semiconductor pattern SP3 and the buried insulating pattern 61. The channel dielectric film PTL may also be located between the second semiconductor pattern SP2 and the buried insulating pattern 61. Although not in Figure 3B , the channel dielectric film PTL may also be located between the first semiconductor pattern SP1 and the buried insulating pattern 61. That is, the channel dielectric film PTL may be located between the first channel pattern CH1 and the buried insulating pattern 61. The channel dielectric film PTL may be located between the second channel pattern CH2 and the buried insulating pattern 61. Although not shown in FIG. Figure 3B , but the channel dielectric film PTL may also be located between the third channel pattern CH3 and the buried insulating pattern 61 and between the fourth channel pattern CH4 and the buried insulating pattern 61 .

[0126] Due to the channel dielectric film PTL, the sidewall CH1t of the first channel pattern CH1 in the second horizontal direction D2 may recede in the second horizontal direction D2. Due to the channel dielectric film PTL, the sidewall CH2t of the second channel pattern CH2 in the second horizontal direction D2 may recede in the second horizontal direction D2. Figure 3B , but due to the channel dielectric film PTL, a sidewall of each of the third channel pattern CH3 and the fourth channel pattern CH4 in the second horizontal direction D2 may recede in the second horizontal direction D2.

[0127] The channel dielectric film PTL may contact each of the first to fourth channel patterns CH1 to CH4 .The channel dielectric film PTL may contact the buried insulating pattern 61 .

[0128] The first channel pattern CH1 may be spaced apart from the buried insulating pattern 61 in the second horizontal direction D2. The second channel pattern CH2 may be spaced apart from the buried insulating pattern 61 in the second horizontal direction D2. Figure 3B , the third channel pattern CH3 may be spaced apart from the buried insulating pattern 61 in the second horizontal direction D2. Figure 3B , but the fourth channel pattern CH4 may be spaced apart from the buried insulation pattern 61 in the second horizontal direction D2.

[0129] and Figure 3A Different from the above, the third width W3 may be a distance between the first portion 51 and the trench dielectric film PTL in the second horizontal direction D2.

[0130] The channel dielectric film PTL may include an oxide layer, a nitride layer, or a combination thereof. As an example, the channel dielectric film PTL may include the same material as the buried insulating pattern 61. In other embodiments, the channel dielectric film PTL may include a material different from that of the buried insulating pattern 61.

[0131] Figure 3C It shows Figure 2C Hereinafter, reference will be made to the enlarged view of another example of the region M1. Figure 3C The lower separator 50 will be described in detail. Figure 1 、 Figures 2A to 2D as well as Figure 3A The same description is given, and only the differences are described in detail.

[0132] Reference Figure 2C and Figure 3CThe first portion 51 may have a first upper surface 51a1 and a second upper surface 51a2. The first upper surface 51a1 may be a portion of the upper surface 51a of the first portion 51 that contacts the lower surface 53b of the second portion 53. The first upper surface 51a1 may be located at the center of the first portion 51. The second upper surface 51a2 may be a portion of the upper surface 51a of the first portion 51 other than the first upper surface 51a1. The second upper surface 51a2 may be located at an edge of the first portion 51. The second upper surface 51a2 may be a portion extending from the first upper surface 51a1 in the second horizontal direction D2.

[0133] The vertical height of the first upper surface 51a1 in the direction D3 may be constant. The vertical height of the second upper surface 51a2 in the direction D3 may decrease as the distance of the second upper surface 51a2 from the first upper surface 51a1 in the second horizontal direction D2 increases. The vertical height of the second upper surface 51a2 in the direction D3 may decrease from the first upper surface 51a1 toward the sidewall CH1t of the first channel pattern CH1 in the second horizontal direction D2.

[0134] For example, the second upper surface 51a2 may have an upwardly convex curve. Figure 3C As shown in FIG. 5 , the second upper surface 51 a 2 may have a downwardly convex curve. That is, the center of the curvature of the second upper surface 51 a 2 may be inside the first portion 51 , or may be outside the first portion 51 .

[0135] Near the inner wall 61t of the buried insulating pattern 61, the vertical height of the second upper surface 51a2 in the D3 direction may be lower than the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction. This relationship may also be applied between the upper surface of each of the second to fourth channel patterns CH2 to CH4 and the second upper surface 51a2.

[0136] The gate dielectric film 41 may be on the second upper surface 51a2 and at least partially cover the second upper surface 51a2. The gate dielectric film 41 may extend from the sidewalls of the second portion 53 to below the vertical height of the upper surface CH1a of the first channel pattern CH1 in the direction D3. The gate dielectric film 41 may also cover at least a portion of the inner wall 61t of the buried insulating pattern 61 and the upper surface 61a of the buried insulating pattern 61.

[0137] Figure 3D It shows Figure 2C Hereinafter, reference will be made to the enlarged view of another example of the region M1. Figure 3D The lower separator 50 will be described in detail. Figure 1 、 Figures 2A to 2D as well as Figure 3AThe same description is given, and only the differences are described in detail.

[0138] Reference Figure 2C and Figure 3D , the vertical height of the upper surface 51a of the first portion 51 in the D3 direction may be lower than the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction. The vertical height of the lower surface 53b of the second portion 53 in the D3 direction may be lower than the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction. The relationship between the vertical height of the upper surface 51a of the first portion 51 in the D3 direction and the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction may also be applied to the relationship between the vertical height of the upper surface 51a of the first portion 51 in the D3 direction and the vertical height of the upper surface of each of the second to fourth channel patterns CH2 to CH4 in the D3 direction. The relationship between the vertical height of the lower surface 53b of the second portion 53 in the D3 direction and the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction can also be applied to the relationship between the vertical height of the lower surface 53b of the second portion 53 in the D3 direction and the vertical height of the upper surface of each of the second to fourth channel patterns CH2 to CH4 in the D3 direction.

[0139] The gate dielectric film 41 may extend from the upper surface CH1a of the first channel pattern CH1 to the inner wall 61t of the buried insulating pattern 61. The gate dielectric film 41 may extend from the inner wall 61t of the buried insulating pattern 61 to the upper surface 51a of the first portion 51. The gate dielectric film 41 may extend from the upper surface 51a of the first portion 51 to the sidewall of the second portion 53. The gate dielectric film 41 may be on the inner wall 61t of the buried insulating pattern 61 and the upper surface 51a of the first portion 51 and at least partially cover the inner wall 61t of the buried insulating pattern 61 and the upper surface 51a of the first portion 51.

[0140] A vertical distance in the D3 direction from the upper surface 51a of the first portion 51 to the upper surface CH1a of the first channel pattern CH1 may be a first height H1. The first height H1 may be greater than 0 and less than or equal to about 35nm, but the embodiment is not limited thereto. For example, a vertical height in the D3 direction of the upper surface 51a of the first portion 51 may be lower than a vertical height in the D3 direction of the lower surface of the third semiconductor pattern SP3.

[0141] Figure 4A and Figure 4B Along the Figure 1 A cross-sectional view taken along line Y1-Y1' and line Y2-Y2'. Figure 5 It shows Figure 4AHereinafter, the above referenced regions M2 are omitted. Figures 1 to 3A The same description is given, and only the differences are described in detail.

[0142] Reference Figure 4A 、 Figure 4B and Figure 5 , the semiconductor device 2 may not be included in Figure 1 and Figures 2A to 2D The semiconductor device 1 includes a protective film 25 and a buried insulating pattern 61 .

[0143] The device isolation film 20 may contact the upper surface of the substrate 10 and a sidewall of each of the first to fourth active fins FA1 to FA4 .

[0144] The first portion 51 of the lower spacer 50 may contact the first to fourth channel patterns CH1 to CH4, the first to fourth active fins FA1 to FA4, and the gate dielectric film 41. The first portion 51 may contact the upper surface of the substrate 10 within the first and second trenches TR1 and TR2.

[0145] Figure 6 It is along Figure 1 A cross-sectional view taken along line Y1-Y1'. Figure 7A It shows Figure 6 An enlarged view of an example of the region M3 in FIG. Figure 1 、 Figures 2A to 2D as well as Figure 3A The same description is given, and only the differences are described in detail.

[0146] Reference Figure 6 and Figure 7A , the semiconductor device 3 may not include Figure 1 and Figures 2A to 2D The semiconductor device 1 includes a protective film 25 and a buried insulating pattern 61 .

[0147] The device isolation film 20 may contact the upper surface of the substrate 10 and a sidewall of each of the first to fourth active fins FA1 to FA4 .

[0148] The first portion 51 of the lower spacer 50 may contact the first to fourth channel patterns CH1 to CH4, the first to fourth active fins FA1 to FA4, and the gate dielectric film 41. The first portion 51 may contact the upper surface of the substrate 10 within the first and second trenches TR1 and TR2.

[0149] The first portion 51 and the second portion 53 of the semiconductor device 3 may be formed as one body, that is, the first portion 51 and the second portion 53 may form an integral structure. That is, there may be no boundary between the first portion 51 and the second portion 53. The first portion 51 and the second portion 53 may include the same material.

[0150] exist Figure 7A , the first portion 51 may be separated from the second portion 53 of the lower spacer 50 by the upper surface CH1a of the first channel pattern CH1 as a boundary. The first portion 51 may be a portion of the lower spacer 50 below the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction. The second portion 53 may be another portion of the lower spacer 50 above the vertical height of the upper surface CH1a of the first channel pattern CH1 in the D3 direction. However, for ease of description, the first portion 51 and the second portion 53 are separated, and the lower spacer 50 may be formed integrally or as a single unitary structure.

[0151] Figure 7B It shows Figure 6 In the following, the above reference to FIG. 16 and FIG. 17 is omitted. Figure 7A as well as Figure 3A The same description is given, and only the differences are described in detail.

[0152] Reference Figure 7B , a vertical height of the upper surface 51 a of the first portion 51 in the direction D3 may become higher from the sidewall CH1 t of the first channel pattern CH1 toward the center of the first portion 51 in the second horizontal direction D2 .

[0153] The upper surface 51a of the first portion 51 may have a curved surface COV. The curved surface COV of the first portion 51 may be convex downward. In other embodiments, the curved surface COV of the first portion 51 may be concave upward.

[0154] The gate dielectric film 41 may extend from the upper surface CH1a of the first channel pattern CH1 to the sidewall CH1t of the first channel pattern CH1 in the second horizontal direction D2. The gate dielectric film 41 may extend from the sidewall CH1t of the first channel pattern CH1 to the curved surface COV of the first portion 51 in the second horizontal direction D2. The gate dielectric film 41 may extend from the curved surface COV of the first portion 51 to the sidewall of the second portion 53. The gate dielectric film 41 may contact the curved surface COV of the first portion 51.

[0155] The first gate electrode 31 may extend between the third semiconductor pattern SP3 and the lower spacer 50. Figure 7BAs shown in FIG, the first gate electrode 31 may also extend between the second semiconductor pattern SP2 and the lower spacer 50 or between the first semiconductor pattern SP1 and the lower spacer 50. The first gate electrode 31 may extend between the first channel pattern CH1 and the lower spacer 50. Similarly, Figure 6 and Figure 7B Each of the second, third, and fourth gate electrodes 32 , 33 , and 34 may extend between a corresponding one of the second, third, and fourth channel patterns CH2 , CH3 , and CH4 and the lower spacer 50 .

[0156] A vertical distance in the D3 direction from the upper surface 51a of the first portion 51 to the upper surface CH1a of the first channel pattern CH1 may be a second height H2. The second height H2 may be 0 nm to about 15 nm, but the embodiment is not limited thereto.

[0157] Figures 8A to 8C 、 Figures 9A to 9C 、 10A to 10C 、 Figures 11A to 11C 、 12A to 12C 、 13A to 13C 、 FIG. 14A to FIG. 14B 、 Figures 15A to 15C 、 16A to 16C 、 17A to 17C 、 18A to 18C 、 Figures 19A to 19B 、 20A to 20C 、 21A to 21D 、 FIG. 22A to FIG. 22B 、 Figures 23A to 23C as well as FIG. 24A to FIG. 24B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A and Figure 24A Along the Figure 1 A cross-sectional view taken along line X1-X1'. Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14A 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 20B 、 Figure 21B and Figure 23B Along the Figure 1 A cross-sectional view taken along line X2-X2'. Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C 、 Figure 12C 、 Figure 13C 、 Figure 14B 、 Figure 15C 、 Figure 16C 、 Figure 17C 、 Figure 18C 、 Figure 19B 、 Figure 20C 、 Figure 21C and Figure 24B Along the Figure 1 A cross-sectional view taken along line Y1-Y1'. Figure 21D 、 Figure 22B and Figure 23C Along the Figure 1 A cross-sectional view taken along line Y2-Y2'.

[0158] In the following, reference is made to Figures 8A to 8C 、 Figures 9A to 9C 、 10A to 10C 、 Figures 11A to 11C 、 12A to 12C 、 13A to 13C 、 FIG. 14A to FIG. 14B 、 Figures 15A to 15C 、 16A to 16C 、 17A to 17C 、 18A to 18C 、 Figures 19A to 19B 、 20A to 20C 、 21A to 21D 、 FIG. 22A to FIG. 22B 、 Figures 23A to 23C and FIG. 24A to FIG. 24B Describe the manufacturing reference above Figure 1 and Figures 2A to 2D A method of manufacturing a semiconductor device 1 is described.

[0159] Reference Figures 8A to 8C A substrate 10 including a first region 10_1, a second region 10_2, a third region 10_3, and a fourth region 10_4 may be provided. The substrate 10 may include first to fourth active fins FA1 to FA4. Each of the first to fourth active fins FA1 to FA4 may be a portion protruding vertically upward from the substrate 10. Each of the first to fourth active fins FA1 to FA4 may extend in a first horizontal direction D1. The first to fourth active fins FA1 to FA4 may be spaced apart from each other in a second horizontal direction D2.

[0160] The first to fourth active fins FA1 to FA4 may be disposed in corresponding regions among the first, second, third, and fourth regions 10_1, 10_2, 10_3, and 10_4, respectively. For example, the first active fin FA1 may be disposed in the first region 10_1.

[0161] The substrate 10 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, and / or InP. The terms SiGe, SiC, GaAs, InAs, InGaAs, and InP used in this specification refer to materials including the elements included in each term and do not represent chemical formulas representing stoichiometric relationships.

[0162] A sacrificial layer SAL and an active layer ACL, alternately stacked one by one, may be disposed on each of the first to fourth active fins FA1 to FA4 of the substrate 10 .

[0163] Each of the sacrificial layers SAL and each of the active layers ACL may extend in the first horizontal direction D1 along a corresponding one of the first to fourth active fins FA1 to FA4 .

[0164] Each of the active layers ACL may include silicon, germanium and / or silicon-germanium. For example, each of the active layers ACL may include crystalline silicon.

[0165] Each of the sacrificial layers SAL may include a material having an etching selectivity with respect to each of the active layers ACL. Each of the sacrificial layers SAL may include one of silicon, germanium, and silicon-germanium, which is different from the material included in the active layer ACL. For example, the active layer ACL may include silicon, and the sacrificial layers SAL may include silicon-germanium. The concentration of germanium in each of the sacrificial layers SAL may be approximately 10 at % to approximately 30 at %.

[0166] A stopper film 110 may be formed on the uppermost one of the active layer ACL and the sacrificial layer SAL. The stopper film 110 may vertically overlap each of the first to fourth active fins FA1 to FA4 in the D3 direction. The stopper film 110 may extend in the first horizontal direction D1.

[0167] The stop film 110 may include, for example, polysilicon.

[0168] A protection mask 120 may be formed on the stopper film 110. The protection mask 120 may vertically overlap the stopper film 110 in a D3 direction.

[0169] The substrate 10 may include a first trench TR1, a second trench TR2, and a third trench TR3. The first trench TR1 may be located between the first active fin FA1 and the second active fin FA2. The second trench TR2 may be located between the third active fin FA3 and the fourth active fin FA4. The third trench TR3 may be located between the second active fin FA2 and the third active fin FA3.

[0170] Reference Figures 9A to 9C A preliminary protective film 130 may be formed. The preliminary protective film 130 may conformally cover the upper surface of the substrate 10 exposed by the first to third trenches TR1 to TR3, the sidewalls of each of the first to fourth active fins FA1 to FA4, the sidewalls of each of the sacrificial layer SAL and the active layer ACL, the sidewalls of the stop film 110, and the sidewalls of the protective mask 120, thereby at least partially covering the upper surface of the substrate 10 exposed by the first to third trenches TR1 to TR3, the sidewalls of each of the first to fourth active fins FA1 to FA4, the sidewalls of each of the sacrificial layer SAL and the active layer ACL, the sidewalls of the stop film 110, and the sidewalls of the protective mask 120. The preliminary protective film 130 may also be on the upper surface of the protective mask 120 and at least partially cover the upper surface of the protective mask 120. The preliminary protective film 130 may extend in both the first horizontal direction D1 and the second horizontal direction D2.

[0171] The preliminary protection film 130 may include an oxide film, a nitride film, or a combination thereof.

[0172] The preliminary protective film 130 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof. CVD may include atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and / or plasma enhanced CVD (PECVD). However, embodiments of the method of forming the preliminary protective film 130 are not limited thereto.

[0173] Reference 10A to 10C , a first separation film 140 may be formed on the preliminary protective film 130. The first separation film 140 may be on the preliminary protective film 130 and at least partially cover the preliminary protective film 130. The first separation film 140 may completely fill the first trench TR1 and the second trench TR2. The first separation film 140 may fill at least a portion of the third trench TR3.

[0174] The first separator film 140 may include an insulating material. As an example, the first separator film 140 may include an oxide, a nitride, or a combination thereof. As an example, the first separator film 140 may include SiN, SiO2, SiBN, SiON, SiOCN, SiBCN, and / or SiOC.

[0175] Reference Figures 11A to 11C, an etch-back process may be performed on the first separation film 140. Due to the etch-back process, a portion of the first separation film 140 may be etched. Here, other components except the first separation film 140 may be protected by the preliminary protection film 130.

[0176] Due to the etching of a portion of the first separation film 140, the vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be reduced. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be lower than the vertical height of the upper surface of the protective mask 120 in the D3 direction. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be higher than the vertical height of the lower surface of the protective mask 120 in the D3 direction. In other embodiments, the vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be lower than the vertical height of the upper surface of the stop film 110 in the D3 direction. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be higher than the vertical height of the lower surface of the stop film 110 in the D3 direction.

[0177] Due to the etch-back process, the portion of the first separation film 140 within the third trench TR3 may be completely removed. The first separation film 140 may remain only in the first trench TR1 and the second trench TR2.

[0178] Reference Figure 12A and Figure 12C , a preliminary device isolation film 150 may be formed on the entire upper surface of the substrate 10. The preliminary device isolation film 150 may be on the preliminary protection film 130 and the first separation film 140 and at least partially cover the preliminary protection film 130 and the first separation film 140.

[0179] The preliminary device isolation film 150 may include an insulating material. The preliminary device isolation film 150 may include an oxide film, a nitride film, or a combination thereof.

[0180] Reference 13A to 13C , a planarization process may be performed on the preliminary device isolation film 150. For example, the planarization process may include chemical mechanical polishing (CMP).

[0181] Due to the planarization process, a portion of the preliminary protective film 130 and the protective mask 120 may be removed. Due to the planarization process, the upper surface of the stopper film 110, the upper surface of the first separation film 140, and the upper surface of the preliminary device isolation film 150 may be coplanar with each other. For example, due to the planarization process, a portion of the stopper film 110 and a portion of the first separation film 140 may also be removed.

[0182] Reference Figure 14A and Figure 14B, an etch-back process may be performed on the first separation film 140. Due to the etch-back process, a portion of the first separation film 140 may be removed. Due to the etch-back process, a first portion 51 may be formed from the first separation film 140. Here, components other than the first separation film 140 may be protected by the preliminary device isolation film 150, the stopper film 110, and the preliminary protective film 130.

[0183] A vertical height of an upper surface 51 a of the first portion 51 in the D3 direction may be lower than a vertical height of an upper surface of the stop film 110 in the D3 direction.

[0184] Reference Figures 15A to 15C A protective spacer film 160 may be formed on the entire upper surface of the substrate 10. The protective spacer film 160 may conformally cover the upper surface of the preliminary device isolation film 150, the upper surface of the stopper film 110, and the upper surface 51a of the first portion 51, and at least partially cover the upper surface of the preliminary device isolation film 150, the upper surface of the stopper film 110, and the upper surface 51a of the first portion 51. Within the first trench TR1 and the second trench TR2, the protective spacer film 160 may be on the inner wall (or surface) of the preliminary protective film 130 and at least partially cover the inner wall (or surface) of the protective film 130.

[0185] The protection spacer film 160 may include a material having an etch selectivity with respect to a material that the stop film 110 may include. For example, the protection spacer film 160 may include silicon oxide.

[0186] Reference 16A to 16C , an etch-back process may be performed on the protective spacer film 160. Due to the etch-back process, the protective spacer film 160 on the flat surface may be removed. That is, due to the etch-back process, a portion of the protective spacer film 160 that is on and at least partially covers the upper surface of the preliminary device isolation film 150 and the upper surface of the stopper film 110 may be removed. In addition, another portion of the protective spacer film 160 that is on and at least partially covers the central portion of the upper surface 51 a of the first portion 51 may also be removed.

[0187] However, another portion of the protective spacer film 160, which is on the inner wall (or surface) of the preliminary protective film 130 and at least partially covers the inner wall (or surface) of the preliminary protective film 130, may remain within the first trench TR1 and the second trench TR2. The remaining portion of the protective spacer film 160 may be referred to as a protective spacer 161. That is, the protective spacer 161 may be formed from the protective spacer film 160 due to the etch-back process. The protective spacer 161 may be on the inner wall (or surface) of the preliminary protective film 130 within the first trench TR1 and the second trench TR2 and at least partially cover the inner wall (or surface) of the preliminary protective film 130 within the first trench TR1 and the second trench TR2. The protective spacer 161 may be on the edge of the upper surface 51a of the first portion 51 and at least partially cover the edge of the upper surface 51a of the first portion 51.

[0188] Reference 17A to 17C The second separation film 170 may be formed on the entire upper surface of the substrate 10. The second separation film 170 may at least partially fill all empty spaces in the first trench TR1 and the second trench TR2. The second separation film 170 may be in contact with the first portion 51. The second separation film 170 may also be formed on the preliminary device isolation film 150 and the stopper film 110.

[0189] The second separation film 170 may include a material that the first portion 51 may include. The second separation film 170 may include the same material as that of the first portion 51 or may include a material different from that of the first portion 51.

[0190] Reference Figure 18A and Figure 18C A planarization process may be performed on the second separation film 170. The planarization process may include a CMP process. Due to the planarization process, the upper surface of the second separation film 170, the upper surface of the preliminary device isolation film 150, and the upper surface of the stopper film 110 may be coplanar with each other.

[0191] Due to the protection spacer 161 , the width of the second separation film 170 in the second horizontal direction D2 may be smaller than the width of the first portion 51 in the second horizontal direction D2 .

[0192] Reference Figure 19A and Figure 19B , the stop film 110 may be removed. To remove the stop film 110, a wet etching process or a dry etching process may be used. While the stop film 110 is being removed, other components may not be removed.

[0193] Reference Figure 20A and Figure 20CAn etching process may be performed on the preliminary device isolation film 150 and the preliminary protective film 130. Due to the etching process, the device isolation film 20 may be formed from the preliminary device isolation film 150, and the protective film 25 and the mask insulating pattern 61 may be formed from the preliminary protective film 130.

[0194] The protection film 25 may be located between the device isolation film 20 and the substrate 10 and between each of the first to fourth active fins FA1 to FA4 and the device isolation film 20. The mask insulating pattern 61 may be a portion at least partially covering a surface of the first portion 51 within the first and second trenches TR1 and TR2.

[0195] Due to the etching process, at least a portion of surfaces of the active layer ACL and the sacrificial layer SAL may be exposed.

[0196] Subsequently, a passivation film EGO may be formed on the device isolation film 20, the active layer ACL, and the sacrificial layer SAL. The passivation film EGO may extend from the upper surface of the device isolation film 20 to the sidewalls of the active layer ACL and the sidewalls of the sacrificial layer SAL. The passivation film EGO may extend from the sidewalls of the active layer ACL and the sidewalls of the sacrificial layer SAL to the sidewalls and upper surface of the second separation film 170.

[0197] The passivation film EGO may include, for example, silicon oxide.

[0198] Reference 21A to 21D , sacrificial patterns PP may be formed across the active layer ACL and the sacrificial layer SAL. Each of the sacrificial patterns PP may be formed in a line shape or a stripe shape extending in the second horizontal direction D2.

[0199] In detail, forming the sacrificial pattern PP may include forming a sacrificial film on the entire upper surface of the substrate 10, forming a photomask (not shown) on the sacrificial film, and patterning the sacrificial film using the photomask as an etching mask. The sacrificial film may include polysilicon. Therefore, the sacrificial pattern PP may include polysilicon.

[0200] When forming the sacrificial pattern PP from the sacrificial film, a portion of the passivation layer EGO that does not vertically overlap the sacrificial pattern PP in the D3 direction may be removed. That is, the remaining passivation layer EGO may vertically overlap the sacrificial pattern PP in the D3 direction.

[0201] A gate spacer film GSa may be formed on both sidewalls of each of the sacrificial patterns PP. The gate spacer film GSa may be conformally formed on the entire upper surface of the substrate 10. Figure 21DAs shown in FIG, in a space not vertically overlapping the sacrificial pattern PP, the gate spacer film GSa may extend from the upper surface of the device isolation film 20 to the sidewalls of the active layer ACL and the sacrificial layer SAL. In a space not vertically overlapping the sacrificial pattern PP, the gate spacer film GSa may extend from the sidewalls of the active layer ACL and the sidewalls of the sacrificial layer SAL to the sidewalls and upper surface of the second separation film 170. In embodiments, the gate spacer film GSa may include a plurality of films including at least two films.

[0202] Next, a hard mask pattern MP may be formed to vertically overlap the sacrificial pattern PP in the D3 direction. The hard mask pattern MP may be formed on the gate spacer film GSa, and in other embodiments, unlike shown, may be directly formed on the sacrificial pattern PP.

[0203] Reference FIG. 22A to FIG. 22B A first recess RS1 may be formed in the active layer ACL and the sacrificial layer SAL on the first active fin FA1. A plurality of first recesses RS1 may be formed. Similarly, a second recess RS2, a third recess RS3, and a fourth recess RS4 may be formed on corresponding active fins of the second to fourth active fins FA2 to FA4, respectively.

[0204] In detail, the active layer ACL and the sacrificial layer SAL may be etched using the hard mask pattern MP and the gate spacer film GSa as etching masks to form first to fourth recesses RS1 to RS4. Each of the first to fourth recesses RS1 to RS4 may be formed between a pair of sacrificial patterns PP. Here, a portion of the gate spacer film GSa may be removed in a space that does not vertically overlap the hard mask pattern MP in the D3 direction.

[0205] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed to be sequentially stacked between adjacent first recesses RS1 from the active layer ACL. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent first recesses RS1 may form a first channel pattern CH1. FIG. 22A to FIG. 22B , but second to fourth channel patterns CH2 to CH4 may also be formed. Thereafter, the hard mask pattern MP may be removed.

[0206] If the width of the second separation film 170 in the horizontal direction D2 is not smaller than the width of the first portion 51 in the horizontal direction D2, portions of the sacrificial layer SAL and the active layer ACL will not be etched when forming the first to fourth recesses RS1 to RS4, but will remain near the sidewalls of the first portion 51. This is because a shadowing effect occurs due to the second separation film 170 during the etching process for forming the first to fourth recesses RS1 to RS4. The remaining sacrificial layer SAL and the active layer ACL may adversely affect the electrical characteristics and reliability of the first to fourth source / drain patterns SD1 to SD4, as described below. In other words, the electrical characteristics and reliability of the semiconductor device 1 may be degraded.

[0207] According to an embodiment of the inventive concept, the width of the second separation film 170 in the second horizontal direction D2 can be smaller than the width of the first portion 51 in the second horizontal direction D2. Due to this, when forming the first to fourth recesses RS1 to RS4, both the sacrificial layer SAL and the active layer ACL can be removed from the first to fourth recesses RS1 to RS4. Therefore, the electrical characteristics and reliability of the semiconductor device 1 can be improved.

[0208] Reference Figure 23A and Figure 23C , a first source / drain pattern SD1 may be formed in the first recess RS1. Specifically, the first source / drain pattern SD1 may be formed by performing a SEG process using the inner wall of the first recess RS1 as a seed layer. The SEG process may be performed multiple times. When the SEG process is performed multiple times, the first source / drain pattern SD1 may include multiple components. Similarly, second to fourth source / drain patterns SD2 to SD4 may also be formed in corresponding recesses in the second to fourth recesses RS2 to RS4, respectively.

[0209] As an example, the SEG process may include a CVD process or a molecular beam epitaxy (MBE) process.

[0210] While forming the first to fourth source / drain patterns SD1 to SD4, impurities may be implanted into the first to fourth source / drain patterns SD1 to SD4, respectively. For example, first conductivity type impurities may be implanted into the first and second source / drain patterns SD1 and SD2, and second conductivity type impurities may be implanted into the third and fourth source / drain patterns SD3 and SD4.

[0211] After forming the first to fourth source / drain patterns SD1 to SD4, the second separation film 170 may be patterned to form the second portion 53. The second portion 53 and the first portion 51 may be collectively referred to as a lower spacer 50.

[0212] Subsequently, an upper spacer 55 may be formed on the first portion 51. The upper spacer 55 may contact the first portion 51 and the second portion 53. A vertical height of an upper surface of the upper spacer 55 in the D3 direction may be higher than a vertical height of an upper surface of the second portion 53 in the D3 direction.

[0213] The upper spacer 55 may overlap the second portion 53 in the first horizontal direction D1. A sidewall of the upper spacer 55 in the first horizontal direction D1 may contact a sidewall of the second portion 53 in the first horizontal direction D1.

[0214] The upper separator 55 may be distinguished from the first portion 51 and the second portion 53, but the embodiment is not limited thereto. As an example, the upper separator 55 may be integrally formed with at least one of the first portion 51 and the second portion 53, that is, the upper separator 55 and the first portion 51 and / or the second portion 53 may form a unitary structure.

[0215] An interlayer insulating layer 60 may be formed on the first to fourth source / drain patterns SD1 to SD4 and at least partially cover them. The interlayer insulating layer 60 may be formed on and at least partially cover a portion of the sidewalls of the gate spacer film GSa. The interlayer insulating layer 60 may also cover the upper spacer 55. As an example, the interlayer insulating layer 60 may include a silicon oxide film.

[0216] Reference Figure 24A and Figure 24B , the sacrificial pattern PP may be exposed by removing a portion of the gate spacer film GSa. As a portion of the gate spacer film GSa is removed, a gate spacer GS may be formed from the gate spacer film GSa.

[0217] The exposed sacrificial pattern PP may be selectively removed. By removing the sacrificial pattern PP, the first to second channel patterns CH1 to CH4 and the sacrificial layer SAL may be exposed. Removing the sacrificial pattern PP may include wet etching using an etchant that selectively etches polysilicon.

[0218] The sacrificial layer SAL may be selectively removed. Specifically, by performing an etching process to selectively etch the sacrificial layer SAL, only the sacrificial layer SAL may be removed while leaving the first, second, and third semiconductor patterns SP1, SP2, and SP3 intact. The etching process may be wet etching.

[0219] Return to reference Figures 2A to 2DA gate dielectric film 41 may be formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP3. The gate dielectric film 41 may be formed to surround each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 in a cross-sectional view taken along the first direction D1. The gate dielectric film 41 may further extend onto the upper surface of the device isolation film 20. The gate dielectric film 41 may further extend to the sidewall of the second portion 53 in the second horizontal direction D2.

[0220] The first, second, third, and fourth gate electrodes 31, 32, 33, and 34 may be formed on the gate dielectric film 41. The capping film 70 may be formed on the first, second, third, and fourth gate electrodes 31, 32, 33, and 34. Thus, the semiconductor device 1 may be manufactured.

[0221] exist Figure 4A 、 Figure 4B and Figure 5 In the method for manufacturing the semiconductor device 2 shown in FIG, the steps in Figures 9A to 9C The preliminary protective film 130 is formed as described in the above reference. Figures 8A to 25B The manufacturing method is described.

[0222] Figures 25A to 25C 、 Figures 26A to 26C 、 Figures 27A to 27C 、 Figures 28A to 28C 、 Figures 29A to 29B 、 FIG. 30A to FIG. 30B 、 Figures 31A to 31B 、 Figure 32 as well as Figure 33 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. Figure 25A 、 Figure 26A 、 Figure 27A 、 Figure 28A and Figure 31A Along the Figure 1 A cross-sectional view taken along line X1-X1'. Figure 25B 、 Figure 26B 、 Figure 27B 、 Figure 28B 、 Figure 29A and Figure 30A It is along Figure 1 A cross-sectional view taken along line X2-X2'. Figure 25C 、 Figure 26C 、 Figure 27C 、 Figure 28C 、 Figure 29B 、 Figure 30B 、 Figure 31B 、 Figure 32 and Figure 33 It is along Figure 1A cross-sectional view taken along line Y1-Y1'.

[0223] In the following, reference is made to Figures 25A to 25C 、 Figures 26A to 26C 、 Figures 27A to 27C 、 Figures 28A to 28C 、 Figures 29A to 29B 、 FIG. 30A to FIG. 30B 、 Figures 31A to 31B 、 Figure 32 and Figure 33 Description of manufacturing reference above Figure 6 、 Figure 7A and Figure 7B The method of the semiconductor device 3 is described.

[0224] By executing the above reference Figures 8A to 8C The manufacturing method described is to set Figures 25A to 25C .

[0225] Reference Figures 25A to 25C A first separation film 140 may be formed on the substrate 10. The first separation film 140 may be on the substrate 10, the active layer ACL, the sacrificial layer SAL, the stop film 110, and the protective mask 120, and at least partially cover the substrate 10, the active layer ACL, the sacrificial layer SAL, the stop film 110, and the protective mask 120. The first separation film 140 may completely fill the first trench TR1 and the second trench TR2. The first separation film 140 may fill at least a portion of the third trench TR3.

[0226] The first separator film 140 may include an insulating material. As an example, the first separator film 140 may include an oxide, a nitride, or a combination thereof. As an example, the first separator film 140 may include SiN, SiO2, SiBN, SiON, SiOCN, SiBCN, and / or SiOC.

[0227] Reference Figures 26A to 26C , an etch-back process may be performed on the first separation film 140. Due to the etch-back process, a portion of the first separation film 140 may be etched.

[0228] Since a portion of the first separation film 140 is etched, the vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be reduced. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be lower than the vertical height of the upper surface of the protective mask 120 in the D3 direction. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be higher than the vertical height of the lower surface of the protective mask 120 in the D3 direction. In other embodiments, the vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be lower than the vertical height of the upper surface of the stop film 110 in the D3 direction. The vertical height of the uppermost surface of the first separation film 140 in the D3 direction may be higher than the vertical height of the lower surface of the stop film 110 in the D3 direction.

[0229] Due to the etch-back process, the portion of the first separation film 140 within the third trench TR3 may be completely removed. The first separation film 140 may remain only in the first trench TR1 and the second trench TR2.

[0230] Reference Figures 27A to 27C , a preliminary device isolation film 150 may be formed on the entire upper surface of the substrate 10. The preliminary device isolation film 150 may be on the substrate 10, the active layer ACL, the sacrificial layer SAL, the stop film 110, the protective mask 120, and the first separation film 140, and at least partially cover the substrate 10, the active layer ACL, the sacrificial layer SAL, the stop film 110, the protective mask 120, and the first separation film 140.

[0231] The preliminary device isolation film 150 may include an insulating material. The preliminary device isolation film 150 may include an oxide film, a nitride film, or a combination thereof.

[0232] Reference Figures 28A to 28C , a planarization process may be performed on the preliminary device isolation film 150. For example, the planarization process may include a planarization CMP process.

[0233] Due to the planarization process, the protective mask 120 may be removed. Due to the planarization process, the upper surface of the stopper film 110, the upper surface of the first separation film 140, and the upper surface of the preliminary device isolation film 150 may be coplanar with each other. For example, due to the planarization process, a portion of the stopper film 110 and a portion of the first separation film 140 may be removed.

[0234] Reference Figure 29A and Figure 29B , an etch-back process may be performed on the first separation film 140. Due to the etch-back process, a portion of the first separation film 140 may be removed. Here, other components except the first separation film 140 may be protected by the stopper film 110 and the preliminary device isolation film 150.

[0235] A vertical height of an upper surface of the first separation film 140 in the D3 direction may be lower than a vertical height of an upper surface of the stopper film 110 in the D3 direction.

[0236] Reference Figure 30A and Figure 30B A protection pattern MPP may be formed on the first separation film 140. The protection pattern MPP may extend in a first horizontal direction D1 along the upper surface of the first separation film 140. The upper surface of the protection pattern MPP may be coplanar with the upper surface of the preliminary device isolation film 150 and the upper surface of the stop film 110, but is not limited thereto. The protection pattern MPP may be on the upper surface of the first separation film 140 and at least partially cover the upper surface of the separation film 140.

[0237] Reference Figure 31A and Figure 31B , the stop film 110 may be removed. To remove the stop film 110, a wet etching process or a dry etching process may be used. When the stop film 110 is removed, other components may not be removed.

[0238] Reference Figure 32 , the lower spacer 50 may be formed by trimming the first separation film 140. Trimming the first separation film 140 may include performing an etching process. The etching process may include dry etching or wet etching.

[0239] When the etching process includes a dry etching process, an undercut phenomenon may be used to trim the first separation film 140. The undercut phenomenon refers to a phenomenon in which a portion of the first separation film 140 vertically overlapping the protection pattern MPP in the D3 direction is also removed when the dry etching process is used.

[0240] As a portion of the first separator film 140 is removed, the first portion 51 and the second portion 53 may be formed. For ease of description, the first portion 51 may be distinguished from the second portion 53, but the first portion 51 may be integrally formed with the second portion 53. That is, the lower separator 50 may be integrally formed or may include a unitary structure.

[0241] Reference Figure 33 , the protection pattern MPP may be removed using an etching process. In addition, the device isolation film 20 may be formed from the preliminary device isolation film 150. Due to the etching process, at least a portion of the surfaces of the active layer ACL and the sacrificial layer SAL may be exposed.

[0242] Afterwards, you can use the above reference as is 20A to 20C 、 21A to 21D 、 FIG. 22A to FIG. 22B 、 Figures 23A to 23C and FIG. 24A to FIG. 24B As a result, the semiconductor device 1 can be manufactured Figure 6 、 Figure 7A and Figure 7B The semiconductor device 3 in FIG.

[0243] While embodiments of the inventive concepts have been particularly shown and described with reference thereto, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern on the first active fin; a second channel pattern on the second active fin; a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer includes a first portion and a second portion, the first portion extending from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin in a third direction, the second portion being on the first portion, and the third direction being perpendicular to a plane defined by the first direction and the second direction; a first gate electrode on the first channel pattern and at least partially surrounding the first channel pattern; and a second gate electrode on the second channel pattern and at least partially surrounding the second channel pattern, wherein the width of the first portion in the second direction on the upper surface of the first portion is a first width, wherein the width of the second portion on the lower surface of the second portion in the second direction is the second width, wherein the first width is greater than the second width, and The first portion extends continuously in a first direction along the first active fin and the second active fin.

2. The semiconductor device according to claim 1, wherein In the third direction, a height of an upper surface of the first portion is lower than a height of an upper surface of the first channel pattern, and an upper surface of the substrate provides a base reference plane.

3. The semiconductor device according to claim 2, wherein A distance from an upper surface of the first portion to an upper surface of the first channel pattern in the third direction is 0 nm to 35 nm.

4. The semiconductor device according to claim 2, further comprising a gate dielectric film on a sidewall of the second portion in the second direction, in, a distance from an upper surface of the first portion to an upper surface of the first channel pattern in the third direction is greater than 0 nm and less than or equal to 35 nm, The gate dielectric film extends between the first channel pattern and the second portion.

5. The semiconductor device according to claim 2, wherein The first gate electrode and the second gate electrode extend between the first channel pattern and the first portion. The semiconductor device according to claim 1 , wherein: The first portion contacts a sidewall of the first channel pattern in the second direction.

7. The semiconductor device according to claim 1, further comprising a buried insulating pattern, on a sidewall of the first portion in the second direction, in, The first portion is spaced apart from the first channel pattern in the second direction.

8. The semiconductor device according to claim 7, further comprising: a device isolation film adjacent to the first active fin in the second direction on the substrate; as well as A protective film is located between the device isolation film and the first active fin, The buried insulating pattern and the protection film include the same material.

9. The semiconductor device according to claim 7, further comprising a channel dielectric film located between the first channel pattern and the buried insulating pattern, in, The trench dielectric film contacts the buried insulating pattern.

10. The semiconductor device according to claim 1, wherein The first portion and the second portion have a tapered shape in the third direction.

11. The semiconductor device according to claim 1, wherein A distance between the first portion and the first channel pattern in the second direction is 1 nm to 5 nm.

12. The semiconductor device according to claim 1, wherein The upper surface of the first portion includes a first upper surface at a center of the first portion and a second upper surface at an edge of the first portion, and The height of the second upper surface in the third direction decreases away from the first upper surface as the distance from the first upper surface in the second direction increases. The upper surface of the substrate provides a basic reference plane.

13. The semiconductor device according to claim 1, further comprising an upper separator on the first portion and overlapping the second portion in the first direction, in, In the third direction, the height of the upper surface of the upper partition is higher than the height of the upper surface of the second portion, and the upper surface of the base provides a base reference plane.

14. A semiconductor device comprising: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern on the first active fin; a second channel pattern on the second active fin; a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer includes a first portion and a second portion, the first portion extending from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin in a third direction, the second portion being on the first portion, and the third direction being perpendicular to a plane defined by the first direction and the second direction; a first gate electrode on the first channel pattern and at least partially surrounding the first channel pattern; and a second gate electrode on the second channel pattern and at least partially surrounding the second channel pattern, wherein the width of the first portion in the second direction is a first width, wherein the width of the second portion in the second direction is the second width, wherein the first width is greater than the second width, and The first part and the second part are formed integrally.

15. The semiconductor device according to claim 14, wherein The upper surface of the first portion has a curved surface, and The curved surface protrudes downward toward the upper surface of the base.

16. The semiconductor device according to claim 14, further comprising a semiconductor pattern included in the first channel pattern and stacked in a third direction; and a gate dielectric film on an upper surface of an uppermost semiconductor pattern among the semiconductor patterns, in, The gate dielectric film extends to the curved surface of the first portion.

17. The semiconductor device according to claim 14, wherein The first portion contacts a sidewall of the first channel pattern in the second direction.

18. The semiconductor device according to claim 14, wherein A distance from an upper surface of the first portion to an upper surface of the first channel pattern in the third direction is 0 nm to 15 nm.

19. The semiconductor device according to claim 18, wherein in, A distance from an upper surface of the first portion to an upper surface of the first channel pattern in the third direction is greater than 0 nm and less than or equal to 15 nm, and The first gate electrode and the second gate electrode extend between the first channel pattern and the first portion.

20. A semiconductor device comprising: a substrate including a first active fin and a second active fin, wherein the first active fin and the second active fin extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern and a second channel pattern, the first channel pattern being on the first active fin and the second channel pattern being on the second active fin, wherein the first channel pattern and the second channel pattern include semiconductor patterns stacked and spaced apart from each other in a third direction, the third direction being perpendicular to a plane defined by the first direction and the second direction; a first source / drain pattern positioned adjacent to the first channel pattern in a first direction and connected to the first channel pattern; a second source / drain pattern positioned adjacent to the second channel pattern in the first direction and connected to the second channel pattern; a lower spacer located between the first channel pattern and the second channel pattern, wherein the lower spacer includes a first portion and a second portion, the first portion extending from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin in a third direction, and the second portion being on the first portion; a first gate electrode crossing the first channel pattern in the second direction; and a second gate electrode crossing the second channel pattern in a second direction, The first channel pattern and the second channel pattern are spaced apart from each other in the second direction, and the first portion is between the first channel pattern and the second channel pattern. wherein the first source / drain pattern and the second source / drain pattern are spaced apart from each other in the second direction, and the first portion is between the first source / drain pattern and the second source / drain pattern; wherein the first gate electrode and the second gate electrode are spaced apart from each other in the second direction, and the second portion is between the first gate electrode and the second gate electrode, wherein the width of the first portion in the second direction on the upper surface of the first portion is a first width, wherein the width of the second portion on the lower surface of the second portion in the second direction is the second width, wherein the first width is greater than the second width, and The first portion extends continuously in a first direction along the first active fin and the second active fin.

Images