Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The manufacturing method of the solar cell comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface which are opposite; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon; forming a transparent conductive layer on the first surface, wherein the transparent conductive layer is located on one side, deviating from the semiconductor substrate, of the first semiconductor layer; and irradiating at least a part of the first semiconductor layer with laser to increase the crystallization degree of at least a local region of the part, irradiated by the laser, of the first semiconductor layer. In the actual manufacturing process, the first semiconductor layer containing the amorphous silicon can be rapidly grown firstly, and then the crystallization degree of at least a local area of the first semiconductor layer is increased by utilizing laser irradiation, so that the contact resistance of the doping layer is reduced, and the contact resistance and transmission loss are reduced while the production efficiency is ensured.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. Once the circuit is connected, current is generated. For a grown film of the same thickness, amorphous silicon layers grow faster than crystals (microcrystals or nanocrystals). However, amorphous silicon lacks the high electrical conductivity of crystalline silicon, resulting in higher contact resistance and transmission losses, which are detrimental to the electrical contact of the solar cell. Summary of the Invention

[0003] The purpose of this application is to provide a solar cell and a manufacturing method thereof, and a photovoltaic module to ensure production efficiency while reducing contact resistance and transmission loss.

[0004] In order to achieve the above objectives, this application provides the following technical solutions:

[0005] A method for manufacturing a solar cell, comprising:

[0006] Providing a semiconductor substrate having a first surface and a second surface opposite to each other;

[0007] forming a first semiconductor layer on the first surface, wherein the first semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon;

[0008] forming a transparent conductive layer on the first surface, wherein the transparent conductive layer is located on a side of the first semiconductor layer facing away from the semiconductor substrate;

[0009] At least a portion of the first semiconductor layer is irradiated with laser light, thereby increasing the degree of crystallization of at least a local region of the first semiconductor layer in the portion irradiated with laser light.

[0010] It is understandable that, under the same conditions as other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller. The first semiconductor layer includes amorphous silicon, whose atomic arrangement is disordered, and the grains in the first semiconductor layer are small and have more grain interfaces, resulting in a larger resistance of the first semiconductor layer. The first semiconductor layer includes nanocrystalline silicon, whose atomic arrangement is also mostly disordered, and the grains in the first semiconductor layer are small and have more grain interfaces, resulting in a larger resistance of the first semiconductor layer relative to microcrystalline silicon and nanocrystalline silicon with larger size or a larger proportion of nanocrystalline grains. In the manufacturing method of the solar cell provided in the present application, after forming a transparent conductive layer on the first surface, at least a portion of the first semiconductor layer is irradiated with a laser, so that the degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser is increased, the grains in the area with increased degree of crystallization are enlarged, the number of grains increases, and the number of grain interfaces is reduced, thereby reducing the contact resistance of the area with increased degree of crystallization of the first semiconductor layer, thereby reducing the contact resistance between the area with increased degree of crystallization of the first semiconductor layer and the transparent conductive layer, thereby reducing the transmission loss of carriers collected in the first semiconductor layer. In this way, in the actual manufacturing process, a first semiconductor layer containing amorphous silicon can be quickly grown first, and then laser irradiation can be used to increase the degree of crystallization of at least a local area of the first semiconductor layer, thereby reducing the contact resistance of a doped layer to ensure production efficiency while reducing contact resistance and transmission loss.

[0011] In one embodiment, the area of the first semiconductor layer with increased crystallization degree includes bubbles; and / or the area of the transparent conductive layer corresponding to the area of the first semiconductor layer with increased crystallization degree includes cracks and / or holes; and / or, there is an air gap between the first semiconductor layer and the transparent conductive layer at the position corresponding to the area of the first semiconductor layer with increased crystallization degree.

[0012] In one implementation, the local area of the first semiconductor layer where the degree of crystallization increases is a crystallization zone. Along the thickness direction of the semiconductor substrate, the crystallization zone extends from the side of the first semiconductor layer away from the semiconductor substrate toward the direction close to the semiconductor substrate, and the thickness of the crystallization zone is less than or equal to the thickness of the first semiconductor layer.

[0013] In one implementation, the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer; forming the first semiconductor layer on the first surface includes: forming the first intrinsic semiconductor layer on the first surface, and forming the first doped semiconductor layer on a side of the first intrinsic semiconductor layer away from the semiconductor substrate.

[0014] In one implementation, irradiating at least a portion of the first semiconductor layer with a laser to increase the degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser includes:

[0015] Laser is used to irradiate at least a portion of the first semiconductor layer, so that the degree of crystallization of at least a local area of the first doped semiconductor layer and the first intrinsic semiconductor layer in the laser-irradiated portion is increased to form a crystallized region. Along the thickness direction of the semiconductor substrate, the crystallized region extends from the side of the first doped semiconductor layer away from the semiconductor substrate to the direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the sum of the thickness of the first doped semiconductor layer and the thickness of the first intrinsic semiconductor layer, or the thickness of the crystallized region is less than or equal to the thickness of the first doped semiconductor layer.

[0016] In one implementation, at least a portion of the first surface of the semiconductor substrate is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface;

[0017] The first semiconductor layer and the transparent conductive layer are formed at least on the velvet surface of the first surface; the area of the first semiconductor layer with increased crystallization degree covers the top area of the pyramid-like structure, and the degree of crystallization of the first semiconductor layer covering the top part of the pyramid-like structure is greater than the degree of crystallization of the first semiconductor layer covering the base part of the pyramid-like structure.

[0018] In one implementation, the orthographic projection of the region of the first semiconductor layer with increased degree of crystallization on the semiconductor substrate is circular, elliptical, square or irregular; and / or, the equivalent radius of the orthographic projection of the region of the first semiconductor layer with increased degree of crystallization on the semiconductor substrate is 50nm to 600nm.

[0019] In one implementation, before forming the transparent conductive layer on the first surface, the method for manufacturing a solar cell further includes:

[0020] forming a second semiconductor layer on the second surface, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; or,

[0021] A second semiconductor layer is formed in a local area of the first surface. The conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer. The second semiconductor layer and the first semiconductor layer are alternately distributed.

[0022] A solar cell comprising:

[0023] a semiconductor substrate having a first surface and a second surface opposite to each other;

[0024] a first semiconductor layer disposed on the first surface, the first semiconductor layer comprising amorphous silicon and / or nanocrystalline silicon, at least a partial region of the first semiconductor layer being configured as a crystallized region, the crystallized region being more crystallized than the remaining region, the crystallized region comprising nanocrystalline silicon and / or microcrystalline silicon; and the crystallized region comprising bubbles;

[0025] The transparent conductive layer is at least disposed on the first surface and located on a side of the first semiconductor layer away from the semiconductor substrate.

[0026] By adopting the above technical solution, the degree of crystallization of at least a local area of the first semiconductor layer is increased to form a crystallized region, thereby reducing the contact resistance of the crystallized region of a doped layer, reducing the contact resistance and transmission loss, and helping to improve the photoelectric conversion efficiency of the solar cell; at the same time, in the actual manufacturing process, the first semiconductor layer containing amorphous silicon can be quickly grown first, which is conducive to improving production efficiency.

[0027] In one implementation, the area of the transparent conductive layer corresponding to the crystallized region includes cracks and / or holes; the width of the cracks and / or holes is 2nm to 100nm; and / or the roughness of the area of the transparent conductive layer corresponding to the crystallized region is greater than the roughness of the remaining areas of the transparent conductive layer; and / or the number of grains in the crystallized region gradually decreases along the thickness direction of the semiconductor substrate; and / or the diameter of a single bubble is 2nm to 100nm; and / or a plurality of bubbles gather to form a bubble group, and the diameter of the bubble group is 200nm to 1000nm; and / or the roughness of the crystallized region is greater than the roughness of the remaining areas of the first semiconductor layer.

[0028] In one implementation, at least a portion of the first surface of the semiconductor substrate is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface;

[0029] The first semiconductor layer at least covers the velvet surface of the first surface; the crystallized region of the first semiconductor layer covers the top area of the pyramid-like structure, and the degree of crystallization of the first semiconductor layer covering the top of the pyramid-like structure is greater than the degree of crystallization of the first semiconductor layer covering the base of the pyramid-like structure.

[0030] In one implementation, the size of bubbles closer to the top of the pyramid-like layer is larger than the size of bubbles farther away from the top of the pyramid-like layer; and / or the number of bubbles closer to the top of the pyramid-like layer is larger than the number of bubbles farther away from the top of the pyramid-like layer; and / or the thickness of the portion of the first semiconductor layer where the crystallized region is formed is greater than the thickness of the remaining area of the first semiconductor layer; and / or the portion of the transparent conductive layer covering the top area of the pyramid-like layer includes cracks and / or holes.

[0031] In one implementation, along the thickness direction of the semiconductor substrate, the crystallized region extends from a side of the first semiconductor layer away from the semiconductor substrate toward a direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the thickness of the first semiconductor layer;

[0032] Alternatively, the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer, and the first intrinsic semiconductor layer is located on a side of the first doped semiconductor layer close to the semiconductor substrate; along the thickness direction of the semiconductor substrate, the crystallized region extends from the side of the first doped semiconductor layer away from the semiconductor substrate toward the direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the sum of the thickness of the first doped semiconductor layer and the thickness of the first intrinsic semiconductor layer, or the thickness of the crystallized region is less than or equal to the thickness of the first doped semiconductor layer.

[0033] In one implementation, the thickness of the crystallized region is greater than or equal to 3 nm along the thickness direction of the semiconductor substrate; and / or the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer, the first intrinsic semiconductor layer is located on a side of the first doped semiconductor layer close to the semiconductor substrate, the thickness of the first doped semiconductor layer is 5 nm to 60 nm, and the thickness of the first intrinsic semiconductor layer is 3 nm to 25 nm.

[0034] In one implementation, the solar cell further includes a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer;

[0035] The second semiconductor layer is provided on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed;

[0036] Alternatively, a second semiconductor layer is disposed on the second surface, the second semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, at least a local area of the second semiconductor layer forms a crystallized region, the degree of crystallization of the crystallized region is greater than that of the remaining regions, and the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon.

[0037] In one implementation, the solar cell further includes a first electrode formed on a side of the transparent conductive layer facing away from the semiconductor substrate, and an orthographic projection of the first electrode on the semiconductor substrate at least partially overlaps with an orthographic projection of the crystallized region on the semiconductor substrate.

[0038] A photovoltaic assembly comprises a plurality of solar cells formed by any one of the above manufacturing methods and at least one interconnecting element, wherein the interconnecting element connects two adjacent solar cells in series or in parallel.

[0039] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, and are not described in detail here.

[0040] In one implementation, a projection of the interconnection on the semiconductor substrate at least partially overlaps with a projection of the crystallized region on the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 1 ;

[0043] Figure 2 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 2 ;

[0044] Figure 3 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 3 ;

[0045] Figure 4 for Figure 3 A top view of a solar cell formed in FIG.

[0046] Figure 5 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 1 ;

[0047] Figure 6 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 2 ;

[0048] Figure 7 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 3 ;

[0049] Figure 8 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 1 ;

[0050] Figure 9 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 2 ;

[0051] Figure 10 is a TEM image of the first semiconductor layer after being irradiated by laser;

[0052] Figure 11 for Figure 10 A partial enlarged view of

[0053] Figure 12 for Figure 11 A magnified view of the top of the middle pyramid;

[0054] Figure 13 This is the TEM image of the transparent conductive layer after being irradiated by laser;

[0055] Figure 14 for Figure 13 A partial enlarged view of

[0056] Figure 15 for Figure 14 A magnified view of the top of the middle pyramid;

[0057] Figure 16 This is a local magnified TEM image of the pyramid-like top;

[0058] Figure 17 for Figure 16 A partial enlarged view of the left side of the middle spire;

[0059] Figure 18 for Figure 16 A partial enlarged view of the right side of the middle spire;

[0060] Figure 19 A partially enlarged TEM image of a pyramid-like top provided in another embodiment;

[0061] Figure 20 for Figure 19 Middle partial enlarged view;

[0062] Figure 21 for Figure 19 A partial enlarged view of the left side of the middle spire;

[0063] Figure 22 for Figure 19 A partial enlarged view of the right side of the middle spire;

[0064] Figure 23 A partially enlarged TEM image of a pyramid-like top provided in another embodiment;

[0065] Figure 24 for Figure 23 Middle partial enlarged view;

[0066] Figure 25 for Figure 23 A partial enlarged view of the left side of the middle spire;

[0067] Figure 26 for Figure 23 A partial enlarged view of the right side of the middle spire;

[0068] Figure 27 A schematic diagram of a photovoltaic module provided in an embodiment of the present application.

[0069] Reference numerals:

[0070] 10-semiconductor substrate, 11-first intrinsic semiconductor layer, 12-first doped semiconductor layer, 12a-bubble, 13-transparent conductive layer, 13a-hole, 14-tunneling oxide layer, 15-second semiconductor layer, 16-laser irradiation area, 17-first electrode, 18-second electrode, 19-opening, 20-crystallized region, 21-first interconnection element, 22-second interconnection element. DETAILED DESCRIPTION

[0071] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0072] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0074] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0075] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0076] During the manufacturing process of solar cells, the applicant discovered that, for amorphous silicon films of the same thickness, they grow faster than crystalline (microcrystal or nanocrystal) films. However, amorphous silicon lacks the high electrical conductivity of crystalline silicon, resulting in higher contact resistance and transmission losses, which are detrimental to the electrical contact of solar cells.

[0077] In view of the above situation, the present application provides a method for manufacturing a solar cell, which can reduce contact resistance and transmission loss while ensuring production efficiency, and improve the photoelectric conversion efficiency of the solar cell.

[0078] The method for manufacturing a solar cell provided in an embodiment of the present application includes:

[0079] S100: providing a semiconductor substrate 10, wherein the semiconductor substrate 10 has a first surface and a second surface opposite to each other;

[0080] That is, the two surfaces facing each other along the thickness of the semiconductor substrate 10 are respectively the first surface and the second surface. Prior to this step, in some embodiments, the semiconductor substrate 10 may be placed in a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 10 using a polishing liquid. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 10 after polishing and cleaning can be adjusted by controlling parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0081] S200: forming a first semiconductor layer on the first surface, where the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon;

[0082] The first semiconductor layer includes a first doped semiconductor layer 12. The first doped semiconductor layer 12 can be formed entirely or locally on the first surface. When the first doped semiconductor layer 12 is locally formed on the first surface, the first doped semiconductor layer 12 can be distributed in a plurality of stripes or in a plurality of quasi-F shapes. The first doped semiconductor layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 using a deposition technique, or can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods.

[0083] The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The amorphous silicon and / or nanocrystalline silicon material contains more hydrogen, so that the first semiconductor layer contains more hydrogen, which is beneficial to hydrogenating the dangling bonds on the surface of the semiconductor substrate 10 and reducing surface defects, thereby having a higher passivation effect on the semiconductor substrate 10.

[0084] S300: forming a transparent conductive layer 13 on the first surface, wherein the transparent conductive layer 13 is located on a side of the first semiconductor layer facing away from the semiconductor substrate 10;

[0085] Specifically, the transparent conductive layer 13 can be formed by deposition or other methods. The material of the transparent conductive layer 13 can include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layer 13 can be a single-layer thin film or a laminated thin film.

[0086] S400: irradiating at least a portion of the first semiconductor layer with laser light to increase the degree of crystallization of at least a local region of the first semiconductor layer irradiated by the laser light.

[0087] That is, after forming the transparent conductive layer 13 on the first surface, the entire or a portion of the first semiconductor layer is irradiated with laser light. Figure 2 As shown, the portion of the first semiconductor layer irradiated by the laser can be referred to as a laser irradiation area 16. The degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser increases, that is, the degree of crystallization of at least a local area of the laser irradiation area 16 increases. Specifically, the degree of crystallization of the entire laser irradiation area 16 can be greater than the degree of crystallization of the portion not irradiated by the laser, or the degree of crystallization of the local area of the laser irradiation area 16 can be greater than the degree of crystallization of the portion not irradiated by the laser. In the embodiments of the present application, the increased degree of crystallization can refer to an increase in the crystallization rate, an increase in the grain size, and / or an increase in the number of grains.

[0088] It can be understood that, under the same conditions as other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller. The first semiconductor layer includes amorphous silicon, whose atomic arrangement is disordered, and the grains in the first semiconductor layer are small and have more grain interfaces, resulting in a larger resistance of the first semiconductor layer. The first semiconductor layer includes nanocrystalline silicon, whose atomic arrangement is also mostly disordered, and the grains in the first semiconductor layer are small and have more grain interfaces, resulting in the resistance of the first semiconductor layer being greater than that of microcrystalline silicon and nanocrystalline silicon with larger size or a larger proportion of nanocrystalline grains. In the manufacturing method of the solar cell provided in the present application, after forming the transparent conductive layer 13 on the first surface, at least a portion of the first semiconductor layer is irradiated with a laser, so that the degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser is increased, the grains in the area with increased degree of crystallization are enlarged, the number of grains is increased, and the grain interfaces are reduced, thereby reducing the contact resistance of the area with increased degree of crystallization of the first semiconductor layer, thereby reducing the contact resistance between the area with increased degree of crystallization of the first semiconductor layer and the transparent conductive layer 13, thereby reducing the transmission loss of the carriers collected in the first semiconductor layer. In this way, in the actual manufacturing process, a first semiconductor layer containing amorphous silicon can be quickly grown first, and then laser irradiation can be used to increase the degree of crystallization of at least a local area of the first semiconductor layer, thereby reducing the contact resistance of a doped layer to ensure production efficiency while reducing contact resistance and transmission loss.

[0089] It should be noted that, in the present application, a greater degree of crystallization means that the grain size of the region with a greater degree of crystallization is relatively larger than that of other regions, and / or the number of grains is relatively large, and / or the crystallization rate is relatively large. For example, when the first semiconductor layer is amorphous silicon, nano-crystal grains will be generated in the crystallized region (i.e., the grain size becomes larger), and at the same time, the amorphous silicon material that originally had basically no grains will produce nano-crystal grains in the crystallized region (i.e., the number of grains increases), which will also increase the final crystallization rate. Of course, these three may appear alone or in combination. For the first semiconductor layer being nanocrystalline silicon (meaning that the first semiconductor layer is mainly nano-crystal grains, which may also include some amorphous silicon and microcrystalline silicon), nano-crystal grain growth will also occur in the crystallized region (i.e., the grain size becomes larger, which may be larger nano-crystal grains or even microcrystalline grains), and nano-crystal grains may be regenerated internally (i.e., the number of grains increases), which will also increase the final crystallization rate. Of course, these three may appear alone or in combination.

[0090] The area of the first semiconductor layer irradiated by the laser is the laser irradiation area 16, and the degree of crystallization of at least a local area of the laser irradiation area 16 increases to form a crystallized area 20, that is, in the laser irradiation area 16 of the first semiconductor layer, the part with increased crystallization is the crystallized area 20, and the area with unchanged crystallization is the unchanged area. Specifically, in the laser irradiation area 16 of the first semiconductor layer, the crystallized area 20 and the unchanged area can be distributed in a direction parallel to the first surface of the semiconductor substrate 10 (that is, when viewed from above, the crystallized area is distributed in the laser irradiation area 16 in the form of multiple discrete sub-portions); or, the crystallized area 20 and the unchanged area can also be distributed in the thickness direction of the semiconductor substrate 10. When the crystallized area 20 and the unchanged area are distributed in the thickness direction of the semiconductor substrate 10, the crystallized area 20 is farther away from the semiconductor substrate 10 than the unchanged area. When the crystallized area 20 and the unchanged area are distributed in a direction parallel to the first surface of the semiconductor substrate 10, from Figure 13-15 It can be seen that the degree of crystallization in the region of the first semiconductor layer close to the top of the pyramid (light-colored circular region) is greater than that in the remaining regions, and the edge contour of the above region is the boundary of the crystallized region 20 .

[0091] In some embodiments, the region of the first semiconductor layer with increased crystallization includes bubbles 12a, that is, the crystallized region 20 includes bubbles 12a. Thus, light irradiated by the bubbles 12a can be scattered back into the semiconductor substrate 10 via the inner walls of the bubbles 12a, thereby improving light absorption and utilization efficiency. The bubbles 12a can be in any shape, such as circular, spherical, ellipsoidal, or linear.

[0092] The bubbles 12a can be in a closed form. The interior of the bubbles 12a is generally hollow, and a small amount of semiconductor material may also be present. The bubbles 12a can also be in an open form, with the inner diameter of the bubbles 12a being larger than the diameter of the opening of the bubbles 12a. For example, a portion of the bubbles 12a formed inside the first semiconductor layer are in a closed form, while another portion of the bubbles 12a formed on the surface of the first semiconductor layer facing away from the semiconductor substrate 10 are in an open form. The maximum size of the open bubbles 12a is larger than the size of their opening on the surface of the first semiconductor layer facing away from the semiconductor substrate 10, that is, the opening size of the open bubbles 12a is relatively small.

[0093] The transparent conductive layer 13 includes cracks and / or holes 13a in the region corresponding to the area where the degree of crystallization of the first semiconductor layer increases. That is, the region of the transparent conductive layer 13 corresponding to the crystallized region 20 includes cracks and / or holes 13a. Specifically, the region of the transparent conductive layer 13 corresponding to the crystallized region 20 may have regular or irregular cracks, and the holes 13a may be through holes extending through the thickness of the transparent conductive layer 13 or blind holes. This configuration allows the slurry forming the first electrode 17 to penetrate into the cracks and / or holes 13a, thereby increasing the contact area between the transparent conductive layer 13 and the first electrode 17, further reducing the transmission resistance between the transparent conductive layer 13 and the first electrode 17, and improving the photoelectric conversion efficiency.

[0094] In some embodiments, an air gap exists between the first semiconductor layer and the transparent conductive layer 13 at locations corresponding to regions where the first semiconductor layer has increased crystallization. Specifically, an air gap exists between the transparent conductive layer 13 and the crystallized region 20. Specifically, an air gap may exist between a portion of the crystallized region 20 and the transparent conductive layer 13, while the remainder of the crystallized region 20 and the transparent conductive layer 13 are in contact. This arrangement facilitates the scattering of light that strikes the air gap back into the semiconductor substrate 10, thereby improving light absorption and utilization efficiency.

[0095] In some embodiments, the localized region of the first semiconductor layer where the degree of crystallization is increased is a crystallized region 20. Along the thickness direction of the semiconductor substrate 10, the crystallized region 20 extends from the side of the first semiconductor layer facing away from the semiconductor substrate 10 toward the semiconductor substrate 10, and the thickness of the crystallized region 20 is less than or equal to the thickness of the first semiconductor layer. Specifically, when the thickness of the crystallized region 20 is less than the thickness of the first semiconductor layer, the crystallized region 20 is formed only in the region of the first semiconductor layer near the surface of the transparent conductive layer 13. With this technical solution, the degree of crystallization is increased at least in the region of the first semiconductor layer near the surface of the transparent conductive layer 13, which reduces the transmission resistance and transmission loss between the first semiconductor layer, the transparent conductive layer 13, and the first electrode 17 while reducing the processing difficulty of the crystallized region 20.

[0096] In other embodiments, the first semiconductor layer includes a first doped semiconductor layer 12 and a first intrinsic semiconductor layer 11; step S200 forms the first semiconductor layer on the first surface, including: forming a first intrinsic semiconductor layer 11 on the first surface, the first intrinsic semiconductor layer 11 including intrinsic amorphous silicon and / or nanocrystalline silicon; forming a first doped semiconductor layer 12 on the side of the first intrinsic semiconductor layer 11 away from the semiconductor substrate 10.

[0097] That is, before forming the first doped semiconductor layer 12, a deposition process or the like can be used to first form the first intrinsic semiconductor layer 11 on the first surface, and then form the first doped semiconductor layer 12 on the side of the first intrinsic semiconductor layer 11 facing away from the semiconductor substrate 10, so that the first intrinsic semiconductor layer 11 is located between the first doped semiconductor layer 12 and the semiconductor substrate 10. In this case, the first intrinsic semiconductor layer 11 and the first doped semiconductor layer 12 can form a selective contact structure, which has an excellent interface passivation effect and can achieve selective collection of carriers, thereby reducing the carrier recombination rate in the region of the semiconductor substrate 10 where the first doped semiconductor layer 12 is formed, and further improving the photoelectric conversion efficiency of the solar cell.

[0098] In some embodiments, S400 uses laser to irradiate at least a portion of the first semiconductor layer to increase the degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser; including: using laser to irradiate at least a portion of the first semiconductor layer to increase the degree of crystallization of at least a local area of the first doped semiconductor layer 12 and the first intrinsic semiconductor layer 11 to form a crystallized region 20, along the thickness direction of the semiconductor substrate 10, the crystallized region 20 extends from the side of the first semiconductor layer away from the semiconductor substrate 10 to the direction close to the semiconductor substrate 10, and the thickness of the crystallized region 20 is less than or equal to the sum of the thickness of the first doped semiconductor layer 12 and the thickness of the first intrinsic semiconductor layer 11.

[0099] In some embodiments, the crystallized region 20 is a plurality of local regions that are only partially disposed within the region of the first semiconductor layer, and along the thickness direction of the semiconductor substrate 10, the crystallized region 20 is disposed corresponding to the first electrode 17. In other embodiments, the crystallized region 20 may occupy more than 80% of the area of the first semiconductor layer, or the crystallized region 20 may be the entire region of the first semiconductor layer.

[0100] Using the above technical solution, the laser irradiation process increases the degree of crystallization of at least a portion of the first doped semiconductor layer 12 while also increasing the degree of crystallization of at least a portion of the first intrinsic semiconductor layer 11. In this technical solution, the region where the degree of crystallization of the first doped semiconductor layer 12 and the first intrinsic semiconductor layer 11 is increased is the crystallized region 20. The thickness of the crystallized region 20 is greater than the thickness of the first doped semiconductor layer 12 and less than or equal to the sum of the thicknesses of the first doped semiconductor layer 12 and the first intrinsic semiconductor layer 11. This configuration further increases the thickness of the crystallized region 20, thereby further reducing the transmission loss of carriers from the semiconductor substrate 10 to the first electrode 17 and further improving the photoelectric conversion efficiency. Alternatively, the thickness of the crystallized region 20 is less than or equal to the thickness of the first doped semiconductor layer 12. Using this technical solution, the degree of crystallization is increased at least in the region near the surface of the first doped semiconductor layer 12 near the transparent conductive layer 13, reducing the transmission resistance and transmission loss between the first doped semiconductor layer 12, the transparent conductive layer 13, and the first electrode 17 while reducing the processing difficulty of the crystallized region 20.

[0101] The crystallized region 20 includes bubbles 12a. The bubbles 12a in the crystallized region 20 near the transparent conductive layer 13 are larger than those near the semiconductor substrate 10. In other words, along the thickness direction of the semiconductor substrate 10, the bubbles 12a increase in size as they are closer to the transparent conductive layer 13. Along the thickness direction of the semiconductor substrate 10, the number of bubbles 12a in the crystallized region 20 increases as they are closer to the transparent conductive layer 13.

[0102] like Figure 13-15 As shown, at least a portion of the first surface of the semiconductor substrate 10 is a velvet surface, on which a plurality of pyramid-like structures are formed. The first semiconductor layer and the transparent conductive layer 13 are formed at least on the velvet surface of the first surface. When the first semiconductor layer and the transparent conductive layer 13 are disposed on the velvet surface, the side of the first semiconductor layer and the transparent conductive layer 13 facing away from the semiconductor substrate 10 has an undulating morphology substantially the same as that of the velvet surface. In this case, the first semiconductor layer and the transparent conductive layer 13 have a larger specific surface area, which can increase the contact area between the first semiconductor layer and the transparent conductive layer 13, further reducing the transmission loss of carriers.

[0103] In terms of the arrangement of the pyramid-like structures, the embodiments of the present invention do not impose any specific restrictions on the morphology, size, and distribution of the pyramid-like structures formed on the velvet surface, as long as they can be applied to the solar cell provided by the embodiments of the present invention.

[0104] For example, the aforementioned quasi-pyramid can be a pyramid with a sharp top angle; or, the quasi-pyramid can be a quasi-pyramid with rounded chamfers; or, the quasi-pyramid can be a quasi-pyramid with a flattened top angle. In this case, the quasi-pyramid can have at least the three aforementioned examples, which helps improve the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. In addition, there is no need to strictly control the manufacturing precision to obtain a quasi-pyramid with a single morphology, which reduces the process difficulty and helps improve the yield of the solar cell.

[0105] In some embodiments, the region of the first semiconductor layer with increased crystallization degree covers the top region of the pyramid-like structure, and the crystallization degree of the portion of the first semiconductor layer covering the top region of the pyramid-like structure is greater than the crystallization degree of the portion of the first semiconductor layer covering the base region of the pyramid-like structure. In other words, the crystallized region 20 of the first semiconductor layer covers the top region of the pyramid-like structure, such as Figure 14 and Figure 15 In the figure, the light-colored area at the top of the pyramid is the crystallized area 20; Figure 16-Figure 18 As shown, the top of the pyramid and the left side of the pyramid tip ( Figure 17 ) and the right side of the pyramid tip ( Figure 18 ) increases in degree of crystallization; Figures 19-22 , the top of the pyramid ( Figure 20 ), the left side of the pyramid-like tip ( Figure 21 ) and the right side of the pyramid tip ( Figure 22 ) increased, especially Figure 20-22 The degree of crystallization increases significantly in the middle dashed area. In some embodiments, the vertical height (i.e., along the thickness direction of the semiconductor substrate) of the portion of the first semiconductor layer covering the top portion of the pyramid-like structure where the degree of crystallization increases is within 50% of the total height of the pyramid-like structure, for example, 1%, 5%, 10%, 20%, 30%, 40%, or 50%.

[0106] By employing the above-described technical solution, the laser energy used in laser irradiation can be appropriately reduced, so that the first semiconductor layer covering the base of the pyramid-like structure still has a relatively high hydrogen content, thereby having a high passivation effect on the velvet surface, reducing the number of defects in the velvet surface, and improving the operating efficiency of the solar cell. In short, the portion of the first semiconductor layer covering the top of the pyramid-like structure forms a crystallized region 20 with a high degree of crystallization, which can reduce the contact resistance between the transparent conductive layer 13 and the first semiconductor layer. At the same time, the portion of the first semiconductor layer covering the base of the pyramid-like structure still maintains its original degree of crystallization and still has a relatively high hydrogen content, which can ensure the passivation effect of the first semiconductor layer, that is, it takes into account the balance between contact resistance and passivation effect.

[0107] It can be understood that when at least a portion of the first surface of the semiconductor substrate 10 is a velvet surface, a plurality of pyramid-like layers are formed on the velvet surface. The first semiconductor layer is conformally arranged on the velvet surface, and the degree of crystallization of the portion of the first semiconductor layer covering at least a portion of the top of the pyramid-like layer is greater than the degree of crystallization of the other portion of the first semiconductor layer covering the base of the pyramid-like layer. In the process of observing the degree of crystallization of the first semiconductor layer, if the observed area is too small, the degree of crystallization of the first semiconductor layer cannot be accurately obtained by observing only the base area of the pyramid-like layer. Therefore, the observed area should contain at least one pyramid-like layer. Preferably, the observed area should be greater than or equal to 5*5μm. 2 , so as to prevent the inability to accurately obtain the crystallization degree of the first semiconductor layer by observing only the pyramid-like base region.

[0108] In some embodiments, as Figure 13-15 As shown, the crystallized region 20 covers the top area of the pyramid-like structure. In this way, the crystallized region 20 can reduce the contact resistance between the transparent conductive layer 13 and the first semiconductor layer. At the same time, the portion of the first semiconductor layer covering the base of the pyramid-like structure still maintains the original degree of crystallization and still has a relatively high hydrogen content, which can ensure the passivation effect of the first semiconductor layer, that is, a balance between contact resistance and passivation effect is taken into account.

[0109] The orthographic projection of the region of the first semiconductor layer with increased crystallization degree on the semiconductor substrate 10 is circular, elliptical, square or irregular, that is, the orthographic projection of the crystallized region 20 on the semiconductor substrate 10 can be any shape and is not limited here.

[0110] The equivalent radius of the orthographic projection of the region with increased crystallization of the first semiconductor layer on the semiconductor substrate 10 is 50 nm to 600 nm. By keeping the area of the region with increased crystallization of the first semiconductor layer within a reasonable range, the laser energy used can be reduced, thereby reducing damage to the semiconductor substrate 10 caused by the laser; at the same time, the region with increased crystallization of the first semiconductor layer can be ensured to have a lower transmission resistance. For example, the equivalent radius of the orthographic projection of the region with increased crystallization of the first semiconductor layer on the semiconductor substrate 10 is 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm.

[0111] In some embodiments, after step S400 of irradiating at least a portion of the first semiconductor layer with a laser to increase the degree of crystallization of at least a local region of the laser-irradiated portion of the first semiconductor layer, the solar cell manufacturing method further includes forming a first electrode 17 on a side of the transparent conductive layer 13 facing away from the semiconductor substrate 10 in step S500, wherein the orthographic projection of the first electrode 17 on the semiconductor substrate 10 at least partially overlaps with the orthographic projection of the region of the first semiconductor layer where the degree of crystallization has increased. That is, the orthographic projection of the first electrode 17 on the semiconductor substrate 10 at least partially overlaps with the orthographic projection of the crystallized region 20 on the semiconductor substrate 10. This arrangement can further reduce the transmission resistance of carriers from the first semiconductor layer to the first electrode 17. Optionally, the orthographic projection of the first electrode 17 on the semiconductor substrate 10 is located within the orthographic projection of the crystallized region 20 on the semiconductor substrate 10.

[0112] The material of the first electrode 17 may include silver, copper, aluminum and alloys thereof.

[0113] In some embodiments, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined based on requirements for the extension range of the crystallized region 20 of the first semiconductor layer covering the top of the pyramid-like shape and having a greater degree of crystallization in actual application scenarios, and are not specifically limited here. It is understood that when the processing wavelength of the laser irradiation process is smaller, the pulse width is larger, the laser energy density is higher, and the processing time is longer, when the laser irradiation process is used to treat the first semiconductor layer, the temperature rise of the first semiconductor layer is greater, and it is more conducive to forming a crystallized region 20 with a greater crystallization depth and a longer extension length.

[0114] For example, the processing wavelength of the laser irradiation process may be greater than or equal to 325 nm and less than or equal to 532 nm. For example, the processing wavelength may be 325 nm, 330 nm, 350 nm, 80 nm, 400 nm, 430 nm, 450 nm, 480 nm, 500 nm, or 532 nm.

[0115] For example, the pulse width of the laser irradiation process may be in the picosecond or nanosecond range, for example, 10 ps, 50 ps, 100 ps, 300 ps, 500 ps, 800 ps, 1 ns, or 5 ns.

[0116] For example, the laser energy density of the laser irradiation process may be greater than or equal to 100 mJ / cm 2 For example, the laser energy density can be 100mJ / cm 2 、140mJ / cm 2 、180mJ / cm 2 , 200mJ / cm 2 , 240mJ / cm2 、280mJ / cm 2 、300mJ / cm 2 , 400mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 4000mJ / cm 2 , 5000mJ / cm 2 or 6000mJ / cm 2 wait.

[0117] In addition, if the solar cell being manufactured is a double-sided contact cell, if the solar cell also includes a second semiconductor layer 15, the second semiconductor layer 15 can be formed on the second surface of the semiconductor substrate 10 before or after forming the first semiconductor layer and before forming the transparent conductive layer 13 on the first surface. The second semiconductor layer 15 has an opposite conductivity type to the first semiconductor layer, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. Specifically, the second semiconductor layer 15 can be additionally formed on the semiconductor substrate 10 through a deposition technique, or can be formed within the semiconductor substrate 10 through diffusion, ion implantation, or other methods.

[0118] like Figure 1-Figure 3 As shown, in the case where the second semiconductor layer 15 of the double-sided contact battery also includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer and the transparent conductive layer 13 are formed on the first surface of the semiconductor substrate 10, and the second semiconductor layer 15 and the transparent conductive layer 13 are formed on the second surface. Figure 2As shown, laser light is used to irradiate at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer 15, thereby increasing the degree of crystallization of at least a local region of the first semiconductor layer irradiated by the laser, forming a crystallized region 20. This also increases the degree of crystallization of at least a local region of the second semiconductor layer 15 irradiated by the laser, forming a crystallized region 20. In this technical solution, the second semiconductor layer 15 may include a second doped semiconductor layer and a second intrinsic semiconductor layer. Forming the second semiconductor layer 15 on the second surface includes: forming a second intrinsic semiconductor layer on the second surface, the second intrinsic semiconductor layer including intrinsic amorphous silicon and / or nanocrystalline silicon; and forming a second doped semiconductor layer on a side of the second intrinsic semiconductor layer facing away from the semiconductor substrate 10. The thickness of the crystallized region 20 formed in the local region of the second semiconductor layer 15 may be less than or equal to the sum of the thickness of the second doped semiconductor layer and the thickness of the second intrinsic semiconductor layer. Alternatively, the thickness of the crystallized region 20 formed in the local region of the second semiconductor layer 15 may be less than or equal to the thickness of the second doped semiconductor layer. It is understood that the laser can be used to first irradiate the first semiconductor layer and then the second semiconductor layer 15, or first irradiate the second semiconductor layer 15 and then the first semiconductor layer, or simultaneously irradiate the first semiconductor layer 15. Of course, when the second semiconductor layer 15 may also include polycrystalline silicon, in this case, there is no need to perform a laser crystallization process, and a tunnel oxide layer 14 may also be provided between the second semiconductor layer 15 and the semiconductor substrate 10.

[0119] Next, if Figure 3 As shown, a first electrode 17 is formed on the first surface. The first electrode 17 is formed on the side of the transparent conductive layer 13 away from the semiconductor substrate 10. Figure 4 As shown, the orthographic projection of the first electrode 17 on the semiconductor substrate 10 is located inside the orthographic projection of the crystallized region 20 of the first semiconductor layer on the semiconductor substrate 10. The second electrode 18 is formed on the second surface and is formed on the side of the transparent conductive layer 13 away from the semiconductor substrate 10.

[0120] In the case where the solar cell being manufactured is a back contact cell, as Figure 5-Figure 7 As shown, the method for manufacturing a solar cell further includes: forming a second semiconductor layer 15 in a localized area of the first surface, wherein the second semiconductor layer 15 and the first semiconductor layer have opposite conductivity types, and the second semiconductor layer 15 and the first semiconductor layer are alternately distributed. It should be noted that when the second semiconductor layer 15 comprises polycrystalline silicon, the first semiconductor layer is formed after the second semiconductor layer 15 is formed on the first surface. When the second semiconductor layer 15 comprises amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer can be formed after the second semiconductor layer 15 is formed on the first surface, or the second semiconductor layer 15 can be formed after the first semiconductor layer is formed on the first surface.

[0121] like Figure 5 As shown, the first surface has an overlapping area, and the first semiconductor layer and the second semiconductor layer 15 can be stacked in the overlapping area. The transparent conductive layer 13 covers the side of the first semiconductor layer and the second semiconductor layer 15 facing away from the semiconductor substrate 10, and the transparent conductive layer 13 has an opening 19 running through its thickness to prevent short circuit.

[0122] like Figure 6 As shown, when the second semiconductor layer 15 includes amorphous silicon and / or nanocrystalline silicon, laser light may be used to irradiate at least a portion of the second semiconductor layer 15, so that at least a local area of the laser-irradiated portion of the second semiconductor layer 15 is crystallized to a greater degree, forming a crystallized region 20. The laser light irradiation of the first semiconductor layer and the second semiconductor layer 15 may be performed simultaneously or separately.

[0123] Next, if Figure 7 As shown, a first electrode 17 is formed on a side of the transparent conductive layer 13 facing away from the first semiconductor layer, and a second electrode 18 is formed on a side of the transparent conductive layer 13 facing away from the second semiconductor layer 15 .

[0124] The characteristics and parameters of the at least partially formed crystallized region 20 of the second semiconductor layer 15 may refer to the characteristics and parameters of the at least partially formed crystallized region 20 of the first semiconductor layer, and are not described in detail here.

[0125] In other embodiments, Figure 8 and Figure 9 As shown, only a portion of the first semiconductor layer may be irradiated with laser light, while the second semiconductor layer 15 is not irradiated with laser light.

[0126] When the second semiconductor layer 15 comprises polycrystalline silicon, a tunneling oxide layer 14 may be further provided between the second semiconductor layer 15 and the semiconductor substrate 10 to enhance the passivation effect and reduce the carrier recombination rate in the region of the semiconductor substrate 10 where the second semiconductor layer 15 is formed. When the second semiconductor layer 15 comprises amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, the second semiconductor layer 15 comprises a second doped semiconductor layer and a second intrinsic semiconductor layer, wherein the second intrinsic semiconductor layer may comprise one or more of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0127] It should be noted that, when the second semiconductor layer 15 includes amorphous silicon and / or nanocrystalline silicon, the second semiconductor layer 15 is preferably also irradiated with laser to form a crystallized region 20 to reduce transmission loss of carriers collected by the second semiconductor layer 15 .

[0128] In addition, the present application also provides a solar cell, comprising a semiconductor substrate 10, a first semiconductor layer and a transparent conductive layer 13. The semiconductor substrate 10 has a first surface and a second surface relative to each other, the first semiconductor layer is provided on the first surface, the first surface may correspond to the backlight side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell. The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, at least a local area of the first semiconductor layer is provided as a crystallization region 20, the degree of crystallization of the crystallization region 20 is greater than the degree of crystallization of the remaining area, the crystallization region 20 includes nanocrystalline silicon and / or microcrystalline silicon. Specifically, after laser irradiation, the amorphous silicon in at least a local area of the laser-irradiated portion of the first semiconductor layer will crystallize to form nanocrystalline grains. Nanocrystalline silicon refers to a crystallized structure in which most of the grains are in the nanometer size, for example, the grain size is below 200 nm. The crystallization region 20 includes bubbles 12a. It should be noted that the crystallization region 20 and the remaining areas of the first semiconductor layer can be distributed in a direction parallel to the first surface of the semiconductor substrate 10, or can be distributed along the thickness direction of the semiconductor substrate 10. When the crystallized region 20 and the remaining area of the first semiconductor layer are distributed along the thickness direction of the semiconductor substrate 10 , the crystallized region 20 is disposed further away from the semiconductor substrate 10 . In some embodiments, the depth of the crystallized region 20 is generally less than the thickness of the first semiconductor layer.

[0129] The transparent conductive layer 13 is at least disposed on the first surface and located on a side of the first semiconductor layer away from the semiconductor substrate 10 . That is, at least a portion of the transparent conductive layer 13 is located on a side of the first semiconductor layer away from the semiconductor substrate 10 .

[0130] By adopting the above technical solution, the degree of crystallization of at least a local area of the first semiconductor layer is increased to form a crystallized region 20, thereby reducing the contact resistance of the crystallized region 20 of the doped layer, reducing the contact resistance and transmission loss, and helping to improve the photoelectric conversion efficiency of the solar cell; at the same time, in the actual manufacturing process, the first semiconductor layer containing amorphous silicon can be quickly grown first, which is conducive to improving production efficiency.

[0131] In some embodiments, the diameter of a single bubble 12a is 2 nm to 100 nm. The diameter of a single bubble 12a may refer to the equivalent diameter of a single bubble 12a, specifically the volume equivalent diameter of a single bubble 12a. For example, the diameter of a single bubble 12a may be 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0132] In some embodiments, a plurality of bubbles 12a are gathered to form a bubble cluster. The number of bubbles 12a contained in the bubble cluster can be tens, hundreds, or even thousands. That is, the number of bubbles 12a contained in the bubble cluster is greater than or equal to 10. For example, the number of bubbles 12a contained in the bubble cluster is 10, 50, 100, 150, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1200, 1500, 2000, etc. The diameter of the bubble cluster is 200 nm to 1000 nm, where the diameter of the bubble cluster is the maximum distance between the two most distant bubbles, that is, the distance between the edges of the two most distant bubbles facing away from each other. For example, the diameter of the bubble cluster can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm.

[0133] In some embodiments, the roughness of the crystallized region 20 of the first semiconductor layer is greater than the roughness of the remaining regions of the first semiconductor layer. Specifically, on the side of the first semiconductor layer facing away from the semiconductor substrate 10, the surface roughness of the crystallized region 20 of the first semiconductor layer is greater than the surface roughness of the remaining regions. This configuration can increase the contact area between the crystallized region of the first semiconductor layer and the transparent conductive layer 13, further reducing the transmission resistance while also improving the bonding strength between the crystallized region 20 of the first semiconductor layer and the transparent conductive layer 13.

[0134] In actual applications, the present invention does not specifically limit the material and conductivity type of the semiconductor substrate 10. For example, the semiconductor substrate 10 may be a silicon substrate. Alternatively, the semiconductor substrate 10 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 10 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0135] In some embodiments, the region of the transparent conductive layer 13 corresponding to the crystallized region 20 includes cracks and / or holes 13 a to increase the contact area between the transparent conductive layer 13 and the first electrode 17 and further reduce the contact resistance.

[0136] The width of the cracks and / or holes 13a is 2 nm to 100 nm. The width of the cracks may refer to the maximum width or average width of the cracks. The width of the holes 13a may refer to the equivalent diameter of the holes 13a, specifically the volume equivalent diameter of the holes 13a. For example, the width of the cracks and / or holes 13a is 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0137] In some embodiments, the roughness of the region of the transparent conductive layer 13 corresponding to the crystallized region 20 is greater than the roughness of the remaining regions of the transparent conductive layer 13. Specifically, the presence of the cracks and / or holes 13a increases the roughness of the region of the transparent conductive layer 13 corresponding to the crystallized region 20, thereby increasing the contact area between the region of the transparent conductive layer 13 corresponding to the crystallized region 20 and the electrode, reducing the transmission resistance therebetween, and improving the adhesion between the transparent conductive layer 13 and the electrode.

[0138] In some embodiments, as Figure 21 and Figure 22 as well as Figure 25 and Figure 26 As shown, the number of crystal grains in the crystallized region 20 gradually decreases along the thickness direction of the semiconductor substrate 10. In other words, the degree of crystallization of the crystallized region 20 closer to the semiconductor substrate 10 is lower than that of the crystallized region 20 farther from the semiconductor substrate 10. This configuration improves the surface conductivity of the crystallized region 20 of the first semiconductor layer near the transparent conductive layer 13, which helps reduce the contact resistance between the transparent conductive layer 13 and the first semiconductor layer, further reducing current loss.

[0139] In some embodiments, at least a portion of the first surface of the semiconductor substrate 10 is a velvet surface, on which a plurality of pyramid-like structures are formed; when the crystallized region 20 of the first semiconductor layer covers the top region of the pyramid-like structure, as shown in FIG. Figure 23 and Figure 24 As shown, the size of bubbles 12a closer to the top of the pyramid-like structure is larger than that of bubbles 12a further away from the top of the pyramid-like structure. In other words, along the thickness direction of the semiconductor substrate 10, the closer the bubbles 12a are to the top of the pyramid-like structure, the larger the size. The number of bubbles 12a closer to the top of the pyramid-like structure is greater than that of bubbles 12a further away from the top of the pyramid-like structure. In other words, the closer to the top of the pyramid-like structure, the more bubbles 12a there are. Given that the top of the pyramid-like structure does not reflect and scatter light well, this technical solution can utilize more bubbles 12a or the inner walls of larger bubbles 12a to reflect light back into the semiconductor substrate 10, thereby further improving the light absorption and utilization rate.

[0140] In some embodiments, as shown in FIG19 , the thickness of the portion of the first semiconductor layer where the crystallized region 20 is formed is greater than the thickness of the remaining regions of the first semiconductor layer. The orthographic projection of the portion of the first semiconductor layer where the crystallized region 20 is formed on the first surface overlaps with the orthographic projection of the crystallized region 20 on the first surface. For example, the thickness of the first semiconductor layer covering the top region of the pyramid-like structure is greater than the thickness of the remaining regions of the first semiconductor layer. This configuration helps improve the absorption efficiency of long-wavelength light and the collection efficiency of the first semiconductor layer, thereby improving the power generation efficiency of the solar cell.

[0141] like Figure 23 and Figure 24 As shown, when the first semiconductor layer and the transparent conductive layer 13 are formed on at least the pyramid-like structure, the portion of the transparent conductive layer 13 covering the top region of the pyramid-like structure includes cracks and / or holes 13a. That is, the cracks and / or holes 13a of the transparent conductive layer 13 are positioned near the top of the pyramid-like structure to further reduce the transmission resistance between the transparent conductive layer 13 and the first electrode 17.

[0142] As for the thickness of the crystallized region 20, please refer to the previous text. The thickness of the crystallized region 20 is less than or equal to the thickness of the first semiconductor layer; or when the first semiconductor layer includes the first doped semiconductor layer 12 and the first intrinsic semiconductor layer 11, the thickness of the crystallized region 20 is less than or equal to the sum of the thickness of the first doped semiconductor layer 12 and the thickness of the first intrinsic semiconductor layer 11. No further details will be given here.

[0143] For example, the thickness of the crystallized region 20 along the thickness direction of the semiconductor substrate 10 is greater than or equal to 3 nm to prevent the thickness of the crystallized region 20 from being too small, which is not conducive to reducing the contact resistance of the crystallized region 20. For example, the thickness of the crystallized region 20 can be 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, or 6 nm. Alternatively, the thickness of the crystallized region 20 can be 5 nm to 10 nm.

[0144] In terms of layer thickness, the embodiment of the present invention does not specifically limit the thickness of the first semiconductor layer. For example, the thickness of the first doped semiconductor layer 12 may be 5 nm to 60 nm. For example, the thickness of the first doped semiconductor layer 12 may be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm.

[0145] The thickness of the first intrinsic semiconductor layer 11 is 3 nm to 25 nm. Exemplarily, the thickness of the first intrinsic semiconductor layer 11 is 3 nm, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, or 25 nm.

[0146] In some embodiments, the solar cell further includes a second semiconductor layer 15 , wherein the conductivity type of the second semiconductor layer 15 is opposite to that of the first semiconductor layer.

[0147] The solar cell can be a double-sided contact cell, with the second semiconductor layer 15 disposed on the second surface. In this technical solution, the second semiconductor layer 15 comprises amorphous silicon and / or nanocrystalline silicon, and at least a partial region of the second semiconductor layer 15 forms a crystallized region 20. The degree of crystallization of the crystallized region 20 is greater than that of the remaining region, and the crystallized region 20 comprises nanocrystalline silicon and / or microcrystalline silicon. Of course, in other embodiments, when the second semiconductor layer 15 comprises nanocrystalline silicon and / or microcrystalline silicon, the entire second semiconductor layer 15 does not need to be crystallized, and the entire second semiconductor layer 15 has the same degree of crystallization.

[0148] The solar cell can also be a back contact cell, with the second semiconductor layer 15 provided on the first surface, and the first and second semiconductor layers 15 being alternately distributed. The first and second semiconductor layers 15 can be alternately distributed in strips or interdigitated on the first surface.

[0149] The characteristics and parameters of the second semiconductor layer 15 and its crystallized region 20 may refer to those of the first semiconductor layer and will not be described in detail here. Of course, in other embodiments, when the second semiconductor layer 15 may include nanocrystalline silicon and / or microcrystalline silicon, the entire second semiconductor layer 15 does not need to be crystallized, and the entire second semiconductor layer 15 or the entire strip has the same degree of crystallization.

[0150] In some embodiments, the solar cell further includes a first electrode 17 formed on the side of the transparent conductive layer 13 facing away from the semiconductor substrate 10. The orthographic projection of the first electrode 17 on the semiconductor substrate 10 at least partially overlaps with the orthographic projection of the crystallized region 20 provided on the first semiconductor layer on the semiconductor substrate 10, thereby ensuring that the first electrode 17 corresponds to the crystallized region provided on the first semiconductor layer, thereby reducing transmission resistance. The solar cell further includes a second electrode 18 formed on the side of the transparent conductive layer 13 facing away from the semiconductor substrate 10. The orthographic projection of the second electrode 18 on the semiconductor substrate 10 at least partially overlaps with the orthographic projection of the crystallized region 20 provided on the second semiconductor layer 15 on the semiconductor substrate 10, thereby reducing transmission resistance.

[0151] Regarding the first and second semiconductor layers 15, in terms of doping type, the doping type of the first semiconductor layer can be N-type, in which case the doping type of the second semiconductor layer 15 is P-type; alternatively, the doping type of the first semiconductor layer can be P-type, in which case the doping type of the second semiconductor layer 15 is N-type. The embodiments of the present invention do not specifically limit the doping types of the first and second semiconductor layers 15, as long as the doping types of the two layers are opposite. When the doping type is P-type, it is generally doped with Group III elements. When the doping type is N-type, it is generally doped with Group V elements or Group VI elements.

[0152] In addition, the present application also provides a photovoltaic module, such as Figure 27 As shown, the photovoltaic module includes a plurality of solar cells provided in any of the above embodiments and at least one interconnecting member, which connects two adjacent solar cells in series or in parallel. When the solar cell is a double-sided contact cell, the interconnecting member includes a first interconnecting member and a second interconnecting member 22, and the two adjacent solar cells are respectively the first solar cell and the second solar cell. The first interconnecting member 21 is connected to the electrode on the first surface of the first solar cell and extends to be connected to the electrode on the second surface of the second solar cell. Similarly, the second interconnecting member 22 is analogous to form an interconnection. When the solar cell is a back-contact solar cell, the interconnecting members are all connected to the electrodes on the first surface of the solar cell to form an interconnection. In addition, when the first electrode 17 and the second electrode 18 are both fine grids, a main grid may be provided at the corresponding position of the interconnecting member, and the current is transmitted through the semiconductor layer, the fine grid, the main grid and the interconnecting member; there may be no main grid or only a main grid with an end at the corresponding position of the interconnecting member, and the current is transmitted through the semiconductor layer, the fine grid and the interconnecting member.

[0153] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, and are not described in detail here.

[0154] In some embodiments, the projection of the interconnection on the semiconductor substrate 10 at least partially overlaps with the projection of the crystallized region 20 on the semiconductor substrate 10. This arrangement reduces transmission losses between the crystallized region 20, the electrode, and the interconnection, thereby improving power generation efficiency.

[0155] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0156] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate having a first surface and a second surface opposite to each other; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon; forming a transparent conductive layer on the first surface, wherein the transparent conductive layer is located on a side of the first semiconductor layer facing away from the semiconductor substrate; At least a portion of the first semiconductor layer is irradiated with laser light, thereby increasing the degree of crystallization of at least a local region of the first semiconductor layer in the portion irradiated with laser light.

2. The method for manufacturing a solar cell according to claim 1, wherein: The area of the first semiconductor layer with increased degree of crystallization includes bubbles; and / or the area of the transparent conductive layer corresponding to the area of the first semiconductor layer with increased degree of crystallization includes cracks and / or holes; and / or, at the position corresponding to the area of the first semiconductor layer with increased degree of crystallization, there is an air gap between the first semiconductor layer and the transparent conductive layer.

3. The method for manufacturing a solar cell according to claim 1, wherein: The local area where the degree of crystallization of the first semiconductor layer increases is a crystallization zone. Along the thickness direction of the semiconductor substrate, the crystallization zone extends from the side of the first semiconductor layer away from the semiconductor substrate toward the direction close to the semiconductor substrate, and the thickness of the crystallization zone is less than or equal to the thickness of the first semiconductor layer.

4. The method for manufacturing a solar cell according to claim 1, wherein: The first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer; Forming the first semiconductor layer on the first surface includes: forming a first intrinsic semiconductor layer on the first surface, and forming a first doped semiconductor layer on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate.

5. The method for manufacturing a solar cell according to claim 4, wherein: Irradiating at least a portion of the first semiconductor layer with a laser so as to increase the degree of crystallization of at least a local area of the first semiconductor layer irradiated by the laser, comprising: Laser is used to irradiate at least a portion of the first semiconductor layer, so that the degree of crystallization of at least local areas of the first doped semiconductor layer and the first intrinsic semiconductor layer in the laser-irradiated portion is increased to form a crystallized region, and along the thickness direction of the semiconductor substrate, the crystallized region extends from the side of the first doped semiconductor layer away from the semiconductor substrate toward the direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the sum of the thickness of the first doped semiconductor layer and the thickness of the first intrinsic semiconductor layer, or the thickness of the crystallized region is less than or equal to the thickness of the first doped semiconductor layer.

6. The method for manufacturing a solar cell according to claim 1, wherein: At least a portion of the first surface of the semiconductor substrate is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface; The first semiconductor layer and the transparent conductive layer are formed at least on the velvet surface of the first surface; the area of the first semiconductor layer with increased crystallization degree covers the top area of the pyramid-like structure, and the degree of crystallization of the first semiconductor layer covering the top part of the pyramid-like structure is greater than the degree of crystallization of the part of the first semiconductor layer covering the base of the pyramid-like structure.

7. The method for manufacturing a solar cell according to claim 6, wherein: The orthographic projection of the region of the first semiconductor layer with increased degree of crystallization on the semiconductor substrate is circular, elliptical, square or irregular; and / or the equivalent radius of the orthographic projection of the region of the first semiconductor layer with increased degree of crystallization on the semiconductor substrate is 50nm to 600nm.

8. The method for manufacturing a solar cell according to any one of claims 1 to 7, wherein: Before forming the transparent conductive layer on the first surface, the method for manufacturing a solar cell further includes: forming a second semiconductor layer on the second surface, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; or, A second semiconductor layer is formed in a local area of the first surface. The conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer. The second semiconductor layer and the first semiconductor layer are alternately distributed.

9. A solar cell, characterized in that: include: a semiconductor substrate having a first surface and a second surface opposite to each other; a first semiconductor layer disposed on the first surface, the first semiconductor layer comprising amorphous silicon and / or nanocrystalline silicon, at least a partial region of the first semiconductor layer being configured as a crystallized region, the crystallized region being more crystallized than the remaining region, the crystallized region comprising nanocrystalline silicon and / or microcrystalline silicon; and the crystallized region comprising bubbles; The transparent conductive layer is at least disposed on the first surface and located on a side of the first semiconductor layer facing away from the semiconductor substrate.

10. The solar cell according to claim 9, characterized in that The area of the transparent conductive layer corresponding to the crystallized zone includes cracks and / or holes; the width of the cracks and / or holes is 2nm to 100nm; and / or, along the thickness direction of the semiconductor substrate, the number of grains in the crystallized zone gradually decreases; and / or, the diameter of a single bubble is 2nm to 100nm; and / or, a plurality of bubbles gather to form a bubble group, and the diameter of the bubble group is 200nm to 1000nm.

11. The solar cell according to claim 9, wherein At least a portion of the first surface of the semiconductor substrate is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface; The first semiconductor layer at least covers the velvet surface of the first surface; the crystallized region of the first semiconductor layer covers the top area of the pyramid-like structure, and the degree of crystallization of the first semiconductor layer covering the top part of the pyramid-like structure is greater than the degree of crystallization of the part of the first semiconductor layer covering the base of the pyramid-like structure.

12. The method for manufacturing a solar cell according to claim 11, wherein: The size of bubbles closer to the top of the pyramid-like structure is larger than the size of bubbles farther away from the top of the pyramid-like structure; and / or the number of bubbles closer to the top of the pyramid-like structure is larger than the number of bubbles farther away from the top of the pyramid-like structure; and / or the thickness of the portion of the first semiconductor layer where the crystallized region is formed is greater than the thickness of the remaining areas of the first semiconductor layer; and / or the portion of the transparent conductive layer covering the top area of the pyramid-like structure includes cracks and / or holes.

13. The solar cell according to claim 9, characterized in that Along the thickness direction of the semiconductor substrate, the crystallized region extends from a side of the first semiconductor layer away from the semiconductor substrate toward a direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the thickness of the first semiconductor layer; Alternatively, the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer, and the first intrinsic semiconductor layer is located on a side of the first doped semiconductor layer close to the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the crystallized region extends from the side of the first doped semiconductor layer away from the semiconductor substrate toward the direction close to the semiconductor substrate, and the thickness of the crystallized region is less than or equal to the sum of the thickness of the first doped semiconductor layer and the thickness of the first intrinsic semiconductor layer, or the thickness of the crystallized region is less than or equal to the thickness of the first doped semiconductor layer.

14. The solar cell according to claim 13, characterized in that Along the thickness direction of the semiconductor substrate, the thickness of the crystallized region is greater than or equal to 3 nm; and / or, the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer, the first intrinsic semiconductor layer is located on the side of the first doped semiconductor layer close to the semiconductor substrate, the thickness of the first doped semiconductor layer is 5 nm to 60 nm, and the thickness of the first intrinsic semiconductor layer is 3 nm to 25 nm.

15. The solar cell according to claim 9, wherein The solar cell further comprises a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; The second semiconductor layer is provided on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed; Alternatively, the second semiconductor layer is disposed on the second surface, the second semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, at least a local area of the second semiconductor layer forms a crystallized region, the degree of crystallization of the crystallized region is greater than the degree of crystallization of the remaining regions, and the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon.

16. The solar cell according to claim 9, characterized in that The solar cell further includes a first electrode formed on a side of the transparent conductive layer away from the semiconductor substrate, wherein an orthographic projection of the first electrode on the semiconductor substrate at least partially overlaps with an orthographic projection of the crystallized region on the semiconductor substrate.

17. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 9 to 16 and at least one interconnector, wherein the interconnector connects two adjacent solar cells in series or in parallel.

18. The photovoltaic module according to claim 17, characterized in that: A projection of the interconnection on the semiconductor substrate at least partially overlaps with a projection of the crystallized region on the semiconductor substrate.

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