Solar cell, battery assembly and photovoltaic system

Abstract

The present invention is applicable to the field of photovoltaic technology and provides a solar cell, a cell module, and a photovoltaic system. The solar cell includes a silicon substrate having a plurality of grooves on its backlight surface; a doped region structure disposed at least in the plurality of grooves, the doped region structure comprising an inner expansion layer disposed in the silicon substrate, a passivation layer and a first doped layer disposed sequentially on the backlight surface of the silicon substrate, the passivation layer having a plurality of hole structures; for at least some of the grooves, the number of hole structures corresponding to positions at the groove edges is greater than the number of hole structures corresponding to positions in the middle of the grooves. Reducing the number of holes in the middle of the grooves improves the passivation effect and reduces surface recombination of carriers; while increasing the number of holes at the groove edges improves the carrier transport capability and reduces carrier transport recombination. These structures cooperate to improve the photoelectric conversion efficiency and overall performance of the solar cell.

Description

Technical Field

[0001] The present invention belongs to the field of photovoltaic technology, and in particular relates to a solar cell, a cell assembly and a photovoltaic system. Background Art

[0002] In the field of solar cells, improving photoelectric conversion efficiency and overall performance has always been a key goal pursued by the industry.

[0003] When a solar cell is operating, the process by which light enters the cell from the outside world involves a complex refraction phenomenon. When light refracts at interfaces between different media, some light deviates from its intended propagation path or even escapes the cell. This reduces the amount of light actually involved in photoelectric conversion, lowering the cell's effective utilization of light energy and directly impacting photoelectric conversion efficiency.

[0004] In addition, the tunneling layer is a key structure of solar cells, and its performance has a significant impact on cell efficiency. When the tunneling layer structure is not properly designed, it will hinder the tunneling process of carriers, increase the probability of carrier recombination, and reduce the efficiency of carrier collection. Moreover, an inappropriate tunneling layer structure may also affect the electric field distribution inside the cell, making the movement of photogenerated carriers disordered, further wasting energy, and making it difficult to improve the photoelectric conversion efficiency. Therefore, overcoming the adverse effects of light refraction and optimizing the tunneling layer structure are key challenges in improving the photoelectric conversion efficiency of solar cells. Summary of the Invention

[0005] The present invention provides a solar cell, a cell assembly and a photovoltaic system, aiming to solve the problem of low photoelectric conversion efficiency of solar cells.

[0006] The present invention is achieved in that a solar cell comprises:

[0007] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of grooves;

[0008] a doping region structure provided at least at a plurality of the grooves, the doping region structure comprising an inner expansion layer provided in the silicon substrate, and a passivation layer and a first doping layer provided in sequence on a backlight surface of the silicon substrate, the passivation layer having a plurality of hole structures;

[0009] For at least a portion of the grooves, the number of the hole structures at positions corresponding to the edges of the grooves is greater than the number of the hole structures at positions corresponding to the middle of the grooves.

[0010] Optionally, the groove has an inclined groove wall, and the number of the hole structures at positions corresponding to the groove wall is greater than the number of the hole structures at positions corresponding to the groove bottom.

[0011] Optionally, two adjacent groove walls have an intersection line, and the hole structure is provided at a position corresponding to the intersection line.

[0012] Optionally, the inner diffusion layer and the first doping layer have the same doping polarity.

[0013] Optionally, the plurality of grooves include N groove groups, and any of the groove groups includes a plurality of grooves arranged in sequence, where N is a positive integer greater than or equal to 2.

[0014] Optionally, for at least two adjacent grooves in the groove group, the number of the hole structures at positions corresponding to the grooves closer to the light-facing surface is smaller than the number of the hole structures at positions corresponding to the grooves farther from the light-facing surface.

[0015] Optionally, along the arrangement direction of the groove group, at least three grooves in the groove group are arranged in sequence, and the bottoms of the three grooves gradually approach the light-facing surface.

[0016] Optionally, the backlight surface of the silicon substrate includes a groove area and a non-groove area, the groove is arranged in the groove area, and the non-groove area is provided with the doping area structure. For an adjacent non-groove area and an adjacent groove area, the number of the hole structures corresponding to the non-groove area is greater than the number of the hole structures corresponding to the groove area.

[0017] Optionally, the thickness of the passivation layer is 0.5 nm-10 nm.

[0018] Optionally, the passivation layer is one or more combinations of an oxide layer, a silicon carbide layer and an amorphous silicon layer.

[0019] Optionally, the oxide layer consists of one or more layers of a silicon oxide layer and an aluminum oxide layer.

[0020] Optionally, the doping concentration of the inner diffusion layer is between the doping concentration of the silicon substrate and the doping concentration of the first doping layer.

[0021] Optionally, it also includes:

[0022] First doping regions and second doping regions are alternately arranged on the backlight surface of the silicon substrate, wherein the polarities of the first doping regions are opposite to those of the second doping regions;

[0023] A first dielectric layer provided on the light-facing surface of the silicon substrate;

[0024] a second dielectric layer disposed between the first doped region and the second doped region; and

[0025] a first conductive layer disposed on the first doping region and a second conductive layer disposed on the second doping region;

[0026] The first doping region and / or the second doping region adopts the doping region structure.

[0027] Optionally, a third doping region and a fourth doping region are included, the polarity of the first doping region is opposite to that of the second doping region, one of the first doping region and the second doping region is arranged on the light-facing side, and the other is arranged on the backlight side, and one or both of the first doping region and the second doping region adopt the described doping region structure.

[0028] Optionally, the second doped layer is a doped polysilicon layer doped with group III or group V elements.

[0029] The present invention also provides a battery assembly, which includes the above-mentioned solar cell.

[0030] The present invention also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0031] The beneficial effects achieved by this invention are due to the design of increasing holes at the edges of the grooves and reducing them in the middle. This strategy optimizes the balance between passivation and carrier transport. By reducing holes in the middle of the grooves, the passivation layer's effectiveness is enhanced, reducing surface carrier recombination. Simultaneously, increasing holes at the edges of the grooves enhances carrier transport and reduces carrier transport recombination. These two factors work together to improve the solar cell's photoelectric conversion efficiency and overall performance, enabling the cell to more efficiently convert light energy into electricity when exposed to sunlight. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic structural diagram of a solar cell provided by one embodiment of the present invention;

[0033] Figures 2 to 8 1 is a schematic structural diagram of various implementations of a solar cell provided by an embodiment of the present invention;

[0034] Figure 9 is a schematic structural diagram of a solar cell provided by another embodiment of the present invention;

[0035] Figure 10 A schematic structural diagram of a passivation layer structure provided by an embodiment of the present invention.

[0036] Description of reference numerals:

[0037] 10. Silicon substrate; 11. Doped region structure; 111. Inner diffusion layer; 112. Passivation layer; 113. First doped layer; 20. First doped region; 30. Second doped region; 40. First dielectric layer; 50. Second dielectric layer; 60. First conductive layer; 70. Second conductive layer; 80. Third dielectric layer; 90. Third doped layer; 100. Fourth dielectric layer; 110. Third conductive layer; 120. Fourth conductive layer; 130. Second doped layer; 140. Third doped region; 150. Fourth doped region. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0043] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use of other materials.

[0044] The present invention's design of increasing holes at the edges of the grooves and reducing them in the middle achieves an optimal balance between passivation and carrier transport. Reducing holes in the middle improves passivation and reduces surface recombination of carriers. Simultaneously, increasing holes at the edges enhances carrier transport and reduces carrier transport recombination. These two factors work together to improve the solar cell's photoelectric conversion efficiency and overall performance, enabling the cell to more efficiently convert light energy into electricity when exposed to sunlight.

[0045] Example 1

[0046] like Figure 1-10 As shown, the present application provides a solar cell, comprising:

[0047] A silicon substrate 10, wherein the backlight surface of the silicon substrate 10 has a plurality of grooves;

[0048] A doping region structure is provided at least in a plurality of grooves, the doping region structure comprising an inner expansion layer 111 provided in the silicon substrate 10, and a passivation layer 112 and a first doping layer 113 provided in sequence on the backlight surface of the silicon substrate 10, wherein the passivation layer 112 has a plurality of hole structures;

[0049] For at least part of the groove, the number of hole structures at positions corresponding to the edges of the groove is greater than the number of hole structures at positions corresponding to the middle of the groove.

[0050] The silicon substrate 10 is the fundamental structure of the solar cell, providing physical support for the other functional layers. Silicon is a semiconductor material with a suitable bandgap, capable of absorbing most of the visible and near-infrared light in sunlight. When sunlight strikes the silicon substrate 10, the energy of the photons is absorbed by silicon atoms, causing electrons in the valence band to transition to the conduction band, generating electron-hole pairs. This is the basis for the solar cell's photoelectric conversion.

[0051] The silicon substrate 10 has two main surfaces, a light-facing surface and a backlight surface. The light-facing surface directly faces the sunlight, while the backlight surface is the other side. The two surfaces are arranged opposite each other.

[0052] The backlit surface of the silicon substrate 10 is provided with multiple grooves, which increase the surface area of ​​the backlit surface compared to a flat surface. An internal diffusion layer 111, a passivation layer 112, and a first doped layer 113 are sequentially stacked on the backlit surface. The internal diffusion layer 111 is created by introducing impurity atoms into the silicon substrate 10 to a specific depth through a specific process, forming a region with a specific doping concentration profile. The term "internal diffusion" emphasizes the process of impurity atoms diffusing from the surface of the silicon substrate 10 into the interior, thereby changing the electrical properties of the silicon substrate 10 to a specific conductivity type (N-type or P-type) and doping concentration profile.

[0053] It can be understood that the inner expansion layer 111 diffuses from the surface of the backlight side of the silicon substrate 10 to the inside, that is, diffuses along the surface contour of the groove. The provision of the groove is conducive to increasing the provision area of ​​the inner expansion layer 111.

[0054] The function of the passivation layer 112 is to reduce the density of dangling bonds on the surface of the silicon substrate 10, reduce surface recombination centers, and thus improve the open circuit voltage and short circuit current of the battery. In some embodiments, the passivation layer 112 is preferably a combination of one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer. Specifically, the passivation layer 112 can be an oxide layer of a single material, a combination of oxide layers of multiple materials and an amorphous silicon layer, or a combination of multiple layers of amorphous silicon with different refractive indices of a single material. In addition, the passivation layer 112 can also be a silicon oxynitride layer, a silicon nitride layer, etc. It is understood that the specific structural arrangement of the passivation layer 112 includes but is not limited to the several methods listed above. The passivation layer 112 is configured accordingly according to actual use needs and is not specifically limited here. Furthermore, the thickness of the passivation layer 112 is 0.5nm-10nm. As a preferred embodiment of the present invention, the thickness of the passivation layer 112 is preferably 0.8nm-2nm. At this time, the thickness of the passivation layer 112 can be set to the same as the tunneling layer thickness in the prior art, or can be set to be thicker than the prior tunneling layer thickness, etc. It is set according to actual use needs and is not specifically limited here.

[0055] In one embodiment of the present invention, the passivation layer 112 is preferably an oxide layer and a silicon carbide layer. In this case, the oxide layer and the silicon carbide layer are arranged sequentially from the silicon substrate 10 outward, with the oxide layer contacting the inner diffusion layer 111, and the silicon carbide layer contacting the outer first doped layer 113. Furthermore, the oxide layer is preferably composed of one or more layers of a silicon oxide layer and an aluminum oxide layer; therefore, the passivation layer 112 can also be a combination of the silicon oxide layer and the aluminum oxide layer in the oxide layer. The silicon carbide layer in the passivation layer 112 includes a hydrogenated silicon carbide layer. In this case, hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate 10 through diffusion mechanisms and thermal effects, neutralizing dangling bonds on the backlight surface of the silicon substrate 10 and passivating defects in the silicon substrate 10, thereby converting the energy band in the band gap into the valence band or conduction band, thereby increasing the probability of carriers passing through the passivation layer 112 and entering the first doped layer 113.

[0056] The passivation layer 112 has a plurality of hole structures, and the hole structures can be prepared by additional chemical corrosion, dry etching or thermal diffusion impact, etc., which are prepared according to actual use needs and are not specifically limited here. It should be pointed out that the hole structure is a hole structure when the passivation layer 112 is observed from a top view angle, and a multi-channel structure when the passivation layer 112 is observed from a cross-sectional angle. At this time, the holes in the hole structure may completely penetrate the passivation layer 112; some may not completely penetrate the passivation layer 112, and form grooves / openings on the surface of the passivation layer 112.

[0057] In some embodiments, the pore size of the hole structure is less than 20 μm, which can be specifically that the average pore size of each hole is less than 20 μm, or that 90% of all holes have pore sizes less than 20 μm. At the same time, the ratio of the area of ​​the hole region in the passivation layer 112 to the overall area of ​​the passivation layer 112 is less than 20%, that is, a number of holes are sparsely distributed on the passivation layer 112. A specific verification method can be to take any cross-section of the passivation layer 112, which is parallel to the backlight surface, and find that the ratio of the area of ​​the hole region in the passivation layer 112 to the overall area of ​​the passivation layer 112 is less than 20%.

[0058] The first doped layer 113 is disposed on the passivation layer 112. The polarity of the first doped layer 113 is the same as that of the inner extension layer 111. That is, when the inner extension layer 111 is P-type, the first doped layer 113 is P-type; when the inner extension layer 111 is N-type, the first doped layer 113 is N-type. It should be noted that the doping polarity of the inner extension layer 111 and the first doped layer 113 can be different from the doping polarity of the silicon substrate 10. For example, if the silicon substrate 10 is N-type single crystal silicon, the inner extension layer 111 and the first doped layer 113 can be P-type doped layers.

[0059] The pore structure contains an inner expansion layer 111 and / or a first doping layer 113. That is, the pore structure may contain entirely the inner expansion layer 111, entirely the first doping layer 113, or a mixture of the inner expansion layer 111 and the first doping layer 113. It should be noted that during the actual production process, the pore structure may also partially contain the inner expansion layer 111 and / or the first doping layer 113. In this case, the remaining portion not filled with the inner expansion layer 111 and / or the first doping layer 113 is a void region. It should also be noted that, in addition to being filled with the inner expansion layer 111 and / or the first doping layer 113, the pore region may also contain impurities (such as hydrogen, oxygen, and various metal elements) generated by precipitation or segregation during thermal processes (multiple high-temperature treatment steps may be involved in solar cell production, depending on the process flow).

[0060] In one embodiment, the non-hole region of the passivation layer 112 (i.e., the portion of the passivation layer 112 not provided with the hole structure) contains a dopant of the same doping type as that of the inner expansion layer 111 and / or the first doping layer 113. For example, when the inner expansion layer 111 and the first doping layer 113 are N-type doped (e.g., phosphorus doped), the non-hole region of the passivation layer 112 contains diffused N-type dopant.

[0061] In one embodiment, the inner diffusion layer 111 is located between the silicon substrate 10 and the passivation layer 112. The inner diffusion layer 111 can be directly diffused and deposited on the silicon substrate 10 by ion implantation or other methods. In this case, the inner diffusion layer 111 is located in the silicon substrate 10, and the passivation layer 112 is directly prepared on the silicon substrate 10. The concentration of the inner diffusion layer 111 can be easily controlled and adjusted. The inner diffusion layer 111 can also be formed by directly passing the doping source through a plurality of hole structures in the passivation layer 112 during the preparation of the first doping layer 113, and then forming the first doping layer 113 in the silicon substrate 10. In this case, the inner diffusion layer 111 is also located in the silicon substrate 10, and the passivation layer 112 is directly prepared on the silicon substrate 10. When the first doping layer 113 is prepared, it is thermally diffused into the silicon substrate 10, so that a portion of the silicon substrate 10 diffuses into the inner diffusion layer 111. In this case, the doping concentration of the inner diffusion layer 111 is between the doping concentration of the silicon substrate 10 and the doping concentration of the first doping layer 113. Preferably, the inner extension layer 111 and the first doping layer 113 have the same doping polarity. For example, when the first doping layer 113 is an N-type doping layer, the inner extension layer 111 is also preferably an N-type doping layer. However, it should be noted that the doping polarity of the inner extension layer 111 and the first doping layer 113 may be different from the doping polarity of the silicon substrate 10. For example, in this embodiment, if the silicon substrate 10 is N-type single crystal silicon, the inner extension layer 111 and the first doping layer 113 may be P-type doping layers.

[0062] In one embodiment of the present invention, the first doped layer 113 is a doped polysilicon layer. Doping crystalline silicon effectively increases the carrier concentration (electrons or holes) in the material. For example, doping with phosphorus to form n-type doped polysilicon provides a large number of free electrons, while doping with boron to form p-type doped polysilicon generates a large number of holes. A higher carrier concentration helps improve the battery's conductivity, thereby reducing the battery's series resistance, minimizing energy loss during transmission, and improving the photovoltaic cell's fill factor and photoelectric conversion efficiency.

[0063] The hole structure on the passivation layer 112 will destroy the integrity of the passivation layer 112. When there are holes on the passivation layer 112, the surface of the silicon substrate 10 is directly exposed at the holes, and the dangling bonds cannot be effectively covered, resulting in an increase in the recombination centers in these areas. Reducing the number of holes in the middle of the groove can keep the passivation layer 112 relatively intact in this area, thereby better playing the passivation role, reducing the surface recombination rate, and improving the overall performance of the battery. For example, in the absence of hole interference, the passivation layer 112 can evenly contact the surface of the silicon substrate 10, effectively reducing the surface dangling bond density, reducing carrier recombination, and improving the open circuit voltage of the battery.

[0064] The bottom of the groove is concave. The edge of the groove forms a relatively high boundary, like the rim of a bowl, while the middle of the groove is significantly lower than the edge, appearing concave, like the interior of the bowl. The height difference between the edge and the middle of the groove creates a space with a certain depth, with the middle of the groove closer to the light than the edge.

[0065] As a case, Figure 10 As shown, a groove is present on the silicon substrate 10, and the thickness of the passivation layer 112 is controlled within a relatively small range. That is, the passivation layer 112 is configured as a relatively thin film layer structure. The profile of the passivation layer 112 formed on and covering the silicon substrate 10 follows the profile of the silicon substrate 10, and a concave structure is formed on the passivation layer 112 at the position corresponding to the groove. The relatively thin thickness of the passivation layer 112 can enhance the tunneling effect of carriers and facilitate carrier collection. Figure 10 This is an SEM image after the first doping layer 113 on the passivation layer 112 in the cell is removed. For example, it can be obtained by removing the first doping layer 113 with a TMAH solution, and the grooves and hole structures on the passivation layer 112 can be clearly observed.

[0066] When carriers are generated in the silicon substrate 10, if they are transmitted through the edge of the groove, the carriers need to travel a longer distance because the edge of the groove is higher than the middle of the groove (the distance to the light-facing surface is longer). The longer the carrier transmission distance, the greater the probability of carrier recombination and the lower the transmission efficiency. The hole structure is the key channel for the conduction between the inner expansion layer 111 and the first doped layer 113. Providing more holes at the edge of the groove can provide more transmission paths for carriers. When carriers pass through these holes, they can be transmitted more quickly from the silicon substrate 10 to the first doped layer 113, and then to the electrode, reducing the recombination loss of carriers during long-distance transmission and improving the carrier transmission efficiency.

[0067] In this embodiment, the design of increasing holes at the edges of the grooves and reducing them in the middle of the grooves represents a strategy for optimizing the balance between passivation and carrier transport. By reducing holes in the middle of the grooves, passivation is enhanced, reducing surface recombination of carriers. Simultaneously, increasing holes at the edges of the grooves enhances carrier transport and reduces carrier transport recombination. These two factors work together to improve the solar cell's photoelectric conversion efficiency and overall performance, enabling the cell to more efficiently convert light energy into electricity when exposed to sunlight.

[0068] In some embodiments, the groove has a groove bottom and sidewalls, and at least part of the groove has inclined sidewalls, which can avoid the formation of sharp points on the sidewalls to cause stress concentration, and is beneficial to the stability of the silicon substrate 10 structure. The edge of the groove includes the sidewall position. When carriers are generated in the silicon substrate 10, if they are transmitted through the sidewalls of the groove, since the sidewalls are higher than the middle of the groove, the carriers need to travel a longer distance. The longer the carrier transmission distance, the greater the probability of carrier recombination and the lower the transmission efficiency. The hole structure is the key channel for the conduction between the inner expansion layer 111 and the first doped layer 113. Providing more holes at the edge of the groove can provide more transmission paths for carriers. When carriers pass through these holes, they can be transmitted more quickly from the silicon substrate 10 to the first doped layer 113, and then to the electrode, reducing the recombination loss of carriers during long-distance transmission and improving the carrier transmission efficiency.

[0069] Furthermore, two adjacent groove walls have an intersection line, and a hole structure is provided at the position corresponding to the intersection line. The hole structure is provided at the intersection line of the two adjacent groove walls for common use by both. Compared with providing a hole in each groove wall separately, this sharing method reduces the number of hole structures to be provided, which can improve the passivation effect of the passivation layer. In addition, the complex operation of opening holes in the two groove walls can now be completed in one operation at the intersection line, which greatly shortens the production time and improves production efficiency. At the same time, the stress concentration inside the structure is reduced. When the hole structure is subjected to stress, the stress can be evenly distributed between the adjacent groove walls through the shared hole structure, avoiding structural damage caused by excessive concentration of stress in local areas.

[0070] Example 2

[0071] In some embodiments, the plurality of grooves include N groove groups, any groove group includes a plurality of grooves arranged in sequence along the same direction, and the arrangement directions of the plurality of grooves in different groove groups are the same or different, and N is a positive integer greater than or equal to 2.

[0072] On the one hand, the multiple grooves in different groove groups adopt the same or different arrangement directions, which can scatter and refract incident light at different angles. When sunlight shines on the surface of the battery, the horizontally arranged groove groups can effectively capture horizontally incident light, while the vertically arranged groove groups can capture vertically or other obliquely incident light. This multi-directional light capture method greatly increases the propagation path of light within the battery, allowing more light to be absorbed by the silicon substrate 10, thereby improving light absorption efficiency.

[0073] Furthermore, the differences in groove size within different groove groups optimize absorption for different wavelengths of light. Deeper and wider grooves better absorb longer wavelengths, while shallower and narrower grooves are more effective at absorbing shorter wavelengths. By rationally designing the groove sizes of different groove groups, the cell can achieve efficient light absorption across the entire solar spectrum, further improving the cell's photoelectric conversion efficiency.

[0074] In some embodiments, for at least two adjacent grooves in a groove group, the number of hole structures at positions corresponding to the grooves closer to the light-facing surface is smaller than the number of hole structures at positions corresponding to the grooves farther from the light-facing surface.

[0075] Specifically, the groove group includes at least two adjacent grooves of different depths, wherein the deeper groove has a smaller distance from the light-facing surface, while the shallower groove has a larger distance from the light-facing surface. The number of hole structures at positions corresponding to the deeper grooves is smaller than the number of hole structures at positions corresponding to the shallower grooves.

[0076] Two grooves of different depths form a step surface at adjacent positions, that is, a shallow groove is on the step surface of the upper level. When multiple grooves of different depths are arranged in sequence, a stepped step surface can be formed. The shallow grooves have a large number of hole structures at the corresponding positions, which can provide more transmission channels for carriers. The carriers generated on the step surface can be transmitted to the first doped layer 113 more quickly through these holes, reducing the recombination probability of the carriers during the transmission process. The deep grooves have a small number of hole structures at the corresponding positions, which helps to maintain the integrity of the passivation layer 112 in this area, reduce surface recombination, and increase the life of the carriers.

[0077] In some embodiments, along the arrangement direction of the groove group, at least three grooves in the groove group are arranged in sequence, and the bottoms of the at least three grooves gradually approach the light-facing surface. That is, along the arrangement direction of the grooves, the depth of the grooves increases.

[0078] When light strikes the overlapping groove structures of increasing depth, it undergoes multiple reflections and scattering between the walls of each groove. The varying depths of the grooves create a complex optical surface, where light constantly changes its direction, increasing the length of its propagation path within the cell. This allows more light to be absorbed by the silicon substrate 10, improving the cell's sunlight absorption efficiency. Because light is fully scattered and absorbed within the overlapping groove structures, photogenerated carriers (electron-hole pairs) are generated more uniformly within the silicon substrate 10. This uniform carrier generation distribution helps reduce localized carrier recombination and improves overall carrier generation efficiency.

[0079] Example 3

[0080] In some embodiments, the backlight surface of the silicon substrate 10 includes a groove area and a non-groove area, the groove is set in the groove area, and the non-groove area is provided with a doped region structure. For an adjacent non-groove area and a groove area, the number of hole structures corresponding to the non-groove area is greater than the number of hole structures corresponding to the groove area.

[0081] The non-grooved areas are typically flatter, providing a simpler carrier transport path. They are also taller than the grooved areas. Providing more holes provides more transport channels for carriers. After photogenerated carriers are generated in the non-grooved areas, they can more quickly travel through these holes to the corresponding first doped layer 113, where they are collected by the electrodes.

[0082] Due to its structural characteristics, the groove region has a high number of dangling bonds and defects on its surface, which can easily lead to carrier recombination. Reducing the number of holes in the groove region allows the passivation layer 112 to better cover the surface of the silicon substrate 10 within the groove, reducing the surface state density and effectively passivating the groove region. The passivation layer 112 can inhibit surface recombination and increase the carrier lifetime, giving carriers generated in the groove region more opportunities to be transmitted to and collected in the non-grooved area.

[0083] Example 4

[0084] In some embodiments, the solar cell further comprises:

[0085] The first doping regions 20 and the second doping regions 30 are alternately arranged on the backlight surface of the silicon substrate 10, and the polarities of the first doping regions 20 and the second doping regions 30 are opposite;

[0086] A first dielectric layer 40 disposed on the light-facing surface of the silicon substrate 10;

[0087] a second dielectric layer 50 disposed between the first doping region 20 and the second doping region 30; and

[0088] A first conductive layer 60 disposed on the first doping region 20 and a second conductive layer 70 disposed on the second doping region 30;

[0089] The first doping region 20 and / or the second doping region 30 adopts the doping region structure 11 as described in the above embodiment.

[0090] Specifically, the solar cell can be such that both the first doping region 20 and the second doping region 30 adopt the doping region structure 11 of the aforementioned embodiment, referring to Figure 2 、 Figure 4 and Figure 6 As shown, at this time, since the polarity of the first doping region 20 and the second doping region 30 is opposite, the doping polarity of the inner extension layer 111 and the first doping layer 113 in the first doping region 20 and the second doping region 30 is opposite. For example, when the inner extension layer 111 and the first doping layer 113 in the first doping region 20 are P-type doping layers, the inner extension layer 111 and the first doping layer 113 in the second doping region 30 are N-type doping layers with opposite doping polarity. In this case, the first doping region 20 is a P-type doping region and the second doping region 30 is an N-type doping region. Of course, it is also possible that the first doping region 20 is an N-type doping region and the second doping region 30 is a P-type doping region. Therefore, one of the first doping region 20 and the second doping region 30 is a P-type doping region and the other is an N-type doping region.

[0091] Of course, the solar cell may also be such that one of the first doping region 20 and the second doping region 30 adopts the doping region structure 11 of the aforementioned embodiment, while the other adopts an existing structure (such as a passivation contact structure or a diffusion structure). In this embodiment, preferably, the other is the second doping layer 130 disposed on the backlight surface of the silicon substrate 10, that is, the other adopts an existing diffusion structure, referring to Figure 3 、 Figure 5 、 Figure 7 and Figure 8 As shown, specifically, the first doping region 20 may adopt the doping region structure 11, and the second doping region 30 may be a second doping layer 130 disposed on the backlight surface of the silicon substrate 10. Alternatively, the other of the two structures may also adopt an existing passivation contact structure, in which case the passivation contact structure includes a tunneling layer and a doped region (not shown). It should be noted that the second doping layer 130 is also a doped single-crystalline silicon layer doped with Group III or Group V elements. Its specific structure can refer to the inner expansion layer 111 in the aforementioned embodiment. It should be noted that since the first doping region 20 and the second doping region 30 have opposite polarities, while the inner expansion layer 111 and the first doping layer 113 have the same doping polarity, the inner expansion layer 111 and the second doping layer 130 are doped with different group elements. That is, when the inner expansion layer 111 is doped with a Group III element, the second doping layer 130 is doped with a Group V element; and when the inner expansion layer 111 is doped with a Group V element, the second doping layer 130 is doped with a Group III element.

[0092] Among them, when the first doping region 20 and the second doping region 30 both adopt the doping region structure 11 of the aforementioned embodiment, the materials and thicknesses selected in each layer structure in the first doping region 20 can be the same as or different from those in the each layer structure in the second doping region 30. For example, when the passivation layer 112 in the first doping region 20 is specifically selected as a silicon oxide layer and a silicon carbide layer, the passivation layer 112 in the second doping region 30 can be selected in the same manner as the passivation layer 112 in the first doping region 20, or a material different from that of the passivation layer 112 in the first doping region 20, such as an aluminum oxide layer and a silicon carbide layer, can be selected.

[0093] At the same time, the thickness of the passivation layer 112 in the first doping region 20 and the passivation layer 112 in the second doping region 30 can be set to be the same or different. Preferably, regardless of whether the passivation layer 112 in the first doping region 20 and the passivation layer 112 in the second doping region 30 are made of the same material, the passivation layer 112 corresponding to the Group III element doped in the inner diffusion layer 111 is set to be thicker, while the passivation layer 112 corresponding to the Group V element doped in the first doping layer 113 is set to be thinner. In other words, the thickness of the passivation layer 112 in the P-type doping region is greater than that of the passivation layer 112 in the N-type doping region. The main reason for this is that the P-type doping region requires processes such as boron doping, which require higher temperatures and multiple heat treatment processes, thus requiring a thicker passivation layer 112. In this embodiment, the structural materials and thicknesses of each layer in the first doping region 20 and the second doping region 30 are set accordingly according to actual use needs and are not specifically limited here.

[0094] In a preferred embodiment of the present invention, the hole density of the passivation layer 112 in the P-type doped region is greater than the hole density of the passivation layer 112 in the N-type doped region. The hole density refers to the number of holes per unit area. That is, within the same unit area, the number of holes in the passivation layer 112 in the P-type doped region is greater than the number of holes in the passivation layer 112 in the N-type doped region. This is primarily due to the poor conductivity of the P-type doped region, which requires more holes to improve conductivity. Furthermore, since the passivation layer 112 in the P-type doped region is thicker, more holes are required to improve conductivity.

[0095] In one embodiment of the present invention, the first dielectric layer 40 and the second dielectric layer 50 are one or more combinations of aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, and silicon oxide. The first dielectric layer 40 and the second dielectric layer 50 serve as a passivation layer, and the first dielectric layer 40 and the second dielectric layer 50 are at least one layer structure, with the refractive index of each layer decreasing outward from the silicon substrate 10. This allows the layer closer to the silicon substrate 10 to serve as a passivation layer, while the layer farther from the silicon substrate 10 serves as an anti-reflection layer. This enhances the anti-reflection effect, thereby increasing the absorption and utilization of light by the silicon substrate 10 and thereby increasing the short-circuit current density. Each of the different film structures in the first dielectric layer 40 and the second dielectric layer can also be composed of multiple layers of films with different refractive indices, and the layers can be arranged such that the refractive index of each film layer decreases outward from the silicon substrate 10. For example, the silicon oxide layer in the first dielectric layer 40 can be composed of multiple layers of silicon oxide films with a refractive index decreasing outward from the silicon substrate 10.

[0096] It should be noted that the structures of the first dielectric layer 40 and the second dielectric layer 50 can be arranged identically or differently. The first dielectric layer 40 and the second dielectric layer 50 are configured accordingly based on actual usage needs, and are not specifically limited here. Preferably, the first dielectric layer 40 and the second dielectric layer 50 are configured identically, so that the first dielectric layer 40 and the second dielectric layer 50 can be obtained by preparing the front and back surfaces of the silicon substrate 10 using the same process.

[0097] In a preferred embodiment of the present invention, the first dielectric layer 40 and / or the second dielectric layer 50 preferably have a two-layer structure of an aluminum oxide layer and a silicon carbide layer, or a two-layer structure of a silicon oxide layer and a silicon carbide layer. In this case, the overall thickness of the first dielectric layer 40 is greater than 50 nm, and the overall thickness of the second dielectric layer 50 is greater than 25 nm. It is understood that the specific structural arrangements of the first dielectric layer 40 and the second dielectric layer 50 include, but are not limited to, the specific examples listed above.

[0098] Furthermore, in one embodiment of the present invention, the thickness of the aluminum oxide layer or silicon oxide layer in the first dielectric layer 40 is less than 40 nm, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer 50 is less than 25 nm, and the thickness of the silicon carbide layer in the first dielectric layer 40 and / or the second dielectric layer 50 is greater than 10 nm. In this case, the silicon carbide layer in the first dielectric layer 40 and / or the second dielectric layer 50 not only provides a hydrogen passivation effect but also reduces parasitic light absorption due to its large optical band gap and low absorption coefficient.

[0099] It should be noted that in the multilayer structure of the embodiment of the present invention, the order is arranged from the silicon substrate 10 to the outside. For example, when the first dielectric layer 40 is an aluminum oxide layer and a silicon carbide layer, the aluminum oxide layer is close to the silicon substrate 10, and the silicon carbide layer is close to the outside. It should also be noted that in the drawings of the specification, Figures 2 to 8 , only the first dielectric layer 40 and the second dielectric layer 50 are shown as a two-layer structure. It is understandable that the first dielectric layer 40 and the second dielectric layer 50 can also have other numbers of layers. The specific structure is set according to actual needs and does not completely follow the drawings in the specification. It should also be pointed out that the various drawings of the present invention are only used to describe the specific structure distribution of the solar cell, but do not correspond to the actual size of each structure. The drawings do not completely correspond to the actual size specified in this embodiment. The specific parameters provided in this embodiment should be followed.

[0100] Furthermore, the silicon carbide layer in the first dielectric layer 40 and / or the second dielectric layer 50 is composed of at least one silicon carbide film with different refractive indices. The refractive index of each silicon carbide film decreases from the silicon substrate 10 outward. Optionally, the refractive indices of the above-mentioned various materials can generally be selected as follows: the refractive index of single-crystalline silicon is 3.88, the refractive index of amorphous silicon is 3.5-4.2, the refractive index of polycrystalline silicon is 3.93, the refractive index of silicon carbide is 2-3.88, the refractive index of silicon nitride is 1.9-3.88, the refractive index of silicon oxynitride is 1.45-3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63. It is understandable that the refractive indices of the above-mentioned various materials can also be set to other values ​​according to actual use needs, and are not specifically limited here.

[0101] Furthermore, in one embodiment of the present invention, a magnesium fluoride layer is further provided on the outer layer of the first dielectric layer 40 and / or the second dielectric layer 50. That is, in addition to the combination of one or more of the aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, silicon carbide layer, amorphous silicon layer, and silicon oxide layer selected for the first dielectric layer 40 and the second dielectric layer 50, a magnesium fluoride layer may be further provided on the outer layer of the first dielectric layer 40 and / or the second dielectric layer 50. The magnesium fluoride layer has the lowest refractive index requirement, generally set at 1.4, and is used to enhance the optical anti-reflection effect.

[0102] Furthermore, in one embodiment of the present invention, an electric field layer or a floating junction is provided between the light-facing surface of the silicon substrate 10 and the first dielectric layer 40. Specifically, the electric field layer is obtained by phosphorus diffusion into the silicon substrate 10, or the floating junction is obtained by boron diffusion into the silicon substrate 10. In this case, the electric field layer or the floating junction serves as the front surface electric field of the solar cell.

[0103] In one embodiment of the present invention, the first conductive layer 60 and / or the second conductive layer 70 are TCO transparent conductive films and / or metal electrodes. The metal electrodes include silver electrodes, copper electrodes, aluminum electrodes, tin-clad copper electrodes or silver-clad copper electrodes. Furthermore, the copper electrode is electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium or tungsten electrodes as its seed layer or protective layer. It should be noted that the first conductive layer 60 and the second conductive layer 70 can also be selected to be the same or different, for example, the first conductive layer 60 and the second conductive layer 70 are both aluminum electrodes; or the first conductive layer 60 is a silver electrode, while the second conductive layer 70 is an aluminum electrode.

[0104] Furthermore, in one embodiment of the present invention, the light-facing surface of the silicon substrate 10 is also subjected to a texturing process before preparing the first dielectric layer 40, so that the morphology formed on the light-facing surface includes but is not limited to an alkali polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical crown shape, a V-groove shape, and a morphology between the above morphologies. At this time, the surface morphology formed on the light-facing surface of the silicon substrate 10 is beneficial to reducing the reflection of sunlight on the light-facing surface and improving the conversion efficiency of solar cells.

[0105] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 may cover only the region between the first doped region 20 and the second doped region 30 on the silicon substrate 10, or may extend to cover the first doped region 20 and / or the second doped region 30. In this case, when the second dielectric layer 50 covers only the region between the first doped region 20 and the second doped region 30 on the silicon substrate 10, the first conductive layer 60 covers the entire backlight surface of the first doped region 20 for electrical connection, and the second conductive layer 70 covers the entire backlight surface of the second doped region 30 for electrical connection. When the second dielectric layer 50 extends to cover the first doped region 20 and / or the second doped region 30, the first conductive layer 60 covers the remaining portion of the back surface of the first doped region 20 not covered by the second dielectric layer 50 for electrical connection, and the second conductive layer 70 covers the remaining portion of the back surface of the second doped region 30 not covered by the second dielectric layer 50 for electrical connection. When the second dielectric layer 50 completely covers the entire backlight surface, the first conductive layer 60 is formed through the second dielectric layer 50 by means of perforations or other means to form an electrical connection with the first doped region 20; the second conductive layer 70 is formed through the second dielectric layer 50 by means of perforations or other means to form an electrical connection with the second doped region 30. The conductive polarity of the first conductive layer 60 and the second conductive layer 70 is determined by the polarity of the first doped region 20 and the second doped region 30, and is not specifically limited here.

[0106] In one embodiment of the present invention, referring to Figure 2 and Figure 3As shown, the first doping regions 20 and the second doping regions 30 are alternately arranged on the backlight surface of the silicon substrate 10. In order to avoid unfavorable phenomena such as leakage caused by the first doping regions 20 and the second doping regions 30 being connected to each other without obstruction, a trench is provided between the first doping regions 20 and the second doping regions 30. At this time, the first doping regions 20 and the second doping regions 30 are separated by the trench, and the corresponding second dielectric layer 50 is also covered on the trench. It should be pointed out that the surface morphology of the groove in contact with the silicon substrate 10 can also be provided with a rough texture structure, wherein the rough texture structure is usually formed by texturing, which includes but is not limited to alkali polishing surface, mechanical polishing surface, random pyramid shape, inverted pyramid shape, spherical crown shape, V-shaped groove shape and morphology between the above morphologies. It can usually form an irregular hemispherical texture by acid texturing, form a pyramid texture by alkali texturing, or first form a pyramid texture by alkali texturing and then smooth the pyramid top by acid texturing. At this time, the surface morphology formed at the groove on the backlight side of the silicon substrate 10 is beneficial to increase the absorption and reuse of light by the silicon substrate 10, thereby increasing the short-circuit current density, thereby improving the conversion efficiency of the solar cell.

[0107] Example 5

[0108] In some embodiments, a third doping region 140 and a fourth doping region 150 are included, the polarity of the third doping region 140 is opposite to that of the fourth doping region 150, one of the third doping region 140 and the fourth doping region 150 is arranged on the light-facing side, and the other is arranged on the backlight side, and one or both of the third doping region 140 and the fourth doping region 150 adopt a doping region structure.

[0109] The third doping region 140 and the fourth doping region 150 have opposite polarities. Specifically, the third doping region 140 may be N-type and the fourth doping region 150 may be P-type, or the third doping region 140 may be P-type and the fourth doping region 150 may be N-type. The third doping region 140 and the fourth doping region 150 are respectively disposed on the light-facing and backlight-facing surfaces of the silicon substrate. The third doping region 140 and the fourth doping region 150 may both utilize the doping region structure 11, or only the third doping region 140 or the fourth doping region 150 may utilize the doping region structure 11.

[0110] In a specific example, Figure 9 As shown, the third doping region 140 is arranged on the backlight side, and the third doping region 140 adopts the doping region structure 11, and the fourth doping region 150 is arranged on the light-facing side. Specifically, the third doping region 140 includes the doping region structure 11 arranged on the backlight side of the silicon substrate 10 and the third dielectric layer 80 arranged on the doping region structure 11;

[0111] The fourth doped region 150 includes a third doped layer 90 and a fourth dielectric layer 100 sequentially disposed on the light-facing surface of the silicon substrate 10 ; and

[0112] a third conductive layer 110 electrically connected to the doped region structure 11 and a fourth conductive layer 120 electrically connected to the third doped layer 90;

[0113] The polarity of the doping region structure 11 is opposite to that of the third doping layer 90 .

[0114] Among them, the third doping layer 90 is a doped polysilicon layer doped with group III or group V elements, and its specific reference can be made to the first doping layer 113 in the doping region structure 11 of the aforementioned embodiment. It should be pointed out at this time that the polarity of the doping region structure 11 is opposite to that of the third doping layer 90. Therefore, the first doping layer 113 and the third doping layer 90 are doped with different group elements respectively, that is, when the first doping layer 113 is doped with group III elements, the third doping layer 90 is doped with group V elements; when the first doping layer 113 is doped with group V elements, the third doping layer 90 is doped with group III elements.

[0115] In one embodiment of the present invention, the third dielectric layer 80 and the fourth dielectric layer 100 are one or more combinations of aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, and silicon oxide. The third dielectric layer 80 and the fourth dielectric layer 100 serve as a passivation layer, and each of the third dielectric layer 80 and the fourth dielectric layer 100 is provided as at least one layer. The refractive index of each layer decreases from the silicon substrate 10 outward, so that the film layer close to the silicon substrate 10 serves as a passivation layer, while the film layer away from the silicon substrate 10 serves as an anti-reflection layer. This enhances the anti-reflection effect, thereby increasing the absorption and utilization of light by the silicon substrate 10 and increasing the short-circuit current density. Each film layer of different structures in the third dielectric layer 80 and the fourth dielectric layer 100 may also be composed of a multilayer film with different refractive indices, and arranged in a manner such that the refractive index of each film layer decreases from the silicon substrate 10 outward. For example, the silicon oxide layer in the third dielectric layer 80 may be composed of a multilayer silicon oxide film with a refractive index decreasing from the silicon substrate 10 outward.

[0116] It should be noted that the structures of the third dielectric layer 80 and the fourth dielectric layer 100 can be arranged identically or differently. The respective film structures of the third dielectric layer 80 and the fourth dielectric layer 100 are configured accordingly based on actual usage needs, and are not specifically limited herein. Preferably, the third dielectric layer 80 and the fourth dielectric layer 100 are configured identically, so that the fourth dielectric layer 100 and the third dielectric layer 80 can be obtained by fabricating the front and back surfaces of the silicon substrate 10 using the same process.

[0117] In a preferred embodiment of the present invention, the third dielectric layer 80 and / or the fourth dielectric layer 100 preferably have a two-layer structure of an aluminum oxide layer and a silicon carbide layer, or a two-layer structure of a silicon oxide layer and a silicon carbide layer. In this case, the overall thickness of the third dielectric layer 80 is greater than 25 nm, and the overall thickness of the fourth dielectric layer 100 is greater than 50 nm. It will be appreciated that the specific structural arrangements of the third dielectric layer 80 and the fourth dielectric layer 100 include, but are not limited to, the specific examples listed above.

[0118] Furthermore, in one embodiment of the present invention, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer 80 is less than 25 nm, the thickness of the aluminum oxide layer or silicon oxide layer in the fourth dielectric layer 100 is less than 40 nm, and the thickness of the silicon carbide layer in the third dielectric layer 80 and / or the fourth dielectric layer 100 is greater than 10 nm. In this case, the silicon carbide layer in the third dielectric layer 80 and / or the fourth dielectric layer 100 not only provides a hydrogen passivation effect but also reduces parasitic light absorption due to its large optical band gap and low absorption coefficient.

[0119] It should be noted that in the multilayer structure of the embodiment of the present invention, the order is arranged from the silicon substrate 10 to the outside. For example, when the third dielectric layer 80 is an aluminum oxide layer and a silicon carbide layer, the aluminum oxide layer is close to the silicon substrate 10, and the silicon carbide layer is close to the outside. It should also be noted that in the drawings of the specification, Figure 9 As shown, it only shows that the third dielectric layer 80 and the fourth dielectric layer 100 are two-layer structures. It is understandable that the third dielectric layer 80 and the fourth dielectric layer 100 can also have other numbers of layers. The specific structure is set according to actual needs and does not completely follow the figures shown in the specification. It should also be pointed out that the various figures of the present invention are only used to describe the specific structure distribution of the solar cell, but they do not correspond to the actual size of each structure. The figures do not completely correspond to the actual size specified in this embodiment. They should be based on the specific parameters provided in this embodiment.

[0120] Furthermore, the silicon carbide layer in the third dielectric layer 80 and / or the fourth dielectric layer 100 is composed of at least one silicon carbide film with a different refractive index. The refractive index of each silicon carbide film decreases from the silicon substrate 10 outward. Optionally, the refractive indices of the aforementioned materials can generally be selected as follows: a refractive index of 3.88 for single-crystalline silicon, a refractive index of 3.5-4.2 for amorphous silicon, a refractive index of 3.93 for polycrystalline silicon, a refractive index of 2-3.88 for silicon carbide, a refractive index of 1.9-3.88 for silicon nitride, a refractive index of 1.45-3.88 for silicon oxynitride, a refractive index of 1.45 for silicon oxide, and a refractive index of 1.63 for aluminum oxide. It is understood that the refractive indices of the aforementioned materials can also be set to other values ​​based on actual use needs, and are not specifically limited here.

[0121] Furthermore, in one embodiment of the present invention, the outer layer of the third dielectric layer 80 and / or the fourth dielectric layer 100 is further provided with a magnesium fluoride layer. That is, in addition to the aforementioned combination of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, silicon carbide layer, amorphous silicon layer, and silicon oxide layer selected for the third dielectric layer 80 and the fourth dielectric layer 100, the outer layer of the third dielectric layer 80 and / or the fourth dielectric layer 100 may further be provided with a magnesium fluoride layer. The magnesium fluoride layer has the lowest refractive index requirement, generally set at 1.4, and is used to enhance the optical anti-reflection effect.

[0122] In one embodiment of the present invention, the third conductive layer 110 and / or the fourth conductive layer 120 are TCO transparent conductive films and / or metal electrodes. The metal electrodes include silver electrodes, copper electrodes, aluminum electrodes, tin-clad copper electrodes, or silver-clad copper electrodes. Furthermore, the copper electrodes are electroplated copper prepared by electroplating or physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer. It should be noted that the third conductive layer 110 and the fourth conductive layer 120 can be the same or different. For example, both the third conductive layer 110 and the fourth conductive layer 120 can be aluminum electrodes; or the third conductive layer 110 can be silver electrodes, while the fourth conductive layer 120 can be aluminum electrodes. Furthermore, the third conductive layer 110 is electrically connected to the doped region structure 11 by perforating the third dielectric layer 80, and the third conductive layer 110 is electrically connected to the fourth doped layer 90 by perforating the fourth dielectric layer 100. The conductive polarity of the third conductive layer 110 and the fourth conductive layer 120 is determined according to the polarity of the doping region structure 11 and the third doping layer 90 , and is not specifically limited here.

[0123] Furthermore, in one embodiment of the present invention, the light-facing surface of the silicon substrate 10 is subjected to a texturing process before preparing the fourth dielectric layer 100, so that the morphology formed on the light-facing surface is but not limited to an alkali polished surface, a mechanically polished surface, a random pyramid, an inverted pyramid, a spherical crown, a V-groove, and a morphology between the above morphologies. At this time, the surface morphology formed on the light-facing surface of the silicon substrate 10 is beneficial to reducing the reflection of sunlight on the light-facing surface and improving the conversion efficiency of solar cells.

[0124] In this embodiment, a doping region structure 11 is provided to replace the passivation contact structure in the prior art, and the passivation layer 112 in the doping region structure is provided as a hole structure, and the hole region has an inner expansion layer 111 and / or a first doping layer 113, so that a conductive channel is formed in the hole region of the passivation layer 112, thereby forming a good resistivity for the passivation layer, which reduces the sensitivity of the passivation layer thickness to the resistance, thereby reducing the control requirements for the passivation layer thickness, so that the preparation method of the passivation layer can be more diverse than the prior art; at the same time, the inner expansion layer 111 is provided between the silicon substrate 10 and the passivation layer to form a The separation electric field of surface electrons and holes is enhanced, thereby improving the field passivation effect; at the same time, since the Fermi energy level of the inner expansion layer 111 is different from that of the silicon substrate 10, the inner expansion layer 111 changes the Fermi energy level, which increases the solid concentration of impurities (transition metals) and forms an additional impurity absorption effect; at the same time, the first doped layer 113 and the silicon substrate 10 in the hole structure are connected through the doped hole area and the first doped layer 113, which further reduces the overall resistance of the prepared battery, and ultimately improves the conversion efficiency of the battery, solving the problem that the precise thickness requirements of the existing tunneling layer make it difficult to produce and limit the conversion efficiency.

[0125] Example 6

[0126] This embodiment provides a battery assembly, characterized in that it includes the above-mentioned solar cell.

[0127] A battery module may include multiple solar cells. The multiple solar cells in the battery module can be connected in series in sequence to form a battery string. The battery strings can be connected in series, in parallel, or in a combination of series and parallel to achieve current convergence output. For example, the connection between the individual battery cells can be achieved by welding welding strips, and the connection between the individual battery strings can be achieved by bus bars.

[0128] The battery assembly may also include a metal frame, backsheet, photovoltaic glass, and adhesive film (not shown). The adhesive film can be filled between the light-facing side of the solar cell and the photovoltaic glass, the backlight side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the adhesive film can be EVA film or POE film. The specific choice can be based on actual conditions and is not limited here.

[0129] Photovoltaic glass covers the film on the light-facing side of the solar cell. This glass can be ultra-clear glass, which offers high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can have a light transmittance exceeding 92%, protecting the solar cell while minimizing its efficiency. The film also bonds the photovoltaic glass to the solar cell, providing a sealed, insulated, and moisture-proof seal.

[0130] The backsheet can be attached to the film on the backlight side of the solar cell. It provides protection and support for the solar cell, offering reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, organic glass, and aluminum alloy TPT composite film. The specific backsheet material can be configured based on specific circumstances and is not limited here. The backsheet, solar cell, film, and photovoltaic glass assembly can be mounted on a metal frame. The metal frame serves as the primary external support structure for the entire battery assembly and provides stable support and installation for the battery assembly. For example, the metal frame allows the battery assembly to be installed in the desired location.

[0131] The beneficial effects of the battery assembly of this embodiment are equivalent to the beneficial effects of the above-mentioned solar cell, and will not be described in detail here.

[0132] Example 7

[0133] This embodiment provides a photovoltaic system, characterized by including the above-mentioned battery assembly.

[0134] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water-surface power stations, etc. They can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is, photovoltaic systems can be used in all fields that require solar power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple battery modules. For example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box, which can combine the current generated by the photovoltaic array. The combined current flows through the inverter to be converted into the AC power required by the mains power grid and then connected to the mains power network to achieve solar power supply.

[0135] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of grooves; a doping region structure provided at least at a plurality of the grooves, the doping region structure comprising an inner expansion layer provided in the silicon substrate, and a passivation layer and a first doping layer provided in sequence on a backlight surface of the silicon substrate, the passivation layer having a plurality of hole structures; For at least a portion of the grooves, the number of the hole structures at positions corresponding to the edges of the grooves is greater than the number of the hole structures at positions corresponding to the middle of the grooves.

2. The solar cell according to claim 1, wherein At least part of the grooves has a groove bottom and an inclined groove wall, and the number of the hole structures at positions corresponding to the groove wall is greater than the number of the hole structures at positions corresponding to the groove bottom.

3. The solar cell according to claim 2, wherein Two adjacent groove walls have an intersection line, and the hole structure is provided at a position corresponding to the intersection line.

4. The solar cell according to claim 1, wherein The doping polarity of the inner extension layer and the first doping layer is the same.

5. The solar cell according to claim 1, wherein The plurality of grooves include N groove groups, and any one of the groove groups includes a plurality of grooves arranged in sequence, where N is a positive integer greater than or equal to 2.

6. The solar cell according to claim 5, wherein For at least two adjacent grooves in the groove group, the number of the hole structures at positions corresponding to the grooves closer to the light-facing surface is smaller than the number of the hole structures at positions corresponding to the grooves farther from the light-facing surface.

7. The solar cell according to claim 6, wherein Along the arrangement direction of the groove group, at least three grooves in the groove group are arranged in sequence, and the bottoms of at least three grooves gradually approach the light-facing surface.

8. The solar cell according to claim 1, wherein The backlight surface of the silicon substrate includes a groove area and a non-groove area, the groove is arranged in the groove area, and the non-groove area is provided with the doping region structure. For an adjacent non-groove area and an adjacent groove area, the number of the hole structures corresponding to the non-groove area is greater than the number of the hole structures corresponding to the groove area.

9. The solar cell according to claim 1, wherein The thickness of the passivation layer is 0.5 nm to 10 nm.

10. The solar cell according to claim 1, wherein The passivation layer is one or more combinations of an oxide layer, a silicon carbide layer and an amorphous silicon layer.

11. The solar cell according to claim 10, wherein The oxide layer is composed of one or more layers of a silicon oxide layer and an aluminum oxide layer.

12. The solar cell according to claim 1, wherein The doping concentration of the inner diffusion layer is between the doping concentration of the silicon substrate and the doping concentration of the first doping layer.

13. The solar cell according to any one of claims 1 to 12, wherein: include: First doping regions and second doping regions are alternately arranged on the backlight surface of the silicon substrate, wherein the polarities of the first doping regions are opposite to those of the second doping regions; A first dielectric layer provided on the light-facing surface of the silicon substrate; a second dielectric layer disposed between the first doped region and the second doped region; and a first conductive layer disposed on the first doping region and a second conductive layer disposed on the second doping region; The first doping region and / or the second doping region adopts the doping region structure.

14. The solar cell according to any one of claims 1 to 12, characterized in that: It includes a third doping region and a fourth doping region, the polarity of the third doping region is opposite to that of the fourth doping region, one of the third doping region and the fourth doping region is arranged on the light-facing side, and the other is arranged on the backlight side, and one or both of the third doping region and the fourth doping region adopt the doping region structure.

15. The solar cell according to claim 1, wherein The first doped layer is a doped polysilicon layer doped with group III or group V elements.

16. The solar cell according to claim 1, wherein The passivation layer forms a recessed structure at a position corresponding to the groove.

17. A battery assembly, characterized in that: The battery assembly includes the solar cell according to any one of claims 1 to 16.

18. A photovoltaic system, characterized in that: The photovoltaic system includes the battery assembly according to claim 17.

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