Multi-purpose low frequency eddy current array (ECA)

Abstract

Configurations of sensors or coil assemblies for performing eddy current (EC) tests are described. The sensor assembly may be manufactured using a printed circuit board (PCB) configuration, such as including a flex circuit including a dielectric layer and a metallization layer. Adjacent coil elements may include overlapping portions where the currents of the overlapping portions cancel each other, thereby conceptually creating larger coils, which may be used to support various receive or transmit configurations.

Description

[0001] Priority claim

[0002] This patent application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 63 / 477,655, filed on December 29, 2022, entitled “MULTI-PURPOSE LOW-FREQUENCYEDDY CURRENT ARRAY (ECA)” which is hereby incorporated by reference in its entirety. Technical Field

[0003] This document relates generally, but not by way of limitation, to apparatus and techniques for nondestructive inspection, such as facilitating eddy current inspection, and more particularly, to apparatus and techniques for providing an eddy current array (ECA) probe assembly including a printed circuit board (PCB) construction, such as one including a flex circuit. Background Art

[0004] Non-destructive testing (NDT) can refer to the use of one or more different techniques to inspect an area on or within an object, such as to determine the presence of flaws or defects, or to otherwise characterize the object being inspected. One type of non-destructive testing can include the use of eddy current testing methods, in which electromagnetic energy is applied to an object and the induced current generated on or within the object is detected, with the value of the detected current (or associated impedance) providing an indication of the structure of the object being inspected, such as to indicate the presence of cracks, voids, pores, or other inhomogeneities. Typically, an eddy current (EC) sensor includes one or more sensor elements, such as an induction coil that can be excited using an alternating current (AC) source. Such a coil (or other electromagnetic sensing element, such as a Hall sensor) can be used to receive a signal indicative of an induced eddy current on or within a structure. Summary of the Invention

[0005] Examples described herein relate to a coil array for eddy current (EC) inspection, comprising: a first coil; and a second coil positioned adjacent to the first coil. A first portion of the first coil overlaps a second portion of the second coil. The first portion of the first coil is configured to enable a first current to flow in a first direction, and the second portion of the second coil is configured to enable a second current to flow in a second direction, with the first and second directions being substantially opposite.

[0006] Examples described herein relate to a method for eddy current (EC) inspection, comprising: providing a first coil; providing a second coil positioned adjacent to the first coil, wherein a first portion of the first coil overlaps a second portion of the second coil; and activating the first and second coils, wherein a first current associated with the first portion of the first coil flows in a first direction and a second current associated with the second portion of the second coil flows in a second direction, the first and second directions being substantially opposite.

[0007] Examples described herein relate to a coil assembly for eddy current (EC) inspection, comprising: a first set of coil elements disposed on a first set of one or more layers of a printed circuit board (PCB); and a second set of coil elements disposed on a second set of one or more layers of the PCB. At least one coil element in the first set of coil elements overlaps at least one coil element in the second set of coil elements in an overlapping portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The subject matter of this disclosure may be better understood by referring to the following description in conjunction with the accompanying drawings. The accompanying drawings are not intended to limit the scope of the claims included herein. For the sake of clarity, not every component is labeled in every figure. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating examples, principles, and concepts. Therefore, the features and advantages of the present disclosure will become more apparent from the following detailed description of examples of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A A simplified block diagram of an example portion of a coil is shown;

[0010] Figure 1B A simplified block diagram showing an example portion of an overlapping coil configuration;

[0011] FIG1(C) shows a simplified trajectory diagram of an example portion of an overlapping coil configuration;

[0012] Figures 2A to 2H shows an example portion of an overlapping coil configuration on multiple layers of a PCB;

[0013] Figure 3 An example portion of a coil assembly array having an overlapping coil configuration is shown;

[0014] Figure 4 shows an example coil configuration for an array of coil assemblies for detecting longitudinal defects; and

[0015] Figure 5 An exemplary coil configuration of a coil assembly array 300 for detecting transverse defects is shown. DETAILED DESCRIPTION

[0016] A configuration of a sensor or coil assembly for performing eddy current (EC) testing is described. The sensor assembly can be manufactured using a printed circuit board (PCB) construction such as one including a flexible circuit comprising a dielectric layer and a metallization layer. The metallization layer can define or provide electrical connections to the coil elements, and such elements can be operated by a multiplexer assembly for both transmission and reception to support scans associated with different defect orientations. Adjacent coil elements can include overlapping portions, wherein the currents in the overlapping portions cancel each other, thereby conceptually creating a larger coil that can be used to support a variety of receive or transmit configurations.

[0017] Figure 1A A simplified block diagram of an example portion of coil 100 is shown. Coil 100 may have a width (w) parameter and a height (h) parameter. Coil 100 may include metallization layers, such as traces, and may be configured for use in EC testing. For example, coil 100 may be energized to generate electromagnetic energy for transmission into a test object, and coil 100 may receive an EC signal induced in the test object. For example, the EC signal may be used to detect various types of defects in the test object.

[0018] In some conventional systems, multiple coils (or coil elements) are arranged in arrays. In these arrays, there is usually space between adjacent coils. Such space between adjacent coils may lead to reduced sensitivity of EC examination.

[0019] Figure 1B A simplified block diagram of an example portion of an overlapping coil configuration is shown. The overlapping coil configuration may include a first coil 100 and a second coil 102 having an overlapping portion 104. The first coil 100 and the second coil 102 may have corresponding width (w) and height (h) parameters. In some examples, the first coil 100 and the second coil 102 may have the same width and height parameters.

[0020] First coil 100 and second coil 102 can be adjacent coils in an array, but without a space between them. Alternatively, the two coils can overlap with an overlap 104 having a width (o). Overlap 104 can include one or more sets of traces belonging to first coil 100 and one or more sets of traces belonging to second coil 102. The orientation of the corresponding traces in overlap 104 can result in opposing currents that cancel each other and produce a response from a substantially larger coil without overlap, which is the combination of first coil 100 and second coil 102. The width of the larger coil can be expressed as (w1) + (w2) – (o), where (w1) is the width of first coil 100, (w2) is the width of second coil 102, and (o) is the width of the overlap. If the two coils have the same width, the width of the larger coil can be expressed as 2(w) - (o).

[0021] FIG1(C) shows a simplified trace diagram of an example portion of an overlapping coil configuration. The first coil 100 includes a plurality of traces. For example, the first coil 100 may include one or more sets of traces disposed on one or more layers of a printed circuit board (PCB). The second coil 102 includes a plurality of traces. For example, the second coil 102 may include one or more sets of traces disposed on one or more layers of the PCB. The overlapping portion 104 may include portions of the traces for the first coil 100 and portions of the traces for the second coil 102, such that, in the overlapping portion 104, the current induced in the portion of the traces for the first coil 100 is in opposite directions to the current induced in the portion of the traces for the second coil 102. Therefore, the overlapping portion 104 may not contribute to the induced EC signal (or transmission) from the coils 100, 102, and the two coils 100, 102 may essentially function as one larger coil. In actual applications, during reception, little actual current may flow in the coils 100, 102 since the inputs may be high impedance, but the coils are configured in the manner described herein to act as a larger coil during reception, with the overlap 104 not contributing to the induced EC signal.

[0022] In some examples, one or more sets of traces for the first coil 100 can be provided on a first set of one or more (two, four, eight, etc.) layers of the PCB, while one or more sets of traces for the second coil can be provided on a second set of one or more layers of the PCB.

[0023] Figures 2A to 2HAn example portion of an overlapping coil configuration on multiple layers of a PCB is shown. Here, the PCB can include at least eight layers. Traces for the first coil 100 can be provided on layers 1, 4, 5, and 8 of the PCB, and traces for the second coil 102 can be provided on layers 2, 3, 6, and 7 of the PCB, as described in further detail below.

[0024] like Figure 2A As shown, a first set of traces 200 for a first coil (left coil) is provided (eg, fabricated) on a first layer of a PCB.

[0025] like Figure 2B As shown, a first set of traces 250 for the second coil (right coil) is disposed on the second layer of the PCB. Portions of the first set of traces 200 for the left coil overlap with portions of the first set of traces 250 for the right coil in an overlapping portion. For example, the overlapping portion of the first set of traces 200 for the left coil is associated with current in a first direction, and the overlapping portion of the first set of traces 250 for the right coil is associated with current in a second direction opposite to the first direction.

[0026] like Figure 2C As shown, the second set of traces 252 for the right coil is disposed on the third layer of the PCB. Portions of the second set of traces 252 for the right coil are disposed in the overlapping portion.

[0027] like Figure 2D As shown, the second set of traces 202 for the left coil is disposed on the fourth layer of the PCB. Portions of the second set of traces 202 for the left coil are disposed in the overlapping portion.

[0028] like Figure 2E As shown, the third set of traces 204 for the left coil is disposed on the fifth layer of the PCB. Portions of the third set of traces 204 for the left coil are disposed in the overlapping portion.

[0029] like Figure 2F As shown, the third set of traces 254 for the right coil is disposed on the sixth layer of the PCB. Portions of the third set of traces 254 for the right coil are disposed in the overlapping portion.

[0030] like Figure 2G As shown, the fourth set of traces 256 for the right coil is disposed on the seventh layer of the PCB. Portions of the fourth set of traces 256 for the right coil are disposed in the overlapping portion.

[0031] like Figure 2H As shown, the fourth set of traces 206 for the left coil is disposed on the eighth layer of the PCB. Portions of the fourth set of traces 206 for the left coil are disposed in the overlapping portion.

[0032] The current in the overlapping group of traces 200 to 206 for the left coil flows in a first direction, and the current in the overlapping group of traces 250 to 256 for the right coil flows in a second, opposite direction, canceling out the currents in the overlapping portion. Therefore, when activated, the group of traces 200 to 206 and the group of traces 250 to 256 can function as a larger coil for both transmission and reception for EC testing.

[0033] An overlapping coil configuration may be applied to an array of coil assemblies. Figure 3 An example portion of a coil assembly array 300 having an overlapping coil configuration is shown. The coil assembly array 300 may include a first row of coils 302.1 to 302.n (e.g., in this example, n=31). The coils 302.1 to 302.n may be arranged in an overlapping coil configuration as described herein. For example, coil 302.1 may overlap with adjacent coil 302.2, and coil 302.2 may overlap with adjacent coil 302.3, and coil 302.3 may overlap with adjacent coil 302.4, and so on. The coils 302.1 to 302.n may be arranged on multiple layers of a PCB. For example, odd-numbered coils (302.1, 302.3, 302.5, ...) may be arranged on a first set of layers of the PCB, and even-numbered coils (302.2, 302.4, 302.6, ...) may be arranged on a second set of layers of the PCB. Reference Figures 2A to 2H , odd-numbered coils ( 302 . 1 , 302 . 3 , 302 . 5 , . . . ) may be disposed on layers 1 , 4 , 5 , and 8 of the PCB, and even-numbered coils ( 302 . 2 , 302 . 4 , 302 . 6 , . . . ) may be disposed on layers 2 , 3 , 6 , and 7 of the PCB.

[0034] The coil assembly array 300 may include a second row of coils 304.1 to 304.n (e.g., in this example, n=31). The first row of coils and the second row of coils may be spaced apart by a distance. The coils 304.1 to 304.n may be arranged in an overlapping coil configuration as described herein. For example, coil 304.1 may overlap with an adjacent coil 304.2, and coil 304.2 may overlap with an adjacent coil 304.3, and coil 304.3 may overlap with an adjacent coil 304.4, and so on. The coils 304.1 to 304.n may be arranged on multiple layers of a PCB. For example, the odd-numbered coils (304.1, 304.3, 304.5, ...) may be arranged on a first set of layers of a PCB, and the even-numbered coils (304.2, 304.4, 304.6, ...) may be arranged on a second set of layers of a PCB. Reference Figures 2A to 2H, odd-numbered coils ( 304 . 1 , 304 . 3 , 304 . 5 , . . . ) may be disposed on layers 1 , 4 , 5 , and 8 of the PCB, and even-numbered coils ( 304 . 2 , 304 . 4 , 304 . 6 , . . . ) may be disposed on layers 2 , 3 , 6 , and 7 of the PCB.

[0035] The coil assembly array 300 with an overlapping coil configuration can be used to perform EC inspections in different transmit and receive configurations. Different configurations can be used to detect defects in different orientations. For example, different configurations using the overlapping coil configuration can be used to detect longitudinal defects and transverse defects.

[0036] Figure 4 An example coil configuration for coil assembly array 300 for detecting longitudinal defects is shown. In this example, coil 304.1 in the second row can be activated to transmit using first transmit region 402 during corresponding time slots. First transmit region 402 can include coil 304.1 to transmit signals for EC inspection. Coils 302.1 and 302.2 in the first row can be activated to receive EC signals using first receive region 404. First receive region 404 can include coils 302.1 and 302.2 sharing an overlapping portion with opposing currents, allowing first receive region 404 to function as a larger coil including coils 302.1 and 302.2, thereby increasing EC inspection sensitivity.

[0037] Additional coil sets may also be used in corresponding time slots. In this example, coil 304.18 in the second row may be activated to transmit using second transmit region 406 in the corresponding time slot. Second transmit region 406 may include coil 304.18. Coils 302.18 and 302.19 in the first row may be activated to receive EC signals using second receive region 408. Second receive region 408 may include coils 302.18 and 302.19 sharing an overlapping portion with opposing currents, allowing second receive region 408 to function as a larger coil including coils 302.18 and 302.19.

[0038] Figure 5An example coil configuration for coil assembly array 300 for detecting transverse defects is shown. In this example, coil 304.1 in the second row can be activated to transmit using first transmit region 502 during corresponding time slots. First transmit region 502 can include coil 304.1. Coils 304.3 and 304.4 in the second row can be activated to receive EC signals using first receive region 504. First receive region 504 can include coils 304.3 and 304.4 sharing an overlapping portion with opposing currents, allowing first receive region 504 to function as a larger coil including coils 304.3 and 304.4, thereby increasing EC inspection sensitivity.

[0039] Additional coil sets can also be used in corresponding time slots. In this example, coil 304.18 in the second row can be activated to transmit using second transmit region 506 in the corresponding time slot. Second transmit region 506 can include coil 304.18. Coils 304.20, 304.21 in the second row can be activated to receive EC signals using second receive region 508. Second receive region 508 can include coils 304.20, 304.21 that share an overlapping portion with opposing currents, allowing second receive region 508 to function as a larger coil including coils 304.20, 304.21, thereby increasing the sensitivity of EC inspection.

[0040] Processing (e.g., performing one or more methods described herein) can be implemented in hardware, software, or a combination of both. Processing can be implemented in a computer program executed on a programmable computer / machine, each of which includes a processor, a storage medium or other article of manufacture readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and one or more output devices. Program code can be applied to data entered using the input device to perform processing and generate output information. The memory may include a machine-readable medium having stored thereon one or more sets of data structures or instructions (e.g., software) implemented or utilized by any one or more of the techniques or functionality described herein.

[0041] In some embodiments, the system may be implemented by one or more programmable processors executing one or more computer programs to perform the functions of the system. In some other embodiments, all or part of the system may be implemented as a dedicated logic circuit system (e.g., a field programmable gate array (FPGA) and / or an application specific integrated circuit (ASIC)). In some other embodiments, all or part of the system may be implemented using, for example, the following electronic hardware circuit system: the electronic hardware circuit system includes an electronic device such as at least one of a processor, a memory, a programmable logic device, or a logic gate.

[0042] In one embodiment, the methods described herein are not limited to the specific examples described. In other embodiments, any of the method steps can be reordered, combined or removed as needed, or performed in parallel or serially to achieve the above results.

[0043] In some embodiments, the system can be implemented at least in part by a computer program product (e.g., in a non-transitory machine-readable storage medium such as, for example, a non-transitory computer-readable medium), which is executed by a data processing device (e.g., a programmable processor, a computer or a plurality of computers) or is used to control the operation of the data processing device. In some embodiments, each such program can be implemented with a high-level process or object-oriented programming language to communicate with the computer system. However, in some other embodiments, the program can be implemented with assembly or machine language. In some embodiments, the language can be a compiled language or an interpreted language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment. In some other embodiments, the computer program can be deployed to execute on a computer or on multiple computers, which are distributed at one site or across multiple sites and interconnected by a communication network.

[0044] The methods and apparatus of the present disclosure may take, at least in part, the form of program code (i.e., instructions) embodied in a tangible, non-transitory medium (e.g., a floppy disk, CD-ROM, hard drive, random access or read-only memory, or any other machine-readable storage medium). Figure 4 When the program code is stored in and executed by a computer machine, the machine becomes an apparatus for practicing the examples of the present subject matter. When implemented on one or more general-purpose processors, the program code combines with such processors to provide a unique apparatus that operates similarly to a specific logic circuit. In this way, a general-purpose digital machine can be converted into a special-purpose digital machine. In some other embodiments, the non-transitory machine-readable medium may include, but is not limited to, a hard drive, a compact disk, a flash memory, a non-volatile memory, a volatile memory, a magnetic disk, etc., but does not itself include a transient signal.

[0045] The term "machine-readable medium" or "machine-readable storage medium" may include any medium that can store, encode, or carry instructions for execution by a machine and that causes the machine to perform any one or more of the techniques of the present disclosure, or any medium that can store, encode, or carry data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. Thus, a machine-readable medium is not a transient propagating signal. Specific examples of high-capacity machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic or other phase-change or state-change memory circuits; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0046] Although the aforementioned examples have been described in some detail for the purpose of clear understanding, it is obvious that certain changes and modifications can be put into practice within the scope of the appended claims. The scope of the present invention is limited only by the claims, and the present invention includes many alternatives, modifications and equivalents. Many specific details have been set forth in the above description in order to provide a thorough understanding of the present invention. These details are provided for the purpose of example, and the present invention can be practiced according to the claims without some or all of these specific details. For the sake of clarity, technical materials known in the technical field related to the present invention are not described in detail so that the present invention will not be unnecessarily obscured. Therefore, the above implementation is considered to be illustrative rather than restrictive, and the present invention is not limited to the details given herein, but can be modified within the scope of the appended claims and their equivalents.

[0047] Various embodiments of the present disclosure have been described with reference to the accompanying drawings. It will be understood that these exemplary embodiments are provided solely to enable those skilled in the art to better understand and subsequently further implement the present disclosure, and are not intended to limit the scope of the present disclosure in any way. It should be noted that these drawings and descriptions are presented only as examples of embodiments, and based on this description, alternative embodiments having the structures and methods disclosed herein are contemplated, and such alternative embodiments may be used without departing from the principles of the present disclosure as claimed in the present disclosure.

[0048] It can be noted that the flow chart and block diagram in the figure can illustrate the device, method and architecture, function and operation that can be performed by computer program product according to the various embodiments of the present disclosure.In this regard, each frame in the flow chart or block diagram can represent a part for module, program segment or code, which can include one or more executable instructions for performing a specified logical function.It should also be noted that in some alternative implementations, the function indicated in the frame can occur in an order different from the order shown in the figure.For example, the two frames shown in succession can be performed substantially in parallel, or sometimes performed in reverse order, depending on the function involved.It should also be noted that each frame in the block diagram or flow chart and the combination of frames can be realized by a special-purpose, hardware-based system for performing a specified function or operation or by a combination of dedicated hardware and computer instructions.

[0049] As used herein, the terms "comprise," "include," their derivatives, and similar expressions should be construed as open ended (i.e., "includes / including, but not limited to"). The term "based on" means "based at least in part on," the term "one embodiment" means "at least one embodiment," and the term "another embodiment" means "at least one other embodiment." Relevant definitions of other terms are provided.

[0050] Herein, as is common in patent literature, the terms "a" or "an" are used to include one or more than one, regardless of any other instance or usage of "at least one" or "one or more." Herein, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B." Herein, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "comprising" and "wherein." In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, combinations, formulations, or processes that include elements in addition to those elements listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0051] The method examples described herein may be at least partially machine or computer-implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that can be operated to configure an electronic device to perform the method described in the above examples. The implementation of such a method may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form a part of a computer program product. In addition, in an example, such as during execution or at other times, the code may be tangibly stored on one or more volatile, non-transient, or non-volatile tangible computer-readable media. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact disks and digital video disks), cassettes, memory cards or memory sticks, random access memories (RAMs), read-only memories (ROMs), etc.

[0052] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects of the examples) can be used in combination with each other. For example, those of ordinary skill in the art can use other implementations after reading the above description. An abstract is provided to enable the reader to quickly determine the nature of the technical disclosure. The abstract is submitted with the following understanding: the abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above-mentioned specific embodiments, various features can be combined together to streamline the present disclosure. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are necessary for any claim. Instead, the subject matter of the invention may be less than all the features of a particular disclosed implementation. Therefore, the attached claims are incorporated into the detailed description as examples or implementations, wherein each claim exists independently as a separate implementation, and it is expected that such implementations can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A coil array for eddy current (EC) inspection, comprising: First coil; as well as a second coil positioned adjacent to the first coil; wherein a first portion of the first coil overlaps a second portion of the second coil, and The first portion of the first coil is configured to enable a first current to flow in a first direction, the second portion of the second coil is configured to enable a second current to flow in a second direction, and the first direction and the second direction are substantially opposite.

2. The coil array according to claim 1, wherein The first coil includes a first set of one or more traces disposed in a first set of one or more layers of a printed circuit board (PCB), wherein the second coil includes a second set of one or more traces disposed in a second set of one or more layers of the PCB.

3. The coil array according to claim 1 , further comprising: a third coil, said third coil being positioned adjacent to said second coil, wherein the third portion of the third coil overlaps with the fourth portion of the second coil, and The third portion of the third coil is configured to enable a third current to flow in the first direction.

4. The coil array according to claim 1, wherein: a first set of traces for the first coil disposed on a first layer of a printed circuit board (PCB); and A first set of traces for the second coil is disposed on a second layer of the PCB.

5. The coil array according to claim 4, wherein: a second set of traces for the second coil disposed on a third layer of the PCB; and A second set of traces for the first coil is disposed on a fourth layer of the PCB.

6. The coil array according to claim 5, wherein: a third set of traces for the first coil disposed on a fifth layer of the PCB; and A third set of traces for the second coil is disposed on a sixth layer of the PCB.

7. The coil array according to claim 6, wherein: a fourth set of traces for the second coil disposed on a seventh layer of the PCB; and A fourth set of traces for the second coil is disposed on an eighth layer of the PCB.

8. The coil array according to claim 1, wherein The first coil and the second coil are configured to be activated together to operate substantially as a larger coil for receiving EC signals.

9. The coil array according to claim 1, wherein: The first coil and the second coil are configured to operate together substantially as a larger coil to transmit at least one signal for EC inspection.

10. A method for eddy current (EC) inspection, comprising: Setting a first coil; providing a second coil positioned adjacent to the first coil, wherein a first portion of the first coil overlaps a second portion of the second coil; and The first coil and the second coil are activated, wherein a first current associated with a first portion of the first coil flows in a first direction and a second current associated with a second portion of the second coil flows in a second direction, the first direction and the second direction being substantially opposite.

11. The method according to claim 10, wherein: The first coil includes a first set of one or more traces disposed in a first set of one or more layers of a printed circuit board (PCB), wherein the second coil includes a second set of one or more traces disposed in a second set of one or more layers of the PCB.

12. The method according to claim 10, further comprising: providing a third coil positioned adjacent to the second coil, wherein a third portion of the third coil overlaps a fourth portion of the second coil; The third coil is activated, wherein a third current associated with a third portion of the third coil flows in the first direction.

13. The method according to claim 10, wherein: A first set of traces for the first coil is provided on a first layer of a printed circuit board (PCB); and A first set of traces for the second coil is disposed on a second layer of the PCB.

14. The method according to claim 13, wherein: a second set of traces for the second coil disposed on a third layer of the PCB; and A second set of traces for the first coil is disposed on a fourth layer of the PCB.

15. The method according to claim 14, wherein: a third set of traces for the first coil disposed on a fifth layer of the PCB; and A third set of traces for the second coil is disposed on a sixth layer of the PCB.

16. The method according to claim 15, wherein: a fourth set of traces for the second coil disposed on a seventh layer of the PCB; and A fourth set of traces for the second coil is disposed on an eighth layer of the PCB.

17. The method according to claim 10, wherein The first coil and the second coil are activated together for operating substantially as a larger coil for receiving EC signals.

18. The method according to claim 1, wherein The first coil and the second coil are activated together to operate substantially as a larger coil to transmit at least one signal for EC inspection.

19. A coil assembly for eddy current (EC) inspection: a first set of coil elements disposed on a first set of one or more layers of a printed circuit board (PCB); a second set of coil elements disposed on a second set of one or more layers of the PCB, in, At least one coil element of the first group of coil elements overlaps with at least one coil element of the second group of coil elements in an overlapping portion.

20. The coil assembly according to claim 19, wherein In the overlapping portion, a portion of at least one coil element of the first set of coil elements and a portion of at least one coil element of the second set of coil elements are configured to generate opposite currents.

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