Capacitor

Abstract

A capacitor according to an embodiment of the present invention comprises: a substrate including a plurality of through holes penetrating from a first surface to a second surface opposite to the first surface; the first electrode layer is arranged on the first surface and the second surface of the substrate and the inner walls of the plurality of through holes; the first dielectric layer is arranged on the first surface and the second surface of the substrate and the first electrode layer on the inner walls of the plurality of through holes; and a second electrode layer disposed on the first surface and the second surface of the substrate and the first dielectric layer on the inner walls of the plurality of through holes.

Description

Technical Field

[0001] An embodiment of the present invention relates to a capacitor. Background Art

[0002] Semiconductor packaging has been applied to various fields such as transportation, communications, and computers, and generally includes a printed circuit board, a semiconductor chip disposed on the printed circuit board, and passive components disposed on the printed circuit board. For example, the passive components may include resistors, inductors, capacitors, etc.

[0003] As semiconductor packaging continues to advance, the demand for high-performance, high-reliability, and ultra-small capacitors is growing. To meet these demands, silicon-based capacitors and anodic aluminum oxide (AAO)-based capacitors have been proposed. Silicon-based capacitors consist of an electrode layer, a dielectric layer, and an electrode layer stacked sequentially on a silicon substrate, while AAO-based capacitors consist of an electrode layer, a dielectric layer, and an electrode layer stacked sequentially on an AAO substrate.

[0004] In particular, as demands for reducing signal paths in semiconductor packages and reducing the size of semiconductor packages increase, there is a need for large-capacity capacitors that can be mounted within or under the semiconductor packages. Summary of the Invention

[0005] Technical issues

[0006] The present invention aims to provide an ultra-small and high-capacity capacitor.

[0007] Technical Solution

[0008] One aspect of the present invention provides a capacitor, comprising: a substrate, comprising a plurality of through holes extending from a first surface to a second surface, the second surface being a surface opposite to the first surface; a first electrode layer, disposed on the first and second surfaces of the substrate and the inner walls of the plurality of through holes; a first dielectric layer, disposed on the first electrode layer on the first and second surfaces of the substrate and the inner walls of the plurality of through holes; and a second electrode layer, disposed on the first dielectric layer on the first and second surfaces of the substrate and the inner walls of the plurality of through holes.

[0009] The substrate may include silicon or anodic aluminum oxide (AAO).

[0010] A width of each of the plurality of through holes may range from 10 nm to 1 μm.

[0011] The length of each of the plurality of through holes may range from 10 nm to 100 μm.

[0012] Each of the first and second electrode layers may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium tin.

[0013] The first dielectric layer may include SiO2, Si3N3, HfO2, ZrO2, Hf x Zr y O z and at least one of Al2O3.

[0014] The capacitor may further include a filler disposed on the second electrode layer on inner walls of the plurality of through-holes to fill the plurality of through-holes.

[0015] The filler may include Al2O3.

[0016] The capacitor may further include a first electrode pad connected to the first electrode layer and a second electrode pad connected to the second electrode layer.

[0017] The capacitor may further include an insulating layer disposed on the second electrode layer on the first surface of the substrate, wherein the insulating layer may include a first opening in which the first electrode pad is disposed and a second opening in which the second electrode pad is disposed, the insulating layer may extend along an edge of the first opening to the first dielectric layer, and the first dielectric layer may include a first hole corresponding to the first opening.

[0018] The capacitor may further include: a second dielectric layer disposed on the second electrode layer on the first and second surfaces of the substrate and the inner walls of the plurality of through holes; and a third electrode layer disposed on the second dielectric layer on the first and second surfaces of the substrate and the inner walls of the plurality of through holes.

[0019] The capacitor may further include a third electrode pad connected to the third electrode layer and an insulating layer disposed on the third electrode layer on the first surface of the substrate, wherein the insulating layer may include a first opening in which the first electrode pad is disposed, a second opening in which the second electrode pad is disposed, and a third opening in which the third electrode pad is disposed.

[0020] The insulating layer may extend to the second dielectric layer along an edge of the first opening, the second dielectric layer may include a first hole corresponding to the first opening, the second dielectric layer may extend to the first dielectric layer along an edge of the first hole, and the first dielectric layer may include a second hole corresponding to the first hole.

[0021] The insulating layer may extend to the second dielectric layer along an edge of the second opening, and the second dielectric layer may include a third hole corresponding to the second opening.

[0022] Beneficial effects

[0023] According to the embodiments of the present invention, an ultra-small high-capacity capacitor can be provided. In addition, according to the embodiments of the present invention, a capacitor with a simple manufacturing process, low cost and high reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a perspective view showing a capacitor according to an embodiment of the present invention.

[0025] Figure 2 is a perspective view showing a substrate included in a capacitor according to an embodiment of the present invention.

[0026] Figures 3 to 5 is a cross-sectional view showing a capacitor according to an embodiment of the present invention.

[0027] Figure 6 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0028] Figure 7 and Figure 8 A method of manufacturing a capacitor according to an embodiment of the present invention is shown.

[0029] Figure 9 and Figure 10 is a cross-sectional view showing a capacitor according to still another embodiment of the present invention. DETAILED DESCRIPTION

[0030] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] However, the technical spirit of the present invention is not limited to some embodiments to be described, but can be implemented in various forms, and one or more components of the embodiments can be selectively combined, replaced and used within the scope of the technical spirit of the present invention.

[0032] In addition, unless the context clearly and specifically defines otherwise, all terms (including technical and scientific terms) used herein may be interpreted as having the meanings commonly understood by those skilled in the art, and the meanings of general terms such as terms defined in general dictionaries will be interpreted in consideration of the contextual meanings of the relevant technology.

[0033] Furthermore, the terms used in the embodiments of the present invention are considered in a descriptive sense only and are not intended to limit the present invention.

[0034] In this specification, unless the context specifically indicates otherwise, the singular includes the plural, and in the case of describing "at least one (or one or more) of A, B and C", this may include at least one of all possible combinations of A, B and C.

[0035] Furthermore, in the description of the components of the present invention, terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used.

[0036] The terms are used only to distinguish components from one another, and the nature, order, etc. of the components are not limited by the terms.

[0037] In addition, when a first component is referred to as being "connected," "coupled," or "linked" to a second component, such description may include a case where the first component is directly connected, coupled, or linked to the second component and a case where the first component is connected, coupled, or linked to the second component via a third component disposed between the first and second components.

[0038] Furthermore, when a first component is described as being formed or disposed “on (above)” or “under (below)” a second component, such description includes both a case where the two components are formed or disposed in direct contact with each other and a case where one or more other components are formed or disposed between the two components. Furthermore, when a first component is described as being formed “on (above) or under (below)” a second component, such description includes a case where the first component is formed on the upper side or the lower side relative to the second component.

[0039] Hereinafter, when the embodiments are described in detail with reference to the accompanying drawings, the same or mutually corresponding components will be denoted by the same or corresponding reference numerals throughout the drawings, and redundant description will be omitted.

[0040] Figure 1 is a perspective view showing a capacitor according to an embodiment of the present invention, Figure 2 is a perspective view showing a substrate included in a capacitor according to an embodiment of the present invention, and Figures 3 to 5 is a cross-sectional view showing a capacitor according to an embodiment of the present invention.

[0041] refer to Figures 1 to 5 The capacitor 100 includes a substrate 110 , a first electrode layer 120 , a first dielectric layer 130 and a second electrode layer 140 .

[0042] like Figure 2 As shown, the substrate 110 includes a first surface 111, a second surface 112 opposite to the first surface 111, and a third surface 113 disposed between the first surface 111 and the second surface 112. The first surface 111, the second surface 112, and the third surface 113 may be referred to as an upper surface, a lower surface, and a side surface, respectively. As shown in the figure, the substrate 110 is formed in a hexahedral shape, but the present invention is not limited thereto. The substrate 110 may be formed in a cylindrical shape, an elliptical cylindrical shape, a prism shape, etc.

[0043] The substrate 110 may include a semiconductor material or a non-conductive material. For example, the substrate 110 may include silicon (Si) or anodized aluminum oxide (AAO), but is not limited thereto.

[0044] According to an embodiment of the present invention, the substrate 110 includes a plurality of through holes TH extending from the first surface 111 to the second surface 112. That is, the plurality of through holes TH extend from the first surface 111 to the second surface 112 of the substrate 110. In this case, at least some of the plurality of through holes TH may be parallel. For example, an imaginary line connecting the center of the first surface 111 and the center of the second surface 112 corresponding to one of the plurality of through holes TH may be parallel to an imaginary line connecting the center of the first surface 111 and the center of the second surface 112 corresponding to another of the plurality of through holes TH. Therefore, since an electrode layer of uniform thickness can be deposited on the inner walls of the plurality of through holes TH, a highly reliable capacitor can be obtained.

[0045] According to an embodiment of the present invention, the width of some of the plurality of through holes TH may range from 10 nm to 1 μm, preferably from 10 nm to 500 nm, and more preferably from 10 nm to 200 nm, and the length of each of the plurality of through holes TH may range from 10 nm to 100 μm, preferably from 50 nm to 10 μm, and more preferably from 100 nm to 5 μm. In this case, since the plurality of through holes TH penetrates the first surface 111 (i.e., the upper surface of the substrate 110) and the second surface 112 (i.e., the lower surface), the length of each of the plurality of through holes TH may be the same as the thickness of the substrate 110. When the width and length of each of the plurality of through holes TH are within this numerical range, the plurality of through holes TH can be easily formed in the substrate 110, and since an electrode layer of uniform thickness can be deposited on the inner walls of the plurality of through holes TH, a highly reliable capacitor can be obtained.

[0046] According to an embodiment of the present invention, the first electrode layer 120 is arranged on the substrate 110, the first dielectric layer 130 is arranged on the first electrode layer 120, the second electrode layer 140 is arranged on the first dielectric layer 130, the first electrode pad 150 is connected to the first electrode layer 120, and the second electrode pad 160 is connected to the second electrode layer 140.

[0047] The capacitance of the capacitor can be calculated according to the following formula 1.

[0048] [Equation 1]

[0049]

[0050] Here, C is the capacitance, ε is the dielectric constant, S is the area of the electrode layer, and d is the distance between the electrode layers. Therefore, it can be seen that capacitance increases with increasing the area of the electrode layer. According to an embodiment of the present invention, the area of the electrode layer is used to increase capacitance.

[0051] More specifically, if Figures 3 to 5As shown, the first electrode layer 120 is disposed on the first surface 111, the second surface 112, and the third surface 113 of the substrate 110, and the inner walls of the plurality of through holes TH. As described above, when the first electrode layer 120 is disposed on the second surface 112 and the third surface 113 of the substrate 110, and the first surface 111 and the inner walls of the plurality of through holes TH, the area of the first electrode layer 120 is increased, and thus the capacitance of the capacitor can be increased while maintaining the same volume.

[0052] In this case, the first electrode layer 120 may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium tin. For example, the first electrode layer 120 may include TiN, TiO2, MoO x , WO x , indium tin oxide (ITO), and indium tin gallium oxide (ITGO), where x is a positive integer. The thickness of the first electrode layer 120 can range from 1 to 50 nm, preferably from 1 to 40 nm, and more preferably from 1 to 30 nm. When the material and thickness of the first electrode layer 120 meet these conditions, the first electrode layer 120 with uniform thickness can be easily deposited on the substrate 110, and a capacitor with high response speed and high performance can be obtained.

[0053] Next, the first dielectric layer 130 is disposed on the first electrode layer 120 on the first surface 111, the second surface 112, the third surface 113, and the inner walls of the plurality of through holes TH of the substrate 110. As described above, when the first dielectric layer 130 is disposed on the second surface 112, the third surface 113, the first surface 111, and the inner walls of the plurality of through holes TH of the substrate 110, the capacitance of the capacitor can be increased while maintaining the same volume.

[0054] In this case, the first dielectric layer 130 may include SiO2, Si3N3, HfO2, ZrO2, Hf x Zr y O z At least one of Al 2 O 3 and Al 2 O 3 , where x, y, and z are positive integers. When the material of the first dielectric layer 130 satisfies this condition, the first dielectric layer 130 with a uniform thickness can be easily deposited on the first electrode layer 120 .

[0055] The thickness of the first dielectric layer 130 may range from 1 to 50 nm, preferably from 1 to 40 nm, more preferably from 1 to 20 nm, and even more preferably from 1 to 15 nm. For example, the thickness of the first dielectric layer 130 may be less than the thickness of the first electrode layer 120. When the thickness of the first dielectric layer 130 meets these conditions, the capacitance of the capacitor can be increased while maintaining the same volume.

[0056] Next, the second electrode layer 140 is disposed on the first dielectric layer 130 on the first surface 111, the second surface 112, and the third surface 113 of the substrate 110 and the inner walls of the plurality of through holes TH. As described above, when the second electrode layer 140 is disposed on the second surface 112 and the third surface 113 of the substrate 110 and the first surface 111 and the inner walls of the plurality of through holes TH, the area of the second electrode layer 140 is increased, and thus the capacitance of the capacitor can be increased while maintaining the same volume.

[0057] In this case, the second electrode layer 140 may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium tin. For example, the second electrode layer 140 may include TiN, TiO2, MoO x , WO x , at least one of ITO and ITGO, where x is a positive integer. The thickness of the second electrode layer 140 can range from 1 to 50 nm, preferably from 1 to 40 nm, and more preferably from 1 to 30 nm. When the material and thickness of the second electrode layer 140 meet these conditions, the second electrode layer 140 with uniform thickness can be easily deposited on the first dielectric layer 130, and a capacitor with high response speed and high performance can be obtained.

[0058] The material of the second electrode layer 140 may be the same as that of the first electrode layer 120 , but is not limited thereto. That is, the material of the second electrode layer 140 may be different from that of the first electrode layer 120 .

[0059] According to an embodiment of the present invention, Figure 3 As shown, the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 are sequentially stacked on the inner wall of the through hole TH of the substrate 110. In this case, the second electrode layer 140 on one side of the inner wall of the through hole TH can be arranged to be spaced apart from the second electrode layer 140 on the other side of the same inner wall of the through hole TH. In other words, a through hole TH_C corresponding to the through hole TH of the substrate 110 can be formed in the capacitor 100, and the width of the through hole TH_C of the capacitor 100 can be smaller than the width of the through hole TH of the substrate 110.

[0060] Or, as Figure 4As shown, the second electrode layer 140 on one side of the inner wall of the through hole TH is spaced apart from the second electrode layer 140 on the other side of the same inner wall of the through hole TH. A through hole TH_C corresponding to the through hole TH of the substrate 110 is formed in the capacitor 100, and the through hole TH_C of the capacitor 100 can be filled with a filler 170. In this case, the filler 170 can be a material having insulating properties and a thermal expansion coefficient smaller than that of the second electrode layer 140. For example, the filler 170 can include Al2O3. Therefore, even if the temperature of the capacitor 100 increases, the internal portion of the through hole TH_C of the capacitor 100 does not thermally expand, thereby achieving a highly reliable capacitor 100.

[0061] Or, as Figure 5 As shown, the second electrode layer 140 on one side of the inner wall of the through hole TH may also be provided to contact the second electrode layer 140 on the other side of the same inner wall of the through hole TH. Therefore, since the total resistance of the capacitor 100 is reduced, a capacitor with a high response speed can be obtained.

[0062] Meanwhile, the example in which the first electrode layer 120, the first dielectric layer 130 and the second electrode layer 140 are sequentially stacked on the substrate 110 is mainly described, but the present invention is not limited thereto. According to an embodiment of the present invention, dielectric layers and electrode layers may be further alternately arranged on the second electrode layer 140.

[0063] Figure 6 1 is a cross-sectional view showing a capacitor according to another embodiment of the present invention. Figures 1 to 5 Repeated description of the same content.

[0064] refer to Figure 6 The second dielectric layer 180 is disposed on the second electrode layer 140 on the first surface 111, the second surface 112, and the third surface 113 of the substrate 110 and the inner walls of the plurality of through holes TH. As described above, when the second dielectric layer 180 is disposed on the second surface 112 and the third surface 113 of the substrate 110 and the first surface 111 and the inner walls of the plurality of through holes TH, the capacitance of the capacitor can be increased while maintaining the same volume.

[0065] In this case, the second dielectric layer 180 may include SiO2, Si3N3, HfO2, ZrO2, Hf x Zr y O z and Al 2 O 3 , where x, y, and z are positive integers. When the material of the second dielectric layer 180 satisfies this condition, the second dielectric layer 140 can be easily deposited on the second electrode layer 140 with a uniform thickness.

[0066] The thickness of the second dielectric layer 180 may range from 1 to 50 nm, preferably from 1 to 40 nm, more preferably from 1 to 20 nm, and even more preferably from 1 to 15 nm. For example, the thickness of the second dielectric layer 180 may be less than the thickness of the second electrode layer 140. When the thickness of the second dielectric layer 180 meets these conditions, the capacitance of the capacitor can be increased while maintaining the same volume.

[0067] Next, the third electrode layer 190 is disposed on the second dielectric layer 180 on the first surface 111, the second surface 112, and the third surface 113 of the substrate 110, and the inner walls of the plurality of through holes TH. As described above, when the third electrode layer 190 is disposed on the second surface 112 and the third surface 113 of the substrate 110, and the first surface 111 and the inner walls of the plurality of through holes TH, the area of the third electrode layer 190 is increased, and thus the capacitance of the capacitor can be increased while maintaining the same volume.

[0068] In this case, the third electrode layer 190 may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium tin. For example, the third electrode layer 190 may include TiN, TiO2, MoO x , WO x , at least one of ITO and ITGO, where x is a positive integer. The thickness of the third electrode layer 190 may range from 1 to 50 nm, preferably from 1 to 40 nm, and more preferably from 1 to 30 nm. When the material and thickness of the third electrode layer 190 meet these conditions, a third electrode layer 190 of uniform thickness can be easily deposited on the second dielectric layer 180, and a capacitor with high response speed and high performance can be obtained.

[0069] The material of the third electrode layer 190 may be the same as that of the first electrode layer 120 and the second electrode layer 140 , but is not limited thereto.

[0070] Figure 7 and Figure 8 A method of manufacturing a capacitor according to an embodiment of the present invention is shown.

[0071] refer to Figure 7 A. Prepare an aluminum substrate. In this case, the aluminum substrate may have an aluminum content of 90% or more, preferably an aluminum content of 99% or more, and more preferably an aluminum content of 99.999% or more. In this case, the aluminum substrate may have a rough surface.

[0072] refer to Figure 7 B. Electrochemical polishing is performed on the surface of the aluminum substrate. Thus, the surface of the aluminum substrate can be flattened.

[0073] refer to Figure 7 C. A first anodizing process is performed on the flattened surface of the aluminum substrate. Thus, AAO can be grown on the aluminum substrate. In this case, AAO can be grown using a wet process. Thus, AAO having pores of a predetermined width can be grown on the aluminum substrate. In this case, the AAO grown using the first anodizing process may be uneven.

[0074] refer to Figure 7 D, AAO on the aluminum substrate was removed by wet etching.

[0075] refer to Figure 7 E. A second anodization process is performed on the aluminum substrate from which the AAO grown in the first anodization process has been removed. As a result, the AAO grown on the aluminum substrate can be more uniform than the AAO grown in the first anodization process. In this case, the pore size, AAO length, and other factors can be adjusted by controlling the solvent, temperature, time, and voltage of the second anodization process.

[0076] refer to Figure 7 F, The aluminum substrate is removed by wet etching.

[0077] refer to Figure 7 G, The lower portion of the AAO, i.e., the area in contact with the aluminum substrate, was removed by wet etching.

[0078] Therefore, reference Figure 7 H, a substrate 110 including a plurality of through holes TH penetrating from the first surface 111 to the second surface 112 can be obtained.

[0079] Next, refer to Figure 8 A, a first electrode layer 120 is deposited on the substrate 110. The first electrode layer 120 can be deposited using an atomic layer deposition (ALD) process. When the ALD process is used, the material of the first electrode layer 120 can be conformally deposited on the surface of the substrate 110 in units of atoms. Therefore, the first electrode layer 120 can be uniformly deposited on the second surface 112 and the third surface 113 of the substrate 110, as well as the first surface 111 and the inner wall of the through hole TH.

[0080] Next, refer to Figure 8 B. A first dielectric layer 130 is deposited on the first electrode layer 120. The first dielectric layer 130 can be deposited using an ALD process. Thus, the material of the first dielectric layer 130 can be conformally deposited on the surface of the first electrode layer 120 in atomic units. Thus, the first dielectric layer 130 can be deposited on the second surface 112 and the third surface 113 of the substrate 110, as well as on the first surface 111 and the inner wall of the through hole TH.

[0081] Next, refer to Figure 8 C. The second electrode layer 140 is deposited on the first dielectric layer 130. The second electrode layer 140 can be deposited using an ALD process. Therefore, the material of the second electrode layer 140 can be conformally deposited on the surface of the first dielectric layer 130 in atomic units. Therefore, the second electrode layer 140 can be deposited on the second surface 112 and the third surface 113 of the substrate 110, as well as the first surface 111 and the inner wall of the through hole TH.

[0082] Next, refer to Figure 8 D, the first electrode pad 150 is connected to the first electrode layer 120, and the second electrode pad 160 is connected to the second electrode layer 140. In order to connect the first electrode pad 150 to the first electrode layer 120, the second electrode layer 140 and the first dielectric layer 130 may be etched. In addition, the first electrode pad 150 and the second electrode pad 160 may be deposited by sputtering.

[0083] In this case, a method of manufacturing a capacitor in which the substrate includes AAO is mainly described, but embodiments of the present invention are not limited thereto. The capacitor according to an embodiment of the present invention may be a silicon-based capacitor in which the substrate includes silicon.

[0084] Figure 9 and Figure 10 1 is a cross-sectional view showing a capacitor according to another embodiment of the present invention. Figures 1 to 8 Repeated description of the same content.

[0085] refer to Figure 9 The capacitor 100 includes a substrate 110, a first electrode layer 120 disposed on the substrate 110, a first dielectric layer 130 disposed on the first electrode layer 120, a second electrode layer 140 disposed on the first dielectric layer 130, a first electrode pad 150 connected to the first electrode layer 120, and a second electrode pad 160 connected to the second electrode layer 140.

[0086] According to an embodiment of the present invention, in order to arrange first electrode pad 150 and second electrode pad 160, capacitor 100 further includes insulating layer 200 disposed on second electrode layer 140 on first surface 111 of substrate 110. As shown, insulating layer 200 may extend into through hole TH to serve as filler 170.

[0087] Insulating layer 200 includes a first opening 200C1 and a second opening 200C2 above second electrode layer 140 on first surface 111 of substrate 110. First electrode pad 150 may be disposed in first opening 200C1, and second electrode pad 160 may be disposed in second opening 200C2. Thus, second electrode pad 160 disposed in second opening 200C2 may be connected to second electrode layer 140. To connect first electrode pad 150 disposed in first opening 200C1 to first electrode layer 120, insulating layer 200 may extend along an edge of first opening 200C1 to first dielectric layer 130, and first dielectric layer 130 may include a first hole 130C1 corresponding to first opening 200C1. Thus, first electrode pad 150 may be connected to first electrode layer 120.

[0088] When the first electrode pad 150 and the second electrode pad 160 are arranged according to the above structure, the upper surfaces of the first electrode pad 150 and the second electrode pad 160 can be arranged to have the same height. Therefore, when the capacitor 100 according to the embodiment of the present invention is mounted on a printed circuit board, since there is no need to additionally adjust the heights of the first electrode pad 150 and the second electrode pad 160, the assembly process can be improved, and the bonding force between the first electrode pad 150 and the second electrode pad 160 and the printed circuit board can be increased.

[0089] refer to Figure 10 The capacitor 100 includes a substrate 110, a first electrode layer 120 disposed on the substrate 110, a first dielectric layer 130 disposed on the first electrode layer 120, a second electrode layer 140 disposed on the first dielectric layer 130, a second dielectric layer 180 disposed on the second electrode layer 140, a third electrode layer 190 disposed on the second dielectric layer 180, a first electrode pad 150 connected to the first electrode layer 120, a second electrode pad 160 connected to the second electrode layer 140, and a third electrode pad 165 connected to the third electrode layer 190.

[0090] According to an embodiment of the present invention, in order to arrange first electrode pad 150, second electrode pad 160, and third electrode pad 165, capacitor 100 further includes insulating layer 200 disposed on third electrode layer 190 on first surface 111 of substrate 110. As shown in the figure, insulating layer 200 may extend into through hole TH to serve as filler 170.

[0091] Insulating layer 200 includes a first opening 200C1, a second opening 200C2, and a third opening 200C3 in third electrode layer 190 on first surface 111 of substrate 110. First electrode pad 150 may be disposed in first opening 200C1, second electrode pad 160 may be disposed in second opening 200C2, and third electrode pad 165 may be disposed in third opening 200C3. Thus, third electrode pad 165 disposed in third opening 200C3 may be connected to third electrode layer 190.

[0092] To connect first electrode pad 150 disposed in first opening 200C1 to first electrode layer 120, insulating layer 200 may extend along the edge of first opening 200C1 to second dielectric layer 180, and second dielectric layer 180 may include first hole 180C1 corresponding to first opening 200C1. Furthermore, second dielectric layer 180 may extend along the edge of first hole 180C1 to first dielectric layer 130, and first dielectric layer 130 may include second hole 130C1 corresponding to first hole 180C1. Thus, first electrode pad 150 may be connected to first electrode layer 120.

[0093] To connect second electrode pad 160 disposed in second opening 200C2 to second electrode layer 140, insulating layer 200 may extend along an edge of second opening 200C2 to second dielectric layer 180, and second dielectric layer 180 may include a third hole 180C2 corresponding to second opening 200C2. Thus, second electrode pad 160 may be connected to second electrode layer 140.

[0094] When the first electrode pad 150, the second electrode pad 160, and the third electrode pad 165 are arranged according to the above structure, the upper surfaces of the first electrode pad 150, the second electrode pad 160, and the third electrode pad 165 can be arranged to have the same height. Therefore, when the capacitor 100 according to the embodiment of the present invention is mounted on a printed circuit board, since there is no need to additionally adjust the heights of the first electrode pad 150, the second electrode pad 160, and the third electrode pad 165, the assembly process can be improved, and the bonding force between the first electrode pad 150, the second electrode pad 160, and the third electrode pad 165 and the printed circuit board can be increased.

[0095] While the present invention has been described above with reference to exemplary embodiments, it will be understood by those skilled in the art that various modifications and variations may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A capacitor comprising: a substrate comprising a plurality of through holes extending from a first surface to a second surface, the second surface being a surface opposite to the first surface; a first electrode layer, disposed on the first surface and the second surface of the substrate and inner wall surfaces of the plurality of through holes; a first dielectric layer disposed on the first surface and the second surface of the substrate and the first electrode layer on the inner wall surfaces of the plurality of through holes; as well as The second electrode layer is disposed on the first surface and the second surface of the substrate and the first dielectric layer on the inner wall surfaces of the plurality of through holes.

2. The capacitor according to claim 1, wherein The substrate includes silicon or anodic aluminum oxide (AAO).

3. The capacitor according to claim 1, wherein A width of each of the plurality of through holes ranges from 10 nm to 1 μm.

4. The capacitor according to claim 1, wherein A length of each of the plurality of through holes ranges from 10 nm to 100 μm. 5 . The capacitor according to claim 1 , further comprising a filler provided on the second electrode layer on inner wall surfaces of the plurality of through holes to fill the plurality of through holes. The capacitor according to claim 5 , wherein: The filler includes Al2O3.

7. The capacitor according to claim 1, further comprising: a first electrode pad connected to the first electrode layer; as well as The second electrode pad is connected to the second electrode layer.

8. The capacitor according to claim 7, further comprising an insulating layer provided on the second electrode layer on the first surface of the substrate, in, The insulating layer includes a first opening in which the first electrode pad is disposed and a second opening in which the second electrode pad is disposed, The insulating layer extends along the edge of the first opening to the first dielectric layer, and The first dielectric layer includes a first hole corresponding to the first opening.

9. The capacitor according to claim 7, further comprising: a second dielectric layer disposed on the first surface and the second surface of the substrate and on the second electrode layer on the inner wall surfaces of the plurality of through holes; as well as The third electrode layer is disposed on the first surface and the second surface of the substrate and the second dielectric layer on the inner wall surfaces of the plurality of through holes.

10. The capacitor of claim 9, further comprising: a third electrode pad connected to the third electrode layer; as well as an insulating layer disposed on the third electrode layer on the first surface of the substrate, The insulating layer includes a first opening in which the first electrode pad is disposed, a second opening in which the second electrode pad is disposed, and a third opening in which the third electrode pad is disposed.

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