Semiconductor device

Abstract

This semiconductor device is provided with: a SiC chip having a first main surface and a second main surface; an element structure formed on the first main surface; and an electrode formed on the second main surface and electrically connected to the element structure. The arithmetic average roughness (Ra) of the second main surface is 30 nm or more. As a result, a low-resistance ohmic contact can be formed on the second main surface on the opposite side from the element structure.

Description

[0001] Related applications

[0002] This application corresponds to Japanese Patent Application No. 2023-004565 filed with the Japan Patent Office on January 16, 2023, and Japanese Patent Application No. 2024-001479 filed with the Japan Patent Office on January 9, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] For example, Patent Document 1 discloses a SiC semiconductor device having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, and including: a SiC semiconductor layer having a first main surface (element forming surface) formed by the SiC epitaxial layer, and side surfaces formed by the SiC semiconductor substrate and the SiC epitaxial layer; and modified lines formed on the side surfaces at a distance from the SiC epitaxial layer in a portion constituted by the SiC semiconductor substrate, and modified to have properties different from those of the SiC semiconductor substrate.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-166265 Summary of the Invention

[0008] A semiconductor device according to one embodiment of the present disclosure includes: a SiC chip having a first main surface and a second main surface; an element structure formed on the first main surface; and an electrode formed on the second main surface and electrically connected to the element structure, wherein the arithmetic mean roughness (Ra) of the second main surface is greater than 30 nm.

[0009] According to a semiconductor device according to one embodiment of the present disclosure, the arithmetic mean roughness (Ra) of the second principal surface of the SiC chip is 30 nm or greater, thereby increasing the contact area between the SiC chip and the electrode. Consequently, a semiconductor device can be provided that forms a low-resistance ohmic contact on the second principal surface opposite the element structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 1 is a diagram showing a unit cell of a 4H-SiC single crystal applicable to an embodiment of the present disclosure.

[0011] Figure 2 Yes Figure 1 Top view of the silicon surface of the unit cell of 4H-SiC single crystal.

[0012] Figure 3 It is a schematic perspective view of a semiconductor device according to the first embodiment of the present disclosure.

[0013] Figure 4 yes Figure 3 Schematic top view of a semiconductor device.

[0014] Figure 5 It is along Figure 4 Cross-sectional view of line VV.

[0015] Figure 6 yes Figure 5 An enlarged view of region VI is shown.

[0016] Figure 7 It is a schematic top view of a semiconductor device according to a second embodiment of the present disclosure.

[0017] Figure 8 It is along Figure 7 A cross-sectional view taken along line VIII-VIII.

[0018] Figure 9 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure.

[0019] Figure 10 4 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure.

[0020] Figure 11 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure.

[0021] Figure 12 A perspective view of a semiconductor wafer used to manufacture semiconductor devices.

[0022] Figure 13A It is a diagram showing a part of the manufacturing process of the above-mentioned semiconductor device.

[0023] Figure 13B Yes Figure 13A The diagram of the next process.

[0024] Figure 13C Yes Figure 13B The diagram of the next process.

[0025] Figure 13D Yes Figure 13C The diagram of the next process.

[0026] Figure 13E Yes Figure 13D The diagram of the next process.

[0027] Figure 14This is a diagram showing a first shape (quadrilateral) of a laser mark formed on the back surface of a chip.

[0028] Figure 15 It is a diagram showing a second shape (circle) of the laser mark formed on the back surface of the chip.

[0029] Figure 16 This is a photographic image showing a first shape (a quadrilateral) of a laser mark formed on the back surface of a chip.

[0030] Figure 17 This is a photographic image showing the second shape (circle) of the laser mark formed on the back surface of the chip.

[0031] Figure 18 This is a photographic image showing a modified example of the first shape (quadrilateral) of the laser marks formed on the back surface of the chip.

[0032] Figure 19 This is a photographic image showing a modified example of the second shape (circular) of the laser mark formed on the back surface of the chip.

[0033] Figure 20 This is a diagram showing a third shape (quadrilateral) of the laser marks formed on the back surface of the chip.

[0034] Figure 21 This is a diagram showing a fourth shape (quadrilateral) of the laser marks formed on the back surface of the chip.

[0035] Figure 22 It is a diagram showing a fifth shape (circle) of the laser mark formed on the back surface of the chip.

[0036] Figure 23 Graphs showing the contact resistance distribution on the wafer back surface of Sample 1 and the state of the wafer back surface.

[0037] Figure 24 Graphs showing the contact resistance distribution on the wafer back surface of Sample 2 and the state of the wafer back surface. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] [Crystal structure of SiC single crystal]

[0040] In the embodiments of the present disclosure, hexagonal SiC (silicon carbide) single crystals are used. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals, depending on the periodicity of the atomic arrangement. While the embodiments of the present disclosure describe an example using 4H-SiC single crystals, other polymorphs are not excluded from the present disclosure.

[0041] Hereinafter, the crystal structure of 4H-SiC single crystal will be described. Figure 1 1 is a diagram illustrating a unit cell of a 4H-SiC single crystal (hereinafter, simply referred to as a “unit cell”) applied to an embodiment of the present disclosure. Figure 2 Yes Figure 1 A top view of the silicon surface of the unit cell is shown.

[0042] Reference Figure 1 as well as Figure 2 The unit cell comprises a tetrahedral structure in which four carbon atoms are bonded to one silicon atom in a tetrahedral arrangement (a regular tetrahedral arrangement). The unit cell has an atomic arrangement in which a tetrahedral structure is stacked four times. The unit cell has a hexagonal prism structure having a regular hexagonal silicon face, a regular hexagonal carbon face, and six side faces connecting the silicon face and the carbon face.

[0043] A silicon face is a terminal face terminated by Si atoms. In a silicon face, one Si atom is located at each of the six vertices of a regular hexagon and one Si atom is located at the center of the regular hexagon.

[0044] A carbon face is a terminal face terminated by carbon atoms. In a carbon face, one carbon atom is located at each of the six vertices of a regular hexagon and one carbon atom is located at the center of the regular hexagon.

[0045] The crystal planes of a unit cell are defined by four coordinate axes (a1, a2, a3, c): the a1-axis, the a2-axis, the a3-axis, and the c-axis. The value of a3 among the four coordinate axes is -(a1 + a2). The following description of the crystal planes of a 4H-SiC single crystal is based on the silicon plane, an example of a hexagonal terminal face.

[0046] The a1-axis, a2-axis, and a3-axis are defined along the direction of the closest Si atom arrangement (hereinafter referred to as the "closest atom direction"), with the central Si atom as the reference in a top view of the silicon surface viewed from the c-axis. The a1-axis, a2-axis, and a3-axis are each defined at an angle of 120°, mimicking the arrangement of Si atoms.

[0047] The c-axis is set in the normal direction of the silicon surface, with the central Si atom as the reference. The silicon surface is the (0001) plane, and the carbon surface is the (000-1) plane.

[0048] In a top view of the silicon surface from the c-axis, the side surface of the hexagonal prism includes six crystal planes along the direction of the closest atoms. More specifically, in a top view of the silicon surface from the c-axis, the side surface of the hexagonal prism includes six crystal planes each including the two closest Si atoms.

[0049] In a plan view of the silicon surface viewed from the c-axis, the side surfaces of the hexagonal prism include the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane in clockwise order from the tip of the a1 axis.

[0050] In a top view of the silicon surface from the c-axis, the diagonal planes along the diagonal lines of the hexagonal prism include six crystal planes along a direction intersecting the closest atomic direction. More specifically, the diagonal planes of the hexagonal prism include six crystal planes each including two Si atoms that are not closest to each other in a top view of the silicon surface from the c-axis. When viewed with the Si atom at the center as a reference, the direction intersecting the closest atomic direction is an orthogonal direction perpendicular to the closest atomic direction.

[0051] In a top view of the silicon surface viewed from the c-axis, the diagonal planes of the hexagonal prism include the (11-20) plane, the (1-210) plane, the (-2110) plane, the (-1-120) plane, the (-12-10) plane, and the (2-1-10) plane.

[0052] The crystal orientation of a unit cell is defined by the direction of the normal to the crystal plane. The normal to the (1-100) plane is the [1-100] direction. The normal to the (0-110) plane is the [0-110] direction. The normal to the (-1010) plane is the [-1010] direction. The normal to the (-1100) plane is the [-1100] direction. The normal to the (01-10) plane is the [01-10] direction. The normal to the (10-10) plane is the [10-10] direction.

[0053] The normal direction of the (11-20) plane is [11-20]. The normal direction of the (1-210) plane is [1-210]. The normal direction of the (-2110) plane is [-2110]. The normal direction of the (-1-120) plane is [-1-120]. The normal direction of the (-12-10) plane is [-12-10]. The normal direction of the (2-1-10) plane is [2-1-10].

[0054] Hexagonal crystals have six-fold symmetry, with equivalent crystal planes and directions occurring every 60°. For example, the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane form equivalent crystal planes.

[0055] In addition, the [1-100] direction, the [0-110] direction, the [-1010] direction, the [-1100] direction, the [01-10] direction, and the [10-10] direction form equivalent crystal directions. In addition, the [11-20] direction, the [1-210] direction, the [-2110] direction, the [-1-120] direction, the [-12-10] direction, and the [2-1-10] direction form equivalent crystal directions.

[0056] The c-axis is in the

[0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

[0057] The (0001) plane and the (000-1) plane are collectively referred to as the c-plane. The

[0001] direction and the [000-1] direction are collectively referred to as the c-axis. The (11-20) plane and the (-1-120) plane are collectively referred to as the a-plane. The [11-20] direction and the [-1-120] direction are collectively referred to as the a-axis. The (1-100) plane and the (-1100) plane are collectively referred to as the m-plane. The [1-100] direction and the [-1100] direction are collectively referred to as the m-axis.

[0058] [Semiconductor Device 1A of First Embodiment]

[0059] Figure 3 This is a perspective view of the semiconductor device 1A according to the first embodiment of the present disclosure as viewed from one angle. Figure 4 yes Figure 3 FIG. 1 is a top view of a semiconductor device 1A shown in FIG. Figure 5 It is along Figure 4 A cross-sectional view taken along line VV is shown.

[0060] Reference Figures 3 to 5 In this embodiment, semiconductor device 1A is a SiC semiconductor device and includes a SiC semiconductor layer 2. SiC semiconductor layer 2 includes 4H-SiC single crystal, which is an example of a hexagonal SiC single crystal. SiC semiconductor layer 2 is formed into a rectangular parallelepiped chip.

[0061] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed into a quadrilateral (a square in this embodiment) in a plan view (hereinafter simply referred to as "plan view") viewed from the normal direction Z thereof.

[0062] First principal surface 3 is the element-forming surface on which the semiconductor element is formed. Second principal surface 4 of SiC semiconductor layer 2 is a ground surface having grinding marks. Side surfaces 5A to 5D are each a smooth cleavage surface facing the crystal plane of the SiC single crystal. Side surfaces 5A to 5D do not have grinding marks.

[0063] The thickness TL of the SiC semiconductor layer 2 can be 50 μm to 350 μm. The thickness TL can be 80 μm to 350 μm, 100 μm to 350 μm, 150 μm to 350 μm, 50 μm to 300 μm, 80 μm to 300 μm, 100 μm to 300 μm, 150 μm to 300 μm, 50 μm to 250 μm, 80 μm to 250 μm, 100 μm to 250 μm, or 150 μm to 250 μm. The thickness TL is preferably 50 μm to 350 μm, more preferably 50 μm to 300 μm. If the thickness TL is within the above range, the series resistance of the Schottky barrier diode D can be reduced, thereby reducing the on-resistance of the Schottky barrier diode D.

[0064] In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon plane), and the second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0065] The first and second principal surfaces 3 and 4 have an off angle θ of 10° or less tilted toward the [11-20] direction relative to the c-plane of the SiC single crystal. The normal direction Z tilts relative to the c-axis (direction) of the SiC single crystal by the off angle θ.

[0066] The deviation angle θ may be greater than or equal to 0° and less than or equal to 5.0°. The deviation angle θ may be set within an angle range of greater than or equal to 0° and less than 1.0°, greater than or equal to 1.0° and less than or equal to 1.5°, greater than or equal to 1.5° and less than or equal to 2.0°, greater than or equal to 2.0° and less than or equal to 2.5°, greater than or equal to 2.5° and less than or equal to 3.0°, greater than or equal to 3.0° and less than or equal to 3.5°, greater than or equal to 3.5° and less than or equal to 4.0°, greater than or equal to 4.0° and less than or equal to 4.5°, or greater than or equal to 4.5° and less than or equal to 5.0°. The deviation angle θ preferably exceeds 0°. The deviation angle θ may also be less than 4.0°.

[0067] The off angle θ may be set to an angle range of 3.0° to 4.5°. In this case, the off angle θ is preferably set to an angle range of 3.0° to 3.5° or 3.5° to 4.0°.

[0068] The deviation angle θ may be set within a range of 1.5° to 3.0°. In this case, the deviation angle θ is preferably set within a range of 1.5° to 2.0° or 2.0° to 2.5°.

[0069] First principal surface 3 is a device-forming surface. First principal surface 3 is a non-mounting surface. Second principal surface 4 is a mounting surface. When semiconductor device 1A is mounted on a connection object, SiC semiconductor layer 2 is mounted on the connection object with second principal surface 4 facing the connection object. Examples of the connection object include electronic components, lead frames, and circuit boards.

[0070] The second main surface 4 is composed of a roughened surface. The second main surface 4 is roughened by irregularly formed unevenness. Preferably, the entire area of the second main surface 4 is roughened. The second main surface 4 is particularly preferably composed of a roughened surface without grinding marks (more specifically, grinding marks extending in a linear shape). More specifically, the second main surface 4 is a crystal surface composed of Si single crystal. Therefore, the second main surface 4 is composed of a crystallized roughened surface of Si single crystal.

[0071] The arithmetic mean roughness Ra of the second main surface 4 can be greater than 30nm. The arithmetic mean roughness Ra of the second main surface 4 can be greater than 30nm and less than 1000nm, greater than 50nm and less than 1000nm, greater than 80nm and less than 1000nm, greater than 100nm and less than 1000nm, greater than 30nm and less than 800nm, greater than 30nm and less than 600nm, greater than 30nm and less than 400nm, or greater than 30nm and less than 300nm. The arithmetic mean roughness Ra of the second main surface 4 is preferably greater than 30nm and less than 300nm. If the arithmetic mean roughness Ra of the second main surface 4 is greater than 30nm and less than 300nm, it is possible to prevent warping of the semiconductor wafer due to excessive surface roughness, and as described later, it is possible to achieve low-resistance ohmic contact on the second main surface 4.

[0072] The lengths of the side surfaces 5A to 5D may each be 0.5 mm to 10 mm. In this embodiment, the surface areas of the side surfaces 5A to 5D are equal. When the first principal surface 3 and the second principal surface 4 are rectangular in plan view, the surface areas of the side surfaces 5A and 5C may be smaller than or greater than the surface areas of the side surfaces 5B and 5D.

[0073] In this embodiment, the side surface 5A and the side surface 5C extend along the first direction X and face each other in a second direction Y intersecting the first direction X. In this embodiment, the side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction orthogonal to the first direction X.

[0074] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0075] Side surface 5A and side surface 5C are formed by the a-plane of SiC single crystal and face each other in the a-axis direction. Side surface 5A is formed by the (-1-120) plane of SiC single crystal. Side surface 5C is formed by the (11-20) plane of SiC single crystal.

[0076] Side surface 5B and side surface 5D are formed by the m-plane of SiC single crystal and face each other in the m-axis direction. Side surface 5B is formed by the (-1100) plane of SiC single crystal. Side surface 5D is formed by the (1-100) plane of SiC single crystal.

[0077] With the normal to first principal surface 3 of SiC semiconductor layer 2 as a reference, side surfaces 5A and 5C may be inclined surfaces inclined toward the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal.

[0078] In this case, when the normal to the first principal surface 3 of the SiC semiconductor layer 2 is set to 0°, the side surfaces 5A and 5C may be inclined at an angle corresponding to the off angle θ relative to the normal to the first principal surface 3 of the SiC semiconductor layer 2. The angle corresponding to the off angle θ may be equal to the off angle θ, or may be an angle greater than 0° and smaller than the off angle θ.

[0079] On the other hand, side surfaces 5B and 5D extend in a planar manner along the normal line of first principal surface 3 of SiC semiconductor layer 2. More specifically, side surfaces 5B and 5D are formed substantially perpendicular to first principal surface 3 and second principal surface 4.

[0080] In this manner, the SiC semiconductor layer 2 has a + The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6 and the stacked structure of the n-type SiC semiconductor substrate 6 and the n-type SiC epitaxial layer 7.

[0081] The first principal surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7 . The side surfaces 5A to 5D of the SiC semiconductor layer 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 .

[0082] The n-type impurity concentration of the SiC epitaxial layer 7 is lower than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is lower than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 may be 1.0×10 18 cm -3Above and 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 can be 1.0×10 15 cm -3 Above and 1.0×10 18 cm -3 the following.

[0083] The thickness TS of the SiC semiconductor substrate 6 can be 40 μm to 150 μm. The thickness TS can be 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, 90 μm to 100 μm, 100 μm to 110 μm, 110 μm to 120 μm, 120 μm to 130 μm, 130 μm to 140 μm, or 140 μm to 150 μm. The thickness TS is preferably 40 μm to 130 μm. Thinning the SiC semiconductor substrate 6 can reduce resistance by shortening the current path.

[0084] The thickness TE of the SiC epitaxial layer 7 may be 1 μm to 50 μm. The thickness TE may be 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. The thickness TE is preferably 5 μm to 15 μm.

[0085] The SiC semiconductor layer 2 includes an active region 8 and an outer region 9. The active region 8 is a region where a Schottky barrier diode D, which is an example of an element structure, is formed. The outer region 9 is a region outside the active region 8.

[0086] Active region 8 is provided in the center of SiC semiconductor layer 2 at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view. Active region 8 is provided in a quadrilateral shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

[0087] Outer region 9 is defined between side surfaces 5A to 5D of SiC semiconductor layer 2 and the periphery of active region 8. Outer region 9 is defined in a ring shape (a quadrilateral ring shape in this embodiment) surrounding active region 8 in a plan view.

[0088] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single layer structure composed of a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer.

[0089] The main surface insulating layer 10 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single-layer structure consisting of a silicon oxide layer.

[0090] Main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from side surfaces 5A to 5D of SiC semiconductor layer 2. Insulating side surfaces 11A to 11D are continuous with side surfaces 5A to 5D of SiC semiconductor layer 2. Insulating side surfaces 11A to 11D are formed to coincide with the surfaces of side surfaces 5A to 5D. Insulating side surfaces 11A to 11D are formed as cleavage planes.

[0091] The thickness of the main surface insulating layer 10 may be 1 μm to 50 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

[0092] A first principal surface electrode 12 is formed on the principal surface insulating layer 10. The first principal surface electrode 12 is formed in the center of the SiC semiconductor layer 2 at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 toward the inner region in a plan view.

[0093] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer.

[0094] The passivation layer 13 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure consisting of a silicon nitride layer.

[0095] Side surfaces 14A, 14B, 14C, and 14D of passivation layer 13 are formed spaced apart from side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view. Passivation layer 13 exposes the periphery of first principal surface 3 of SiC semiconductor layer 2 in a plan view. Passivation layer 13 exposes principal surface insulating layer 10.

[0096] Sub-pad opening 15 exposing a portion of first main surface electrode 12 as a pad region is formed in passivation layer 13. Sub-pad opening 15 is formed in a quadrilateral shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view.

[0097] The thickness of the passivation layer 13 may be 1 μm to 50 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

[0098] A resin layer 16 is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form an insulating laminate structure. Figure 4 In FIG, the resin layer 16 is indicated by hatching.

[0099] The resin layer 16 may include a negative or positive photosensitive resin. In this embodiment, the resin layer 16 includes polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 16 may also include polyimide, which is an example of a negative photosensitive resin.

[0100] Resin side surfaces 17A, 17B, 17C, and 17D of resin layer 16 are formed spaced apart from side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view. Resin layer 16 exposes the periphery of first principal surface 3 of SiC semiconductor layer 2 in a plan view. Resin layer 16, together with passivation layer 13, exposes principal surface insulating layer 10. In this embodiment, resin side surfaces 17A to 17D of resin layer 16 are formed to coincide with the surfaces of side surfaces 14A to 14D of passivation layer 13.

[0101] The resin side surfaces 17A to 17D of the resin layer 16 define scribe lines when semiconductor devices 1A to 1E are cut from a single SiC semiconductor wafer. In this embodiment, the side surfaces 14A to 14D of the passivation layer 13 also define scribe lines.

[0102] By exposing the periphery of first principal surface 3 of SiC semiconductor layer 2 from resin layer 16 and passivation layer 13, there is no need to physically cut resin layer 16 and passivation layer 13. This allows semiconductor devices 1A to be smoothly cut from a single SiC semiconductor wafer. Furthermore, the insulation distance from side surfaces 5A to 5D of SiC semiconductor layer 2 can be increased.

[0103] The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) can be 1 μm to 25 μm. The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) can be 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 25 μm. Of course, the side surfaces 14A to 14D of the passivation layer 13 can also be formed to coincide with the surfaces of the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0104] A pad opening 18 is formed in resin layer 16 to expose a portion of first principal surface electrode 12 as a pad region. Pad opening 18 is formed into a quadrilateral shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 when viewed from above. Pad opening 18 is formed into a quadrilateral shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 when viewed from above.

[0105] The pad opening 18 communicates with the sub-pad opening 15. The inner wall of the pad opening 18 is formed to coincide with the inner wall surface of the sub-pad opening 15. The inner wall of the pad opening 18 may be located closer to the side surfaces 5A to 5D of the SiC semiconductor layer 2 than the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located inward of the SiC semiconductor layer 2 relative to the inner wall of the sub-pad opening 15. The resin layer 16 may also cover the inner wall of the sub-pad opening 15.

[0106] The thickness of the resin layer 16 may be 1 μm to 50 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

[0107] A second principal surface electrode 19 is formed on the second principal surface 4 of the SiC semiconductor layer 2. The second principal surface electrode 19 forms an ohmic contact with the second principal surface 4 of the SiC semiconductor layer 2 (SiC semiconductor substrate 6).

[0108] Reference Figure 6 The second main surface electrode 19 has a stacked structure including a plurality of electrode layers stacked on the second main surface 4. In this embodiment, the second main surface electrode 19 has a stacked structure including a metal layer 191, a first electrode layer 192, and a second electrode layer 193 stacked in this order from the second main surface 4 side.

[0109] The metal layer 191 is directly connected to the roughened second main surface 4. The metal layer 191 preferably covers the entire area of the second main surface 4. In this embodiment, the metal layer 191 is the base layer of the first electrode 192 and the second electrode 193, and can also be called a "metal base layer."

[0110] From a material perspective, in this embodiment, metal layer 191 may also be a silicide layer. Examples of metal layer 191 include nickel silicide (NiSi, NiSi2, etc.), titanium silicide (TiSi, TiSi2, Ti5Si3, etc.), tungsten silicide (WSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), cobalt silicide (CoSi2), and platinum silicide (PtSi2). Metal layer 191 is preferably a nickel silicide layer or a titanium silicide layer, and more preferably a nickel silicide layer.

[0111] The first electrode layer 192 is sandwiched between the metal layer 191 and the second electrode layer 193. The first electrode layer 192 preferably covers the entire area of the metal layer 191. The first electrode layer 192 includes the same metal as the metal layer 191. In this embodiment, the first electrode layer 192 is a Ni layer.

[0112] Second electrode layer 193 is the outermost electrode layer of second principal surface electrode 19 and is directly connected to the connection target of semiconductor device 1A. Second electrode layer 193 can also be referred to as the outermost electrode layer. Second electrode layer 193 preferably covers the entire area of first electrode layer 192. In this embodiment, second electrode layer 193 is an Au layer.

[0113] Reference Figure 5 In active region 8, an n-type diode region 20 is formed on the surface of first principal surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 20 is formed in the center of first principal surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 20 is configured to have a quadrilateral shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 when viewed from above.

[0114] The n-type impurity concentration of the diode region 20 may be higher than the n-type impurity concentration of the SiC epitaxial layer 7. In this embodiment, the diode region 20 is formed using a portion of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 20 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The diode region 20 may also be formed by introducing n-type impurities into the surface layer of the SiC epitaxial layer 7.

[0115] In the outer region 9 , a p-type layer is formed on the surface portion of the first main surface 3 of the SiC semiconductor layer 2 . + The protective region 21 is formed in a strip shape extending along the diode region 20 in a plan view.

[0116] More specifically, the guard region 21 is formed into a ring shape (e.g., a square ring, a square ring with chamfered corners, or a circular ring) surrounding the diode region 20 when viewed from above. Thus, the guard region 21 forms a guard ring region. In this embodiment, the diode region 20 is demarcated by the guard region 21. Furthermore, the active region 8 is demarcated by the guard region 21.

[0117] The p-type impurity in the protection region 21 may not be activated. In this case, the protection region 21 is formed as a non-semiconductor region. The p-type impurity in the protection region 21 may also be activated. In this case, the protection region 21 is formed as a p-type semiconductor region.

[0118] The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 22 is formed in the main surface insulating layer 10 to expose the diode region 20. The diode opening 22 exposes the inner periphery of the protection region 21 in addition to the diode region 20. In plan view, the diode opening 22 is formed into a quadrilateral shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0119] The aforementioned first main surface electrode 12 is formed on the main surface insulating layer 10. The first main surface electrode 12 extends from above the insulating layer into the diode opening 22. The first main surface electrode 12 is electrically connected to the diode region 20 within the diode opening 22. The first main surface electrode 12 is not particularly limited as long as it is made of a metal that forms a Schottky junction by bonding with n-type SiC. For example, titanium (Ti), molybdenum (Mo), palladium (Pd), platinum (Pt), etc. can be used.

[0120] More specifically, the first main surface electrode 12 forms a Schottky junction with the diode region 20 , thereby forming a Schottky barrier diode D with the first main surface electrode 12 as an anode and the diode region 20 as a cathode. The passivation layer 13 and the resin layer 16 are formed on the main surface insulating layer 10 .

[0121] [Semiconductor Device 1B of Second Embodiment]

[0122] Figure 7 It is a schematic top view of a semiconductor device 1B according to a second embodiment of the present disclosure. Figure 8 It is along Figure 7 Hereinafter, structures corresponding to those described in the above-mentioned embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0123] In the semiconductor device 1B, a p-type semiconductor layer is formed on the surface portion of the first main surface 3 of the diode region 20. +The plurality of JBS (Junction Barrier Schottky) structures 23 of the type are formed. In this embodiment, the plurality of JBS structures 23 are formed in a stripe shape extending along the diode region 20 in a plan view. The plurality of JBS structures 23 are formed by + The JBS structures 23 are formed by discretely arranging semiconductor regions in the diode region 20. The plurality of JBS structures 23 may be arranged in the diode region 20 in a matrix or staggered manner in addition to being arranged in a stripe pattern.

[0124] [Semiconductor Device 1C According to Third Embodiment]

[0125] Figure 9 Schematic cross-sectional view of a semiconductor device 1C according to a third embodiment of the present disclosure. Components corresponding to those described in the previous embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0126] Semiconductor device 1C includes a trench-gate MOSFET as an example of an element structure. Gate trenches 25 that define a plurality of unit cells 24 are formed on the surface of first principal surface 3 of SiC epitaxial layer 7. Multiple gate trenches 25 may be formed in a stripe shape extending along the a-axis direction.

[0127] The bottom of each gate trench 25 is located midway in the thickness direction of the SiC epitaxial layer 7. The edge where the side surface and the bottom of each gate trench 25 intersect is formed to bend toward the outside of each gate trench 25, and each gate trench 25 is formed into a U-shaped cross-section. The curved edge of each gate trench 25 can alleviate the electric field concentrated at the edge.

[0128] A gate electrode 27 is embedded in each gate trench 25 via a gate insulating film 26. The gate electrode 27 has a surface aligned with the first main surface 3 of the SiC epitaxial layer 7. The gate insulating film 26 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an aluminum oxide film, or a tantalum oxide film. Alternatively, the gate electrode 27 can be composed of, for example, polysilicon reduced in resistance by impurity implantation. A p-type body region 28 constituting the unit cell 24 is formed in the region between adjacent gate trenches 25.

[0129] The bottom of the body region 28 is located between the first main surface 3 of the SiC epitaxial layer 7 and the bottom of the gate trench 25 in the thickness direction of the SiC epitaxial layer 7. In the lateral direction along the first main surface 3 of the SiC epitaxial layer 7, the end of the body region 28 forms a portion of the gate trench 25. In other words, the body region 28 faces the gate electrode 27 with the gate insulating film 26 interposed therebetween.

[0130] In this embodiment, the SiC semiconductor substrate 6 is n +The drain region 29 of the type, the area between the main region 28 and the drain region 29 is n - Type drift region 30.

[0131] An n-type source region 31 is formed inside the body region 28. Source region 31 is formed shallower than body region 28 in the thickness direction of SiC epitaxial layer 7. In the lateral direction along first principal surface 3 of SiC epitaxial layer 7, the end of source region 31 forms a portion of gate trench 25. In other words, source region 31 faces gate electrode 27 via gate insulating film 26.

[0132] In the thickness direction of the SiC epitaxial layer 7, the region between the lower end of the source region 31 and the lower end of the body region 28 along the side of the gate trench 25 is a p-type channel region 32. A p-type channel region 32 is formed so as to penetrate the source region 31. + Type of main body contact area 33.

[0133] The body contact region 33 is formed so as to penetrate the source region 31 and cross the boundary between the source region 31 and the body region 28 . The body contact region 33 has a higher impurity concentration than the body region 28 .

[0134] An interlayer insulating film 34 is formed on the SiC epitaxial layer 7, covering the gate electrode 27. Contact holes 36 are formed in the interlayer insulating film 34 to selectively expose a portion of the source region 31 and the body contact region 33. A source electrode 35 is formed on the interlayer insulating film 34. The source electrode 35 may include, for example, at least one of a pure Al layer (an Al layer with a purity of 99% or greater), a Cu layer (a Cu layer with a purity of 99% or greater), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0135] The source electrode 35 forms an ohmic contact with the body region 28, a portion of the source region 31, and the body contact region 33 within the contact hole 36. On the other hand, a drain electrode 37 is formed on the second main surface 4 of the SiC semiconductor substrate 6. The drain electrode 37 forms an ohmic contact with the drain region 29. The drain electrode 37 is formed of the same material as the second main surface electrode 19 described above. That is, the drain electrode 37 has a Figure 6 The stacked structure of the metal layer 191, the first electrode layer 192 and the second electrode layer 193 is shown.

[0136] [Semiconductor Device 1D According to Fourth Embodiment]

[0137] Figure 10 1 is a schematic cross-sectional view of a semiconductor device 1D according to a fourth embodiment of the present disclosure. Components corresponding to those described in the previous embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0138] The semiconductor device 1D differs from the aforementioned semiconductor device 1C in that a planar gate structure is formed along the first main surface 3, and a gate electrode 38 is formed instead of the gate electrode 27. That is, the semiconductor device 1D includes a MOSFET of a planar gate structure as an example of an element structure.

[0139] Body regions 39 are formed at intervals on the SiC epitaxial layer 7, and source regions 40 are formed in the inner region thereof. Source regions 40 are formed at intervals from the periphery of body regions 39. In semiconductor device 1D, p-type body regions 39 and n-type source regions 40 are doubly diffused in the surface layer of SiC epitaxial layer 7 (drift region 30). The region between the periphery of source regions 40 and the periphery of body regions 39 constitutes channel region 41.

[0140] A plurality of gate electrodes 38 are formed on the SiC epitaxial layer 7 so as to face the channel region 41 via a gate insulating film 42. The materials of the gate insulating film 42 and the gate electrodes 38 are the same as those of the aforementioned semiconductor device 1C.

[0141] Each gate electrode 38 faces a region spanning the SiC epitaxial layer 7 outside the body region 39, the body region 39, and the source region 40. The gate electrode 38 also includes an overlapping portion extending from the boundary between the source region 40 and the body region 39 toward the source region 40.

[0142] [Semiconductor Device 1E of Fifth Embodiment]

[0143] Figure 11 1 is a schematic cross-sectional view of a semiconductor device 1E according to a fifth embodiment of the present disclosure. Components corresponding to those described in the previous embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0144] The semiconductor device 1E differs from the aforementioned semiconductor device 1C in that the drain region 29 is replaced by a p + The semiconductor device 1E includes an IGBT (Insulated Gate Bipolar Transistor) as an example of an element structure. The body region 28, source region 31, source electrode 35, and drain electrode 37 may also be a p-type base region 44, an n-type emitter region 45, an emitter electrode 46, and a collector electrode 47, respectively.

[0145] [Method for Manufacturing Semiconductor Devices 1A to 1E]

[0146] Figure 121A is a perspective view showing a SiC semiconductor wafer 48 used in the process of manufacturing semiconductor devices 1A to 1E. Figures 13A to 13D The diagram shows part of the manufacturing process of the semiconductor devices 1A to 1E in order of the process steps.

[0147] SiC semiconductor wafer 48 is a component that serves as a base for SiC semiconductor substrate 6. SiC semiconductor wafer 48 is made of 4H-SiC single crystal, an example of a hexagonal SiC single crystal. In this embodiment, SiC semiconductor wafer 48 has an n-type impurity concentration corresponding to the n-type impurity concentration of SiC semiconductor substrate 6.

[0148] The SiC semiconductor wafer 48 is formed into a plate or disk shape. The SiC semiconductor wafer 48 can also be formed into a disk shape. The SiC semiconductor wafer 48 has a first wafer main surface 49 on one side, a second wafer main surface 50 on the other side, and a wafer side surface 51 connecting the first wafer main surface 49 and the second wafer main surface 50.

[0149] The thickness TW of the SiC semiconductor wafer 48 exceeds the thickness TS of the SiC semiconductor substrate 6 (see Figure 3 )(TS<TW). The thickness TW of the SiC semiconductor wafer 48 is made equal to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0150] Thickness TW may be greater than 150 μm and less than 750 μm. Thickness TW may be greater than 150 μm and less than 300 μm, greater than 300 μm and less than 450 μm, greater than 450 μm and less than 600 μm, or greater than 600 μm and less than 750 μm. Considering the grinding time of SiC semiconductor wafer 48, thickness TW is preferably greater than 150 μm and less than 500 μm. Thickness TW is typically greater than 300 μm and less than 450 μm.

[0151] In this embodiment, the first wafer main surface 49 and the second wafer main surface 50 face the c-plane of the SiC single crystal. The first wafer main surface 49 faces the (0001) plane (silicon plane), and the second wafer main surface 50 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0152] The first wafer main surface 49 and the second wafer main surface 50 are tilted at an off angle θ of 10° or less in the [11-20] direction relative to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 49 is tilted relative to the c-axis (

[0001] direction) of the SiC single crystal by the amount of the off angle θ.

[0153] The deviation angle θ may be greater than or equal to 0° and less than or equal to 5.0°. The deviation angle θ may be set within an angle range of greater than or equal to 0° and less than 1.0°, greater than or equal to 1.0° and less than or equal to 1.5°, greater than or equal to 1.5° and less than or equal to 2.0°, greater than or equal to 2.0° and less than or equal to 2.5°, greater than or equal to 2.5° and less than or equal to 3.0°, greater than or equal to 3.0° and less than or equal to 3.5°, greater than or equal to 3.5° and less than or equal to 4.0°, greater than or equal to 4.0° and less than or equal to 4.5°, or greater than or equal to 4.5° and less than or equal to 5.0°. The deviation angle θ preferably exceeds 0°. The deviation angle θ may also be less than 4.0°.

[0154] The off angle θ may be set to an angle range of 3.0° to 4.5°. In this case, the off angle θ is preferably set to an angle range of 3.0° to 3.5° or 3.5° to 4.0°.

[0155] The deviation angle θ may be set within a range of 1.5° to 3.0°. In this case, the deviation angle θ is preferably set within a range of 1.5° to 2.0° or 2.0° to 2.5°.

[0156] SiC semiconductor wafer 48 includes a first wafer corner 52 connecting first wafer main surface 49 and wafer side surface 51, and a second wafer corner 53 connecting second wafer main surface 50 and wafer side surface 51. First wafer corner 52 has a first chamfered portion 54 that slopes downward from first wafer main surface 49 toward wafer side surface 51. Second wafer corner 53 has a second chamfered portion 55 that slopes downward from second wafer main surface 50 toward wafer side surface 51.

[0157] The first chamfered portion 54 may be formed in a convex curved shape. The second chamfered portion 55 may be formed in a convex curved shape. The first chamfered portion 54 and the second chamfered portion 55 suppress cracks in the SiC semiconductor wafer 48 .

[0158] An orientation flat 56 is formed on the wafer side surface 51 of the SiC semiconductor wafer 48 as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 56 is a notch formed in the wafer side surface 51 of the SiC semiconductor wafer 48. In this embodiment, the orientation flat 56 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0159] A plurality (eg, two) of orientation flats 56 indicating crystal orientation may be formed on the wafer side surface 51 of the SiC semiconductor wafer 48. The plurality (eg, two) of orientation flats 56 may include a first orientation flat and a second orientation flat.

[0160] The first orientation flat may be a notch extending linearly along the a-axis ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch extending linearly along the m-axis ([1-100] direction) of the SiC single crystal.

[0161] A plurality of device formation regions 57 corresponding to semiconductor devices 1A to 1E are defined on first wafer main surface 49 of SiC semiconductor wafer 48. Device formation regions 57 are arranged in rows and columns at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0162] Each device formation region 57 has four sides 58A, 58B, 58C, and 58D aligned with the crystal orientation of the SiC single crystal. These four sides 58A to 58D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. These four sides 58A to 58D include two sides 58A and 58C aligned with the m-axis (1-100) direction, and two sides 58B and 58D aligned with the a-axis (11-20).

[0163] The device formation regions 57 are divided by grid-shaped planned cutting lines 59 extending along the m-axis ([1-100] direction) and the a-axis ([11-20] direction). The planned cutting lines 59 include a plurality of first planned cutting lines 60 and a plurality of second planned cutting lines 61.

[0164] The plurality of first lines to cut 60 extend along the m-axis direction ([1-100] direction), and the plurality of second lines to cut 61 extend along the a-axis direction ([11-20] direction).

[0165] In the manufacturing process of the semiconductor devices 1A to 1E, referring to Figure 13A , a predetermined element structure 62 (the aforementioned Schottky barrier diode D, and each unit cell 24 of the trench gate structure MOSFET, the planar gate structure MOSFET and the trench gate structure IGBT, etc.) is produced in multiple device formation regions 57.

[0166] Next, refer to Figure 13B The second main surface 50 of the SiC semiconductor wafer 48 is ground. The second main surface 50 of the SiC semiconductor wafer 48 can also be ground by CMP (Chemical Mechanical Polishing). In this way, the SiC semiconductor wafer 48 is thinned to a desired thickness.

[0167] Next, refer to Figure 13CThe second wafer main surface 50 of the SiC semiconductor wafer 48 is roughened. The second wafer main surface 50 is preferably roughened by etching. The second wafer main surface 50 can be roughened to an arithmetic average roughness Ra of 30 nm or greater. The second wafer main surface 50 is preferably roughened to an arithmetic average roughness Ra of 30 nm or greater and 300 nm or less.

[0168] Next, refer to Figure 13D The back electrode 63 is formed on the entire area of the roughened second wafer main surface 50. The back electrode 63 includes the aforementioned second main surface electrode 19 (see Figure 5 as well as Figure 8 ), the drain electrode 37 (refer to Figure 9 as well as Figure 10 ) and the collector electrode 47 (refer to Figure 11 ) The back electrode 63 is formed by sequentially stacking the electrode materials of the first electrode layer 192 and the second electrode layer 193 by, for example, sputtering.

[0169] Next, refer to Figure 13E By irradiating the interface 64 between the first electrode layer 192 and the second wafer main surface 50 with laser light, the contact portion of the first electrode layer 192 is subjected to laser annealing. As a result, the material of the first electrode layer 192 (Ni in this embodiment) reacts with Si in the SiC semiconductor wafer 48 to form a metal layer 191 between the first electrode layer 192 and the SiC semiconductor wafer 48 (see Figure 6 ).

[0170] During the laser annealing process, the entire area of the second wafer main surface 50 is continuously irradiated with laser light, with the ranges of the irradiation units that can be processed by a single shot of laser irradiation overlapping with each other. The irradiation range of a single laser shot varies depending on the pulse energy of the single laser shot. For example, the higher the pulse energy, the more the energy needs to be concentrated in a narrow range, and thus the irradiation range of a single shot becomes narrower.

[0171] The irradiation range of one shot varies depending on the laser irradiation device, but for example, Figure 15 , the pulse energy of one emission is only 3.0J / cm 2 The irradiation range of one shot can also be a small circle 65. The size of the circle 65 can be, for example, 10 μm in diameter. Above and 100μm in diameter The following. Figure 15 As shown, the laser light is irradiated in such a manner that a plurality of circles 65 overlap each other.

[0172] In contrast, reference Figure 14If the pulse energy of a single shot is a second energy lower than the first energy, the irradiation range of a single shot can also be a quadrilateral 66 having an area larger than the circle 65. Regarding the dimensions of quadrilateral 66, for example, if quadrilateral 66 is a rectangle, the length L1 of any long side 67 in the second direction Y can be at least five times the length L2 of any short side 68 in the first direction X, which is orthogonal to the second direction Y. More specifically, the length L2 of the short side 68 can be between 0.1 mm and 0.4 mm, and the length L1 of the long side 67 can be between 1.0 mm and 4.0 mm. Furthermore, the first direction X and the second direction Y are merely mutually orthogonal directions, defined for convenience. The first direction X can also be referred to as the "transverse direction" or the "second direction," and the second direction Y can also be referred to as the "longitudinal direction" or the "first direction."

[0173] Figure 14 as well as Figure 15 The shape of the laser shot shown in one shot remains as a laser mark (processing mark) on the second wafer main surface 50 after the laser annealing process. The laser mark can be confirmed by, for example, removing the back electrodes 63 (second main surface electrode 19, drain electrode 37, collector electrode 47, etc.) of the completed semiconductor devices 1A to 1E and observing the second main surface 4. Figure 14 In the case of , a plurality of processing units 69 formed into a rectangular shape in plan view overlap each other and remain on the second main surface 4 (the second main surface 50 of the wafer). Figure 15 In this case, on the second main surface 4 (the wafer second main surface 50 ), a plurality of processing units 70 formed in a circular shape in plan view overlap with each other and remain.

[0174] Figure 16 This is a photographic image showing a first shape (a quadrilateral) of a laser mark 71 formed on the second main surface 4 (the wafer second main surface 50 ). Figure 17 : is a photographic image showing the second shape (circular) of the laser mark 72 formed on the second main surface 4 (the wafer second main surface 50). Figure 16 as well as Figure 17 Respectively, they represent Figure 14 as well as Figure 15 Photographic images of laser marks 71 and 72 formed by overlapping processing units 69 and 70.

[0175] Reference Figure 16 , based on relatively small pulse energy (e.g., 2.0 J / cm 2 In the laser irradiation (hereinafter), a plurality of black band-shaped laser marks 71 are formed, which extend elongatedly along the second direction Y of the second main surface 50 of the wafer. The plurality of laser marks 71 are regularly arranged along the first direction X. In particular, Figure 16In the embodiment, a plurality of stripe-shaped laser marks 71 are arranged along the first direction X at substantially equal intervals.

[0176] Reference Figure 17 , based on relatively large pulse energy (e.g., 3.0 J / cm 2 In the laser irradiation of the above), a plurality of black elliptical laser marks 72 having a long diameter along the second direction Y of the second main surface 50 of the wafer are formed. The plurality of laser marks 72 are regularly arranged along the first direction X. In particular, Figure 17 In the embodiment, a plurality of elliptical laser marks 72 are arranged along the first direction X at substantially equal intervals.

[0177] Figure 18 This is a photographic image showing a modified example of the laser mark 71 . Figure 19 This is a photographic image showing a modified example of the laser mark 72 .

[0178] Reference Figure 18 , laser mark 71 can also be Figure 16 The laser marks 71 shown are short strips. A plurality of laser marks 71 can also be selectively formed on the second main surface 4 (the second main surface 50 of the wafer) to form a strip-shaped area extending along the first direction X. The strip-shaped area can be a shadow area 74 formed by configuring a plurality of laser marks 71 with a black color. The shadow area 74 is an area that is darker in color than the base area 73 of the second main surface 4 (the second main surface 50 of the wafer). In this manner, the base area 73 and the shadow area 74 are arranged alternately along the second direction Y. In addition, the aspect ratio (W / L) between the length (L) of the shadow area 74 in the first direction X and the width (W) in the second direction Y can be less than 0.1.

[0179] Reference Figure 19 , the laser mark 72 may also be a curved line that is longer along the second direction Y (in other statements, an arc shape that is longer along the second direction Y). A plurality of laser marks 72 may also be selectively formed on the second main surface 4 (the second main surface 50 of the wafer) to form a strip-shaped area extending along the first direction X. The strip-shaped area may also be a shadow area 76 formed by arranging a plurality of laser marks 72 with black color. The shadow area 76 is an area that is darker in color than the base area 75 of the second main surface 4 (the second main surface 50 of the wafer). In this manner, the base area 75 and the shadow area 76 are alternately arranged along the second direction Y. In addition, the aspect ratio (W / L) of the length (L) of the shadow area 75 in the first direction X to the width (W) in the second direction Y may also be less than 0.1.

[0180] in addition, Figure 14 The processing unit 69 is a rectangle, but as a quadrilateral processing unit 69, it can also be used Figure 20The square processing unit 69 shown, Figure 21 The diamond-shaped processing unit 69 is shown. In addition, Figure 15 The processing unit 70 is an elliptical shape, but as a circular processing unit 70, it can also be used. Figure 22 The processing unit 70 shown is a perfect circle.

[0181] Thereafter, SiC semiconductor wafer 48 is cut along planned cutting lines 59 to thereby separate a plurality of semiconductor devices 1A to 1E.

[0182] [Effect of Roughening the Second Main Surface 4]

[0183] As described above, according to the semiconductor devices 1A to 1E, the second main surface 4 of the SiC semiconductor layer 2 is roughened so that the arithmetic mean roughness Ra is 30 nm or more. As a result, even with a relatively low energy laser annealing process, a low-resistance ohmic contact can be formed between the back electrode 63 (second main surface electrode 19, drain electrode 37, collector electrode 47, etc.) and the second main surface 4. This effect can be seen, for example, in Figure 23 as well as Figure 24 , which can be confirmed by comparing sample 1 with sample 2.

[0184] In Samples 1 and 2, the back electrode 63 was formed on the second wafer main surface 50 (second main surface 4) under the same conditions except that the arithmetic mean roughness Ra of the second wafer main surface 50 was different. The energy of the laser shot during the annealing process on the back electrode 63 was 2.0 J / cm 2 the following.

[0185] Figure 23 4 is a diagram showing the contact resistance distribution of the second wafer main surface 50 of the SiC semiconductor wafer 48 of Sample 1 and the state of the second wafer main surface 50 . Figure 24 4 is a diagram showing the contact resistance distribution of the second wafer main surface 50 of the SiC semiconductor wafer 48 of Sample 2 and the state of the second wafer main surface 50 .

[0186] exist Figure 23 In the SiC semiconductor wafer 48 on the right side of the paper, the black dots indicate portions having a higher contact resistance than the other white areas. Figure 23 The photographic image on the left side of the paper shows the surface condition of the second wafer main surface 50 . Figure 23 This is the surface state of the second wafer main surface 50 when the arithmetic mean roughness Ra of the second wafer main surface 50 is 60 μm.

[0187] exist Figure 24In the SiC semiconductor wafer 48 on the right side of the paper, the black dots, cross-hatched areas, and diagonally hatched areas indicate portions where the contact resistance is higher than that of the other white areas. The cross-hatched areas have a particularly high resistance. Figure 24 The photographic image on the left side of the paper shows the surface condition of the second wafer main surface 50 . Figure 24 This is the surface state of the second wafer main surface 50 when the arithmetic mean roughness Ra of the second wafer main surface 50 is 15 μm.

[0188] Compare Figure 23 and Figure 24 It can be seen that even based on 2.0J / cm 2 The following low-energy laser annealing treatment can also form a low-resistance ohmic contact between the back electrode 63 and the second main surface 4 in Sample 1 roughened to 30 μm Ra or more. This resistance reduction is also due to the increase in the contact area between the second main surface 4 and the back electrode 63 due to the roughening of the second main surface 4.

[0189] Thus, by 2.0 J / cm 2 The following low energy laser annealing process can obtain low resistance ohmic contact, so Figure 14 As shown in FIG, the irradiation area of each laser emission can be increased. For example, Figure 15 The processing unit 70 shown is larger than the processing unit 69. As a result, the laser annealing process can be performed efficiently, thereby improving the manufacturing efficiency of the semiconductor devices 1A to 1E.

[0190] In addition, in sample 1, Ra is about 60 μm, so the SiC semiconductor wafer 48 hardly warps, and no problems occur during the formation of the back electrode 63 and during the transportation after formation. Figure 24 Flattening the second main surface 4, as in Sample 2, effectively reduces the warpage of the SiC semiconductor wafer 48. However, without high-energy laser annealing, it is difficult to achieve a low-resistance ohmic contact. In other words, Sample 1 achieves a good balance between preventing the warpage of the SiC semiconductor wafer 48 and reducing the low-resistance ohmic contact on the second main surface 4.

[0191] The aforementioned reduction in resistance of the ohmic contact on the second wafer main surface 50 (second main surface 4) is effective for semiconductor devices 1A to 1E having a relatively thin SiC semiconductor layer 2 of 50 μm or greater and 350 μm or less. In the case of a vertical device in which current flows along the thickness direction of the SiC semiconductor layer 2, if the thickness TL of the SiC semiconductor layer 2 is thin, the series resistance in the thickness direction of the SiC semiconductor layer 2 decreases. Since the resistance of the ohmic contact on the second wafer main surface 50 (second main surface 4) has a greater impact on the series resistance, the aforementioned reduction in resistance of the ohmic contact on the second wafer main surface 50 (second main surface 4) becomes effective.

[0192] In particular, in Schottky barrier diodes such as semiconductor devices 1A and 1B, the device structure on the first main surface 3 side is simple, and there are fewer elements that contribute to increased series resistance. Therefore, the resistance of the ohmic contact on the second wafer main surface 50 (second main surface 4) has a greater impact on the series resistance than in devices such as MOSFETs with complex device structures. Therefore, reducing the resistance of the ohmic contact on the second wafer main surface 50 (second main surface 4) as described above becomes more effective.

[0193] Although the embodiments of the present disclosure have been described, the present disclosure can also be implemented in other forms.

[0194] For example, in each of the aforementioned embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, a p-type portion may be changed to an n-type portion, and an n-type portion may be changed to a p-type portion.

[0195] The embodiments of the present disclosure described above are illustrative in all aspects and should not be interpreted restrictively, but are intended to include modifications in all aspects.

[0196] The following features can be extracted from the description of this specification and the drawings.

[0197] [Supplementary Note 1-1] A semiconductor device 1A to 1E includes:

[0198] A SiC chip 2 having a first main surface 3 and a second main surface 4;

[0199] an element structure D, 24 formed on the first main surface 3; and

[0200] Electrodes 19, 37, 47 are formed on the second main surface 4 and are electrically connected to the device structures D and 24, and include a metal layer 191 bonded to the second main surface 4.

[0201] The arithmetic mean roughness Ra of the second main surface 4 is greater than 30 nm.

[0202] Laser marks are formed on the second main surface 4 by overlapping a plurality of processing units 69 and 70 each formed into a rectangular shape or a circle in plan view.

[0203] With this structure, the arithmetic mean roughness Ra of second principal surface 4 of SiC chip 2 is 30 nm or greater, thereby increasing the contact area between SiC chip 2 and electrodes 19, 37, and 47. Consequently, semiconductor devices 1A to 1E can be provided that form low-resistance ohmic contacts on second principal surface 4 opposite to element structures D and 24.

[0204] [Supplementary Note 1-2] The semiconductor device 1A to 1E according to Supplementary Note 1-1, wherein:

[0205] The thickness TL of the SiC chip 2 is greater than or equal to 50 μm and less than or equal to 350 μm.

[0206] [Supplementary Note 1-3] The semiconductor device 1A to 1E according to Supplementary Note 1-2, wherein:

[0207] The thickness TL of the SiC chip 2 is greater than or equal to 100 μm and less than or equal to 350 μm.

[0208] [Notes 1-4]

[0209] The semiconductor device 1A to 1E according to any one of Supplementary Notes 1-1 to 1-3, wherein:

[0210] The Ra of the second main surface 4 is 100 nm or less.

[0211] [Supplementary Note 1-5] The semiconductor device 1A to 1E according to any one of Supplementary Notes 1-1 to 1-4, wherein:

[0212] Each of the processing units 69 and 70 is formed into a rectangular shape in plan view including a short side 68 and a long side 67.

[0213] The length L1 of the long side 67 is at least five times the length L2 of the short side 68 .

[0214] [Supplementary Note 1-6] The semiconductor device 1A to 1E according to any one of Supplementary Notes 1-5, wherein:

[0215] The length L2 of the short side 68 of each of the processing units 69 and 70 is greater than or equal to 0.1 mm and less than or equal to 0.4 mm, and the length L1 of the long side 67 of each of the processing units 69 and 70 is greater than or equal to 1.0 mm and less than or equal to 4.0 mm.

[0216] [Supplementary Note 1-7] The semiconductor device 1A to 1E according to any one of Supplementary Notes 1-1 to 1-6, wherein:

[0217] The metal layer 191 is a silicide layer 191 .

[0218] [Supplementary Note 1-8] The semiconductor device 1A to 1E according to Supplementary Note 1-7, wherein:

[0219] The silicide layer 191 is a nickel silicide layer 191.

[0220] The electrodes 19 , 37 , and 47 are formed of a metal containing Ni.

[0221] [Supplementary Note 1-9] The semiconductor device 1A to 1E according to any one of Supplementary Notes 1-1 to 1-8, wherein:

[0222] The first main surface 3 is a silicon surface, and the second main surface 4 is a carbon surface.

[0223] [Supplementary Note 1-10] The semiconductor device 1A or 1B according to any one of Supplementary Notes 1-1 to 1-9, wherein:

[0224] The device structure D includes a Schottky barrier diode D formed on the first main surface 3 and having a Schottky metal 19 forming a Schottky junction on the first main surface 3 .

[0225] [Supplementary Note 1-11] The semiconductor device 1B according to Supplementary Note 1-10, wherein:

[0226] The SiC chip 2 includes: a first semiconductor region 7 of a first conductivity type, which is formed on the surface portion of the first main surface 3; and a JBS (Junction Barrier Schottky) structure 23, which is formed by multiple second conductivity type semiconductor regions selectively formed in the Schottky junction formation area 20 in the first main surface 3.

[0227] [Supplementary Note 1-12] The semiconductor device 1C or 1E according to any one of Supplementary Notes 1-1 to 1-9, wherein:

[0228] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0229] The element structure 24 includes: a gate trench 25 formed on the first main surface 3; a gate electrode 27 buried in the gate trench 25 through a gate insulating film 26; and a first conductive type second semiconductor region 31, 45 and a second conductive type third semiconductor region 28, 44, which are formed sequentially from the first main surface 3 along the depth direction of the gate trench 25.

[0230] [Supplementary Note 1-13] The semiconductor device 1C according to Supplementary Note 1-12, wherein:

[0231] The SiC chip 2 includes a first conductivity type drain region 29 formed on the surface of the second main surface 4 .

[0232] The second semiconductor region is a source region 31 .

[0233] [Supplementary Note 1-14] The semiconductor device 1E according to Supplementary Note 1-12, wherein

[0234] The SiC chip 2 includes a second conductivity type collector region 43 formed on the surface of the second main surface 4 .

[0235] The second semiconductor region is the emitter region 45 .

[0236] [Supplementary Note 1-15] The semiconductor device 1D according to any one of Supplementary Notes 1-1 to 1-9, wherein

[0237] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0238] The element structure 24 includes: a second conductive type main region 39 and a first conductive type source region 40 inside the main region 39, which are doubly diffused in the surface portion of the first semiconductor regions 7 and 30; and a gate electrode 38, which is formed on the first main surface 3 through a gate insulating film 42 and is opposite to the channel region 41 between the outer edge of the main region 39 and the outer edge of the source region 40.

[0239] [Supplementary Note 2-1] A semiconductor device 1A to 1E includes:

[0240] A SiC chip 2 having a first main surface 3 and a second main surface 4;

[0241] an element structure D, 24 formed on the first main surface 3; and

[0242] Electrodes 19, 37, 47 are formed on the second main surface 4 and are electrically connected to the device structures D and 24, and include a metal layer 191 bonded to the second main surface 4.

[0243] The arithmetic mean roughness Ra of the second main surface 4 is greater than 30 nm.

[0244] Processing regions 74 and 76 extending in a strip shape in the first direction X are formed on the second main surface 4 by regularly arranging a plurality of laser marks 71 and 72 having a predetermined shape along the first direction X.

[0245] [Supplementary Note 2-2] The semiconductor device 1A to 1E according to Supplementary Note 2-1, wherein:

[0246] The predetermined shape of the laser marks 71 and 72 includes a line shape that is long along a second direction Y that is perpendicular to the first direction X.

[0247] [Supplementary Note 2-3] The semiconductor device 1A to 1E according to Supplementary Note 2-2, wherein:

[0248] The line shape is a straight line or a curved line extending along the second direction Y.

[0249] [Supplementary Note 2-4] The semiconductor device 1A to 1E according to any one of Supplementary Notes 2-1 to 2-3, wherein:

[0250] The thickness TL of the SiC chip 2 is greater than or equal to 50 μm and less than or equal to 350 μm.

[0251] [Supplementary Note 2-5] The semiconductor device 1A to 1E according to Supplementary Note 2-4, wherein:

[0252] The thickness TL of the SiC chip 2 is greater than or equal to 100 μm and less than or equal to 350 μm.

[0253] [Supplementary Note 2-6] The semiconductor device 1A to 1E according to any one of Supplementary Notes 2-1 to 2-5, wherein:

[0254] The Ra of the second main surface 4 is 100 nm or less.

[0255] [Supplementary Note 2-7] The semiconductor device 1A to 1E according to any one of Supplementary Notes 2-1 to 2-6, wherein:

[0256] The metal layer 191 is a silicide layer 191 .

[0257] [Supplementary Note 2-8] The semiconductor device 1A to 1E according to Supplementary Note 2-7, wherein:

[0258] The silicide layer 191 is a nickel silicide layer 191.

[0259] The electrodes 19 , 37 , and 47 are formed of a metal containing Ni.

[0260] [Supplementary Note 2-9] The semiconductor device 1A to 1E according to any one of Supplementary Notes 2-1 to 2-8, wherein:

[0261] The first main surface 3 is a silicon surface, and the second main surface 4 is a carbon surface.

[0262] [Supplementary Note 2-10] The semiconductor device 1A or 1B according to any one of Supplementary Notes 2-1 to 2-9, wherein:

[0263] The device structure D includes a Schottky barrier diode D formed on the first main surface 3 and having a Schottky metal 19 forming a Schottky junction on the first main surface 3 .

[0264] [Supplementary Note 2-11] The semiconductor device 1B according to Supplementary Note 2-10, wherein

[0265] The SiC chip 2 includes: a first semiconductor region 7 of a first conductivity type, which is formed on the surface portion of the first main surface 3; and a JBS (Junction Barrier Schottky) structure 23, which is formed by multiple second conductivity type semiconductor regions selectively formed in the Schottky junction formation area 20 in the first main surface 3.

[0266] [Supplementary Note 2-12] The semiconductor device 1C or 1E according to any one of Supplementary Notes 2-1 to 2-9, wherein:

[0267] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0268] The element structure 24 includes: a gate trench 25 formed on the first main surface 3; a gate electrode 27 buried in the gate trench 25 through a gate insulating film 26; and a first conductive type second semiconductor region 31, 45 and a second conductive type third semiconductor region 28, 44, which are formed sequentially from the first main surface 3 along the depth direction of the gate trench 25.

[0269] [Supplementary Note 2-13] The semiconductor device 1C according to Supplementary Note 2-12, wherein

[0270] The SiC chip 2 includes a first conductivity type drain region 29 formed on the surface of the second main surface 4 .

[0271] The second semiconductor region is a source region 31 .

[0272] [Supplementary Note 2-14] The semiconductor device 1E according to Supplementary Note 2-12, wherein:

[0273] The SiC chip 2 includes a second conductivity type collector region 43 formed on the surface of the second main surface 4 .

[0274] The second semiconductor region is the emitter region 45 .

[0275] [Supplementary Note 2-15] The semiconductor device 1D according to any one of Supplementary Notes 2-1 to 2-9, wherein

[0276] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0277] The element structure 24 includes: a second conductive type main region 39 and a first conductive type source region 40 inside the main region 39, which are doubly diffused in the surface portion of the first semiconductor regions 7 and 30; and a gate electrode 38, which is formed on the first main surface 3 through a gate insulating film 42 and is opposite to the channel region 41 between the outer edge of the main region 39 and the outer edge of the source region 40.

[0278] [Supplementary Note 3-1] A semiconductor device 1A to 1E includes:

[0279] A SiC chip 2 having a first main surface 3 and a second main surface 4;

[0280] an element structure D, 24 formed on the first main surface 3; and

[0281] Electrodes 19, 37, 47 are formed on the second main surface 4 and are electrically connected to the device structures D and 24, and include a metal layer 191 bonded to the second main surface 4.

[0282] The arithmetic mean roughness Ra of the second main surface 4 is greater than 30 nm.

[0283] The second main surface 4 includes base areas 73 and 75 having a first color and shadow areas 74 and 76 having a second color darker than the first color.

[0284] The shadow regions 74 and 76 are selectively formed on the base regions 73 and 75 by the laser marks 71 and 72 , respectively extending in a strip shape along a first direction X and arranged at intervals along a second direction Y perpendicular to the first direction X.

[0285] [Supplementary Note 3-2] The semiconductor device 1A to 1E according to Supplementary Note 3-1, wherein:

[0286] An aspect ratio W / L of the shaded areas 74 and 76 between a length L in the first direction X and a width W in the second direction Y is equal to or less than 0.1.

[0287] [Supplementary Note 3-3] The semiconductor device 1A to 1E according to Supplementary Note 3-1 or Supplementary Note 3-2, wherein:

[0288] The thickness TL of the SiC chip 2 is greater than or equal to 50 μm and less than or equal to 350 μm.

[0289] [Supplementary Note 3-4] The semiconductor device 1A to 1E according to Supplementary Note 3-3, wherein:

[0290] The thickness TL of the SiC chip 2 is greater than or equal to 100 μm and less than or equal to 350 μm.

[0291] [Supplementary Note 3-5] The semiconductor device 1A to 1E according to any one of Supplementary Notes 3-1 to 3-4, wherein:

[0292] The Ra of the second main surface 4 is 100 nm or less.

[0293] [Supplementary Note 3-6] The semiconductor device 1A to 1E according to any one of Supplementary Notes 3-1 to 3-5, wherein:

[0294] The metal layer 191 is a silicide layer 191 .

[0295] [Supplementary Note 3-7] The semiconductor device 1A to 1E according to Supplementary Note 3-6, wherein:

[0296] The silicide layer 191 is a nickel silicide layer 191.

[0297] The electrodes 19 , 37 , and 47 are formed of a metal containing Ni.

[0298] [Supplementary Note 3-8] The semiconductor device 1A to 1E according to any one of Supplementary Notes 3-1 to 3-7, wherein:

[0299] The first main surface 3 is a silicon surface, and the second main surface 4 is a carbon surface.

[0300] [Supplementary Note 3-9] The semiconductor device 1A or 1B according to any one of Supplementary Notes 3-1 to 3-8, wherein:

[0301] The device structure D includes a Schottky barrier diode D formed on the first main surface 3 and having a Schottky metal 19 forming a Schottky junction on the first main surface 3 .

[0302] [Supplementary Note 3-10] The semiconductor device 1B according to Supplementary Note 3-9, wherein:

[0303] The SiC chip 2 includes: a first semiconductor region 7 of a first conductivity type, which is formed on the surface portion of the first main surface 3; and a JBS (Junction Barrier Schottky) structure 23, which is formed by multiple second conductivity type semiconductor regions selectively formed in the Schottky junction formation area 20 in the first main surface 3.

[0304] [Supplement 3-11] The semiconductor device 1C or 1E according to any one of Supplement 3-1 to Supplement 3-8, wherein:

[0305] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0306] The element structure 24 includes: a gate trench 25 formed on the first main surface 3; a gate electrode 27 buried in the gate trench 25 through a gate insulating film 26; and a first conductive type second semiconductor region 31, 45 and a second conductive type third semiconductor region 28, 44, which are formed sequentially from the first main surface 3 along the depth direction of the gate trench 25.

[0307] [Supplementary Note 3-12] The semiconductor device 1C according to Supplementary Note 3-11, wherein

[0308] The SiC chip 2 includes a first conductivity type drain region 29 formed on the surface of the second main surface 4 .

[0309] The second semiconductor region is a source region 31 .

[0310] [Supplementary Note 3-13] The semiconductor device 1E according to Supplementary Note 3-11, wherein

[0311] The SiC chip 2 includes a second conductivity type collector region 43 formed on the surface of the second main surface 4 .

[0312] The second semiconductor region is the emitter region 45 .

[0313] [Supplement 3-14] The semiconductor device 1D according to any one of Supplement 3-1 to Supplement 3-8, wherein:

[0314] The SiC chip 2 includes: first semiconductor regions 7 and 30 of a first conductivity type, which are formed on the surface of the first main surface 3;

[0315] The element structure 24 includes: a second conductive type main region 39 and a first conductive type source region 40 inside the main region 39, which are doubly diffused in the surface portion of the first semiconductor regions 7 and 30; and a gate electrode 38, which is formed on the first main surface 3 through a gate insulating film 42 and is opposite to the channel region 41 between the outer edge of the main region 39 and the outer edge of the source region 40.

[0316] Explanation of symbols

[0317] 1A—semiconductor device; 1B—semiconductor device; 1C—semiconductor device; 1D—semiconductor device; 1E—semiconductor device; 2—SiC semiconductor layer; 3—first main surface; 4—second main surface; 5A—side surface; 5B—side surface; 5C—side surface; 5D—side surface; 6—SiC semiconductor substrate; 7—SiC epitaxial layer; 8—active region; 9—outer region; 10—main surface insulating layer; 11A—insulating side surface; 11B—insulating side surface; 11C—insulating side surface; 11D—insulating side surface; 12—first main surface electrode; 13—passivation layer; 14A—side surface; 14B—side surface; 14C—side surface; 14D—side surface; 15—sub-pad opening; 16—resin layer; 17A—resin side surface; 17B—resin side surface; 17C—resin side surface; 17D—resin side surface; 18—pad opening; 19—second main surface electrode; 20—diode region; 21—protection region; 22—diode opening; 23—JBS structure; 24—unit cell; 25—gate trench; 26—gate insulating film; 27—gate electrode; 28—body region; 29—drain region; 30—drift region; 31—source region; 32—channel region; 33—body contact region; 34—unit cell; 35—gate trench; 36—gate insulating film; 37—gate electrode; 38—main body region; 39—drain region; 40—drift region; 41—source region; 42—channel region; 43—main body contact region; 44—unit cell; 45—gate trench; 46—gate insulating film; 47—gate electrode; 48—main body region; 49—drain region; 50—drift region; 51—source region; 52—channel region; 53—main body contact region; 54—unit cell; 55—gate trench; 56—gate insulating film; 57—gate electrode; 58—main body region; 59—drain region; 60—drift region; 61—source region; 62—channel region; 63—main body contact region; 64—unit cell; 65—gate trench; 66—gate insulating film; 67—gate electrode; 68—main body region; 69—drain region; 70—drift region; 71—source region; 72—channel region; 73—main body contact region; 74—unit cell; 75—gate 4—interlayer insulating film; 35—source electrode; 36—contact hole; 37—drain electrode; 38—gate electrode; 39—body region; 40—source region; 41—channel region; 42—gate insulating film; 43—collector region; 44—base region; 45—emitter region; 46—emitter electrode; 47—collector electrode; 48—SiC semiconductor wafer; 49—first wafer main surface; 50—second wafer main surface; 51—wafer side surface; 52—first wafer corner; 53—second wafer corner; 54—first chamfer; 55—second chamfer; 56—orientation plane; 5 7—device formation area; 58A—edge; 58B—edge; 58C—edge; 58D—edge; 59—predetermined cutting line; 60—first predetermined cutting line; 61—second predetermined cutting line; 62—element structure; 63—back electrode; 64—boundary surface; 65—circle; 66—quadrilateral; 67—long side; 68—short side; 69—processing unit; 70—processing unit; 71—laser mark; 72—laser mark; 73—base area; 74—shadow area; 75—base area; 76—shadow area; 191—silicide layer; 192—first electrode layer; 193—second electrode layer.

Claims

1. A semiconductor device, characterized in that: include: A SiC chip having a first main surface and a second main surface; a component structure formed on the first main surface; as well as an electrode formed on the second main surface, electrically connected to the element structure, and comprising a metal layer bonded to the second main surface; The arithmetic mean roughness Ra of the second main surface is greater than 30 nm. The second main surface is provided with laser marks formed by overlapping a plurality of processing units each having a rectangular shape or a circular shape in plan view.

2. The semiconductor device according to claim 1, wherein The SiC chip has a thickness of 50 μm or more and 350 μm or less.

3. The semiconductor device according to claim 2, wherein The SiC chip has a thickness of 100 μm or more and 350 μm or less.

4. The semiconductor device according to any one of claims 1 to 3, wherein The Ra of the second main surface is 100 nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein Each of the processing units is formed into a rectangular shape in plan view including short sides and long sides. The length of the long side is at least 5 times the length of the short side.

6. The semiconductor device according to claim 5, wherein The length of the short side of each of the processing units is greater than or equal to 0.1 mm and less than or equal to 0.4 mm, and the length of the long side of each of the processing units is greater than or equal to 1.0 mm and less than or equal to 4.0 mm.

7. The semiconductor device according to any one of claims 1 to 6, wherein The metal layer is a silicide layer.

8. The semiconductor device according to claim 7, wherein The silicide layer is a nickel silicide layer, The electrodes are formed of a metal containing Ni.

9. The semiconductor device according to any one of claims 1 to 8, wherein The first main surface is a silicon surface, and the second main surface is a carbon surface.

10. The semiconductor device according to any one of claims 1 to 9, wherein The device structure includes a Schottky barrier diode formed on the first main surface and having a Schottky metal forming a Schottky junction on the first main surface.

11. The semiconductor device according to claim 10, wherein The SiC chip includes: a first semiconductor region of the first conductivity type, which is formed on the surface portion of the first main surface; and a JBS structure, i.e., a junction barrier Schottky structure, which is formed by multiple semiconductor regions of the second conductivity type selectively formed in the Schottky junction formation area on the first main surface.

12. The semiconductor device according to any one of claims 1 to 9, wherein The SiC chip includes a first semiconductor region of a first conductivity type, the first semiconductor region of the first conductivity type being formed on a surface portion of the first main surface. The element structure includes: a gate trench formed on the first main surface; a gate electrode buried in the gate trench through a gate insulating film; and a second semiconductor region of the first conductivity type and a third semiconductor region of the second conductivity type, which are formed sequentially from the first main surface along the depth direction of the gate trench.

13. The semiconductor device according to claim 12, wherein: The SiC chip includes a first conductivity type drain region formed on a surface portion of the second main surface. The second semiconductor region is a source region.

14. The semiconductor device according to claim 12, wherein The SiC chip includes a second conductivity type collector region formed on a surface portion of the second main surface. The second semiconductor region is an emitter region.

15. The semiconductor device according to any one of claims 1 to 9, wherein The SiC chip includes a first semiconductor region of a first conductivity type, the first semiconductor region of the first conductivity type being formed on a surface portion of the first main surface. The element structure includes: a second conductive type body region doubly diffused in the surface portion of the first semiconductor region and a first conductive type source region inside the body region; and a gate electrode formed on the first main surface via a gate insulating film and opposite to the channel region between the outer edge of the body region and the outer edge of the source region.

Images