Semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes that sandwich a semiconductor layer of the first transistor, and the second gate electrode is provided on the semiconductor layer of the first transistor so as to overlap the first gate electrode. The second transistor includes a third gate electrode on a semiconductor layer of the second transistor. The second transistor is stacked on the first transistor, the third gate electrode overlaps the second gate electrode, the first conductor electrically connects the source electrode of the first transistor and the source electrode of the second transistor, and the second conductor electrically connects the drain electrode of the first transistor and the drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a transistor and a method for manufacturing a transistor. Another embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical field. Examples of the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices incorporating these devices, and methods for driving or manufacturing these devices.

[0003] Note that in this specification and other documents, the term "semiconductor device" refers to any device that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic equipment may also be considered semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed and are mainly used in LSIs, CPUs, memories, etc. A CPU is an assembly of elements including an integrated circuit (including at least transistors and capacitors) formed by processing a semiconductor wafer into a chip and having electrodes serving as connection terminals.

[0005] Integrated circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as components of various electronic devices.

[0006] In recent years, with the miniaturization and lightweighting of electronic devices, the demand for further high-density integrated circuits has increased. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. In order to achieve high density of integrated circuits, it is necessary to miniaturize the transistors that constitute the integrated circuits. As a micro transistor structure, for example, the Fin structure is well known, but as a micro structure to replace the Fin structure, non-patent document 1 discloses a GAA (Gate All Around: full-surround gate) nanosheet structure, in which silicon layers formed into nanosheets are stacked and surrounded by gate electrodes.

[0007] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate with an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). As semiconductor thin films that can be used in transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0008] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely low in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a memory device that utilizes the low leakage current characteristic of transistors using oxide semiconductors to achieve long-term retention of stored data.

[0009] Furthermore, Patent Document 3 discloses a microstructured transistor in which a source electrode layer and a drain electrode layer are provided in contact with the top surface of an oxide semiconductor layer.

[0010] [Prior technical literature]

[0011] [Patent Document]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0013] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0014] [Patent Document 3] International Patent Application Publication No. 2016 / 125052

[0015] [Non-patent literature]

[0016] [Non-patent document 1] 2017 Symposium on VLSI Technology Digest of Technical Papers, T230 Summary of the Invention

[0017] Technical problem to be solved by the invention

[0018] One method for achieving a semiconductor device with high on-state current is to increase the number of transistors included in the semiconductor device and connect them in parallel, placing them adjacent to each other on the same substrate. However, this method increases the area occupied by each semiconductor device within the substrate surface, making it difficult to manufacture a compact and highly integrated semiconductor device.

[0019] As a structure for a semiconductor device capable of achieving a high on-state current without increasing the area occupied within the substrate surface, the GAA nanosheet structure (see Non-Patent Document 1) and the like have been disclosed. However, this structure is based on the premise that silicon is used for the semiconductor layer that forms the channel of the transistor. Therefore, from the perspective of manufacturing methods, etc., it is sometimes difficult to use materials other than silicon for this structure.

[0020] In view of this, one of the objects of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with small unevenness in the electrical characteristics of the transistor. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. In addition, one of the objects of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0021] Note that the inclusion of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the aforementioned objectives. Objectives other than those described above may be extracted from the description, drawings, and claims.

[0022] Means of solving technical problems

[0023] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulator, a first conductor, a second conductor, and a third conductor, wherein the first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator, and a second gate electrode, and the second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator, and a third gate electrode, wherein the first gate insulator is provided on the first gate electrode, the first semiconductor layer is provided on the first gate insulator so as to have a region overlapping with the first gate electrode, the second gate insulator is provided on the first semiconductor layer, the second gate electrode is provided on the second gate insulator so as to have a region overlapping with the first gate electrode, and the first source electrode and the first drain electrode are provided so as to overlap with each other when viewed from a planar perspective. The first insulator is provided on the second gate electrode, the second semiconductor layer is provided on the first insulator so as to have a region overlapping with the first semiconductor layer, the third gate insulator is provided on the second semiconductor layer, the third gate electrode is provided on the third gate insulator so as to have a region overlapping with the second gate electrode, the second source electrode and the second drain electrode are provided on the second semiconductor layer so as to sandwich the third gate electrode when viewed from a plane, the first conductor is provided so as to penetrate the second source electrode and the second semiconductor layer and have a region in contact with the first source electrode, the second conductor is provided so as to penetrate the second drain electrode and the second semiconductor layer and have a region in contact with the first drain electrode, and the third conductor is provided so as to have regions in contact with the first gate electrode, the second gate electrode, and the third gate electrode.

[0024] Furthermore, in the above semiconductor device, the first transistor and the second transistor preferably include a metal oxide in their semiconductor layers.

[0025] In addition, in the above-mentioned semiconductor device, it is preferred that it includes a second insulator covering the first transistor and a third insulator covering the second transistor, the third insulator, the second source electrode, the second semiconductor layer and the second insulator have a first opening reaching the first source electrode, the third insulator, the second drain electrode, the second semiconductor layer and the second insulator have a second opening reaching the first drain electrode, the second conductor is arranged in a manner that contacts the side walls and bottom surface of the first opening, and the third conductor is arranged in a manner that contacts the side walls and bottom surface of the second opening.

[0026] Furthermore, in the above-described semiconductor device, the length of the third gate electrode in the channel width direction is preferably shorter than the length of the second gate electrode in the channel width direction.

[0027] In addition, in the above-mentioned semiconductor device, preferably, the width between the first source electrode and the first drain electrode and the width between the second source electrode and the second drain electrode are both less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm or less than 10nm and are greater than 1nm or greater than 5nm.

[0028] In addition, in the above-mentioned semiconductor device, it is preferred that it includes a second insulator covering the first transistor and a third insulator covering the second transistor, the second insulator has a first opening reaching the first semiconductor layer between the first source electrode and the first drain electrode, the third insulator has a second opening reaching the second semiconductor layer between the second source electrode and the second drain electrode, the second gate insulator is arranged in a manner that contacts the side walls and bottom surface of the first opening, the second gate electrode is arranged on the second gate insulator in a manner that is embedded in the first opening, the third gate insulator is arranged in a manner that contacts the side walls and bottom surface of the second opening, the third gate electrode is arranged on the third gate insulator in a manner that is embedded in the second opening, the height of the top surface of the second gate insulator is approximately consistent with the height of the top surface of the second gate electrode, and the height of the top surface of the third gate insulator is approximately consistent with the height of the top surface of the third gate electrode.

[0029] In addition, in the above-mentioned semiconductor device, it is preferred that the side surfaces of the first source electrode and the first drain electrode that do not face the second gate electrode are roughly aligned with the side surfaces of the first semiconductor layer, and the side surfaces of the second source electrode and the second drain electrode that do not face the third gate electrode are roughly aligned with the side surfaces of the second semiconductor layer.

[0030] Furthermore, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulator, a first conductor, a second conductor, and a third conductor, wherein the first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator, and a second gate electrode, and the second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator, and a third gate electrode, wherein the first gate insulator is provided on the first gate electrode, the first semiconductor layer is provided on the first gate insulator so as to have a region overlapping with the first gate electrode, the second gate insulator is provided on the first semiconductor layer, the second gate electrode is provided on the second gate insulator so as to have a region overlapping with the first gate electrode, and the first source electrode and the first drain electrode are provided on the first gate insulator so as to sandwich the second gate electrode when viewed from a planar perspective. On the semiconductor layer, a first insulator is arranged on the second gate electrode, the second semiconductor layer is arranged on the first insulator in a manner that has an overlapping area with the first semiconductor layer, a third gate insulator is arranged on the second semiconductor layer, the third gate electrode is arranged on the third gate insulator in a manner that has an overlapping area with the second gate electrode, the second source electrode and the second drain electrode are arranged on the second semiconductor layer in a manner that sandwiches the third gate electrode when viewed from a plane, the first conductor is arranged in a manner that contacts the side surfaces of the first semiconductor layer, the side surfaces of the first source electrode, the side surfaces of the second semiconductor layer, and the side surfaces of the second source electrode, the second conductor is arranged in a manner that contacts the side surfaces of the first semiconductor layer, the side surfaces of the first drain electrode, the side surfaces of the second semiconductor layer, and the side surfaces of the second drain electrode, and the third conductor is arranged in a manner that has an area that contacts the top surface of the first gate electrode, the top surface of the second gate electrode, and the top surface of the third gate electrode.

[0031] Furthermore, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulator, a first conductor, and a second conductor, wherein the first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator, and a second gate electrode, and the second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator, and a third gate electrode, wherein the first gate insulator is provided on the first gate electrode, the first semiconductor layer is provided on the first gate insulator so as to have a region overlapping with the first gate electrode, the second gate insulator is provided on the first semiconductor layer, and the second gate electrode is provided on the second gate insulator so as to have a region overlapping with the first gate electrode and has a region in contact with a top surface of the first gate electrode through openings provided in the first gate insulator and the second gate insulator. The first source electrode and the first drain electrode are arranged on the first semiconductor layer so as to sandwich the second gate electrode when viewed from a planar surface. The first insulator is arranged on the second gate electrode. The second semiconductor layer is arranged on the first insulator so as to have a region overlapping with the first semiconductor layer. The third gate insulator is arranged on the second semiconductor layer so as to have a region overlapping with the second gate electrode and has a region in contact with the top surface of the second gate electrode through openings provided in the first insulator and the third gate insulator. The second source electrode and the second drain electrode are arranged on the second semiconductor layer so as to sandwich the third gate electrode when viewed from a planar surface. The first conductor is arranged so as to penetrate the second source electrode and the second semiconductor layer and have a region in contact with the first source electrode. The second conductor is arranged so as to penetrate the second drain electrode and the second semiconductor layer and have a region in contact with the first drain electrode.

[0032] Furthermore, in the above-described semiconductor device, it is preferable that an end portion of the second gate electrode and an end portion of the third gate electrode are substantially aligned with each other when viewed from a planar perspective.

[0033] In addition, one embodiment of the present invention is a semiconductor device including: a first conductor; a first insulator on the first conductor; a first oxide on the first insulator; a second insulator, a second conductor, and a third conductor on the first oxide; a fourth conductor on the second insulator; a third insulator on the second and fourth conductors; a second oxide on the third insulator; a fourth insulator, a fifth conductor, and a sixth conductor on the second oxide; a seventh conductor on the fourth insulator; an eighth conductor penetrating the fifth conductor and the second oxide and in contact with the second conductor; a ninth conductor penetrating the sixth conductor and the second oxide and in contact with the third conductor; and a tenth conductor in contact with a top surface of the first conductor, a top surface of the fourth conductor, and a top surface of the seventh conductor, wherein the first conductor overlaps with the fourth conductor via the first oxide, the fourth conductor overlaps with the seventh conductor via the second oxide, the second conductor is electrically connected to the fifth conductor, the third conductor is electrically connected to the sixth conductor, the first conductor, the fourth conductor, and the seventh conductor are electrically connected, and the third insulator has a region in contact with a top surface of the second insulator and a top surface of the fourth conductor.

[0034] Furthermore, in the semiconductor device, preferably, the top surface of the second insulator is substantially equal to the top surface of the fourth conductor, and the top surface of the fourth insulator is substantially equal to the top surface of the seventh conductor.

[0035] In addition, in the above-mentioned semiconductor device, it is preferred that the side surfaces of the second and third conductors not facing the fourth conductor are roughly aligned with the side surfaces of the first oxide, and the side surfaces of the fifth and sixth conductors not facing the seventh conductor are roughly aligned with the side surfaces of the second oxide.

[0036] Effects of the Invention

[0037] According to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with small variations in the electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0038] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device.

[0040] Figure 2 is a cross-sectional view showing an example of a semiconductor device.

[0041] Figure 3A and Figure 3B is a plan view showing an example of a semiconductor device.

[0042] Figure 4A and Figure 4B is a cross-sectional view showing an example of a semiconductor device.

[0043] Figure 5A and Figure 5B is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 6 is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 7 is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 8A and Figure 8B is a cross-sectional view showing an example of a semiconductor device.

[0047] Figure 9A and Figure 9B is a cross-sectional view showing an example of a semiconductor device.

[0048] Figure 10A is a plan view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device.

[0049] Figure 11A and Figure 11B is a plan view showing an example of a semiconductor device.

[0050] Figure 12 is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 13A is a plan view showing an example of a semiconductor device. Figure 13B is a cross-sectional view showing an example of a semiconductor device.

[0052] Figure 14A is a plan view showing an example of a semiconductor device. Figure 14B is a cross-sectional view showing an example of a semiconductor device.

[0053] Figure 15 is a plan view showing an example of a semiconductor device.

[0054] Figure 16 is a cross-sectional view showing an example of a semiconductor device.

[0055] Figure 17 is a cross-sectional view showing an example of a semiconductor device.

[0056] Figure 18 is a plan view showing an example of a semiconductor device.

[0057] Figure 19 is a cross-sectional view showing an example of a semiconductor device.

[0058] Figure 20 is a plan view showing an example of a semiconductor device.

[0059] Figure 21 is a cross-sectional view showing an example of a semiconductor device.

[0060] Figure 22 is a plan view showing an example of a semiconductor device.

[0061] Figure 23 is a cross-sectional view showing an example of a semiconductor device.

[0062] Figure 24 is a cross-sectional view showing an example of a semiconductor device.

[0063] Figure 25 is a cross-sectional view showing an example of a semiconductor device.

[0064] Figure 26 is a plan view showing an example of a semiconductor device.

[0065] Figure 27 is a cross-sectional view showing an example of a semiconductor device.

[0066] Figure 28A and Figure 28B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0067] Figure 29A and Figure 29BThis is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0068] Figure 30A and Figure 30B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0069] Figure 31A and Figure 31B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0070] Figure 32A and Figure 32B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0071] Figure 33A and Figure 33B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0072] Figure 34A and Figure 34B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0073] Figure 35A and Figure 35B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0074] Figure 36A and Figure 36B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0075] Figure 37A and Figure 37B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0076] Figure 38A and Figure 38B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0077] Figure 39A and Figure 39B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0078] Figure 40A and Figure 40B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0079] Figure 41A and Figure 41B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0080] Figure 42A and Figure 42BThis is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0081] Figure 43A and Figure 43B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0082] Figure 44A and Figure 44B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0083] Figure 45A and Figure 45B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0084] Figure 46A and Figure 46B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0085] Figure 47A and Figure 47B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0086] Figure 48A and Figure 48B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0087] Figure 49A and Figure 49B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0088] Figure 50A and Figure 50B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0089] Figure 51A and Figure 51B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0090] Figure 52A and Figure 52B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0091] Figure 53A and Figure 53B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0092] Figure 54A and Figure 54B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0093] Figure 55A and Figure 55BThis is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0094] Figure 56A and Figure 56B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0095] Figures 57A to 57C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0096] Figure 58A and Figure 58B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0097] Figure 59A and Figure 59B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0098] Figure 60A and Figure 60B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0099] Figure 61A and Figure 61B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0100] Figure 62A and Figure 62B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0101] Figure 63A and Figure 63B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0102] Figure 64A and Figure 64B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0103] Figure 65A and Figure 65B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0104] Figure 66A and Figure 66B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0105] Figure 67A and Figure 67B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0106] Figure 68A and Figure 68B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0107] Figure 69A and Figure 69B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0108] Figure 70A and Figure 70B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0109] Figure 71A and Figure 71B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0110] Figure 72A and Figure 72B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0111] Figure 73A and Figure 73B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0112] Figure 74A and Figure 74B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0113] Figure 75A and Figure 75B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0114] Figure 76A and Figure 76B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0115] Figure 77A and Figure 77B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0116] Figure 78A and Figure 78B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0117] Figure 79A and Figure 79B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0118] Figure 80A and Figure 80B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0119] Figure 81A and Figure 81B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0120] Figure 82A and Figure 82B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0121] Figure 83A and Figure 83B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0122] Figure 84A and Figure 84B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0123] Figure 85A and Figure 85B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0124] Figure 86A and Figure 86B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0125] Figure 87A and Figure 87B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0126] Figure 88A and Figure 88B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0127] Figure 89A and Figure 89B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0128] Figure 90A and Figure 90B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0129] Figure 91A and Figure 91B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0130] Figure 92A and Figure 92B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0131] Figure 93A and Figure 93B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0132] Figure 94A and Figure 94B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0133] Figure 95A and Figure 95B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0134] Figure 96A and Figure 96B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0135] Figure 97A and Figure 97B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0136] Figure 98A and Figure 98B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0137] Figure 99A and Figure 99B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0138] Figure 100A and Figure 100B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0139] Figure 101A and Figure 101B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0140] Figure 102A and Figure 102B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0141] Figure 103A and Figure 103B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0142] Figure 104A and Figure 104B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0143] Figure 105A and Figure 105B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0144] Figure 106A is a plan view showing an example of a semiconductor device. Figure 106B is a cross-sectional view showing an example of a semiconductor device.

[0145] Figure 107A is a cross-sectional view showing an example of a semiconductor device. Figure 107B This is a circuit diagram illustrating a semiconductor device.

[0146] Figure 108A and Figure 108B is a diagram showing an example of a semiconductor device.

[0147] Figures 109A to 109J is a diagram illustrating an example of an electronic device.

[0148] Figures 110A to 110E is a diagram illustrating an example of an electronic device.

[0149] Figures 111A to 111C is a diagram illustrating an example of an electronic device.

[0150] Figure 112 This is a diagram showing an example of space equipment. DETAILED DESCRIPTION

[0151] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily appreciate that the embodiments and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the embodiments described below.

[0152] Note that in the structures of the invention described below, the same symbols are used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when parts with the same function are represented, the same hatching is sometimes used without adding a special symbol.

[0153] Furthermore, for ease of understanding, the positions, sizes, and ranges of components shown in the drawings may not necessarily represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0154] Note that in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these numbers do not limit the number of components or the order of the components (for example, the order of steps or the order of stacking). In addition, the ordinal numbers assigned to components in one part of this specification may not be consistent with the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0155] Furthermore, depending on the situation or circumstances, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film." Furthermore, "insulating film" may be interchanged with "insulating layer." Furthermore, depending on the situation or circumstances, "conductive body" may be interchanged with "conductive layer" or "conductive film." Furthermore, depending on the situation or circumstances, "insulator" may be interchanged with "insulating layer" or "insulating film."

[0156] The opening includes, for example, a groove, a slit, etc. In addition, a region where an opening is formed may be referred to as an opening portion.

[0157] In addition, the drawings used in this embodiment illustrate a case where the sidewalls of the insulator in the opening portion of the insulator are approximately perpendicular to the substrate surface or the formed surface, but a tapered shape is also possible. Note that in this specification, etc., "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, this also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0158] In this specification, etc., a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to a substrate surface or a formed surface. For example, this refers to a shape in which the angle formed between the inclined side surface and the substrate surface or the formed surface (hereinafter sometimes referred to as the tapered angle) is less than 90°. Note that the side surface of a component and the substrate surface do not necessarily need to be completely flat; they may also be approximately planar with slight curvature or have fine irregularities.

[0159] In this specification, etc., "island-like" refers to a state in which two or more layers made of the same material formed in the same process are physically separated.

[0160] In this specification, "substantially consistent in height" refers to a structure in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are substantially equal when viewed from a cross section. Furthermore, in this specification, "substantially consistent" includes both completely consistent and approximately consistent structures.

[0161] In this specification and other documents, "source" refers to a source region, source electrode, and part or all of the source wiring. A source region is a region in a semiconductor layer with a resistivity below a certain value. A source electrode is a conductive layer having a portion connected to the source region. Source wiring is wiring that electrically connects the source electrode of at least one transistor to other electrodes or other wiring.

[0162] Throughout this specification and other documents, the term "drain" refers to a portion or all of a drain region, drain electrode, and drain wiring. A drain region is a region of a semiconductor layer with a resistivity below a certain value. A drain electrode is a conductive layer having a portion connected to the drain region. Drain wiring is wiring that electrically connects the drain electrode of at least one transistor to other electrodes or other wiring.

[0163] (Implementation Method 1)

[0164] One embodiment of the present invention is a semiconductor device including a transistor. A transistor according to one embodiment of the present invention includes n island-shaped semiconductor layers (n is an integer greater than or equal to 2) that form a channel. In other words, n semiconductor layers are used as the channel of the transistor. In addition, n semiconductor layers are stacked. Note that the semiconductor layer of the first layer is represented as the first semiconductor layer, and the semiconductor layer of the second layer is represented as the second semiconductor layer. In addition, the semiconductor layer of the i-th layer (i is an integer greater than or equal to 1 and less than or equal to n) is represented as the i-th semiconductor layer, and the semiconductor layer of the n-th layer is represented as the n-th semiconductor layer.

[0165] Each of the n semiconductor layers has a source and a drain. In the n semiconductor layers, the sources are electrically connected to one another, and the drains are electrically connected to one another.

[0166] A first conductor is disposed below the first semiconductor layer. The first conductor has a region overlapping with the first semiconductor layer. Furthermore, a second conductor is disposed above the first semiconductor layer and below the second semiconductor layer. The second conductor has regions overlapping with both the first and second semiconductor layers. In other words, the second semiconductor layer has regions overlapping with the first semiconductor layer via the second conductor. The second conductor has regions overlapping with the first conductor via the first semiconductor layer and regions not overlapping with the first conductor via the first semiconductor layer. Furthermore, an (i+1)th conductor is disposed above the (i)th semiconductor layer and below the (i+1)th semiconductor layer. The (i+1)th conductor has regions overlapping with the (i)th semiconductor layer and the (i+1)th semiconductor layer. In other words, the (i+1)th semiconductor layer has regions overlapping with the (i)th semiconductor layer via the (i+1)th conductor. The (i+1)th conductor has regions overlapping with the (i)th conductor via the (i)th semiconductor layer and regions not overlapping with the (i)th conductor via the (i)th semiconductor layer. Furthermore, an (n+1)th conductor is disposed above the (n)th semiconductor layer. The (n+1)th conductor has regions overlapping with the (n)th semiconductor layer. Furthermore, the first to n+1th electrical conductors are electrically connected to each other and serve as gate electrodes of transistors.

[0167] In other words, a transistor according to one embodiment of the present invention includes n semiconductor layers and (n+1) conductors. By providing a conductor serving as a gate electrode above and below each semiconductor layer, the channel width of the transistor can be increased, thereby increasing the on-state current of the transistor. Furthermore, by stacking n semiconductor layers, a transistor with a large on-state current can be realized without increasing the area occupied within the substrate surface. In other words, a transistor with a small size, high integration density, and large on-state current can be realized.

[0168] Note that each semiconductor layer has a channel, a source, and a drain. In addition, a conductor serving as a gate electrode is provided above and below each semiconductor layer. That is, it can be considered that each semiconductor layer constitutes a transistor. Therefore, a semiconductor device according to one embodiment of the present invention includes n semiconductor layers, so it can be said to be composed of n transistors. The n transistors are stacked. In addition, in the n transistors, the sources are electrically connected to each other, the drains are electrically connected to each other, and the gate electrodes are electrically connected to each other. That is, a semiconductor device according to one embodiment of the present invention is composed of n transistors that are stacked and connected in parallel. By adopting this structure, a semiconductor device with a large on-state current can be realized without increasing the occupied area within the substrate surface. That is, a semiconductor device that is fine, highly integrated, and has a large on-state current can be realized.

[0169] One method for increasing the on-state current of a semiconductor device is to increase the number of transistors included in the semiconductor device and connect them in parallel to improve the overall current generation capability of the semiconductor device. For example, by connecting m (m is an integer greater than or equal to 1) transistors of the same size and made of the same material in parallel (each transistor having the same current generation capability), the semiconductor device as a whole can output m times the on-state current of a single transistor.

[0170] Figures 106A to 107B A structural example of a semiconductor device 300 is shown in which three transistors of the same size and formed of the same material are connected in parallel. Figure 106A is a plan view of the semiconductor device 300 . Figure 106B It is along Figure 106A FIG. 3 is a cross-sectional view of the semiconductor device 300 taken along the dashed line B1 - B2 . Figure 107A It is along Figure 106A FIG. 1 is a cross-sectional view of the semiconductor device 300 taken along the dashed line B3 - B4 . Figure 107B 3 is a circuit diagram showing the structure of the semiconductor device 300. Note that in this specification and the like, a plan view refers to a view when an object is viewed from a plane.

[0171] like Figure 106A 、 Figure 107A and Figure 107B As shown, the semiconductor device 300 includes a transistor 200_1, a transistor 200_2, and a transistor 200_3. Figure 106A As shown, transistors 200_1, 200_2, and 200_3 are adjacently arranged along a dashed line B3-B4. Transistors 200_1, 200_2, and 200_3 all have the same channel length and width and have the same current generating capability.

[0172] like Figure 106BAs shown, the transistor 200_1 is provided so as to have a region overlapping with the conductor 205 (the conductor 205 a and the conductor 205 b ) with the insulator 222 interposed therebetween.

[0173] Conductor 205 is provided so as to be embedded in insulator 215 on a substrate (not shown) and insulator 216 on insulator 215. Conductor 205 includes conductor 205a and conductor 205b on conductor 205a. An opening is provided in insulator 216 that reaches insulator 215, so that conductor 205a is provided so as to contact the side surface of insulator 216 and the top surface of insulator 215 in the opening. Furthermore, conductor 205b is provided on conductor 205a so as to be embedded in the opening.

[0174] The conductor 205a is formed of a conductive material having a function of suppressing oxygen diffusion, and the conductor 205b is formed of a material having higher conductivity than the conductor 205a.

[0175] The top surface of conductor 205a (the surface in contact with insulator 222), the top surface of conductor 205b, and the top surface of insulator 216 are all at substantially the same height. Insulator 222 is provided so as to contact the top surface of conductor 205a, the top surface of conductor 205b, and the top surface of insulator 216.

[0176] The transistor 200_1 includes an oxide 230_1 (an oxide 230a1 and an oxide 230b1), a conductor 242a1, a conductor 242b1, an insulator 250, and a conductor 260 (a conductor 260a and a conductor 260b).

[0177] In transistor 200_1, oxide 230_1 is used as a semiconductor layer forming a channel. Conductor 242a1 is used as one of a source electrode and a drain electrode. Conductor 242b1 is used as the other of the source electrode and the drain electrode. Insulator 250 is used as a first gate insulator. Conductor 260 is used as a first gate electrode (also called a top gate electrode). Therefore, Figure 106B It can be said that it is a cross-sectional view of the transistor 200_1 in the channel length direction. Figure 107A It can be said to be a cross-sectional view of the transistor 200_1 in the channel width direction.

[0178] Furthermore, the conductor 205 can be used as the second gate electrode (also referred to as a bottom gate electrode or back gate electrode) of the transistor 200_1. In this case, the insulator 222 serves as the second gate insulator of the transistor 200_1. For example, when the conductor 260 is electrically connected to the conductor 205 so as to sandwich the oxide 230_1 from above and below, a gate electric field can be applied from above and below the oxide 230_1. In this case, by making the thickness of the insulator 250 and the thickness of the insulator 222 approximately equal, a gate electric field of uniform strength can be applied from above and below the oxide 230.

[0179] Here, if Figure 106A and Figure 107A As shown, conductor 205 is provided so as to extend in the channel width direction of transistors 200_1, 200_2, and 200_3. Therefore, conductor 205 can be used not only as the second gate electrode of transistor 200_1, but also as the second gate electrodes of transistors 200_2 and 200_3. Similarly, insulator 222 is provided in a planar shape across transistors 200_1, 200_2, and 200_3. Therefore, insulator 222 can be used not only as the second gate insulator of transistor 200_1, but also as the second gate insulator of transistors 200_2 and 200_3.

[0180] The oxide 230_1 includes an oxide 230a1 and an oxide 230b1 on the oxide 230a1. The oxide 230_1 is provided in an island shape on the insulator 222 so as to have a region overlapping with the conductor 205.

[0181] Conductor 260 is provided on oxide 230b1 via insulator 250. Conductor 260 has a region that overlaps with conductor 205 via oxide 230b1. Conductor 260 includes conductor 260a and conductor 260b on conductor 260a. Conductor 260a is formed of a conductive material that inhibits oxygen diffusion. Conductor 260b is formed of a material with higher conductivity than conductor 260a.

[0182] Furthermore, when viewed from a planar perspective, the conductors 242a1 and 242b1 are provided on the oxide 230b1 in such a manner as to sandwich the insulator 250 and the conductor 260. Figure 106B As shown, the side surfaces of the conductors 242 a 1 and 242 b 1 that do not face the conductor 260 are substantially aligned with the side surfaces of the oxides 230 a 1 and 230 b 1 .

[0183] Insulator 275 is provided in contact with the top surface of conductor 242a1, the top surface of conductor 242b1, oxide 230a1, substantially aligned side surfaces of oxide 230b1 and conductor 242a1, substantially aligned side surfaces of oxide 230a1, oxide 230b1, and conductor 242b1, and the top surface of insulator 222. Insulator 275 has the function of suppressing diffusion of impurities from above transistor 200_1 into oxide 230_1.

[0184] An insulator 280 is provided over transistor 200_1 and insulator 275. The top surface of insulator 280 is flattened. An opening is formed in the region of insulator 280 and insulator 275 that overlaps with conductor 205. Insulator 250 is provided so as to contact the side surfaces of insulator 280, side surfaces of insulator 275, side surfaces of conductor 242a1, side surfaces of conductor 242b1, and the top surface of oxide 230b1 within the opening. Conductor 260a is provided over insulator 250, and conductor 260b is provided on conductor 260a so as to fit into the opening.

[0185] In addition, if Figure 106A and Figure 107A As shown, insulator 250 and conductor 260 cover the side and top surfaces of each oxide (oxide 230_1 to oxide 230_3) of transistors 200_1 to 200_3 in the channel width direction of transistors 200_1 to 200_3. Therefore, insulator 250 can be used not only as the first gate insulator of transistor 200_1, but also as the first gate insulator of transistors 200_2 and 200_3. Similarly, conductor 260 can be used not only as the first gate electrode of transistor 200_1, but also as the first gate electrode of transistors 200_2 and 200_3.

[0186] Furthermore, in the channel width direction of transistors 200_1 to 200_3, conductor 205 is provided below transistors 200_1 to 200_3 via insulator 222. Therefore, the oxides (oxides 230_1 to 230_3) of transistors 200_1 to 200_3 can be surrounded by the electric field from conductor 260 and the electric field from conductor 205.

[0187] The top surface of insulator 250 (the surface in contact with insulator 286), the top surface of conductor 260a (the surface in contact with insulator 286), the top surface of conductor 260b, and the top surface of insulator 280 are all approximately the same height. Insulator 286 is provided so as to be in contact with the top surface of insulator 250, the top surface of conductor 260a, the top surface of conductor 260b, and the top surface of insulator 280. If insulator 286 contains a large amount of oxygen, the oxygen contained in insulator 286 can be supplied to insulator 280 during deposition of insulator 286 or during a subsequent heat treatment.

[0188] Insulator 283 is provided on insulator 286, and insulator 287 is provided on insulator 283. Insulator 283 has the function of suppressing the diffusion of impurities from above insulator 286 into transistor 200_1. If insulator 215 also has the same function as insulator 283, both the top and bottom of transistor 200_1 can be covered with an insulator that suppresses impurity diffusion. The top surface of insulator 287 is flat.

[0189] Insulators 287, 283, 286, 280, and 275 have openings that reach conductor 242a1. Conductor 244a (conductor 244a1 and conductor 244a2) is disposed within the opening. Conductor 244a includes conductor 244a1 and conductor 244a2 on conductor 244a1. Conductor 244a1 is disposed in contact with the sidewalls of the opening and the top surface of conductor 242a1, while conductor 244a2 is disposed so as to be embedded in the opening.

[0190] Insulators 287, 283, 286, 280, and 275 also have openings that reach conductor 242b1. Conductors 244b (conductors 244b1 and 244b2) are disposed within these openings. Conductors 244b include conductor 244b1 and conductor 244b2 on conductor 244b1. Conductor 244b1 is disposed in contact with the sidewalls of the opening and the top surface of conductor 242b1, while conductor 244b2 is disposed so as to be embedded within the opening.

[0191] Conductor 244a1 and conductor 244b1 are formed of a conductive material that has the function of suppressing oxygen diffusion. In addition, conductor 244a2 is formed of a material with higher conductivity than conductor 244a1. Conductor 244b2 is formed of a material with higher conductivity than conductor 244b1.

[0192] The top surface of conductor 244a1 (the surface in contact with conductor 245a), the top surface of conductor 244a2, the top surface of conductor 244b1 (the surface in contact with conductor 245b), the top surface of conductor 244b2, and the top surface of insulator 287 are all approximately the same height. Conductor 245a is arranged so as to contact the top surface of conductor 244a1, the top surface of conductor 244a2, and the top surface of insulator 287. Conductor 245b is arranged so as to contact the top surface of conductor 244b1, the top surface of conductor 244b2, and the top surface of insulator 287. Conductors 245a and 245b are both used as wiring. Conductor 244a serves as a plug connecting conductor 242a1 and conductor 245a. Conductor 244b serves as a plug connecting conductor 242b1 and conductor 245b.

[0193] The conductor 255 is provided between the conductor 245a and the conductor 245b in such a manner as to be in contact with the top surface of the insulator 287. The conductor 255 is provided so as to have an area overlapping with the conductor 205 and the conductor 260. Figure 106A and Figure 107A As shown, the conductor 255 is provided so as to extend in the channel width direction of the transistor 200_1, the transistor 200_2, and the transistor 200_3. Figure 106A and Figure 107A Although not shown, the conductor 205, the conductor 260, and the conductor 255 extending toward the B4 side are electrically connected to each other. Therefore, the conductor 255 is used as a wiring connected to the conductor 260 serving as the first gate electrode and the conductor 205 serving as the second gate electrode.

[0194] Although mainly Figure 106B The above components are described using the transistor 200_1 as an example. However, the same description can be applied to the transistor 200_2 and the transistor 200_3 by swapping the last digits (the digits after “_”) of the symbols.

[0195] Figure 107B It is an explanation Figures 106A to 107A FIG. 1 is a circuit diagram showing the connection relationship between the transistors 200_1 to 200_3 included in the semiconductor device 300. Figure 107B As shown, one of the source and drain of transistors 200_1 through 200_3 is electrically connected to each other via conductor 245a. The other of the source and drain of transistors 200_1 through 200_3 is electrically connected to each other via conductor 245b. The gates of transistors 200_1 through 200_3 are electrically connected. In other words, transistors 200_1 through 200_3 are connected in parallel.

[0196] Since the transistors 200_1 to 200_3 are connected in parallel, the semiconductor device 300 can output three times the on-state current of one transistor (assuming that the transistors 200_1 to 200_3 have the same current generating capability).

[0197] However, in Figures 106A to 107B In the structure shown, transistors 200_1 to 200_3 are all arranged adjacent to each other on the same substrate. Figures 106A to 107B The structure shown is very effective as a semiconductor device structure for obtaining a large on-state current. However, there is still room for further structural improvement in order to realize a micro-sized and highly integrated semiconductor device.

[0198] As a structure for a semiconductor device capable of achieving a high on-state current without increasing the area occupied within the substrate surface, the GAA nanosheet structure (see Non-Patent Document 1) and the like have been disclosed. However, this structure assumes the use of silicon for the semiconductor layer forming the channel of the transistor, and, for example, from the perspective of manufacturing methods, it is difficult to use the oxide of one embodiment of the present invention in place of silicon.

[0199] In view of the above problems, in a semiconductor device according to one embodiment of the present invention, multiple transistors have a stacked structure corresponding to the number of transistors, rather than being arranged adjacent to each other on the same substrate. This structure allows the semiconductor device according to one embodiment of the present invention to output a high on-state current without increasing the area occupied within the substrate surface. Furthermore, it expands the range of materials that can be used for the semiconductor layer forming the channel of the transistor.

[0200] Hereinafter, a configuration example of a semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. Note that the following description may omit portions that overlap with the above description.

[0201] <Structural Example 1 of Semiconductor Device>

[0202] Figure 1A 、 Figure 1B and Figure 2 A structural example of a semiconductor device 200 according to one embodiment of the present invention is shown. Figure 1A is a plan view of the semiconductor device 200 . Figure 1B It is along Figure 1A FIG. 2 is a cross-sectional view of the semiconductor device 200 taken along the dashed line A1 - A2 . Figure 2 It is along Figure 1A The cross-sectional view of the semiconductor device 200 is shown along the dashed line A3 - A4 .

[0203] The semiconductor device 200 according to one embodiment of the present invention includes a conductor 205 (conductor 205a and conductor 205b), a transistor 200_1, a transistor 200_2, a transistor 200_3, a conductor 243a (conductor 243a1 and conductor 243a2), a conductor 244a (conductor 244a1 and conductor 244a2), a conductor 243b (conductor 243b1 and conductor 243b2), a conductor 244b (conductor 244b1 and conductor 244b2), and a conductor 254 (conductor 254a and conductor 254b). Note that Figure 1B and Figure 2 The semiconductor device 200 is shown as including three transistors, but is not limited thereto. The semiconductor device 200 only needs to include at least two transistors. Therefore, the semiconductor device 200 may include two transistors or four or more transistors.

[0204] The transistor 200_1 is provided on the insulator 222_1 so as to have a region overlapping with the conductor 205 .

[0205] The transistor 200_2 is stacked on the transistor 200_1 so as to overlap with the transistor 200_1 .

[0206] The transistor 200_3 is stacked on the transistor 200_2 so as to overlap with the transistor 200_2 .

[0207] therefore, Figure 1B It can also be said that it is a cross-sectional view of each channel length direction of the transistor 200_1, the transistor 200_2, and the transistor 200_3. Figure 2 It can also be said to be a cross-sectional view of the transistor 200_1 , the transistor 200_2 , and the transistor 200_3 in the channel width direction.

[0208] The following describes the structures of transistors 200_1 to 200_3 included in a semiconductor device 200 according to one embodiment of the present invention. Figures 106A to 107A The content in the description is repeated.

[0209] like Figure 1B As shown, the transistor 200_1 is provided so as to have a region overlapping with the conductor 205 (the conductor 205 a and the conductor 205 b ) via the insulator 222_1 .

[0210] Conductor 205 is provided so as to be embedded in insulator 215 on a substrate (not shown) and insulator 216 on insulator 215. Conductor 205 includes conductor 205a and conductor 205b on conductor 205a. An opening is provided in insulator 216 that reaches insulator 215, so that conductor 205a is provided so as to contact the side surface of insulator 216 and the top surface of insulator 215 in the opening. Furthermore, conductor 205b is provided on conductor 205a so as to be embedded in the opening.

[0211] Conductor 205a is preferably formed of a conductive material that has the function of inhibiting oxygen diffusion. By using this conductive material, the decrease in conductivity caused by oxidation of conductor 205b can be suppressed. In addition, conductor 205b is preferably formed of a material with higher conductivity than conductor 205a.

[0212] The top surface of conductor 205a (the surface in contact with insulator 222_1), the top surface of conductor 205b, and the top surface of insulator 216 are all at substantially the same height. Insulator 222_1 is provided so as to be in contact with the top surface of conductor 205a, the top surface of conductor 205b, and the top surface of insulator 216.

[0213] The transistor 200_1 includes an oxide 230_1 (an oxide 230a1 and an oxide 230b1), a conductor 242a1, a conductor 242b1, an insulator 250_1, and a conductor 260_1 (a conductor 260a1 and a conductor 260b1).

[0214] In transistor 200_1, oxide 230_1 serves as a semiconductor layer forming a channel. Conductor 242a1 serves as one of a source electrode and a drain electrode. Conductor 242b1 serves as the other of the source electrode and the drain electrode. Insulator 250_1 serves as a first gate insulator. Conductor 260_1 serves as a first gate electrode.

[0215] Alternatively, the conductor 205 may be used as a second gate electrode of the transistor 200_1 , and the insulator 222_1 may be used as a second gate insulator of the transistor 200_1 .

[0216] like Figure 2 As shown, semiconductor device 200 according to one embodiment of the present invention has a structure in which conductor 260_1 is electrically connected to conductor 205 via conductor 254. Therefore, a gate electric field can be applied from above and below oxide 230_1. In this case, the thickness of insulator 222_1 is preferably substantially equal to the thickness of insulator 250_1. This allows a gate electric field of uniform strength to be applied from above and below oxide 230_1.

[0217] The oxide 230_1 includes an oxide 230a1 and an oxide 230b1 on the oxide 230a1. The oxide 230_1 is provided in an island shape on the insulator 222_1 so as to have a region overlapping with the conductor 205.

[0218] Conductor 260_1 is disposed on oxide 230b1 via insulator 250_1. Conductor 260_1 has a region that overlaps with conductor 205 via oxide 230_1. Conductor 260_1 includes conductor 260a1 and conductor 260b1 on conductor 260a1. Conductor 260a1 is preferably formed of a conductive material that inhibits oxygen diffusion. This conductive material can suppress a decrease in conductivity due to oxidation of conductor 260b1. Furthermore, conductor 260b1 is preferably formed of a material with higher conductivity than conductor 260a1.

[0219] Furthermore, when viewed from a planar perspective, the conductors 242a1 and 242b1 are provided on the oxide 230b1 in such a manner as to sandwich the insulator 250_1 and the conductor 260_1. Figure 1B As shown, the side surfaces of the conductors 242 a 1 and 242 b 1 that do not face the conductor 260_ 1 are substantially aligned with the side surfaces of the oxides 230 a 1 and 230 b 1 .

[0220] Note that in Figure 1B In the embodiment shown in FIG. 2 , the substantially aligned side surfaces of oxide 230a1, oxide 230b1, and conductor 242a1, as well as the substantially aligned side surfaces of oxide 230a1, oxide 230b1, and conductor 242b1, all have a tapered shape, but the invention is not limited thereto. The side surfaces may also be substantially perpendicular to the substrate surface. When the side surfaces have a tapered shape, the coverage of the side surfaces by the layers formed on transistor 200_1 can be improved. On the other hand, when the side surfaces are substantially perpendicular to the substrate surface, the miniaturization of transistor 200_1 can be further achieved.

[0221] Insulator 275_1 is provided in contact with the top surface of conductor 242a1, the top surface of conductor 242b1, oxide 230a1, substantially aligned side surfaces of oxide 230b1 and conductor 242a1, substantially aligned side surfaces of oxide 230a1, oxide 230b1, and conductor 242b1, and the top surface of insulator 222_1. Insulator 275_1 has the function of suppressing diffusion of impurities from above transistor 200_1 into oxide 230_1.

[0222] An insulator 280_1 is provided over transistor 200_1 and insulator 275_1. The top surface of insulator 280_1 is preferably planarized. An opening is formed in the region of insulator 280_1 and insulator 275_1 that overlaps with conductor 205. Insulator 250_1 is provided so as to contact the side surfaces of insulator 280_1, the side surfaces of insulator 275_1, the side surfaces of conductor 242a1, the side surfaces of conductor 242b1, and the top surface of oxide 230b1 within the opening. Conductor 260a1 is provided over insulator 250_1, and conductor 260b1 is provided on conductor 260a1 so as to fit within the opening.

[0223] An insulator 222_2 is provided on the transistor 200_1 and the insulator 280_1. The top surface of the insulator 250_1 (the surface in contact with the insulator 222_2), the top surface of the conductor 260a1 (the surface in contact with the insulator 222_2), the top surface of the conductor 260b1, and the top surface of the insulator 280_1 are all at substantially the same height.

[0224] Transistor 200_2 is provided over transistor 200_1 with insulator 222_2 interposed therebetween. Transistor 200_2 includes oxide 230_2 (oxide 230a2 and oxide 230b2), conductor 242a2, conductor 242b2, insulator 250_2, and conductor 260_2 (conductor 260a2 and conductor 260b2). Insulator 275_2 is provided to cover transistor 200_2, and insulator 280_2 is provided over insulator 275_2. Insulator 222_3 is provided over insulator 280_2 and transistor 200_2.

[0225] Transistor 200_3 is provided over transistor 200_2 with insulator 222_3 interposed therebetween. Transistor 200_3 includes oxide 230_3 (oxide 230a3 and oxide 230b3), conductor 242a3, conductor 242b3, insulator 250_3, and conductor 260_3 (conductor 260a3 and conductor 260b3). Insulator 275_3 is provided to cover transistor 200_3, and insulator 280_3 is provided over insulator 275_3.

[0226] For the components of insulator 222_2, transistor 200_2, insulator 275_2 and insulator 280_2, as well as the components of insulator 222_3, transistor 200_3, insulator 275_3 and insulator 280_3, the same description as that of insulator 222_1, transistor 200_1, insulator 275_1 and insulator 280_1 can be applied by replacing the numbers at the end of the symbols (the numbers after "_").

[0227] In addition, if Figure 2 As shown, in a semiconductor device 200 of one embodiment of the present invention, the channel formation regions of transistors 200_1 to 200_3 are all surrounded by the first gate electrode (conductor 260_1 to conductor 260_3). In this specification, etc., a transistor structure in which the channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is arranged in a manner that surrounds at least two or more sides of the channel (specifically, two sides, three sides, or four sides, etc.). By adopting the Fin-type structure and the S-channel structure, the resistance to the short channel effect can be improved. In other words, a transistor that is not prone to the short channel effect can be realized.

[0228] By adopting the above-mentioned S-channel structure as transistors 200_1 to 200_3, the channel formation region can be electrically surrounded. Note that the S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is essentially equivalent to a GAA structure or an LGAA (Lateral GAA: lateral all-around gate) structure. By making transistors 200_1 to 200_3 have an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region can be formed as the entire bulk of oxide 230_1 to oxide 230_3 at or near the interface between oxide 230_1 to oxide 230_3 and the gate insulator (insulator 250 and insulator 222). Therefore, the current density flowing through the transistor can be increased, so an increase in the on-state current of the transistor or the field-effect mobility of the transistor can be expected.

[0229] like Figure 1A As shown, a semiconductor device 200 according to one embodiment of the present invention has a structure in which transistors 200_1 through 200_3 overlap when viewed from above. Therefore, the area occupied by the semiconductor device within the substrate surface can be significantly reduced. Furthermore, the number of transistors can be increased while suppressing the increase in this area.

[0230] The semiconductor device 200 according to one embodiment of the present invention is different from the semiconductor device 300 described above in that: Figure 2 As shown, the conductor 205 can be used as the second gate electrode only in the transistor 200_1.

[0231] In addition, the difference between the semiconductor device 200 of one embodiment of the present invention and the above-mentioned semiconductor device 300 is that: although all transistors in the above-mentioned semiconductor device 300 share the second gate insulator (insulator 222), in the semiconductor device 200 of one embodiment of the present invention, each transistor includes a different second gate insulator (insulator 222_1 to insulator 222_3).

[0232] In addition, the difference between the semiconductor device 200 of one embodiment of the present invention and the above-mentioned semiconductor device 300 is that: although all transistors in the above-mentioned semiconductor device 300 share the first gate insulator (insulator 250), in the semiconductor device 200 of one embodiment of the present invention, each transistor includes a different first gate insulator (insulator 250_1 to insulator 250_3).

[0233] In addition, the difference between the semiconductor device 200 of one embodiment of the present invention and the above-mentioned semiconductor device 300 is that: although all transistors in the above-mentioned semiconductor device 300 share the first gate electrode (conductor 260), in the semiconductor device 200 of one embodiment of the present invention, each transistor includes a different first gate electrode (conductor 260_1 to conductor 260_3).

[0234] In this specification and other documents, the lower oxides (oxides 230a1 to 230a3) included in transistors 200_1 to 200_3 are sometimes collectively referred to as oxides 230a. The upper oxides (oxides 230b1 to 230b3) included in transistors 200_1 to 200_3 are sometimes collectively referred to as oxides 230b. Oxides 230a and 230b are sometimes collectively referred to as oxides 230. One of the source and drain electrodes (conductors 242a1 to 242a3) included in transistors 200_1 to 200_3 is sometimes collectively referred to as conductor 242a. The other of the source and drain electrodes (conductors 242b1 to 242b3) included in transistors 200_1 to 200_3 is sometimes collectively referred to as conductor 242b. The first gate insulators (insulators 250_1 to 250_3 ) included in the transistors 200_1 to 200_3 are sometimes collectively referred to as the insulator 250 . The gate electrodes (conductors 260_1 to 260_3 ) included in the transistors 200_1 to 200_3 are sometimes collectively referred to as the conductor 260 .

[0235] In the semiconductor device 200, transistors 200_1 to 200_3 stacked in an overlapping manner are connected in parallel. Figure 107BAs shown, the sources of transistors 200_1 to 200_3 are electrically connected to each other. The drains of transistors 200_1 to 200_3 are electrically connected to each other. The gates of transistors 200_1 to 200_3 are electrically connected to each other.

[0236] like Figure 1B As shown, in a semiconductor device 200 according to one embodiment of the present invention, a conductor 242a1, which serves as one of the source and drain electrodes of a transistor 200_1, is electrically connected to a conductor 242a2, which serves as one of the source and drain electrodes of a transistor 200_2, via a conductor 243a (conductor 243a1 and conductor 243a2). Conductor 243a is provided so as to penetrate conductor 242a2 and oxide 230_2. Conductor 242b1, which serves as the other of the source and drain electrodes of the transistor 200_1, is electrically connected to conductor 242b2, which serves as the other of the source and drain electrodes of the transistor 200_2, via a conductor 243b (conductor 243b1 and conductor 243b2). Conductor 243b is provided so as to penetrate conductor 242b2 and oxide 230_2.

[0237] Furthermore, conductor 242a2, which serves as one of the source and drain electrodes of transistor 200_2, is electrically connected to conductor 242a3, which serves as one of the source and drain electrodes of transistor 200_3, via conductor 243a (conductor 243a1 and conductor 243a2) and conductor 244a (conductor 244a1 and conductor 244a2). Conductor 244a is provided so as to penetrate conductor 242a3 and oxide 230_3. Conductor 242b2, which serves as the other of the source and drain electrodes of transistor 200_2, is electrically connected to conductor 242b3, which serves as the other of the source and drain electrodes of transistor 200_3, via conductor 243b (conductor 243b1 and conductor 243b2) and conductor 244b (conductor 244b1 and conductor 244b2). The conductor 244b is provided so as to penetrate the conductor 242b3 and the oxide 230_3.

[0238] The conductor 243a serves as a plug that electrically connects one of the source and drain electrodes of the transistor 200_1 (the conductor 242a1) and one of the source and drain electrodes of the transistor 200_2 (the conductor 242a2). The conductor 243b serves as a plug that electrically connects the other of the source and drain electrodes of the transistor 200_1 (the conductor 242b1) and the other of the source and drain electrodes of the transistor 200_2 (the conductor 242b2).

[0239] The conductor 243a includes a conductor 243a1 and a conductor 243a2 on the conductor 243a1. The conductor 243b includes a conductor 243b1 and a conductor 243b2 on the conductor 243b1.

[0240] As described above, the insulator 275_1 is provided to cover the transistor 200_1, and the insulator 280_1 is provided on the insulator 275_1. The insulator 222_2 is provided on the insulator 280_1 and the transistor 200_1, and the transistor 200_2 is provided on the insulator 222_2.

[0241] Furthermore, an insulator 275_2 is provided to cover the transistor 200_2, and an insulator 280_2 is provided on the insulator 275_2. The top surface of the insulator 280_2, the topmost surface of the insulator 250_2 (the surface in contact with the insulator 222_3), the topmost surface of the conductor 260a2 (the surface in contact with the insulator 222_3), and the top surface of the conductor 260b2 are all at substantially the same height. The insulator 222_3 is provided to contact the top surface of the insulator 280_2, the topmost surface of the insulator 250_2, the topmost surface of the conductor 260a2, and the top surface of the conductor 260b2.

[0242] A first opening reaching the top surface of conductor 242a1 is provided in insulator 222_3, insulator 280_2, insulator 275_2, conductor 242a2, oxide 230_2, insulator 222_2, insulator 280_1, and insulator 275_1. Similarly, a second opening reaching the top surface of conductor 242b1 is provided in insulator 222_3, insulator 280_2, insulator 275_2, conductor 242b2, oxide 230_2, insulator 222_2, insulator 280_1, and insulator 275_1. The first and second openings are preferably provided at positions that are axisymmetric with respect to conductor 260 when viewed from a planar perspective.

[0243] Conductor 243a1 is disposed in contact with the sidewalls of the first opening and the top surface of conductor 242a1, while conductor 243a2 is disposed on conductor 243a1 so as to be embedded in the first opening. Similarly, conductor 243b1 is disposed in contact with the sidewalls of the second opening and the top surface of conductor 242b1, while conductor 243b2 is disposed on conductor 243b1 so as to be embedded in the second opening.

[0244] Figure 3A FIG shows a plan view of the semiconductor device 200. Note that Figure 3A The region including transistor 200_2 and its vicinity is shown. Note that for clarity, Figure 3A Some components are omitted in the plan view.

[0245] like Figure 3A As shown, the conductor 243a is provided inside the opening formed in the conductor 242a2. The conductor 243b is provided inside the opening formed in the conductor 242b2. Note that Figure 3A The top surfaces of the openings formed in the conductor 242a2 and the openings formed in the conductor 242b2 are shown as circular, but the present invention is not limited thereto. For example, the top surfaces of these openings may be elliptical, polygonal, or polygonal with rounded corners.

[0246] In addition, Figure 3A In the embodiment, the top surface of the conductor 242a2 is a quadrangular shape with rounded corners, but is not limited thereto. For example, it may be a shape combining multiple polygons or a shape combining multiple polygons with rounded corners. Figure 3B As shown, a structure can also be employed in which the length of the region of conductor 242a2, including the opening for conductor 243a, in the channel width direction is greater than the length of the side of conductor 242a2 facing conductor 260_2 in the channel width direction. This structure increases the area of conductor 242a2 when viewed from above, thereby easing the accuracy of the opening's position alignment. This reduces the difficulty in manufacturing the micro memory cell. The top surface shape of conductor 242b2 is also similar.

[0247] Conductors 243a1 and 243b1 are preferably formed of a conductive material that inhibits oxygen diffusion. Using this conductive material can prevent a decrease in conductivity caused by oxidation of conductors 243a2 and 243b2. Furthermore, conductor 243a2 is preferably formed of a material with higher conductivity than conductor 243a1. Conductor 243b2 is preferably formed of a material with higher conductivity than conductor 243b1.

[0248] The top surface of the conductor 243a1 (the surface in contact with the oxide 230a3), the top surface of the conductor 243a2, the top surface of the conductor 243b1 (the surface in contact with the oxide 230a3), the top surface of the conductor 243b2 and the top surface of the insulator 222_3 are all roughly the same height.

[0249] The conductor 244a serves as a plug for electrically connecting the conductor 243a to one of the source and drain electrodes of the transistor 200_3 (the conductor 242a3), and the conductor 244b serves as a plug for electrically connecting the conductor 243b to the other of the source and drain electrodes of the transistor 200_3 (the conductor 242b3).

[0250] The conductor 244a includes a conductor 244a1 and a conductor 244a2 on the conductor 244a1. The conductor 244b includes a conductor 244b1 and a conductor 244b2 on the conductor 244b1.

[0251] As described above, transistor 200_3 is provided on insulator 222_3. Insulator 275_3 is provided to cover transistor 200_3, and insulator 280_3 is provided on insulator 275_3. The top surface of insulator 280_3, the topmost surface of insulator 250_3 (the surface in contact with insulator 286), the topmost surface of conductor 260a3 (the surface in contact with insulator 286), and the top surface of conductor 260b3 are all at approximately the same height.

[0252] Insulator 286 is provided so as to contact the top surface of insulator 280_3, the topmost surface of insulator 250_3, the topmost surface of conductor 260a3, and the top surface of conductor 260b3. Insulator 286 preferably contains a large amount of oxygen. By providing insulator 286, oxygen contained in insulator 286 can be supplied to insulator 280_3 during deposition of insulator 286 or during subsequent heat treatment.

[0253] Insulator 283 is provided on insulator 286, and insulator 287 is provided on insulator 283. Insulator 283 has the function of suppressing the diffusion of impurities from above insulator 286 into transistors 200_1 through 200_3. Furthermore, insulator 215 preferably has the same function as insulator 283. This is preferable because it allows transistors 200_1 through 200_3 to be covered from above and below by an insulator that suppresses impurity diffusion. The top surface of insulator 287 is preferably flat.

[0254] A third opening reaching the top surface of conductor 243a is provided in insulator 287, insulator 283, insulator 286, insulator 280_3, insulator 275_3, conductor 242a3, and oxide 230_3. Similarly, a fourth opening reaching the top surface of conductor 243b is provided in insulator 287, insulator 283, insulator 286, insulator 280_3, insulator 275_3, conductor 242b3, and oxide 230_3.

[0255] Conductor 244a1 is disposed in contact with the sidewalls of the third opening and the top surface of conductor 243a, and conductor 244a2 is disposed on conductor 244a1 so as to be embedded in the third opening. Similarly, conductor 244b1 is disposed in contact with the sidewalls of the fourth opening and the top surface of conductor 243b, and conductor 244b2 is disposed on conductor 244b1 so as to be embedded in the fourth opening.

[0256] As with the semiconductor device 300 described above, Figures 1A to 2 In the semiconductor device 200 shown, conductors 244a1 and 244b1 are preferably formed of a conductive material that inhibits oxygen diffusion. This conductive material can suppress a decrease in conductivity caused by oxidation of conductors 244a2 and 244b2. Furthermore, conductor 244a2 is preferably formed of a material with higher conductivity than conductor 244a1. Conductor 244b2 is preferably formed of a material with higher conductivity than conductor 244b1.

[0257] The top surface of conductor 244a1 (the surface in contact with conductor 245a), the top surface of conductor 244a2, the top surface of conductor 244b1 (the surface in contact with conductor 245b), the top surface of conductor 244b2, and the top surface of insulator 287 are all approximately the same height. Conductor 245a is provided so as to contact the top surface of conductor 244a1, the top surface of conductor 244a2, and the top surface of insulator 287. Conductor 245b is provided so as to contact the top surface of conductor 244b1, the top surface of conductor 244b2, and the top surface of insulator 287. Both conductors 245a and 245b serve as wiring.

[0258] Conductor 244a electrically connects conductor 243a and conductor 245a. Conductor 244b electrically connects conductor 243b and conductor 245b. Therefore, it can be said that one of the source and drain electrodes of transistors 200_1 to 200_3 (conductors 242a1 to 242a3) is electrically connected to conductor 245a, which serves as a wiring, via conductor 243a and conductor 244a, which serve as plugs. It can be said that the other of the source and drain electrodes of transistors 200_1 to 200_3 (conductors 242b1 to 242b3) is electrically connected to conductor 245b, which serves as a wiring, via conductor 243b and conductor 244b, which serve as plugs.

[0259] In addition, if Figure 2 As shown, the conductors (conductors 260_1 to 260_3) serving as gate electrodes for transistors 200_1 to 200_3 have different lengths in the channel width direction (hereinafter also referred to as gate widths). Specifically, transistor 200_1 has the largest gate width, transistor 200_2 has a relatively large gate width, and transistor 200_3 has the smallest gate width. In other words, among the multiple stacked transistors included in semiconductor device 200, the gate width of the transistor located in the lower layer is the largest, and the gate width of the transistor located in the upper layer decreases.

[0260] In addition, if Figure 1A and Figure 2As shown, the ends of the conductors (conductors 260_1 to 260_3) serving as the gate electrodes of transistors 200_1 to 200_3 on the A3 side are roughly aligned. On the other hand, the ends of the transistors 200_1 to 200_3 on the A4 side are not aligned, and the ends closer to the gate electrodes of the lower transistors are closer to the A4 side. In other words, in the semiconductor device 200 of one embodiment of the present invention, when viewed from a cross section in the channel width direction of the transistor (see Figure 2 ), the gate electrode of each transistor has a step shape.

[0261] The height (H) of the oxide 230 is preferably greater than the channel width of the oxide 230 (the length in the A3-A4 direction, i.e., W). For example, the ratio of the height of the oxide 230 to the channel width of the oxide 230 (H / W) is preferably greater than 1, more preferably greater than 2, and further preferably greater than 5. By adopting such a structure, the channel formation area can be increased without increasing the area occupied by the transistor. In addition, even if the thickness of the insulator 250 is large, the area to which the gate electric field of the conductor 260 is applied can be increased. Therefore, the on-state current or field-effect mobility of the transistor can be increased. Therefore, the electrical characteristics of the transistor can be improved.

[0262] Note that, while there is no particular upper limit on H / W, it is preferably within a range that does not cause collapse of the oxide 230 during the semiconductor device manufacturing process. For example, H / W is preferably 100 or less, 50 or less, 20 or less, or 10 or less. Therefore, H / W is preferably 1 or more and 100 or less, 1 or more and 50 or less, 2 or more and 50 or less, 2 or more and 20 or less, or 5 or more and 20 or less.

[0263] like Figure 2 As shown, in the semiconductor device 200 according to one embodiment of the present invention, the conductors (conductors 260_1 to 260_3) serving as gate electrodes of transistors 200_1 to 200_3 are electrically connected to each other via conductor 254 (conductor 254a and conductor 254b). Furthermore, conductor 254 is also electrically connected to conductor 205. In other words, conductor 205 is electrically connected to conductor 260. Conductor 254 includes conductor 254a and conductor 254b on conductor 254a.

[0264] like Figure 2 As shown, the semiconductor device 200 of one embodiment of the present invention includes a fifth opening reaching the top surface of the conductor 205 in the insulator 287, the insulator 283, the insulator 286, the insulator 280_3, the insulator 275_3, the insulator 222_3, the insulator 280_2, the insulator 275_2, the insulator 222_2, the insulator 280_1, the insulator 275_1 and the insulator 222_1.

[0265] Conductor 254a is provided so as to contact the sidewalls of the fifth opening and the top surface of conductor 205. Conductor 254b is provided on conductor 254a so as to be embedded in the fifth opening. Conductor 254a has a region in contact with the top surface of conductor 260_3, a region in contact with the top surface of conductor 260_2, and a region in contact with the top surface of conductor 260_1. Conductor 254a is preferably formed of a conductive material that inhibits oxygen diffusion. By using this conductive material, a decrease in conductivity due to oxidation of conductor 254b can be suppressed. Furthermore, conductor 254b is preferably formed of a material with higher conductivity than conductor 254a.

[0266] Figure 3A The conductor 254 is shown in contact with the top surface of the conductor 260_2 and the top surface of the conductor 260_1. In addition, the top surface shape of the opening formed in the insulator 287 for setting the conductor 254 can also be circular, elliptical, polygonal or polygonal with rounded corners. Figure 3A As shown, the top surface of the opening is a circular shape with a notch. Since the conductor 260_3 and the insulator 250_3 are located above the notch, the top surface of the opening is Figure 3A In addition, Figure 3B The case where the top surface of the opening is a polygonal shape having a notch portion and rounded corners is shown.

[0267] Conductor 254 serves as a plug that electrically connects conductors 260_1 to 260_3, which serve as the gate electrodes (first gate electrodes) of transistors 200_1 to 200_3, conductor 205, which serves as the second gate electrode of transistor 200_1, and conductor 255, which serves as wiring. In transistor 200_3, conductor 260_3 serves as the first gate electrode, and conductor 260_2 serves as the second gate electrode. In transistor 200_2, conductor 260_2 serves as the first gate electrode, and conductor 260_1 serves as the second gate electrode. In transistor 200_1, conductor 260_1 serves as the first gate electrode, and conductor 205 serves as the second gate electrode.

[0268] The top surface of conductor 254a (the surface in contact with conductor 255), the top surface of conductor 254b, and the top surface of insulator 287 are all at substantially the same height. Conductor 255 is provided so as to be in contact with the top surface of conductor 254a, the top surface of conductor 254b, and the top surface of insulator 287. Conductor 255 serves as wiring.

[0269] Since the semiconductor device 200 according to one embodiment of the present invention has the above-described structure, it is possible to output a large on-state current without increasing the area occupied within the substrate surface.

[0270] In the semiconductor device 200 according to one embodiment of the present invention, the oxide 230 (oxides 230_1 to 230_3) preferably includes an oxide 230a (oxides 230a1 to 230a3) and an oxide 230b (oxides 230b1 to 230b3) located above the oxide 230a. The inclusion of the oxide 230a below the oxide 230b can suppress diffusion of impurities from structures formed below the oxide 230a into the oxide 230b.

[0271] This embodiment shows an example in which the oxide 230 has a two-layer structure of oxide 230a and oxide 230b, but the present invention is not limited thereto. The oxide 230 may have a single-layer structure of oxide 230b or a stacked-layer structure of three or more layers.

[0272] Figure 4A An enlarged cross-sectional view in the channel length direction of transistors (transistors 200_1 to 200_3 ) included in a semiconductor device 200 according to one embodiment of the present invention is shown. Figure 7 An enlarged cross-sectional view of the transistor in the channel width direction is shown.

[0273] Figure 4A The example in which the sidewalls of the openings of the insulator 250 serving as the gate insulator of the transistor and the conductor 260 (conductor 260a and conductor 260b) serving as the gate electrode have tapered shapes is shown. Figure 1B Thus, in the semiconductor device 200 according to one embodiment of the present invention, the sidewalls of the opening can be tapered or substantially perpendicular to the substrate surface. Tapered sidewalls of the opening can improve coverage of the insulator 250 and conductor 260 provided in the opening. Furthermore, substantially perpendicular sidewalls of the opening can further miniaturize the transistor.

[0274] like Figure 4A As shown, oxide 230b includes region 230bc, regions 230ba, and regions 230bb, which sandwich region 230bc. Region 230bc serves as a channel formation region for the transistor. Region 230ba serves as one of the source and drain regions of the transistor, while region 230bb serves as the other of the source and drain regions of the transistor. At least a portion of region 230bc overlaps with conductor 260. Region 230ba overlaps with conductor 242a, and region 230bb overlaps with conductor 242b.

[0275] Since region 230bc has fewer oxygen vacancies and a lower impurity concentration than regions 230ba and 230bb, it is a high-resistance region with a low carrier concentration.

[0276] Furthermore, regions 230ba and 230bb have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, and therefore are low-resistance regions with high carrier concentrations. In other words, regions 230ba and 230bb are n-type regions (low-resistance regions) with higher carrier concentrations than region 230bc.

[0277] The carrier concentration of the region 230bc is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the region 230bc, and it can be, for example, 1×10 -9 cm -3 .

[0278] When the carrier concentration of the oxide 230 b is to be reduced, the impurity concentration in the oxide 230 b can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0279] Therefore, to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in oxide 230b. To reduce the impurity concentration in oxide 230b, it is also preferable to reduce the impurity concentration in nearby films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in oxide 230b refer to elements other than the main component of oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0280] Furthermore, the region 230bc, the region 230ba, and the region 230bb may be formed not only in the oxide 230b but also in the oxide 230a.

[0281] In oxide 230, it is sometimes difficult to clearly observe the boundaries between regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region; they can also change continuously within each region. In other words, the concentrations of impurity elements such as hydrogen and nitrogen can decrease as they approach region 230bc.

[0282] Note that a metal oxide serving as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a and the oxide 230 b ).

[0283] The band gap of the metal oxide used as a semiconductor is preferably greater than 2eV, more preferably greater than 2.5eV. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. Therefore, a transistor containing a metal oxide in the channel formation region is called an OS transistor. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be substantially reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0284] Oxide 230 preferably includes a metal oxide (oxide semiconductor). As metal oxides that can be used for oxide 230, for example, indium oxide, gallium oxide and zinc oxide can be mentioned. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three selected from indium, element M and zinc. In addition, element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a higher bond energy with oxygen than indium. Specifically, as element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be mentioned. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements may be collectively referred to as “metal elements”, and “metal elements” described in this specification and the like may include metalloid elements.

[0285] The oxide 230 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0286] By increasing the ratio of the number of indium atoms contained in the metal oxide to the total number of atoms of all metal elements, the field effect mobility of the transistor can be increased.

[0287] In addition, metal oxides can also replace indium or contain one or more metal elements with large periodic numbers in the periodic table in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with large periodic numbers in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be enumerated. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be enumerated. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0288] Furthermore, the metal oxide may contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0289] Furthermore, by increasing the ratio of zinc atoms in the metal oxide to the total number of atoms of all metal elements, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0290] Furthermore, by increasing the ratio of the number of atoms of the element M contained in the metal oxide to the total number of atoms of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Consequently, the generation of carriers due to oxygen vacancies is suppressed, thereby enabling the realization of a transistor with a low off-state current. Furthermore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0291] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0292] Oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230a is preferably greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 230a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. This structure can suppress the diffusion of impurities and oxygen from the structure formed below oxide 230a into oxide 230b.

[0293] Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 230 b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230 a. With this structure, the transistor can achieve large on-state current and high frequency characteristics.

[0294] Furthermore, since oxide 230a and oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor to achieve high on-state current and high frequency characteristics.

[0295] Specifically, metal oxides with a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto can be used as oxide 230a. Furthermore, metal oxides with a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto can be used as oxide 230b. Note that these compositions fall within a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, the metal oxides used for oxide 230a can also be used as oxide 230b. Furthermore, the compositions of the metal oxides that can be used for the oxide 230a and the oxide 230b are not limited thereto. For example, the composition of the metal oxide that can be used for the oxide 230a can also be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b can also be applied to the oxide 230a.

[0296] Furthermore, when depositing a metal oxide by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of a sputtering target used for depositing the metal oxide.

[0297] The oxide 230 b preferably has crystallinity. In particular, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) is preferably used as the oxide 230 b.

[0298] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after formation at a temperature at which the metal oxide does not undergo polycrystallization (e.g., 400°C to 600°C), CAAC-OS can be given a dense structure with even higher crystallinity. By further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0299] Furthermore, CAAC-OS rarely has clear grain boundaries, making it less likely to cause a drop in electron mobility due to these boundaries. Consequently, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0300] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230 b, oxygen extraction from the source or drain electrode can be suppressed. Consequently, even during heat treatment, oxygen extraction from the oxide 230 b is reduced, making the transistor stable even against the high temperatures (so-called thermal budget) experienced during the manufacturing process.

[0301] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the region 230bc forming the channel of the oxide semiconductor, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the region 230bc in the oxide semiconductor is reduced and the region 230bc is made i-type (intrinsic) or substantially i-type.

[0302] In contrast, by providing an insulator containing oxygen released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that if excessive oxygen is supplied to region 230ba or region 230bb, the on-state current of the transistor may decrease or the field-effect mobility may decrease. Furthermore, if the amount of oxygen supplied to region 230ba or region 230bb is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor may become uneven. In addition, when oxygen supplied from the insulator to the oxide semiconductor diffuses into conductive bodies such as the gate electrode, source electrode, and drain electrode, the conductive bodies may be oxidized, resulting in a loss of conductivity, thereby negatively affecting the electrical characteristics and reliability of the transistor.

[0303] Therefore, in the oxide semiconductor, it is preferable that the carrier concentration of the region 230bc is reduced and the region 230bc is i-type or substantially i-type, while it is preferable that the carrier concentration of the regions 230ba and 230bb is high and the region 230bb is n-type. In other words, it is preferable to reduce the oxygen vacancies and V O H. In addition, it is preferable that the regions 230ba and 230bb are not supplied with excessive oxygen and that the V of the regions 230ba and 230bb are not excessively reduced. O H content. In addition, it is preferable to have a structure that suppresses the reduction of the conductivity of the conductor 260, the conductor 242a, the conductor 242b, etc. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, etc. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0304] Therefore, the semiconductor device in this embodiment has a structure in which the hydrogen concentration in the region 230bc is reduced, oxidation of the conductors 242a, 242b, and 260 is suppressed, and reduction in the hydrogen concentration in the regions 230ba and 230bb is suppressed.

[0305] Figure 4B Shown with Figure 4A The transistors shown are different structures of the transistors in the channel length direction of the cross-sectional enlarged view. Note that Figure 4B The enlarged cross-sectional view of the transistor in the channel width direction shown can be referred to Figure 7 .

[0306] Figure 4BThe transistor shown includes an insulator 271a on a conductor 242a and an insulator 271b on a conductor 242b. The insulator 271a includes an insulator 271a1 and an insulator 271a2 on the insulator 271a1. The insulator 271b includes an insulator 271b1 and an insulator 271b2 on the insulator 271b1.

[0307] By providing an insulator 271a on the conductor 242a and providing an insulator 271b on the conductor 242b, it is possible to prevent the ends of the conductor 242a and the conductor 242b from being over-etched when the oxide film that will become the oxide 230 and the conductive film that will become the conductor 242a and the conductor 242b are processed into an island shape at one time. That is, the insulator 271a and the insulator 271b are used as an etching stop layer to protect the conductor 242a and the conductor 242b when the above-mentioned conductive film is processed into an island shape. In addition, as the insulator 271a and the insulator 271b, it is preferable to use an inorganic insulator that does not easily oxidize the conductors 242a and 242b. For example, it is preferable to use a nitride insulator or an oxide insulator. By providing the above-mentioned insulator used as an etching stop layer on the conductor 242a and the conductor 242b, the micro transistor can be processed with high precision. Note that although in Figure 4B The middle insulator 271 a and the insulator 271 b both have a two-layer stacked structure, but may also have a single-layer structure or a stacked structure of three or more layers.

[0308] Figure 5A Shown with Figure 4B The transistors shown are different structures of the transistors in the channel length direction of the cross-sectional enlarged view. Note that Figure 5A The enlarged cross-sectional view of the transistor in the channel width direction shown can be referred to Figure 8A .

[0309] Figure 5A The transistor shown with Figure 4B The transistors shown differ in that: Figure 5A In the transistor shown, the insulator 250 has a three-layer stacked structure of an insulator 250 a , an insulator 250 b on the insulator 250 a , and an insulator 250 c on the insulator 250 b .

[0310] exist Figure 5A In the transistor shown, the insulator 250a in contact with the region 230bc in the oxide 230b preferably has the function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the region 230bc of the oxide 230b. Therefore, the V O H makes the region 230bci-type or substantially i-type.

[0311] Examples of insulators capable of capturing and fixing hydrogen include metal oxides having an amorphous structure. For example, magnesium oxide or a metal oxide containing one or both of aluminum and hafnium is preferably used as the insulator 250a. These metal oxides having an amorphous structure sometimes have the property of having dangling bonds in their oxygen atoms, which can capture or fix hydrogen. In other words, it can be said that metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.

[0312] Furthermore, a high-k dielectric material is preferably used for insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for insulator 250a can reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0313] Therefore, as the insulator 250 a , it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably to use aluminum oxide having an amorphous structure.

[0314] As the insulator 250 b, an insulator having a thermally stable structure, such as silicon oxide or silicon oxynitride, is preferably used. Note that in this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, and "nitride oxide" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0315] An insulator that functions as an oxygen-blocking insulator is preferably used as insulator 250c. Insulator 250c is in contact with conductor 260. Therefore, by using an insulator that functions as an oxygen-blocking insulator as insulator 250c, oxidation of conductor 260 caused by diffusion of oxygen contained in insulator 250b through insulator 250c to conductor 260 can be suppressed.

[0316] In this specification, etc., a blocking insulator refers to an insulator with barrier properties. In this specification, etc., barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, they refer to the ability to capture and immobilize the corresponding substance (also known as gettering).

[0317] In addition, if Figure 5B and Figure 8BAs shown, a structure in which an insulator 250d is provided on insulator 250b can also be employed. In this case, the same insulator that can be used as insulator 250a can be provided as insulator 250d. For example, hafnium oxide can be used as insulator 250d. By providing insulator 250d between insulator 250b and insulator 250c, hydrogen contained in insulator 250b and the like can be more effectively captured and fixed.

[0318] Furthermore, to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen-blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators 250a, 250c, 250d, and 275 are provided near the conductors 242a, 242b, and 260.

[0319] Examples of oxygen-blocking insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, insulators 250a, 250c, and 275 preferably use a single layer or a stack of these oxygen-blocking insulators.

[0320] Insulator 250a preferably has oxygen barrier properties. Insulator 250a is preferably at least less permeable to oxygen than insulator 280. Insulator 250a has regions that contact the side surfaces of conductor 242a and conductor 242b. Oxygen barrier properties of insulator 250a can prevent oxidation of the side surfaces of conductors 242a and 242b, which could lead to the formation of oxide films on these side surfaces. This can prevent a decrease in the on-state current of the transistor or a decrease in field-effect mobility.

[0321] In addition, if Figure 8A and Figure 8B As shown, insulator 250a is provided in contact with the top and side surfaces of oxide 230b, and the side surfaces of oxide 230a and the top surface of insulator 222. When insulator 250a has oxygen barrier properties, it can suppress the release of oxygen from region 230bc of oxide 230b during heat treatment, etc. Thus, the formation of oxygen vacancies in oxides 230a and 230b can be reduced.

[0322] Furthermore, by providing the insulator 250a, even if the insulator 280 contains excessive oxygen, excessive supply of oxygen to the oxides 230a and 230b can be suppressed, and an appropriate amount of oxygen can be supplied to the oxides 230a and 230b. Therefore, a decrease in the on-state current of the transistor or a decrease in the field-effect mobility due to excessive oxidation of the regions 230ba and 230bb can be suppressed.

[0323] Since an oxide containing one or both of aluminum and hafnium has oxygen barrier properties, it can be suitably used as the insulator 250 a .

[0324] In addition, as described above, the insulator 250c preferably has oxygen barrier properties. Figure 5A and Figure 5B As shown, insulator 250c is provided between region 230bc of oxide 230 and conductor 260, and between insulator 280 and conductor 260. This structure prevents oxygen in region 230bc of oxide 230 from diffusing into conductor 260 and forming oxygen vacancies in region 230bc of oxide 230. Furthermore, oxygen in oxide 230 and insulator 280 from diffusing into conductor 260 and causing oxidation of conductor 260 can be prevented. Insulator 250c is preferably less permeable to oxygen than insulator 280. For example, silicon nitride is preferably used as insulator 250c. In this case, insulator 250c contains at least nitrogen and silicon.

[0325] Furthermore, the insulator 250c preferably has a hydrogen barrier property, thereby preventing impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0326] Insulator 275 preferably has oxygen barrier properties. Insulator 275 is provided between insulator 280 and conductor 242a, and between insulator 280 and conductor 242b. This structure can prevent oxygen contained in insulator 280 from diffusing into conductors 242a and 242b. Therefore, it is possible to prevent oxygen contained in insulator 280 from causing oxidation of conductors 242a and 242b, thereby increasing resistivity and reducing on-state current. Insulator 275 is preferably at least less permeable to oxygen than insulator 280. For example, silicon nitride is preferably used as insulator 275. In this case, insulator 275 contains at least nitrogen and silicon.

[0327] To suppress a decrease in hydrogen concentration in regions 230ba and 230bb in oxide 230, a hydrogen blocking insulator is preferably provided near regions 230ba and 230bb. In the semiconductor device described in this embodiment, insulator 275 is provided near regions 230ba and 230bb.

[0328] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned hydrogen barrier insulators.

[0329] The insulator 275 preferably has a hydrogen barrier property. When the insulator 275 has a hydrogen barrier property, it can prevent the insulator 250 from capturing and fixing hydrogen in the regions 230ba and 230bb. Therefore, the regions 230ba and 230bb can be converted to n-type.

[0330] By adopting the above structure, region 230bc can be i-type or substantially i-type, and regions 230ba and 230bb can be n-type, thereby providing a transistor with excellent electrical characteristics. By adopting the above structure, even when the transistor is miniaturized or highly integrated, it can still have excellent electrical characteristics. Furthermore, miniaturization of the transistor can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased.

[0331] Insulators 250a to 250d serve as part of the gate insulator. Insulators 250a to 250d are disposed together with conductor 260 in an opening formed in insulator 280 or the like. To achieve miniaturization of the transistor, the thickness of insulators 250a to 250d is preferably thin. The thickness of insulators 250a to 250d is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, further preferably 0.5 nm to 5.0 nm, further preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Furthermore, at least a portion of insulators 250a to 250d may include a region having the aforementioned thickness.

[0332] To reduce the thickness of insulators 250a to 250d as described above, atomic layer deposition (ALD) is preferably used. ALD methods include thermal ALD, which uses only thermal energy to react precursors and reactants, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. PEALD is sometimes preferred because it allows deposition at lower temperatures by utilizing plasma.

[0333] ALD deposits atoms layer by layer, enabling the deposition of extremely thin films, structures with high aspect ratios, deposition with minimal defects such as pinholes, deposition with excellent coverage, and deposition at low temperatures. Therefore, insulator 250 can be deposited with a relatively small thickness and high coverage on the sides of openings formed in insulator 280 and the side edges of conductors 242a and 242b.

[0334] The precursors used in the ALD method sometimes contain carbon, etc. Therefore, films formed using the ALD method may contain more impurities such as carbon than films formed using other deposition methods. Furthermore, quantitative analysis of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0335] Note that while the insulator 250 is described above as having a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, the present invention is not limited thereto. Insulator 250 may have a structure including at least one of insulators 250a to 250d. By configuring insulator 250 with one, two, or three layers of insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0336] In this embodiment, in addition to the above-described structure, the semiconductor device preferably further includes a structure that suppresses hydrogen from entering the transistor, etc. For example, an insulator that suppresses hydrogen diffusion is preferably provided so as to cover one or both of the upper and lower portions of the transistor, etc. In the semiconductor device described in this embodiment, examples of such insulators include insulator 215 and insulator 283. Insulator 215 and insulator 283 may also have similar structures.

[0337] Insulator 283 is preferably used as a blocking insulator to inhibit the diffusion of impurities such as water and hydrogen from above semiconductor device 200 into transistors included in the semiconductor device. Therefore, insulator 283 preferably includes an insulating material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (preventing these impurities from penetrating). Alternatively, insulator 283 preferably includes an insulating material that inhibits the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (preventing these oxygen atoms from penetrating).

[0338] The insulator 283 is made of an insulator having a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen, and can be made of, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0339] Note that in Figure 1B In the examples, the insulator 283 has a single-layer structure, but is not limited thereto. The insulator 283 may also have a stacked structure with more than two layers. For example, when the insulator 283 has a two-layer stacked structure, silicon nitride or the like having a higher hydrogen barrier property is preferably used as the insulator constituting the second layer of the insulator 283. In addition, for example, aluminum oxide or magnesium oxide having a strong function of capturing and fixing hydrogen is preferably used as the insulator constituting the first layer of the insulator 283. Thus, it is possible to suppress impurities such as water and hydrogen from diffusing from the interlayer insulating film or the like disposed on the upper side of the insulator 283 to the transistor. In addition, it is possible to suppress the oxygen contained in the insulator 280 or the like from diffusing through the insulator 283 to the top of the transistor.

[0340] Furthermore, by employing the same structure as that of the insulator 283 as the insulator 215 , diffusion of impurities such as water and hydrogen from the substrate side through the insulator 215 into the transistor can be suppressed.

[0341] In this manner, it is preferable to adopt a structure in which the upper and lower sides of the transistor are surrounded by an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0342] The conductor 205 is arranged so as to overlap with the oxide 230_1 and the conductor 260_1. Thus, the conductor 205 can be used as the second gate electrode of the transistor 200_1. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Figure 1A and Figure 2 As shown in FIG. 1 , the conductor 205 is preferably extended in the channel width direction. By adopting this structure, the conductor 205 can be used as wiring when multiple transistors are provided on the same substrate surface.

[0343] The conductor 205 may have a single-layer structure or a stacked-layer structure. Figure 1B , etc., show an example in which the conductor 205 has a two-layer stacked structure of conductors 205a and 205b. Conductor 205a is provided so as to contact the sidewalls of the opening and the top surface of insulator 215. Conductor 205b is provided so as to fit into a recessed portion of conductor 205a formed along the opening. Here, the height of the top surface of conductor 205 is substantially the same as the height of the top surface of insulator 216.

[0344] Here, the conductor 205a preferably includes a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably included a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0345] By using a conductive material that has the function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide 230_1 through the insulator 216 and the like. In addition, by using a conductive material that has the function of inhibiting oxygen diffusion as the conductor 205a, oxidation of the conductor 205b and a decrease in conductivity caused by oxygen diffused from the insulator 216 can be suppressed. Examples of conductive materials that have the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single layer structure or a stacked layer structure of the above conductive materials. For example, the conductor 205a preferably includes titanium nitride.

[0346] Furthermore, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0347] Note that the resistivity of the conductor 205 is designed taking into account the potential applied to the conductor 205, and the thickness of the conductor 205 is set based on this resistivity. Furthermore, the thickness of the insulator 216 is substantially the same as that of the conductor 205. It is preferable to reduce the thickness of the conductor 205 and the insulator 216 within the design allowable range of the conductor 205. Reducing the thickness of the insulator 216 can reduce the absolute amount of impurities such as hydrogen contained in the insulator 216, thereby suppressing the diffusion of these impurities into the oxide 230_1.

[0348] Insulator 222 (insulators 222_1 to 222_3) serves as an interlayer film between the transistors included in semiconductor device 200. Furthermore, insulators 222_1 to 222_3 serve as second gate insulators for transistors 200_1 to 200_3, respectively. Therefore, insulator 222 is preferably formed using the same material and thickness as insulator 250. In particular, if insulator 250 has a stacked structure, insulator 222 preferably has a stacked structure and is stacked in the opposite order to insulator 250. For example, if insulator 250 has a stacked structure of a first insulator and a second insulator on the first insulator, insulator 222 preferably has a stacked structure of a second insulator and a first insulator on the second insulator. By adopting this structure, oxide 230 can be surrounded by an insulator having the same function (e.g., the first insulator). Insulator 222 may be formed using a different material and thickness than insulator 250, but the EOT of insulator 222 and insulator 250 are preferably substantially equal. This allows the electric field strength from conductor 260_1 applied to oxide 230_1 to be substantially equal to the electric field strength from conductor 205. Furthermore, the electric field strength from conductor 260_2 applied to oxide 230_2 can be substantially equal to the electric field strength from conductor 260_1. Furthermore, the electric field strength from conductor 260_3 applied to oxide 230_3 can be substantially equal to the electric field strength from conductor 260_2.

[0349] By making the EOT of the insulator 222 and the insulator 250 substantially equal in this manner, a gate electric field can be applied substantially uniformly from all directions to each oxide 230 included in the transistors 200_1 to 200_3 , which is preferable.

[0350] In addition, a portion or all of the insulator 222 in the region that does not overlap with the oxide 230 may also be removed. Figure 9A As shown in FIG. 1 , the semiconductor device 200 may also have a structure in which the insulator 222 in the region not overlapping with the oxide 230 is partially removed. In this case, it can be said that the insulator 222 has a convex portion in the region overlapping with the oxide 230. Figure 9B As shown, the semiconductor device 200 may also have a structure in which the insulator 222 is removed from the region not overlapping with the oxide 230. In this case, the insulator 222 has an island shape. In addition, the insulator 250 is in contact with the top surface of the second gate electrode in the region not overlapping with the oxide 230.

[0351] By adopting this structure, the bottom surface of the conductor 260 in the region not overlapping with the oxide 230 can be further lowered (closer to the substrate). This is preferable because the electric field from the conductor 260 serving as the gate electrode can act uniformly on the entire channel formation region, thereby enabling the transistor to operate satisfactorily.

[0352] As the conductors 242a (conductors 242a1 to 242a3), the conductors 242b (conductors 242b1 to 242b3), and the conductors 260 (conductors 260_1 to 260_3), it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 contain at least metal and nitrogen.

[0353] The conductors 242a and 242b may have a single-layer structure or a stacked-layer structure. In addition, the conductor 260 may have a single-layer structure or a stacked-layer structure.

[0354] As the conductors 242a and 242b, metal nitrides are preferably used. For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0355] Note that hydrogen contained in the oxide 230 or the like may diffuse into the conductor 242 a or the conductor 242 b. In particular, when a tantalum nitride is used as the conductor 242 a or the conductor 242 b, hydrogen contained in the oxide 230 or the like may easily diffuse into the conductor 242 a or the conductor 242 b, and this diffused hydrogen may bond with nitrogen contained in the conductor 242 a or the conductor 242 b. In other words, hydrogen contained in the oxide 230 or the like may be absorbed by the conductor 242 a or the conductor 242 b.

[0356] In addition, if Figure 5BAs shown, conductors 242a and 242b may also have a two-layer structure. In this case, conductor 242a is a laminated film of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b is a laminated film of conductor 242b1 and conductor 242b2 on conductor 242b1. In this case, the layers in contact with oxide 230b (conductors 242a1 and 242b1) are preferably made of the aforementioned conductive materials that are not easily oxidized or have a function of inhibiting oxygen diffusion. This can prevent a decrease in the conductivity of conductors 242a and 242b.

[0357] The electrical conductivity of conductors 242a2 and 242b2 is preferably higher than that of conductors 242a1 and 242b1. For example, the thickness of conductors 242a2 and 242b2 is preferably greater than that of conductors 242a1 and 242b1. The conductors described above for conductor 205b can be used as conductors 242a2 and 242b2. This structure reduces the resistance of conductors 242a2 and 242b2, thereby increasing the operating speed of the transistor.

[0358] For example, tantalum nitride or titanium nitride can be used as the conductor 242 a 1 and the conductor 242 b 1 , and tungsten can be used as the conductor 242 a 2 and the conductor 242 b 2 .

[0359] Furthermore, to prevent a decrease in the conductivity of conductors 242a and 242b, a crystalline oxide such as CAAC-OS is preferably used as oxide 230b. In particular, a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin is preferably used. Using CAAC-OS can prevent conductors 242a and 242b from extracting oxygen from oxide 230b. Furthermore, a decrease in the conductivity of conductors 242a and 242b can be prevented.

[0360] like Figure 7 As shown in FIG, when the oxide 230 b is viewed from a cross section in the channel width direction, a curved surface may exist between the side surface of the oxide 230 b and the top surface of the oxide 230 b. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0361] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of oxide 230 b in the region overlapping conductor 242 a or conductor 242 b, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting this shape, the coverage of oxide 230 b by insulator 250 and conductor 260 in the channel width direction of the transistor can be improved.

[0362] exist Figure 1B In the embodiment shown in FIG. 1 , conductor 260 (conductors 260_1 to 260_3) has a two-layer structure. Conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed so as to surround the bottom and side surfaces of conductor 260b. In this case, conductor 260a is preferably made of a conductive material that is not easily oxidized or has a function of inhibiting oxygen diffusion.

[0363] Conductors 260a (conductors 260a1 to 260a3) are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) are preferably used.

[0364] Furthermore, when the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0365] Furthermore, conductors 260b (conductors 260b1 to 260b3) preferably use a highly conductive material. For example, conductors 260b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, conductors 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials.

[0366] In addition, if Figure 1B As shown in FIG, the conductor 260 is formed in a self-aligned manner so as to fit into an opening formed in the insulator 280. By forming the conductor 260 in this manner, the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without requiring alignment.

[0367] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 283. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0368] For example, the insulator 216 and the insulator 280 preferably each include one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having pores.

[0369] Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with pores are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0370] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0371] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0372] Figure 6 Shown with Figure 5A The transistors shown are different structures of the transistors in the channel length direction of the cross-sectional enlarged view. Note that Figure 6 The enlarged cross-sectional view of the transistor in the channel width direction shown can be referred to Figure 8A .

[0373] Figure 6 The transistor shown with Figure 5A The transistors shown differ in that: Figure 6 In the transistor shown, an insulator 256 is provided between the insulator 250 and the insulator 280 or the like in the opening formed in the insulator 280 or the like.

[0374] Insulator 256 is provided in such a manner as to be in contact with the sidewalls of the opening formed in insulator 280. Figure 6 As shown, insulator 256 has a region on one side wall of the opening that contacts the side surfaces of insulator 280, the side surfaces of insulator 275, the side surfaces of insulator 271a (insulator 271a1 and insulator 271a2), the side surfaces of conductor 242a2, and the top surface of conductor 242a1. Furthermore, insulator 256 has a region on the other side wall of the opening that contacts the side surfaces of insulator 280, the side surfaces of insulator 275, the side surfaces of insulator 271b (insulator 271b1 and insulator 271b2), the side surfaces of conductor 242b2, and the top surface of conductor 242b1.

[0375] like Figure 6As shown, when viewed from a cross section in the channel length direction of the transistor, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. Specifically, the difference between the distance L1 and the distance L2 is equal to or approximately equal to twice the thickness of the insulator 256. Here, the thickness of the insulator 256 refers to the thickness of at least a portion of the insulator 256 in the channel length direction of the transistor. By adopting this structure, the distance between the source and the drain can be further reduced, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of the transistor can be improved. In this way, by miniaturizing the channel length of the transistor, a semiconductor device with improved operating speed can be provided.

[0376] The opening provided in insulator 280 and the like overlaps the area between conductors 242a2 and 242b2. When viewed from a planar perspective, the side surfaces of the opening in insulator 280 are aligned or substantially aligned with the side surfaces of conductors 242a2 and 242b2. Furthermore, portions of conductors 242a1 and 242b1 are formed to protrude into the aforementioned opening. Here, a portion of the top surface of conductor 242a1 contacts conductor 242a2, and a portion of the top surface of conductor 242b1 contacts conductor 242b2. Therefore, insulator 256 contacts another portion of the top surface of conductor 242a1, another portion of the top surface of conductor 242b1, the side surfaces of conductor 242a2, and the side surfaces of conductor 242b2 within the aforementioned opening. Furthermore, insulator 250 contacts the top surface of oxide 230, the side surfaces of conductor 242a1, the side surfaces of conductor 242b1, and the side surfaces of insulator 256.

[0377] Insulator 256 is preferably an insulator that is not easily oxidized, such as a nitride. Insulator 256 is formed into a sidewall shape (also referred to as a sidewall insulating layer, sidewall protective layer, etc.) by anisotropic etching so as to contact the sidewalls of the opening provided in insulator 280. Insulator 256 is formed so as to contact the side surfaces of conductor 242a2 and conductor 242b2, and has the function of protecting conductors 242a2 and conductor 242b2. Since insulator 256 is formed so as to contact the side surfaces of conductor 242a2 and conductor 242b2, it can prevent conductors 242a2 and conductor 242b2 from excessive oxidation.

[0378] <Structural Example 2 of Semiconductor Device>

[0379] Figure 10A and Figure 10B A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 1> is shown. Figure 10A is a plan view of the semiconductor device 200 . Figure 10B It is along Figure 10A The cross-sectional view of the semiconductor device 200 is shown along the dot-dash line A1-A2. Figure 10A The cross-sectional view of the semiconductor device 200 along the dot-dash line A3-A4 can be referred to. Figure 2 or Figure 12 .

[0380] Figure 10A and Figure 10B The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 1 in that: Figure 10A and Figure 10B In the semiconductor device 200 shown in FIG. 1 , the conductor 243a is in contact with the side surface of the oxide 230_1, the side surface of the conductor 242a1, the side surface of the oxide 230_2, the side surface of the conductor 242a2, and the top surface of the conductor 242a2, and the conductor 243b is in contact with the side surface of the oxide 230_1, the side surface of the conductor 242b1, the side surface of the oxide 230_2, the side surface of the conductor 242b2, and the top surface of the conductor 242b2. Figure 10A and Figure 10B In the semiconductor device 200 shown, the conductor 244a contacts the side surfaces of the oxide 230_3, the side surfaces of the conductor 242a3, and the top surface of the conductor 242a3, and the conductor 244b contacts the side surfaces of the oxide 230_3, the side surfaces of the conductor 242b3, and the top surface of the conductor 242b3.

[0381] In addition, Figure 10A and Figure 10B In the semiconductor device 200 shown, the lengths of the oxides 230 (oxides 230_1 to 230_3 ) included in the transistors 200_1 to 200_3 in the channel length direction are shorter than those of the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>.

[0382] exist Figure 10A and Figure 10BIn the semiconductor device 200 shown, when viewed in a cross-section along the channel length of the transistor, the conductor 243a has a region in contact with the top surface of the insulator 216, one side surface of the oxide 230_1, one side surface of the conductor 242a1, one side surface of the oxide 230_2, and one side surface of the conductor 242a2. The conductor 243b has a region in contact with the top surface of the insulator 216, the other side surface of the oxide 230_1, one side surface of the conductor 242b1, the other side surface of the oxide 230_2, and one side surface of the conductor 242b2. For details other than those described above regarding the conductors 243a and 243b, refer to the description of the conductors 243a and 243b included in the semiconductor device 200 described in "Structural Example 1 of Semiconductor Device."

[0383] Figure 11A FIG shows a plan view of the semiconductor device 200. Note that Figure 11A The area including transistor 200_2 and its vicinity is shown. Figure 11A In the plan view, some components are omitted for clarity.

[0384] like Figure 11A As shown, the conductor 243a has a region in contact with the top surface of the conductor 242a2, and the conductor 243b has a region in contact with the top surface of the conductor 242b2. Figure 11A The top surfaces of the conductors 243a and 243b are shown as circular, but the present invention is not limited thereto. For example, the top surfaces of the conductors 243a and 243b may be elliptical, polygonal, or polygonal with rounded corners.

[0385] exist Figure 11B In FIG. 1 , the top surface of the conductor 243a is a polygonal shape with rounded corners. Figure 11B As shown, conductor 243a preferably contacts not only one side surface in the channel length direction but also the side surface in the channel width direction. This structure increases the contact area between conductor 243a and conductor 242a2, thereby improving the on-state current, field-effect mobility, and frequency characteristics of transistor 200_2. The same applies to conductor 243b.

[0386] In addition, Figure 10A and Figure 10BIn the semiconductor device 200 shown, when viewed in a cross-section along the channel length of the transistor, the conductor 244a has a region in contact with the top surface of the conductor 243a, one side surface of the oxide 230_3, and one side surface of the conductor 242a3. The conductor 244b has a region in contact with the top surface of the conductor 243b, the other side surface of the oxide 230_3, and one side surface of the conductor 242b3. For details other than those described above regarding the conductors 244a and 244b, refer to the description of the conductors 244a and 244b included in the semiconductor device 200 described in "Structural Example 1 of Semiconductor Device."

[0387] about Figure 10A and Figure 10B Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 1>.

[0388] pass Figure 10A and Figure 10B The semiconductor device 200 shown has the above-described structure, and can realize a semiconductor device that is even more miniaturized and highly integrated compared to the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>.

[0389] <Structural Example 3 of Semiconductor Device>

[0390] Figure 12 A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 1> is shown. Figure 12 This is a modified example of the cross-sectional view along the dot-dash line A3-A4 of the semiconductor device 200 shown in <Semiconductor device structure example 1> (a cross-sectional view in the channel width direction of each transistor of the semiconductor device 200). Note that the plan view of the semiconductor device 200 can be referred to. Figure 1A or Figure 10A In addition, the cross-sectional view of each transistor in the channel length direction of the semiconductor device 200 can be referred to Figure 1B or Figure 10B .

[0391] Figure 12 The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 1 in that: Figure 12 In the semiconductor device 200 shown, conductors serving as plugs for electrically connecting gate electrodes of transistors are composed of a conductor 253 (a conductor 253a and a conductor 253b) and a conductor 254 (a conductor 254a and a conductor 254b).

[0392] Conductor 253 includes conductor 253a and conductor 253b on conductor 253a. Conductor 253a is provided so as to contact the sidewalls of the openings provided in insulators 222_1, 275_1, 280_1, 222_2, 275_2, 280_2, and 222_3, and the top surface of conductor 205. Conductor 253a has a region in contact with the top surface of conductor 260_1. Conductor 253b is provided so as to fit into the openings.

[0393] Conductor 254 includes conductor 254a and conductor 254b on conductor 254a. Conductor 254a is provided so as to contact the sidewalls of openings provided in insulators 222_3, 275_3, 280_3, 286, 283, and 287. Conductor 254a has a region in contact with the top surface of conductor 253, the top surface of conductor 260_2, and the top surface of conductor 260_3. Conductor 254b is provided so as to fit into the openings. For details other than those described above regarding conductor 254, refer to the description of conductor 254 included in semiconductor device 200 described in "Structural Example 1 of Semiconductor Device."

[0394] Conductor 253a can be formed of the same material as conductor 254a. Conductor 253b can be formed of the same material as conductor 254b. In other words, conductor 253a is preferably formed of a conductive material that has the function of inhibiting oxygen diffusion. Conductor 253b is preferably formed of a material with higher conductivity than conductor 253a.

[0395] The conductors 253 and 254 are electrically connected to the conductor 205, the conductor 260_1, the conductor 260_2, and the conductor 260_3. Therefore, the conductors 253 and 254 function as a plug that electrically connects the conductors 260_1 to 260_3, which serve as the gate electrodes (first gate electrodes) of the transistors 200_1 to 200_3, the conductor 205, which serves as the second gate electrode of the transistor 200_1, and the conductor 255, which serves as a wiring.

[0396] about Figure 12 Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 1>.

[0397] By making Figure 12 The semiconductor device 200 shown has the above-described structure, and can simultaneously form a plug for electrically connecting the source electrodes of each transistor, a plug for electrically connecting the drain electrodes of each transistor, and a plug for electrically connecting the gate electrodes of each transistor.

[0398] For example, in Figure 12 It is along Figure 10A and Figure 10B In the case of the cross-sectional view of the semiconductor device 200 shown along the dotted line A3-A4, the conductors 243a, 243b, and 253 can be formed in the same process. In addition, the conductors 244a, 244b, and 254 can be formed in the same process. Therefore, compared with the semiconductor device 200 shown in <Structural Example 1 of the Semiconductor Device>, Figure 12 The semiconductor device 200 shown can reduce the number of steps.

[0399] <Structural Example 4 of Semiconductor Device>

[0400] Figure 13A and Figure 13B A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 1> is shown. Figure 13A is a plan view of the semiconductor device 200 . Figure 13B It is along Figure 13A The cross-sectional view of the semiconductor device 200 is shown along the dot-dash line A3-A4. Figure 13A The cross-sectional view of the semiconductor device 200 along the dot-dash line A1-A2 can be referred to. Figure 1B or Figure 10B .

[0401] Figure 13A and Figure 13B The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 1 in that: Figure 13A and Figure 13B In the semiconductor device 200 shown, the conductors serving as gate electrodes of transistors 200_1 through 200_3 (conductors 260_1 through 260_3) have the same size and shape in the channel width direction. That is, when viewed from a planar perspective, the ends of conductors 260_1 through 260_3 are substantially aligned. Furthermore, the aforementioned differences are as follows: Figure 13A and Figure 13B The semiconductor device 200 shown does not include a conductor serving as a plug for connecting the gate electrodes of the transistors, and the two gate electrodes of the transistors are directly connected.

[0402] like Figure 13B As shown, the conductor 260_1 (the conductor 260a1 and the conductor 260b1) serving as the gate electrode of the transistor 200_1 has a region in contact with the top surface of the conductor 205 through the openings provided in the insulator 222_1 and the insulator 250_1.

[0403] Furthermore, the conductor 260_2 (the conductor 260a2 and the conductor 260b2) serving as the gate electrode of the transistor 200_2 has a region in contact with the top surface of the conductor 260_1 through the openings provided in the insulator 222_2 and the insulator 250_2.

[0404] Furthermore, the conductor 260_3 (the conductor 260a3 and the conductor 260b3) serving as the gate electrode of the transistor 200_3 has a region in contact with the top surface of the conductor 260_2 through the openings provided in the insulator 222_3 and the insulator 250_3.

[0405] Conductors 254 (conductors 254a and 254b) are provided so as to contact the sidewalls of the openings provided in insulators 286, 283, and 287. Conductor 254a has a region in contact with the top surface of conductor 260_3. Conductor 254b is provided on conductor 254a so as to fit into the opening. Regarding conductors 254 other than those described above, refer to the description of conductors 254 included in semiconductor device 200 described in "Structural Example 1 of Semiconductor Device."

[0406] like Figure 13A and Figure 13B As shown, the ends of the conductive bodies (conductors 260_1 to 260_3) serving as gate electrodes included in each transistor are substantially aligned in the channel width direction. In other words, they have the same size and shape.

[0407] In addition, Figure 13A and Figure 13B In the semiconductor device 200 shown, the top surface of the gate electrode of one transistor contacts the bottom surface of the gate electrode of another transistor located above it. Therefore, there is no need for a plug connecting the gate electrodes of the transistors, as in the semiconductor device 200 shown in <Semiconductor Device Structure Example 1>.

[0408] Therefore, since the plug is not included, the size of the semiconductor device in the channel width direction can be reduced.

[0409] Furthermore, because the gate electrodes of the transistors included in semiconductor device 200 have the same size and shape, it is not necessary to use a different mask to form the gate electrodes of each transistor in each layer. In other words, the gate electrodes of all transistors can be formed using only one mask. Consequently, compared to semiconductor device 200 described in <Semiconductor Device Structure Example 1>, manufacturing costs can be reduced.

[0410] Furthermore, even if the ends of conductors 260_1 through 260_3 are misaligned in the channel width direction, conductors 260_1 and 260_2 can be reliably connected via the openings provided in insulators 222_2 and 250_2. Furthermore, conductors 260_2 and 260_3 can be reliably connected via the openings provided in insulators 222_3 and 250_3. Consequently, the positional alignment accuracy of the openings provided in conductors 260 and 250 is relaxed, thereby reducing the difficulty in manufacturing the micro memory cell.

[0411] Note that when the conductor 205 is also used as wiring, as in Figure 14A and Figure 14B As shown in FIG, the conductor 255 and the conductor 254 may not be provided. In this case, since the manufacturing process of the conductor 255 and the conductor 254 is not required, Figure 13A and Figure 13B Compared with the semiconductor device 200 shown in FIG. 1 , the number of steps can be reduced and the manufacturing cost can be reduced.

[0412] about Figure 13A and Figure 13B Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 1>.

[0413] <Structural Example 5 of Semiconductor Device>

[0414] Figures 15 to 17 A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 1> is shown. Figure 15 is a plan view of the semiconductor device 200 . Figure 16 It is along Figure 15 FIG. 2 is a cross-sectional view of the semiconductor device 200 taken along the dashed line A1 - A2 . Figure 17 It is along Figure 15 The cross-sectional view of the semiconductor device 200 is shown along the dashed line A3 - A4 .

[0415] Figures 15 to 17 The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 1 in that: Figures 15 to 17 In the semiconductor device 200 shown, the oxides 230_1 to 230_3 of the semiconductor layers used to form the channels of the transistors 200_1 to 200_3 all have a single-layer structure. Figure 16 As shown, in the channel length direction ( Figure 15In the direction of the dotted line A1-A2 shown in the figure, the conductors 242a1 to 242a3 used as one of the source electrodes and drain electrodes of the transistors 200_1 to 200_3 and the conductors 242b1 to 242b3 used as the other of the source electrodes and drain electrodes of the transistors 200_1 to 200_3 all cover the side surfaces and top surfaces of the oxides 230_1 to 230_3.

[0416] In addition, the above differences are: Figure 17 As shown, in the channel width direction ( Figure 15 In the dashed-dotted line A3-A4 direction shown in FIG. 1 , the transistors 200_1 to 200_3, the conductor 205, the conductor 254, and the conductor 255 are arranged so as to face each other on the A3 side and the A4 side.

[0417] That is to say, Figures 15 to 17 The semiconductor device 200 shown can be said to have a structure including two transistors 200_1 to 200_3 , two conductors 205 , two conductors 254 , and two conductors 255 .

[0418] In addition, as described below, Figures 15 to 17 The semiconductor device 200 shown can simultaneously form the two transistors 200_1, the two transistors 200_2, and the two transistors 200_3.

[0419] Note that unlike the transistor 200_1 included in the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>, Figures 15 to 17 In the transistor 200_1 included in the semiconductor device 200 shown, the oxide 230_1 has a single-layer structure. Figures 15 to 17 The oxide 230_1 in the transistor 200_1 included in the semiconductor device 200 shown in the figure can be made of the same material as either the oxide 230a1 or the oxide 230b1 constituting the oxide 230_1 in the transistor 200_1 included in the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>.

[0420] Furthermore, unlike the transistor 200_1 included in the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>, Figures 15 to 17 In the transistor 200_1 included in the semiconductor device 200 shown in the figure, the conductor 242a1 and the conductor 242b1 extend to the outside of the side surface of the oxide 230_1 that does not face the conductor 260_1. Figures 15 to 17In the transistor 200_1 included in the semiconductor device 200 shown, the conductor 242a1 contacts one (A1 side) top and side surface of the oxide 230_1, with the conductor 260_1 as the axis, and one (A1 side) top surface of the insulator 222_1. Furthermore, the conductor 242b1 contacts the other (A2 side) top and side surface of the oxide 230_1, with the conductor 260_1 as the axis, and the other (A2 side) top surface of the insulator 222_1. By adopting this structure, the area of contact between the oxide 230_1 and the conductor 242a1 increases, thereby reducing the contact resistance between the oxide 230_1 and the conductor 242a1. Furthermore, the area of contact between the oxide 230_1 and the conductor 242b1 increases, thereby reducing the contact resistance between the oxide 230_1 and the conductor 242b1. Consequently, a transistor 200_1 with a large on-state current can be realized.

[0421] Furthermore, when viewed from a planar perspective, the conductor 242a1 and the conductor 242b1 are provided on the oxide 230_1 so as to sandwich the insulator 250_1 and the conductor 260_1. Figure 16 As shown, the side surfaces of the conductors 242 a 1 and 242 b 1 that do not face the conductor 260_ 1 extend outside the side surfaces of the oxide 230_ 1 .

[0422] The insulator 275_1 is provided in contact with the top surface of the conductor 242a1, the side surface of the conductor 242a1 not facing the conductor 260_1, the top surface of the conductor 242b1, the side surface of the conductor 242b1 not facing the conductor 260_1, and the top surface of the insulator 222_1.

[0423] Regarding transistor 200_2 and transistor 200_3, by replacing the last digits (the digits after “_”) of the symbols of oxide 230_1, conductor 242a1, conductor 242b1, insulator 250_1, conductor 260_1, insulator 222_1, and insulator 275_1 in transistor 200_1 respectively, the contents described above for transistor 200_1 can be referred to.

[0424] In addition, if Figures 15 to 17 As shown, the ends of the conductors (conductors 260_1 to 260_3) serving as the gate electrodes of the transistors 200_1 to 200_3 on the sides facing each other are roughly aligned. On the other hand, the ends of the two transistors 200_1 to 200_3 on the sides not facing each other are not aligned, and the ends of the gate electrodes of the transistors are closer to the outside as they are closer to the lower layer. That is, in the semiconductor device 200 of one embodiment of the present invention, when viewed from a cross section in the channel width direction of the transistor (refer to Figure 17 ), the gate electrode of each transistor has two step shapes facing each other.

[0425] As mentioned above, in Figures 15 to 17 The semiconductor device 200 shown in the figure includes two transistors 200_1 to 200_3 , and thus a larger on-state current can be obtained compared to the semiconductor device 200 shown in <Structural Example 1 of Semiconductor Device>.

[0426] about Figures 15 to 17 Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 1>.

[0427] <Structural Example 6 of Semiconductor Device>

[0428] Figure 18 and Figure 19 A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 5> is shown. Figure 18 is a plan view of the semiconductor device 200 . Figure 19 It is along Figure 18 The cross-sectional view of the semiconductor device 200 along the dashed line A3-A4 (a cross-sectional view along the channel width direction of each transistor of the semiconductor device 200) is shown. Figure 18 The cross-sectional view of the semiconductor device 200 along the dot-dash line A1-A2 (a cross-sectional view along the channel length direction of each transistor of the semiconductor device 200) can be referred to. Figure 16 .

[0429] Figure 18 and Figure 19 The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in <Structural Example 5 of Semiconductor Device> in that: Figure 18 and Figure 19 The semiconductor device 200 shown includes only one conductor 254 serving as a plug for electrically connecting the gate electrodes (conductor 260 and conductor 205) of the transistors and one conductor 255 serving as a wiring. Figure 18 and Figure 19 The example shows conductors 254 and 255 provided between two transistors 200_1, 200_2, and 200_3 in the channel width direction of transistors 200_1 to 200_3. Also shown is an example where both conductors 205 and 255 extend toward A4.

[0430] In addition, the above differences are: Figure 18 and Figure 19In the semiconductor device 200 shown, two oxides 230_1 provided in the channel width direction of the transistor 200_1 share the conductor 205 .

[0431] about Figure 18 and Figure 19 Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 5>.

[0432] By making Figure 18 and Figure 19 The semiconductor device 200 shown has the above-described structure, and can apply a gate electric field to all oxides 230 of each transistor included in the semiconductor device 200 using only one plug (conductor 254 ) and one wiring (conductor 255 ).

[0433] In addition, by Figure 18 and Figure 19 The number of conductors 254 and 255 included in the semiconductor device 200 shown is reduced to half the number of conductors 254 and 255 included in the semiconductor device 200 shown in <Structural Example 5 of Semiconductor Device>, which can reduce the area occupied by the semiconductor device 200 within the substrate surface.

[0434] <Structural Example 7 of Semiconductor Device>

[0435] Figure 20 and Figure 21 A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 5> is shown. Figure 20 is a plan view of the semiconductor device 200 . Figure 21 It is along Figure 20 The cross-sectional view of the semiconductor device 200 along the dot-dash line A3-A4 (a cross-sectional view along the channel width direction of each transistor of the semiconductor device 200) is shown. Figure 20 The cross-sectional view of the semiconductor device 200 along the dot-dash line A1-A2 (a cross-sectional view along the channel length direction of each transistor of the semiconductor device 200) can be referred to. Figure 16 .

[0436] Figure 20 and Figure 21 The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 5 in that: Figure 20 and Figure 21In the semiconductor device 200 shown, two oxides 230 provided in the channel width direction of each transistor share one insulator 250 used as the first gate insulator of each transistor and one conductor 260 used as the first gate electrode of each transistor. Figure 20 and Figure 21 In the semiconductor device 200 shown, two oxides 230_1 provided in the channel width direction of the transistor 200_1 share one conductor 205 serving as the second gate electrode of the transistor 200_1 .

[0437] In addition, the above differences are: Figure 20 and Figure 21 The semiconductor device 200 shown includes only one conductor 254 serving as a plug for electrically connecting the gate electrodes (conductor 260 and conductor 205) of the transistors and one conductor 255 serving as a wiring. Figure 20 and Figure 21 The example in which the conductors 254 and 255 are provided only on the A4 side in the channel width direction of each transistor and not on the A3 side is shown. The example in which the conductor 205 extends to the A4 side is also shown.

[0438] about Figure 20 and Figure 21 Regarding the semiconductor device 200 shown, for details other than those described above, reference can be made to the description of the semiconductor device 200 shown in <Semiconductor Device Configuration Example 5>.

[0439] By making Figure 20 and Figure 21 The semiconductor device 200 shown has the above-described structure, and can apply a gate electric field to all oxides 230 of each transistor included in the semiconductor device 200 using only one plug (conductor 254 ) and one wiring (conductor 255 ).

[0440] In addition, by Figure 20 and Figure 21 The number of conductors 254 and 255 included in the semiconductor device 200 shown is reduced to half the number of conductors 254 and 255 included in the semiconductor device 200 shown in <Structural Example 5 of Semiconductor Device>, which can reduce the area occupied by the semiconductor device 200 within the substrate surface.

[0441] In addition, Figure 20 and Figure 21In the semiconductor device 200 shown, the insulator 280 does not need to remain between two oxides 230 adjacent in the channel width direction. Therefore, the distance between two oxides 230 adjacent in the channel width direction can be reduced, thereby reducing the area occupied by the semiconductor device 200 within the substrate surface.

[0442] <Structural Example 8 of Semiconductor Device>

[0443] Figures 22 to 24 A structural example of a semiconductor device 200 different from that of <Semiconductor Device Structural Example 5> is shown. Figure 22 is a plan view of the semiconductor device 200 . Figure 23 It is along Figure 22 1 is a cross-sectional view of the semiconductor device 200 taken along the dashed line A1 - A2 (a cross-sectional view taken along the channel length direction of each transistor of the semiconductor device 200 ). Figure 24 It is along Figure 22 The cross-sectional view of the semiconductor device 200 is shown along the dot-dash line A5-A6. Figure 22 The cross-sectional view of the semiconductor device 200 along the dot-dash line A3-A4 (a cross-sectional view along the channel width direction of each transistor of the semiconductor device 200) can be referred to. Figure 21 .

[0444] Figures 22 to 24 The semiconductor device 200 shown in FIG. 1 is different from the semiconductor device 200 shown in FIG. 5 in that: Figures 22 to 24 In the semiconductor device 200 shown, the conductor 242a included in the transistor 200_1 is located on a portion of the top surface and a portion of the side surface of the oxide 230 included in another transistor 200_1 arranged in the channel width direction of the transistor 200_1. In other words, the difference is that: Figures 22 to 24 In the semiconductor device 200 shown, two oxides 230_1 provided in the channel width direction of the transistor 200_1 share the conductor 242a. Figures 22 to 24 In the semiconductor device 200 shown, the conductor 242b included in the transistor 200_1 is located on a portion of the top surface and a portion of the side surface of the oxide 230 included in another transistor 200_1 arranged in the channel width direction of the transistor 200_1. In other words, the difference is that: Figures 22 to 24 In the semiconductor device 200 shown, two oxides 230_1 provided in the channel width direction of the transistor 200_1 share the conductor 242b.

[0445] In addition, the above differences are: Figures 22 to 24In the semiconductor device 200 shown in FIG. 1 , the conductor 243a is in contact with the region of the conductor 242a1 that does not overlap with the oxide 230_1 and the region of the conductor 242a2 that does not overlap with the oxide 230_2. Figures 22 to 24 In the semiconductor device 200 shown, the conductor 243 b is in contact with a region of the conductor 242 b 1 that does not overlap with the oxide 230_1 and a region of the conductor 242 b 2 that does not overlap with the oxide 230_2 .

[0446] In addition, the above differences are: Figures 22 to 24 In the semiconductor device 200 shown, the conductor 244a is in contact with the region of the conductor 242a3 that does not overlap with the oxide 230_3. Figures 22 to 24 In the semiconductor device 200 shown, the conductor 244 b is in contact with a region of the conductor 242 b 3 that does not overlap with the oxide 230_3 .

[0447] By adopting the above structure, the transistors 200_1 to 200_3 can be connected in parallel with the transistors 200_1 to 200_3 arranged in the channel width direction of the transistors 200_1 to 200_3. Therefore, compared with the case of including only one of the transistors 200_1 to 200_3, Figures 22 to 24 The semiconductor device 200 shown can output six times the on-state current (assuming that the transistors 200_1 to 200_3 all have the same current generating capability).

[0448] also, Figure 24 The structure shown is that conductor 244a is in contact with conductor 243a, and conductor 244b is in contact with conductor 243b. Furthermore, the structure shown is that conductor 243a is in contact with conductor 242a1, and conductor 243b is in contact with conductor 242b1. Specifically, conductor 244a is disposed within openings formed in insulator 287, insulator 283, insulator 286, insulator 280_3, insulator 275_3, and conductor 242a3, and conductor 243a is disposed within openings formed in insulator 222_3, insulator 280_2, insulator 275_2, conductor 242a2, insulator 222_2, insulator 280_1, and insulator 275_1. In addition, the conductor 244b is configured in an opening formed in the insulator 287, the insulator 283, the insulator 286, the insulator 280_3, the insulator 275_3 and the conductor 242b3, and the conductor 243b is configured in an opening formed in the insulator 222_3, the insulator 280_2, the insulator 275_2, the conductor 242b2, the insulator 222_2, the insulator 280_1 and the insulator 275_1.

[0449] Note that the present invention is not limited to the above structure. Conductor 244a and conductor 243a may be electrically connected via conductor 242a3, and conductor 244b and conductor 243b may be electrically connected via conductor 242b3. Furthermore, conductor 243a and conductor 242a1 may be electrically connected via a conductor provided between transistor 200_1 and transistor 200_2, and conductor 243b and conductor 242b1 may be electrically connected via a conductor provided between transistor 200_1 and transistor 200_2.

[0450] For example, Figure 25 As shown, it is preferred that the conductor 244a is set in the opening formed in the insulator 287, the insulator 283, the insulator 286, the insulator 280_3 and the insulator 275_3, the conductor 243a is set in the opening formed in the insulator 222_3, the insulator 280_2 and the insulator 275_2, and the conductor 246a is set in the opening formed in the insulator 222_2, the insulator 280_1 and the insulator 275_1. Similarly, it is preferable to arrange the conductor 244b in the openings formed in the insulators 287, 283, 286, 280_3, and 275_3; arrange the conductor 243b in the openings formed in the insulators 222_3, 280_2, and 275_2; and arrange the conductor 246b in the openings formed in the insulators 222_2, 280_1, and 275_1. This allows the conductors 242a1 to 242a3 to be electrically connected to the conductor 245a. Similarly, the conductors 242b1 to 242b3 to the conductor 245b can be electrically connected.

[0451] The above structure eliminates the need for openings in the conductors 242a2, 242b2, 242a3, and 242b3. Therefore, the distance between the two transistors 200_1 in the channel width direction can be reduced, thereby reducing the area occupied by the semiconductor device 200 within the substrate surface.

[0452] also, Figure 22 The structure in which the oxide 230_1 is separated between transistors 200_1 that share the conductor 242a and the conductor 242b is shown. Note that the present invention is not limited to this. The oxide 230 may also be provided as a continuous layer between transistors 200_1 that share the conductor 242a and the conductor 242b.

[0453] For example, Figure 26As shown, the top surface shape of the oxide 230_1 can also be a quadrangle. By adopting this structure, it is unnecessary to separate the oxide 230_1 between the transistors 200_1 that share the conductor 242a and the conductor 242b. Therefore, the total number of steps can be reduced, thereby realizing an inexpensive semiconductor device. Note that Figure 27 It is along Figure 26 The cross-sectional view of the semiconductor device 200 is shown along the dashed line A5 - A6 .

[0454] <Materials Constituting Semiconductor Devices>

[0455] The following describes constituent materials that can be used for the semiconductor device 200 according to one embodiment of the present invention. Note that each layer constituting the semiconductor device 200 may have a single-layer structure or a stacked-layer structure.

[0456] <<Substrate>>

[0457] As a substrate for forming the transistors included in semiconductor device 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides, substrates containing metal oxides, insulating substrates provided with conductors or semiconductors, semiconductor substrates provided with conductors or insulators, and conductive substrates provided with semiconductors or insulators. Alternatively, substrates having one or more elements provided on these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

[0458] <<Insulator>>

[0459] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0460] For example, as transistors become increasingly miniaturized and highly integrated, problems such as leakage current may arise due to thinner gate insulators. Using a high-k material as a gate insulator allows for lower transistor operating voltages while maintaining the physical thickness. On the other hand, using a material with a low relative dielectric constant as an insulator for the interlayer film reduces parasitic capacitance between wiring lines. Therefore, it is preferable to select the insulator material based on its function.

[0461] Examples of insulators with a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0462] Examples of insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, silicon oxide having pores, and resins.

[0463] In addition, by surrounding a transistor using a metal oxide with an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or a stack of insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0464] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies contained in the oxide 230 can be filled.

[0465] <<Conductor>>

[0466] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, an oxide comprising lanthanum and nickel, etc. can be enumerated. In addition, tantalum nitride, titanium nitride, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, an oxide comprising lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Alternatively, a semiconductor with high conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0467] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0468] Furthermore, when an oxide is used in the channel formation region of a transistor, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen is preferably employed as the conductor used as the gate electrode. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. By positioning the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0469] In particular, as a conductor used as a gate electrode, it is preferable to use a conductive material containing a metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal elements and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0470] <<Metal Oxides>>

[0471] A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Hereinafter, a metal oxide that can be used as the oxide 230 in one embodiment of the present invention will be described.

[0472] The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, it preferably contains aluminum, gallium, yttrium, tin, antimony, and the like. Furthermore, it may contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0473] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or antimony. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that the element M may sometimes be a combination of multiple of the above elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0474] In this specification and other documents, metal oxides containing nitrogen may also be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0475] Hereinafter, In—Ga—Zn oxide will be described as an example of the metal oxide.

[0476] Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC, CAC (Cloud-Aligned Composite), single crystal, and polycrystal.

[0477] In addition, when focusing on the structure of oxide semiconductors, the classification of oxide semiconductors is sometimes different from the above. For example, oxide semiconductors can be classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0478] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0479] [CAAC-OS]

[0480] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axes of the plurality of crystalline regions are oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a uniform lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a uniform lattice arrangement and other regions having a uniform lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0481] In addition, each of the plurality of crystalline regions is composed of one or more microcrystals (crystals having a maximum diameter of less than 10 nm). In the case where a crystalline region is composed of a single microcrystal, the maximum diameter of the crystalline region is less than 10 nm. In the case where a crystalline region is composed of a plurality of microcrystals, the maximum diameter of the crystalline region is sometimes about several tens of nm.

[0482] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the incorporation of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor containing CAAC-OS are stable. Therefore, the oxide semiconductor containing CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called heat accumulation) in the manufacturing process. Therefore, by using CAAC-OS in the OS transistor, the degree of freedom of the manufacturing process can be expanded.

[0483] [nc-OS]

[0484] In nc-OS, the atomic arrangement in a tiny region (for example, a region greater than 1 nm and less than 10 nm, in particular a region greater than 1 nm and less than 3 nm) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is greater than 1 nm and less than 10 nm, in particular greater than 1 nm and less than 3 nm, and the tiny crystal is called a nanocrystal. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductor in certain analysis methods.

[0485] [a-like OS]

[0486] An a-like OS is an oxide semiconductor with a structure intermediate between that of amorphous oxide semiconductors and nc-OS. It contains voids or low-density regions. This means that a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in an a-like OS film is higher than that in nc-OS and CAAC-OS films.

[0487] Next, the details of the aforementioned CAC-OS will be described. Furthermore, CAC-OS is related to material composition.

[0488] [CAC-OS]

[0489] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing these metal elements are mixed is also referred to as a mosaic or patch-like structure below, and the size of these regions is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0490] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is separated into a first region and a second region, forming a mosaic shape, and the first region is distributed in the film (hereinafter also referred to as a cloud shape). In other words, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0491] Furthermore, CAC-OS in In-Ga-Zn oxide refers to a structure in which a portion of the main component, In (first region) and a portion of the main component, Ga (second region), are irregularly distributed in a mosaic pattern within a material composition containing In, Ga, Zn, and O. Therefore, it is speculated that CAC-OS has a structure in which the metal elements are unevenly distributed.

[0492] CAC-OS can be formed, for example, by sputtering without heating the substrate. When forming CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen, and nitrogen can be used as the deposition gas. Furthermore, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0493] Here, the first region has higher conductivity than the second region. That is, when carriers flow through the first region, it exhibits the conductivity of a metal oxide. Therefore, when the first region is distributed in a cloud-like pattern within the metal oxide, a high field-effect mobility (μ) can be achieved.

[0494] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0495] Thus, when CAC-OS is used in transistors, the complementary effects of the conductivity of the first region and the insulation of the second region can give the CAC-OS a switching function (a function that controls on / off). In other words, a portion of the CAC-OS material has a conductive function and another portion has an insulating function, resulting in the material as a whole having a semiconductor function. By separating the conductive and insulating functions, each function can be maximized. Therefore, by using CAC-OS in transistors, a large on-state current (I on ), high field-effect mobility (μ) and good switching performance.

[0496] Furthermore, transistors using CAC-OS have high reliability, making it ideal for various semiconductor devices such as display devices.

[0497] Oxide semiconductors have various structures and properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0498] <<Other semiconductor materials>>

[0499] Note that the semiconductor material that can be used for the semiconductor layer of the transistor is not limited to the above-mentioned metal oxides. As the semiconductor, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) can also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used as the semiconductor material.

[0500] Here, in this specification, etc., layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0501] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used in semiconductor layers include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0502] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used in the semiconductor layer preferably includes crystals having a cubic structure.

[0503] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogenides. Chalcogenides are a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and lead. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0504] In addition, as the semiconductor layer of the transistor, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As transition metal chalcogenides that can be used as the semiconductor layer of the transistor, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be mentioned. By using the above-mentioned transition metal chalcogenides for the semiconductor layer of the transistor, a semiconductor device with a large on-state current can be provided.

[0505] <Example 1 of Method for Manufacturing Semiconductor Device>

[0506] use Figures 28A to 56B An example of a method for manufacturing a semiconductor device 200 according to one embodiment of the present invention is described. Figures 1A to 2 The case of the semiconductor device 200 shown will be described as an example.

[0507] In FIG. 28 to FIG. 56, A of each figure is along Figure 1A The cross-sectional view along the dotted line A1-A2 is also a cross-sectional view along the channel length direction of each transistor included in the semiconductor device 200. Figure 1A The cross-sectional view taken along the dashed line A3 - A4 is also a cross-sectional view of each transistor included in the semiconductor device 200 in the channel width direction.

[0508] Hereinafter, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors may be appropriately deposited using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0509] Examples of sputtering methods include RF sputtering, which uses a high-frequency power source for the sputtering power supply; DC sputtering, which utilizes a direct current power source; and pulsed DC sputtering, which varies the voltage applied to the electrode in a pulsed manner. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metallic conductive films. Furthermore, pulsed DC sputtering is primarily used for depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0510] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, they can be further categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0511] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, because plasma is not used, the thermal CVD method is a deposition method that can reduce the plasma damage caused to the object to be processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charge. On the other hand, because the above-mentioned plasma damage is not generated in the case of the thermal CVD method without plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0512] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, and the like are used.

[0513] CVD and ALD differ from sputtering, which deposits particles released from a target material. Therefore, CVD and ALD are deposition methods that are less susceptible to the shape of the workpiece and exhibit excellent step coverage. In particular, ALD offers excellent step coverage and thickness uniformity, making it suitable for coating surfaces with openings having high aspect ratios. However, ALD has a relatively slow deposition rate, making it sometimes preferable to combine it with other deposition methods, such as CVD, which have faster deposition rates.

[0514] Furthermore, when using the CVD method, films of arbitrary compositions can be deposited by adjusting the flow ratio of the source gases. For example, by changing the flow ratio of the source gases during deposition, films with continuously varying compositions can be deposited. When deposition is performed while changing the flow ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transferring or adjusting the pressure is not required. Consequently, the productivity of semiconductor devices can sometimes be improved.

[0515] When using the ALD method, a film of any composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0516] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate. Insulator 215 preferably uses an insulator that inhibits the permeation of impurities such as hydrogen and oxygen. For example, insulator 215 can be deposited by sputtering, CVD, MBE, PLD, or ALD. Sputtering, which does not require the use of molecules containing hydrogen as a deposition gas, is preferred because it can reduce the hydrogen concentration in insulator 215.

[0517] Next, an insulator 216 is deposited on the insulator 215 ( Figure 28A and Figure 28B The insulator 216 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method. For example, a CVD method, an MBE method, a PLD method, or an ALD method may also be used as appropriate.

[0518] For example, silicon oxide is deposited by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen as the insulator 216. Pulsed DC sputtering can make the thickness distribution more uniform, thereby improving the sputtering rate and film quality.

[0519] Insulators 215 and 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows deposition of insulators 215 and 216 while reducing the amount of hydrogen in the film and reducing the incorporation of hydrogen into the film between deposition steps.

[0520] Next, an opening 121 ( Figure 29A and Figure 29B When forming the opening 121, a wet etching method can be used, but a dry etching method is preferred for micromachining. As the insulator 215, it is preferable to select an insulator that is used as an etching stopper when etching the insulator 216 to form the groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as the insulator 215.

[0521] Note that when the opening 121 is formed, the thickness of the insulator 215 in a region overlapping with the opening 121 may be smaller than the thickness of the insulator 215 in a region not overlapping with the opening 121 .

[0522] After the opening 121 is formed, a conductive film serving as the conductor 205a is deposited. The conductive film preferably includes a conductor that inhibits oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like may be used. Alternatively, the conductive film may include a laminated film of a conductor that inhibits oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film may be deposited, for example, by sputtering, CVD, MBE, PLD, ALD, or the like.

[0523] For example, titanium nitride is formed as the conductive film used as the conductor 205a. By using the above-mentioned metal nitride as the lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. In addition, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, diffusion of the metal from the conductor 205a to the outside can be prevented.

[0524] Next, a conductive film, which will become the conductor 205b, is deposited. For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used for this conductive film. This conductive film can be deposited, for example, by plating, sputtering, CVD, MBE, PLD, or ALD. For example, tungsten is deposited as this conductive film.

[0525] Next, a chemical mechanical polishing (CMP) process is performed to remove the conductive film to be the conductor 205a and a portion of the conductive film to be the conductor 205b, thereby exposing the top surface of the insulator 216 ( Figure 30A and Figure 30B ). As a result, the conductors 205a and 205b remain only in the opening 121. Note that part of the insulator 216 may be removed by the CMP process.

[0526] Next, an insulator 222_1 is deposited on the insulator 216 and the conductor 205 (the conductor 205a and the conductor 205b). As the insulator 222_1, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222_1 has a barrier property to hydrogen and water, it is possible to suppress the diffusion of hydrogen and water contained in the surrounding structures of the transistor into the inside of the transistor through the insulator 222_1, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0527] Alternatively, the insulator 222_1 may be a stacked film of an insulator including an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0528] The insulator 222_1 can be deposited, for example, by sputtering, CVD, MBE, PLD, ALD, or the like. For example, hafnium oxide is deposited by ALD as the insulator 222_1. Alternatively, the insulator 222_1 can be a stacked structure of silicon nitride deposited by PEALD and hafnium oxide deposited by ALD.

[0529] Next, an oxide film 230A1 is deposited on the insulator 222_1, and an oxide film 230B1 is deposited on the oxide film 230A1. A metal oxide corresponding to the oxide 230a described above can be used for the oxide film 230A1, and a metal oxide corresponding to the oxide 230b described above can be used for the oxide film 230B1. It is preferable to continuously deposit the oxide films 230A1 and 230B1 without exposing them to the atmosphere. Depositing the oxide films without exposing them to the atmosphere prevents impurities and moisture from the atmosphere from adhering to the oxide films 230A1 and 230B1, thereby keeping the interface between the oxide films 230A1 and 230B1 clean.

[0530] The oxide film 230A1 and the oxide film 230B1 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. For example, sputtering is used as a deposition method for the oxide film 230A1 and the oxide film 230B1.

[0531] For example, when depositing the oxide films 230A1 and 230B1 by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the oxygen ratio contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the oxide films by sputtering, an In-M-Zn oxide target or the like can be used.

[0532] In particular, when depositing the oxide film 230A1, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 222_1. Therefore, the ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.

[0533] In the case of forming the oxide film 230B1 by sputtering, an oxygen-excess oxide semiconductor can be formed by depositing the oxide film 230B1 under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 230B1 by sputtering, an oxygen-deficient oxide semiconductor is formed when deposition is performed under the condition that the ratio of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field-effect mobility. In addition, by depositing the oxide film while heating the substrate, the crystallinity of the oxide film can be improved.

[0534] For example, oxide film 230A1 is deposited by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 1:3:2 or an In:Ga:Zn atomic ratio of 1:3:4. Alternatively, oxide film 230B1 can be deposited by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 1:1:1, an In:Ga:Zn atomic ratio of 1:1:1.2, an In:Ga:Zn atomic ratio of 4:2:4.1, or an In:Ga:Zn atomic ratio of 1:1:2. Each oxide film is preferably formed by appropriately selecting deposition conditions and atomic ratios based on the desired properties of oxide 230a and oxide 230b.

[0535] Note that the oxide films 230A1 and 230B1 are preferably deposited by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus may be used. This can reduce the incorporation of hydrogen into the oxide films 230A1 and 230B1 between deposition steps.

[0536] When the ALD method is used as a deposition method for the oxide film 230A1 and the oxide film 230B1, by adopting one or both of the conditions of high substrate temperature during deposition and the implementation of impurity removal treatment, the amount of carbon and chlorine in the film can be reduced compared to the case where the ALD method is used without adopting these conditions.

[0537] For example, when depositing the oxide film 230A1 and the oxide film 230B1, it is preferable to intermittently perform an impurity removal treatment in an oxygen-containing atmosphere. Furthermore, after depositing the oxide film 230A1 and the oxide film 230B1, it is preferable to perform an impurity removal treatment in an oxygen-containing atmosphere. By performing the impurity removal treatment during or after the deposition of the oxide film 230A1 and the oxide film 230B1, impurities in the film can be removed. This can prevent impurities (such as hydrogen, carbon, and nitrogen) contained in raw materials such as precursors from remaining in the oxide film 230A1 and the oxide film 230B1. Consequently, the impurity concentration in the oxide film 230A1 and the oxide film 230B1 can be reduced. Furthermore, the crystallinity of the oxide film 230A1 and the oxide film 230B1 can be improved.

[0538] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0539] When plasma treatment or microwave treatment is performed, the substrate temperature is preferably, for example, room temperature (e.g., 25° C.) or higher and 500° C. or lower, 100° C. or higher and 500° C. or lower, 200° C. or higher and 500° C. or lower, 300° C. or higher and 500° C. or lower, 400° C. or higher and 500° C. or lower, or 400° C. or higher and 450° C. In addition, the temperature of heat treatment is preferably, for example, 100° C. or higher and 500° C. or lower, 200° C. or higher and 500° C. or lower, 300° C. or higher and 500° C. or lower, 400° C. or higher and 500° C. or lower, or 400° C. or higher and 450° C. or lower.

[0540] In particular, setting the temperature during the impurity removal process to a temperature below the maximum temperature during the transistor or semiconductor device manufacturing process is preferred because the impurity content of the metal oxide can be reduced without reducing productivity. For example, by setting the maximum temperature during the manufacture of a semiconductor device according to one embodiment of the present invention to 500°C or below, preferably 450°C or below, the productivity of the transistor or semiconductor device can be improved.

[0541] Here, microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or higher and 300 GHz or lower. Microwave treatment may also be referred to as microwave-excited high-density plasma treatment.

[0542] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range where polycrystallization does not occur in the oxide film 230A1 and the oxide film 230B1. The heat treatment temperature is preferably, for example, 100°C to 650°C, 250°C to 600°C, or 350°C to 550°C.

[0543] Heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen, the ratio of oxygen is preferably set to approximately 20%. Heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in a nitrogen or inert gas atmosphere, and then heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replace the oxygen that has been released.

[0544] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using highly purified gas for the heat treatment, it is possible to minimize absorption of water and the like by the oxide film 230A1 and the oxide film 230B1.

[0545] For example, as a heat treatment, treatment is performed at 450°C for one hour at a flow rate ratio of nitrogen to oxygen of 4:1. This heat treatment involving oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide films 230A1 and 230B1. By reducing impurities in the films, the crystallinity of the oxide film 230B1 is improved, enabling a denser structure with a higher density. Consequently, the crystalline region in the oxide films 230A1 and 230B1 can be increased, and in-plane unevenness in the crystalline region in the oxide films 230A1 and 230B1 can be reduced. Consequently, in-plane unevenness in the electrical characteristics of the transistor can be reduced.

[0546] Next, a conductive film 242F1 is deposited on the oxide film 230B1 ( Figure 31A and Figure 31B Conductors corresponding to the above-described conductors 242a and 242b can be used as the conductive film 242F1. After the oxide film 230B1 is deposited, the conductive film 242F1 is deposited on and in contact with the oxide film 230B1 without undergoing an etching step or the like. This allows the top surface of the oxide film 230B1 to be protected by the conductive film 242F1. This reduces the diffusion of impurities into the oxide 230 constituting the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0547] The conductive film 242F1 can be deposited by sputtering, CVD, MBE, PLD, electroplating, or ALD. For example, tantalum nitride is deposited as the conductive film 242F1 by sputtering. In addition, a heat treatment may be performed before depositing the conductive film 242F1. The heat treatment may also be performed under reduced pressure, wherein the conductive film 242F1 is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide film 230B1 can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A1 and the oxide film 230B1 can be reduced. The temperature of the heat treatment is preferably not less than 100° C. and not more than 400° C. For example, the temperature of the heat treatment is set to 250° C.

[0548] The conductive film 242F1 may also be a laminated film. Figure 5B As shown in FIG. 1 , when a stacked-layer structure of the conductors 242a1 and 242b1 and the conductors 242a2 and 242b2 is employed, tantalum nitride may be deposited as the conductive film 242F1 by sputtering, and tungsten may be deposited thereon by sputtering.

[0549] Next, the oxide film 230A1, the oxide film 230B1, and the conductive film 242F1 are processed into island shapes by photolithography, thereby forming the oxide 230a1, the oxide 230b1, and the conductor 242_1 ( Figure 32A and Figure 32B ).

[0550] It is preferred that oxide 230a1, oxide 230b1, and conductor 242_1 are all processed into island shapes at once. In this case, the side edges of conductor 242_1 are preferably substantially aligned with the side edges of oxide 230a1 and oxide 230b1 when viewed from above. By adopting this structure, the number of steps in the semiconductor device of one embodiment of the present invention can be reduced. This provides a method for manufacturing a semiconductor device with high productivity.

[0551] At least a portion of the oxide 230a1, the oxide 230b1, and the conductor 242_1 is formed to overlap with the conductor 205. The insulator 222_1 is exposed in a region that does not overlap with the oxide 230a1, the oxide 230b1, and the conductor 242_1.

[0552] also, Figure 32A and Figure 32BThe side surfaces of oxide 230a1, oxide 230b1, and conductor 242_1 are shown as tapered, but the present invention is not limited thereto. Alternatively, the side surfaces of oxide 230a1, oxide 230b1, and conductor 242_1 may be substantially perpendicular to the top surface of insulator 222_1. This structure allows for a reduction in the area of transistors and a higher density when multiple transistors are arranged within the substrate.

[0553] Furthermore, when the side surfaces of the oxide 230a1, the oxide 230b1, and the conductor 242_1 have a tapered shape, the tapered angle is preferably, for example, not less than 60° and less than 90°. Thus, by tapering the side surfaces of the oxide 230a1, the oxide 230b1, and the conductor 242_1, the coverage of the side surfaces by the insulator 275 and the like can be improved in subsequent steps, thereby reducing defects such as voids formed in the insulator 275.

[0554] Next, an insulator 275_1 is deposited to cover the oxide 230a1, the oxide 230b1, and the conductor 242_1. Figure 33A and Figure 33B ). The insulator 275_1 is preferably in contact with the top surface of the insulator 222_1.

[0555] Insulator 275_1 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. Insulator 275_1 preferably uses an insulator that has the aforementioned function of inhibiting oxygen permeation. For example, silicon nitride is preferably deposited by PEALD as insulator 275_1. Alternatively, aluminum oxide is preferably deposited by sputtering, and silicon nitride is deposited thereon by PEALD. Providing insulator 275_1 with the above-described structure enhances the function of inhibiting the diffusion of impurities such as water and hydrogen, as well as oxygen.

[0556] By covering the oxide 230a1, the oxide 230b1, and the conductor 242_1 with the insulator 275_1 having the function of suppressing oxygen diffusion, oxygen directly diffused from the insulator 280 and the like into the oxide 230a1, the oxide 230b1, and the conductor 242_1 in subsequent steps can be reduced.

[0557] Next, an insulator 280_1 is deposited on the insulator 275_1. The insulator 280_1 can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. As the insulator 280_1, the above-mentioned insulators can be used.

[0558] After the insulator 280_1 is deposited, the top surface of the insulator 280_1 is preferably planarized by CMP. Figure 34A and Figure 34B) Alternatively, silicon nitride may be deposited on the insulator 280_1 by, for example, sputtering, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280_1.

[0559] In addition, silicon oxide is preferably deposited as the insulator 280_1 using a sputtering method. By depositing the insulating film that will become the insulator 280_1 using a sputtering method in an oxygen-containing atmosphere, the insulator 280_1 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280_1 can be reduced. In addition, a heat treatment can also be performed before depositing the insulator 280_1. This heat treatment can also be performed under reduced pressure, in which the insulator 280_1 is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the insulator 275_1 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a1 and the oxide 230b1 can be reduced. Note that the temperature of the heat treatment is preferably not less than 100°C and not more than 400°C. For example, the temperature of the heat treatment is 250°C.

[0560] Next, the conductor 242_1, the insulator 275_1, and the insulator 280_1 are processed by photolithography to form an opening 122 reaching the oxide 230b1 (see FIG. 1 ). Figure 35A and Figure 35B The opening 122 reaching the oxide 230 b 1 is provided in a region where the oxide 230 b 1 and the conductor 205 overlap.

[0561] The above-mentioned processing can be performed using either dry etching or wet etching. Dry etching is suitable for micromachining. Furthermore, the processing of conductor 242_1, insulator 275_1, and insulator 280_1 can be performed under different conditions. In particular, when dry etching conductor 242_1, an ICP etching apparatus is preferably used. In this case, it is preferable to apply a bias power to increase the etching rate of conductor 242_1 during etching.

[0562] By performing this processing, the conductor 242_1 is divided into island-shaped conductors 242a1 and 242b1.

[0563] The width of the opening 122 (the width in the channel length direction of the transistor 200_1) is reflected in the channel length of the transistor 200_1, so it is preferably small. For example, the width of the opening 122 is preferably greater than 1 nm and less than 60 nm, greater than 5 nm and greater than 50 nm, greater than 5 nm and less than 40 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. When the channel length of the transistor is small and the ratio of the channel width to the channel length increases, the resistance of the channel formation region (also called the channel resistance) decreases, which contributes to the increase of the on-state current. On the other hand, if the above-mentioned channel resistance decreases so that the contact resistance between the semiconductor layer of the transistor and the source electrode or the contact resistance between the semiconductor layer of the transistor and the drain electrode becomes greater than the channel resistance, the contact resistance becomes a bottleneck, and even if the channel length is further miniaturized, the on-state current cannot be increased. In one embodiment of the present invention, by setting the width of the opening 122 within the above range, the channel resistance can be kept greater than the contact resistance, thereby realizing a micro transistor 200_1 with a large on-state current. Thus, in order to process the opening into a micro form, photolithography using short-wavelength light such as EUV light or an electron beam is preferably used.

[0564] The etching process described above may cause impurities to adhere to the side surfaces of oxide 230a1, the top and side surfaces of oxide 230b1, the side surfaces of conductors 242a1 and 242b1, the side surfaces of insulator 275_1, and the side surfaces of insulator 280_1, or to diffuse into these surfaces. A process for removing these impurities may be performed. Furthermore, the dry etching process may also result in damaged areas on the surface of oxide 230b1. Such damaged areas may also be removed. Examples of such impurities include components contained in insulator 280_1, insulator 275_1, and conductors 242a1 and 242b1; components contained in components of the apparatus used to form opening 122; and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0565] In particular, impurities such as aluminum and silicon may reduce the crystallinity of oxide 230b1. Therefore, impurities such as aluminum and silicon are preferably removed from and near the surface of oxide 230b1. Furthermore, the concentration of these impurities is preferably reduced. For example, the concentration of aluminum atoms on and near the surface of oxide 230b1 is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, even more preferably 1.5 atomic % or less, further preferably 1.0 atomic % or less, and particularly preferably less than 0.3 atomic %.

[0566] Impurities such as aluminum and silicon reduce the density of the crystal structure in the low crystallinity region of the oxide 230b1, thus generating a large amount of V O Therefore, it is preferable to reduce or remove the low-crystallinity region in the oxide 230b1.

[0567] In addition, the oxide 230b1 preferably has a layered CAAC structure. In particular, the lower end of the drain of the oxide 230b1 preferably also has a CAAC structure. Here, in the transistor 200_1, the conductor 242a1 or the conductor 242b1 is preferably used as a drain electrode. In other words, the oxide 230b1 near the lower end of the conductor 242a1 or the conductor 242b1 preferably has a CAAC structure. In this way, by removing the low-crystallinity region of the oxide 230b1 at the drain end that has a significant impact on the drain withstand voltage and giving it a CAAC structure, the fluctuation of the electrical characteristics of the transistor 200_1 can be further suppressed. In addition, the reliability of the transistor 200_1 can be further improved.

[0568] In order to remove impurities and the like that adhered to the surface of oxide 230b1 during the etching process, a cleaning process is performed. Examples of cleaning methods include wet cleaning (also referred to as wet etching) using a cleaning solution, plasma treatment using plasma, and the like. These cleaning methods may also be appropriately combined. Note that this cleaning process may deepen opening 122.

[0569] As wet cleaning, an aqueous solution, pure water, or carbonated water obtained by diluting one or more of ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water can be used. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water, or carbonated water. In addition, the above cleaning can also be appropriately combined.

[0570] Note that in this specification and other documents, an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia solution. Furthermore, the concentration, temperature, and other factors of the aqueous solution are appropriately adjusted depending on the impurities to be removed and the structure of the semiconductor device being cleaned. The ammonia concentration of the dilute ammonia solution is preferably set to 0.01% to 5%, more preferably 0.1% to 0.5%. Furthermore, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01 ppm to 100 ppm, more preferably 0.1 ppm to 10 ppm.

[0571] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide 230 b 1 and the like can be reduced.

[0572] Furthermore, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, a treatment using dilute hydrofluoric acid or dilute ammonia water may be performed as the first washing treatment, and a treatment using pure water or carbonated water may be performed as the second washing treatment.

[0573] The cleaning process may be wet cleaning using, for example, dilute ammonia. This cleaning process can remove impurities adhering to the surface of, or diffusing into, the oxides 230a1 and 230b1. Furthermore, it can remove portions of the oxide 230b1 with low crystallinity, thereby improving the overall crystallinity of the oxide 230b1.

[0574] In addition, heat treatment may be performed after the above-mentioned etching or the above-mentioned washing. The temperature of the heat treatment is preferably, for example, 100°C or higher and 650°C or lower, 250°C or higher and 600°C or lower, 350°C or higher and 550°C or lower, or 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas, an inert gas, or an oxidizing gas containing 10 ppm or higher, 1% or higher, or 10% or higher. For example, the treatment is preferably performed at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide 230a1 and the oxide 230b1, thereby reducing oxygen vacancies. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide 230b1 can be improved. Furthermore, the hydrogen remaining in the oxide 230a1 and the oxide 230b1 reacts with the supplied oxygen and the hydrogen can be removed (dehydrated) in the form of H2O. Thus, the hydrogen remaining in the oxide 230a1 and the oxide 230b1 can be prevented from recombining with oxygen vacancies to form V O H. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under an oxygen atmosphere and then continuously under a nitrogen atmosphere without being exposed to the atmosphere.

[0575] When heat treatment is performed while the conductors 242a1 and 242b1 are in contact with the oxide 230b1, the sheet resistance of the oxide 230b1 in the region overlapping with the conductors 242a1 and 242b1 may decrease. Furthermore, the carrier concentration may increase. Therefore, the resistance of the oxide 230b1 in the region overlapping with the conductors 242a1 and 242b1 may be reduced in a self-aligned manner.

[0576] In addition, the above-mentioned heating treatment may not be performed. Figure 5BAs shown in FIG. 1 , when the conductors 242a and 242b have a stacked structure and a tungsten film that is easily oxidized is used as the conductors 242a2 and 242b2, the heat treatment may not be performed. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment.

[0577] Next, an insulating film that will become the insulator 250_1 is deposited on the oxide 230b1 and the insulator 280_1. The insulating film is deposited in a manner that contacts the sidewalls and bottom surface of the opening 122. The insulating film can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulating film is preferably deposited by the ALD method. The insulating film is preferably formed thin, and the thickness non-uniformity needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.). Since the thickness of the film can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, the insulating film needs to be deposited on the bottom and side surfaces of the opening 122 with high coverage. By using the ALD method, since each atomic layer can be deposited on the bottom and side surfaces of the opening 122, the insulating film can be formed with high coverage in the opening 122.

[0578] When depositing the insulating film using ALD, ozone (O3), oxygen (O2), water (H2O), etc. can be used as an oxidant. By using ozone (O3), oxygen (O2), etc. that does not contain hydrogen as an oxidant, hydrogen diffusion into the oxide 230b1 can be reduced.

[0579] like Figure 5A and Figure 8A as well as Figure 5B and Figure 8B As shown, the insulating film to be the insulator 250_1 may have a stacked structure. Figure 5A and Figure 8A In the structure shown, aluminum oxide can be deposited as the insulating film to be the insulator 250a by thermal ALD, silicon oxide can be deposited as the insulating film to be the insulator 250b by PEALD, and silicon nitride can be deposited as the insulating film to be the insulator 250c by PEALD. Figure 5B and Figure 8B In the structure shown, hafnium oxide is deposited thereon by a thermal ALD method as an insulating film to be the insulator 250d.

[0580] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Note that when the insulator 250_1 has a stacked structure, the microwave treatment is not necessarily performed after the insulating film that will become the insulator 250_1 is deposited. For example, when using Figure 5A and Figure 8AIn the case of the structure shown in FIG. 1 , microwave treatment may be performed after depositing the insulating film to be the insulator 250a and the insulating film to be the insulator 250b, and then the insulating film to be the insulator 250c may be deposited. Figure 5B and Figure 8B In the case of the structure shown, microwave treatment may be performed after depositing the insulating film to become the insulator 250a and the insulating film to become the insulator 250b. Subsequently, microwave treatment may be performed after depositing the insulating film to become the insulator 250d. Finally, the insulating film to become the insulator 250c may be deposited. In this manner, microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0581] For example, microwave treatment preferably uses a microwave processing device that includes a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. In addition, the power of the power supply for applying microwaves in the microwave processing device is preferably 1000 W or more and 10,000 W or less, preferably 2000 W or more and 5000 W or less. In addition, the microwave processing device may also include a power supply for applying RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230b1.

[0582] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. In addition, the treatment temperature is preferably 750° C. or less, more preferably 500° C. or less, for example, about 250° C. In addition, it is also possible to continuously perform heat treatment without exposing to the outside air after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100° C. or more and 750° C. or less, more preferably 300° C. or more and 500° C. or less.

[0583] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably greater than 10% and less than 40%, and even more preferably greater than 10% and less than 30%. Thus, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide 230b1 can be reduced. Furthermore, by preventing excessive oxygen from being introduced into the treatment chamber during microwave treatment, an excessive reduction in the carrier concentration in the oxide 230b1 can be prevented.

[0584] By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to convert oxygen gas into plasma, and the oxygen plasma can be applied to the region between the conductors 242a1 and 242b1 of the oxide 230b1. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 5A and Figure 8A or Figure 5B and Figure 8B In the structure shown, it is preferable to use an insulating film having the function of capturing and fixing hydrogen (e.g., aluminum oxide) as the insulating film to be the insulator 250a. By adopting the above structure, the insulator 250a can capture or fix hydrogen generated by the microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O Furthermore, by supplying oxygen radicals generated in the oxygen plasma to oxygen vacancies formed in the channel formation region, oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0585] Oxygen injected into the channel formation region may be in the form of oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also known as O radicals, which are atoms, molecules, or ions containing unpaired electrons). The oxygen injected into the channel formation region may be in one or more of the above forms, with oxygen radicals being particularly preferred. Furthermore, since the film quality of the insulator 250_1 can be improved, the reliability of the transistor 200_1 is improved.

[0586] On the other hand, oxide 230b1 includes a region that overlaps with either conductor 242a1 or 242b1. This region can be used as a source region or a drain region. Conductors 242a1 or 242b1 are preferably used as shielding films to protect against microwaves, high frequencies such as RF, or oxygen plasma during microwave processing in an oxygen-containing atmosphere. Therefore, conductors 242a1 or 242b1 preferably have the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0587] The conductors 242a1 and 242b1 block the effects of microwaves, high frequencies such as RF, and oxygen plasma, so that the effect does not act on the region of the oxide 230b1 that overlaps with either of the conductors 242a1 and 242b1. As a result, V is not generated in the source and drain regions by microwave treatment. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0588] Furthermore, an insulating film serving as the insulator 250_1 having oxygen barrier properties is provided in contact with the side surfaces of the conductors 242a1 and 242b1. This prevents the formation of an oxide film on the side surfaces of the conductors 242a1 and 242b1 due to microwave treatment.

[0589] Since the film quality of the insulating film to be the insulator 250_1 can be improved, the reliability of the transistor 200_1 is improved.

[0590] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. O H, thereby making the channel formation region i-type or substantially i-type. Furthermore, excessive oxygen supply to the region serving as the source region or drain region can be prevented, thereby maintaining the conductivity (low resistance region state) before the microwave treatment. This can suppress variations in the electrical characteristics of the transistor 200_1 and reduce variations in the electrical characteristics of the transistor 200_1 within the substrate surface.

[0591] Furthermore, during microwave treatment, electromagnetic interactions between microwaves and molecules in oxide 230b1 may directly transfer thermal energy to oxide 230b1. This thermal energy may heat oxide 230b1. This heating process is sometimes referred to as microwave annealing. Microwave treatment in an oxygen-containing atmosphere can sometimes achieve an effect equivalent to oxygen annealing. Furthermore, it is believed that when oxide 230b1 contains hydrogen, this thermal energy is transferred to the hydrogen in oxide 230b1, and the activated hydrogen is released from oxide 230b1.

[0592] Alternatively, microwave treatment may be performed before depositing the insulating film to be the insulator 250_1 instead of performing microwave treatment after depositing the insulating film.

[0593] In addition, after the microwave treatment after the deposition of the insulating film that will become the insulator 250_1, the heat treatment can be performed while maintaining a reduced pressure state. By performing this treatment, hydrogen in the insulating film, the oxide 230b1, and the oxide 230a1 can be efficiently removed. In addition, a portion of the hydrogen is sometimes doped by the conductors 242a1 and 242b1. In addition, the step of maintaining a reduced pressure state and performing the heat treatment after the microwave treatment can be repeated. By repeatedly performing the heat treatment, hydrogen in the insulating film, the oxide 230b1, and the oxide 230a1 can be further efficiently removed. Note that the heat treatment temperature is preferably above 300°C and below 500°C. The above-mentioned microwave treatment, that is, microwave annealing, can also serve as the heat treatment. When the oxide 230b1 and the like are sufficiently heated by microwave annealing, the heat treatment can also be omitted.

[0594] Furthermore, by performing microwave treatment to change the film quality of the insulating film that will become the insulator 250_1, diffusion of hydrogen, water, impurities, etc. can be suppressed. This can prevent hydrogen, water, impurities, etc. from diffusing through the insulator 250_1 into the oxide 230b1, the oxide 230a1, etc., during post-processes such as deposition of the conductive film that will become the conductor 260_1 or post-processes such as heat treatment.

[0595] Next, a conductive film to become the conductor 260a1 and a conductive film to become the conductor 260b1 are sequentially deposited. The conductive film to become the conductor 260a1 and the conductive film to become the conductor 260b1 can be deposited by sputtering, CVD, MBE, PLD, electroplating, ALD, or the like. For example, titanium nitride can be deposited as the conductive film to become the conductor 260a1 by ALD, and tungsten can be deposited as the conductive film to become the conductor 260b1 by CVD.

[0596] Next, the insulating film to be the insulator 250_1, the conductive film to be the conductor 260a1, and the conductive film to be the conductor 260b1 are polished by CMP until the insulator 280_1 is exposed. In other words, the insulating film to be the insulator 250_1, the conductive film to be the conductor 260a1, and the conductive film to be the conductor 260b1 are removed so as to be exposed from the opening 122. As a result, the insulator 250_1 and the conductor 260_1 (the conductor 260a1 and the conductor 260b1) ( Figure 36A and Figure 36B ).

[0597] Thus, the insulator 250_1 is provided so as to be in contact with the side and bottom of the opening 122. Furthermore, the conductor 260_1 is arranged so as to be embedded in the opening 122 via the insulator 250_1. Thus, the transistor 200_1 is formed.

[0598] Next, an insulator 286 ( Figure 37A and Figure 37B The insulator 286 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 286 is preferably deposited by sputtering. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 286 can be reduced.

[0599] As described above, insulator 286 preferably contains a large amount of oxygen. Thus, oxygen contained in insulator 286 can be supplied to insulator 280_1 during deposition of insulator 286 or through a post-deposition heat treatment. Furthermore, by supplying oxygen supplied to insulator 280_1 to oxide 230_1, oxygen vacancies in oxide 230_1 can be reduced. Consequently, transistor 200_1 having excellent electrical characteristics and reliability can be realized.

[0600] For example, aluminum oxide is deposited as the insulator 286 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality. In addition, the RF power applied to the substrate is set to 1.86 W / cm 2 Below. Preferably 0W / cm 2 Above 0.62W / cm 2 Note that the RF power is 0W / cm 2 It means that RF power is not applied to the substrate. The amount of oxygen injected into the lower layer of the insulator 286 can be controlled according to the size of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the lower layer of the insulator 286, and the oxygen amount is easily saturated even if the insulator 286 is thin. In addition, the greater the RF power, the more oxygen is injected into the lower layer of the insulator 286. By reducing the RF power, the amount of oxygen injected into the insulator 280_1 can be suppressed. Alternatively, an insulator 286 having a two-layer stacked structure can be deposited. At this time, for example, the RF power applied to the substrate is set to 0W / cm 2 To deposit the lower layer of insulator 286, the RF power applied to the substrate was set to 0.62 W / cm 2 to deposit an upper layer of insulator 286 .

[0601] Furthermore, the RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0602] Alternatively, by depositing the insulator 286 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280_1 during deposition. This allows the insulator 280_1 to contain excess oxygen. In this case, the insulator 286 is preferably deposited while the substrate is heated.

[0603] Furthermore, a heat treatment may be performed before depositing insulator 286. This heat treatment may be performed under reduced pressure, with insulator 286 continuously deposited without being exposed to the atmosphere. This treatment removes moisture and hydrogen adhering to the surface of insulator 280_1 and reduces the moisture and hydrogen concentrations in insulator 280_1. The heat treatment temperature is preferably 100°C to 400°C. For example, the heat treatment temperature is 250°C.

[0604] Next, the insulator 286 is removed. Dry etching, wet etching, or CMP can be used to remove the insulator 286. This removal exposes the top surface of the insulator 250_1, the top surface of the conductor 260_1, and the top surface of the insulator 280_1.

[0605] Note that the insulator 286 may be used as the insulator 222_2 without being removed. Alternatively, the insulator 286 may be thinned by removing a portion thereof and used as the insulator 222_2 or a portion of the insulator 222_2.

[0606] Alternatively, oxygen may be supplied to the insulator 280_1 by oxygen plasma treatment, etc. In this case, the insulator 286 may not be formed.

[0607] Next, the insulator 222_2 is formed to contact the top surfaces of the insulator 250_1, the conductor 260_1, and the insulator 280_1. The materials and formation methods for the insulator 222_2 can be referred to the description of the insulator 222_1.

[0608] Next, an oxide film 230A2 is deposited on the insulator 222_2, and an oxide film 230B2 is deposited on the oxide film 230A2. The materials and formation methods of the oxide film 230A2 can be referred to as those described above for the oxide film 230A1. The materials and formation methods of the oxide film 230B2 can be referred to as those described above for the oxide film 230B1.

[0609] Next, a conductive film 242F2 is deposited on the oxide film 230B2 ( Figure 38A and Figure 38B ) The materials and formation methods that can be used for the conductive film 242F2 can refer to the description of the conductive film 242F1.

[0610] Next, the oxide film 230A2, the oxide film 230B2, and the conductive film 242F2 are processed into island shapes by photolithography, thereby forming the oxide 230a2, the oxide 230b2, and the conductor 242_2 ( Figure 39A and Figure 39B). In addition, oxide 230a2, oxide 230b2, and at least a portion of conductor 242_2 are formed so as to overlap with conductor 260_1. The processing methods of oxide 230a2, oxide 230b2, and conductor 242_2 can refer to the description of the processing methods of oxide 230a1, oxide 230b1, and conductor 242_1. By performing this processing, opening 131a is formed in the region overlapping with conductor 242a1, and opening 131b is formed in the region overlapping with conductor 242b1. In the region that does not overlap with oxide 230a2, oxide 230b2, and conductor 242_2 (such as the region overlapping with opening 131a or opening 131b), insulator 222_2 is exposed.

[0611] Next, an insulator 275_2 is deposited to cover the oxide 230a2, the oxide 230b2, and the conductor 242_2. Figure 40A and Figure 40B Insulator 275_2 is provided so as to contact the sidewalls and bottom surfaces of openings 131a and 131b. Insulator 275_2 has regions that contact the side surfaces of oxide 230a2, the side surfaces of oxide 230b2, the side surfaces and top surface of conductor 242_2, and the top surface of insulator 222_2. Note that the materials and deposition conditions that can be used for insulator 275_2 can refer to the description of insulator 275_1 above.

[0612] Next, an insulator 280_2 is deposited on the insulator 275_2. The materials and deposition conditions that can be used for the insulator 280_2 can refer to the description of the insulator 280_1.

[0613] It is preferred to perform CMP treatment on the top surface of the insulator 280_2 after deposition to flatten the top surface ( Figure 41A and Figure 41B For example, silicon nitride may be deposited on the insulator 280_2 by sputtering, and the silicon nitride may be subjected to CMP until it reaches the insulator 280_2.

[0614] Next, the conductor 242_2, the insulator 275_2, and the insulator 280_2 are processed by photolithography to form an opening 123 ( Figure 42A and Figure 42B The opening 123 is provided in the region where the oxide 230b2 and the conductor 260_1 overlap. The method for forming the opening 123 can refer to the description of the method for forming the opening 122.

[0615] By performing this processing, the conductor 242_2 is divided into island-shaped conductors 242a2 and 242b2.

[0616] The width of the opening 123 (the width in the channel length direction of the transistor 200_2) is reflected in the channel length of the transistor 200_2 and is therefore preferably small. For example, the width of the opening 123 is preferably 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 5 nm to 10 nm. In order to miniaturize the opening, photolithography using short-wavelength light such as EUV light or an electron beam is preferably used.

[0617] Next, an insulating film, which will become insulator 250_2, is deposited over oxide 230b2 and insulator 280_2. This insulating film is deposited so as to contact the sidewalls and bottom surface of opening 123. The materials and formation methods for the insulating film that will become insulator 250_2 can be found in the description of the materials and formation methods for the insulating film that will become insulator 250_1.

[0618] Next, a conductive film to become the conductor 260a2 and a conductive film to become the conductor 260b2 are sequentially deposited. The materials and formation methods of the conductive films to become the conductor 260a2 and the conductive films to become the conductor 260b2 can be referred to the materials and formation methods of the conductive films to become the conductor 260a1 and the conductive films to become the conductor 260b1, respectively.

[0619] Next, the insulating film to become the insulator 250_2, the conductive film to become the conductor 260a2, and the conductive film to become the conductor 260b2 are polished by CMP until the insulator 280_2 is exposed. In other words, the insulating film to become the insulator 250_2, the conductive film to become the conductor 260a2, and the conductive film to become the conductor 260b2 are removed so as to be exposed from the opening 123. As a result, the insulator 250_2 and the conductor 260_2 (the conductor 260a2 and the conductor 260b2) ( Figure 43A and Figure 43B ).

[0620] Thus, the insulator 250_2 is provided so as to be in contact with the side and bottom of the opening 123. Furthermore, the conductor 260_2 is arranged so as to be embedded in the opening 123 via the insulator 250_2. Thus, the transistor 200_2 is formed.

[0621] Next, an insulator 286 ( Figure 44A and Figure 44B) The materials and formation methods that can be used for the insulator 286 can refer to the above description.

[0622] Next, the insulator 286 is removed. Dry etching, wet etching, or CMP can be used to remove the insulator 286. This removal exposes the top surface of the insulator 250_2, the top surface of the conductor 260_2, and the top surface of the insulator 280_2.

[0623] Note that the insulator 286 may be used as the insulator 222_3 without being removed. Alternatively, the insulator 286 may be thinned by removing a portion thereof and used as the insulator 222_3 or a portion of the insulator 222_3.

[0624] Alternatively, oxygen may be supplied to the insulator 280_2 by oxygen plasma treatment, etc. In this case, the insulator 286 may not be formed.

[0625] Next, the insulator 222_3 is formed so as to be in contact with the top surface of the insulator 250_2, the top surface of the conductor 260_2, and the top surface of the insulator 280_2. Figure 45A and Figure 45B The materials and formation methods that can be used for the insulator 222_3 can refer to the description of the insulator 222_1.

[0626] Next, the insulator 222_3, the insulator 280_2, the insulator 275_2, the insulator 222_2, the insulator 280_1, and the insulator 275_1 are processed by photolithography to form an opening 132a that reaches the conductor 242a1 in a region overlapping with the opening 131a, and an opening 132b that reaches the conductor 242b1 in a region overlapping with the opening 131b. Figure 46A and Figure 46B This process can be performed using a dry etching method or a wet etching method. By performing this process, the region of the insulator 275_2 that contacts the side walls of the opening 131a and the opening 131b is removed.

[0627] As described above, opening 132a is formed in a region overlapping with opening 131a. Furthermore, opening 132b is formed in a region overlapping with opening 131b. Therefore, it can be said that opening 131a is included in opening 132a. Furthermore, it can be said that opening 131b is included in opening 132b. Thus, by pre-forming openings 131a and 131b in the regions where openings 132a and 132b are to be formed, it is possible to easily process openings 132a and 132b that reach conductors 242a1 and 242b1, respectively.

[0628] To form opening 132a so that it overlaps with opening 131a, the maximum diameter of opening 132a when viewed from a plan view is preferably larger than the maximum diameter of opening 131a when viewed from a plan view. To form opening 132b so that it overlaps with opening 131b, the maximum diameter of opening 132b when viewed from a plan view is preferably larger than the maximum diameter of opening 131b when viewed from a plan view. At this time, portions of insulator 275_2 on conductor 242a2 and insulator 275_2 on conductor 242b2 are removed.

[0629] Note that the opening 132 a corresponds to the above-mentioned first opening, and the opening 132 b corresponds to the above-mentioned second opening.

[0630] Next, a conductive film, which will become the conductors 243a1 and 243b1, is deposited over the conductors 242a1 and 242b1 and the insulator 222_3. This conductive film is deposited so as to contact the sidewalls and bottom surfaces of the openings 132a and 132b. For materials and formation methods for the conductive films that will become the conductors 243a1 and 243b1, refer to the description of materials and formation methods for the conductive film that will become the conductor 260a1, for example.

[0631] Next, conductive films to become the conductors 243a2 and 243b2 are deposited on the conductive films to become the conductors 243a1 and 243b1. For materials and formation methods that can be used for the conductive films to become the conductors 243a2 and 243b2, refer to the description of the materials and formation methods that can be used for the conductive film to become the conductor 260b1, for example.

[0632] Next, the conductive films to become the conductors 243a1 and 243b1, and the conductive films to become the conductors 243a2 and 243b2, are polished by CMP treatment until the insulator 222_3 is exposed. In other words, the portions of the conductive films to become the conductors 243a1 and 243b1, and the conductive films to become the conductors 243a2 and 243b2, exposed from the openings 132a and 132b, are removed. Thus, the conductors 243a (conductors 243a1 and 243a2) are formed in the openings 132a. Furthermore, the conductors 243b (conductors 243b1 and 243b2) are formed in the openings 132b. Figure 47A and Figure 47B ).

[0633] Thus, the conductor 242a1 and the conductor 242a2 are electrically connected via the conductor 243a. In addition, the conductor 242b1 and the conductor 242b2 are electrically connected via the conductor 243b.

[0634] Next, an oxide film 230A3 is deposited on the conductors 243a and 243b, and the insulator 222_3. An oxide film 230B3 is deposited on the oxide film 230A3. The materials and formation methods for the oxide film 230A3 can be found in the description of the oxide film 230A1. The materials and formation methods for the oxide film 230B3 can be found in the description of the oxide film 230B1.

[0635] Next, a conductive film 242F3 is deposited on the oxide film 230B3 ( Figure 48A and Figure 48B ) Materials and formation methods that can be used for the conductive film 242F3 can refer to the description of the conductive film 242F1.

[0636] Next, the oxide film 230A3, the oxide film 230B3, and the conductive film 242F3 are processed into island shapes by photolithography, thereby forming the oxide 230a3, the oxide 230b3, and the conductor 242_3 ( Figure 49A and Figure 49B ). Furthermore, at least a portion of oxide 230a3, oxide 230b3, and conductor 242_3 are formed so as to overlap with conductor 260_2. The processing methods for oxide 230a3, oxide 230b3, and conductor 242_3 can refer to the processing methods for oxide 230a1, oxide 230b1, and conductor 242_1 described above. This processing forms opening 133a in the region overlapping conductor 243a, and opening 133b in the region overlapping conductor 243b. In the region not overlapping oxide 230a3, oxide 230b3, and conductor 242_3, conductor 243a, conductor 243b, and insulator 222_3 are exposed.

[0637] Next, an insulator 275_3 is formed to cover the oxide 230a3, the oxide 230b3, and the conductor 242_3. Figure 50A and Figure 50B Insulator 275_3 is provided so as to contact the side walls and bottom surfaces of openings 133a and 133b. Insulator 275_3 has regions that contact the side surfaces of oxide 230a3, the side surfaces of oxide 230b3, the side surfaces and top surface of conductor 242_3, the top surface of conductor 243a, the top surface of conductor 243b, and the top surface of insulator 222_3. Note that the materials and deposition conditions that can be used for insulator 275_3 can refer to the description of insulator 275_1 above.

[0638] Next, an insulator 280_3 is deposited on the insulator 275_3. The materials and deposition conditions that can be used for the insulator 280_3 can refer to the description of the insulator 280_1.

[0639] It is preferred to perform CMP treatment on the top surface of the insulator 280_3 after deposition to flatten the top surface ( Figure 51A and Figure 51B For example, silicon nitride may be deposited on the insulator 280_3 by sputtering, and the silicon nitride may be subjected to CMP until it reaches the insulator 280_3.

[0640] Next, the conductor 242_3, the insulator 275_3, and the insulator 280_3 are processed by photolithography to form an opening 124 ( Figure 52A and Figure 52B The opening 124 is provided in the region where the oxide 230b3 and the conductor 260_2 overlap. The method for forming the opening 124 can refer to the description of the method for forming the opening 122.

[0641] By performing this processing, the conductor 242_3 is divided into island-shaped conductors 242a3 and 242b3.

[0642] The width of the opening 124 (the width in the channel length direction of the transistor 200_3) is reflected in the channel length of the transistor 200_3 and is therefore preferably small. For example, the width of the opening 124 is preferably 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 5 nm to 10 nm. In order to miniaturize the opening, photolithography using short-wavelength light such as EUV light or an electron beam is preferably used.

[0643] The widths of the openings 124, 123, and 122 are preferably uniform. This structure allows the channel lengths of the transistors 200_1 to 200_3 to be uniform, thereby reducing variations in electrical characteristics of the semiconductor device 200.

[0644] Next, an insulating film, which will become insulator 250_3, is formed over oxide 230b3 and insulator 280_3. This insulating film is formed so as to contact the sidewalls and bottom surface of opening 124. The materials and formation methods for the insulating film that will become insulator 250_3 can be found in the description of the materials and formation methods for the insulating film that will become insulator 250_1.

[0645] Next, a conductive film to become the conductor 260a3 and a conductive film to become the conductor 260b3 are sequentially deposited. The materials and formation methods of the conductive films to become the conductor 260a3 and the conductive films to become the conductor 260b3 can be referred to the materials and formation methods of the conductive films to become the conductor 260a1 and the conductive films to become the conductor 260b1, respectively.

[0646] Next, the insulating film to become the insulator 250_3, the conductive film to become the conductor 260a3, and the conductive film to become the conductor 260b3 are polished by CMP processing until the insulator 280_3 is exposed. In other words, the portions of the insulating film to become the insulator 250_3, the conductive film to become the conductor 260a3, and the conductive film to become the conductor 260b3 exposed from the opening 124 are removed. As a result, the insulator 250_3 and the conductor 260_3 (conductor 260a3 and conductor 260b3) ( Figure 53A and Figure 53B ).

[0647] Thus, the insulator 250_3 is provided so as to be in contact with the sidewalls and bottom surface of the opening 124. Furthermore, the conductor 260_3 is arranged so as to be embedded in the opening 124 via the insulator 250_3. Thus, the transistor 200_3 is formed.

[0648] Next, an insulator 286 is formed on the insulator 250_3, the conductor 260_3, and the insulator 280_3. The material and formation method of the insulator 286 can be referred to the above description.

[0649] Next, insulator 283 is formed on insulator 286. Insulator 283 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. Insulator 283 is preferably deposited by sputtering. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in insulator 283 can be reduced. Insulator 283 can use the aforementioned materials. For example, silicon nitride can be deposited by sputtering as insulator 283.

[0650] Next, an insulator 287 ( Figure 54A and Figure 54B ). Insulator 287 can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. A material with a low relative dielectric constant is preferably used as insulator 287. By using a material with a low relative dielectric constant for insulator 287, parasitic capacitance generated between wirings provided across insulator 287 can be reduced.

[0651] Here, it is preferable to continuously deposit insulator 286, insulator 283, and insulator 287 without being exposed to the atmosphere. By depositing insulator 286, insulator 283, and insulator 287 without being exposed to the atmosphere, impurities and moisture from the atmosphere can be prevented from adhering to insulator 286, insulator 283, and insulator 287. Therefore, the vicinity of the interface between insulator 286 and insulator 283, and the vicinity of the interface between insulator 283 and insulator 287 can be kept clean.

[0652] Next, by processing the insulator 287, the insulator 283, the insulator 286, the insulator 280_3, and the insulator 275_3 using a photolithography method, an opening 134a that reaches the conductor 243a is formed in a region overlapping with the opening 133a, and an opening 134b that reaches the conductor 243b is formed in a region overlapping with the opening 133b. Figure 55A ).

[0653] This process can be performed using dry etching or wet etching. By performing this process, the region of the insulator 275_3 that is in contact with the sidewalls of the opening 133a and the opening 133b is removed.

[0654] As described above, opening 134a is formed in a region overlapping with opening 133a. Furthermore, opening 134b is formed in a region overlapping with opening 133b. Therefore, it can be said that opening 133a is included in opening 134a. Furthermore, it can be said that opening 133b is included in opening 134b. Thus, by pre-forming openings 133a and 133b in the regions where openings 134a and 134b are to be formed, it is possible to easily process openings 134a and 134b that reach conductors 243a and 243b, respectively.

[0655] To form opening 134a so that it overlaps with opening 133a, the maximum diameter of opening 134a when viewed from a plan view is preferably larger than the maximum diameter of opening 133a when viewed from a plan view. To form opening 134b so that it overlaps with opening 133b, the maximum diameter of opening 134b when viewed from a plan view is preferably larger than the maximum diameter of opening 133b when viewed from a plan view. At this time, portions of insulator 275_3 on conductor 242a3 and insulator 275_3 on conductor 242b3 are removed.

[0656] Note that the opening 134 a corresponds to the third opening described above, and the opening 134 b corresponds to the fourth opening described above.

[0657] Next, a conductive film, which will become conductors 244a1 and 244b1, is deposited over conductors 243a, 243b, 242a3, 242b3, and insulator 287. This conductive film is deposited so as to contact the sidewalls and bottom surfaces of openings 134a and 134b. Consequently, conductor 244a1 contacts the top surfaces of conductors 243a and 242a3. Conductor 244b1 contacts the top surfaces of conductors 243b and 242b3. For materials and formation methods for the conductive films that will become conductors 244a1 and 244b1, reference can be made to the description of materials and formation methods for the conductive film that will become conductor 260a1.

[0658] Next, conductive films to become the conductors 244a2 and 244b2 are deposited on the conductive films to become the conductors 244a1 and 244b1. For materials and formation methods that can be used for the conductive films to become the conductors 244a2 and 244b2, refer to the description of the materials and formation methods that can be used for the conductive film to become the conductor 260b1, for example.

[0659] Next, the conductive films to become the conductors 244a1 and 244b1, and the conductive films to become the conductors 244a2 and 244b2, are polished by CMP treatment until the insulator 287 is exposed. In other words, the portions of the conductive films to become the conductors 244a1 and 244b1, and the conductive films to become the conductors 244a2 and 244b2, exposed from the openings 134a and 134b, are removed. Thus, the conductor 244a (conductor 244a1 and conductor 244a2) is formed in the opening 134a that reaches the conductor 243a. Furthermore, the conductor 244b (conductor 244b1 and conductor 244b2) is formed in the opening 134b that reaches the conductor 243b. Figure 56A ).

[0660] Thus, conductor 242a3 is electrically connected to conductor 243a via conductor 244a. Furthermore, conductor 242b3 is electrically connected to conductor 243b via conductor 244b. That is, the conductors serving as one of the source and drain electrodes of transistors 200_1 to 200_3 (conductors 242a1 to 242a3) are electrically connected to one another via conductor 243a and conductor 244a. Furthermore, the conductors serving as the other of the source and drain electrodes of transistors 200_1 to 200_3 (conductors 242b1 to 242b3) are electrically connected to one another via conductor 243b and conductor 244b.

[0661] Next, the insulator 287, the insulator 283, the insulator 286, the insulator 280_3, the insulator 275_3, the insulator 222_3, the insulator 280_2, the insulator 275_2, the insulator 222_2, the insulator 280_1, the insulator 275_1, and the insulator 222_1 are processed by photolithography to form an opening 125 ( Figure 55B ) The opening 125 has a region overlapping with the top surface of the conductor 205 , the top surface of the conductor 260_1 , the top surface of the conductor 260_2 , and the top surface of the conductor 260_3 when viewed from above.

[0662] This processing can be performed by dry etching or wet etching. By performing this processing, a portion of the top surface of the conductor 205 , a portion of the top surface of the conductor 260_1 , a portion of the top surface of the conductor 260_2 , and a portion of the top surface of the conductor 260_3 are exposed in the opening 125 .

[0663] Note that the opening 125 corresponds to the fifth opening described above.

[0664] Next, a conductive film, which will become the conductor 254a, is formed over the conductor 205, the conductor 260_1, the conductor 260_2, the conductor 260_3, and the insulator 287. This conductive film is deposited so as to contact the sidewalls and bottom surface of the opening 125. Therefore, this conductive film is in contact with the top surfaces of the conductor 205, the conductor 260_1, the conductor 260_2, and the conductor 260_3. For materials and formation methods that can be used for the conductive film that will become the conductor 254a, for example, refer to the description of materials and formation methods that can be used for the conductive film that will become the conductor 260a1.

[0665] Next, a conductive film to become the conductor 254b is deposited on the conductive film to become the conductor 254a. For example, the material and formation method of the conductive film to become the conductor 254b can be referred to the description of the material and formation method of the conductive film to become the conductor 260b1 described above.

[0666] Next, the conductive film to be the conductor 254a and the conductive film to be the conductor 254b are polished by CMP treatment until the insulator 287 is exposed. In other words, the portion of the conductive film to be the conductor 254a and the conductive film to be the conductor 254b exposed from the opening 125 is removed. Thus, the conductor 254 (the conductor 254a and the conductor 254b) ( Figure 56B ).

[0667] Thus, the conductors 260_1 to 260_3 and the conductor 205 are electrically connected to each other via the conductor 254. That is, the conductors (conductors 260_1 to 260_3) serving as gate electrodes of the transistors 200_1 to 200_3 and the conductor 205 are electrically connected to each other via the conductor 254.

[0668] Note that while the above method describes a method of forming the conductive bodies 244 a and 244 b and the conductive body 254 using separate processes, the present invention is not limited thereto. For example, the openings 134 a, 134 b, and 125 may be formed simultaneously, and the first conductive film and the second conductive film may be sequentially deposited until the top surface of the insulator 287 is exposed, followed by CMP treatment, thereby forming the conductive bodies 244 a, 244 b, and 254 simultaneously.

[0669] Next, conductive films to become the conductors 245a, 245b, and 255 are formed over the conductors 244a, 244b, 254, and the insulator 287. For materials and formation methods that can be used for these conductive films, for example, refer to the description of the materials and formation methods that can be used for the conductive film that can become the conductor 260b1.

[0670] Next, by photolithography, the conductor 245 a is formed to have a region overlapping with the conductor 244 a , the conductor 245 b is formed to have a region overlapping with the conductor 244 b , and the conductor 255 is formed to have a region overlapping with the conductor 254 .

[0671] Thus, it is possible to produce Figures 1A to 2 The semiconductor device 200 is shown.

[0672] <Example 2 of Method for Manufacturing Semiconductor Device>

[0673] Reference Figures 57A to 57C illustrate Figure 13A and Figure 13B An example of a method for manufacturing the semiconductor device 200 is shown.

[0674] Note that the following only describes Figure 13A and Figure 13B FIG. 2 is a diagram showing a portion of a method for manufacturing a semiconductor device 200 .

[0675] Figures 57A to 57C All along Figure 13A The cross section shown is the dot-dash line A3-A4.

[0676] First, the steps described in <Example 1 of the method for manufacturing a semiconductor device> are performed. Figure 35B .

[0677] Then, with Figure 35B The insulating film 250F is deposited in such a manner that the sidewalls and the bottom surface of the opening 122 are in contact with each other. Figure 57A ) The materials and formation methods that can be used for the insulating film 250F can refer to the description of the materials and formation methods that can be used for the insulating film that will become the insulator 250_1.

[0678] Next, by photolithography, an opening 126 ( 126_1 ) that reaches the conductor 205 is formed in the insulating film 250F and the insulator 222_1 in a region of the bottom surface of the opening 122 that does not overlap with the oxide 230_1 . Figure 57B When forming the opening 126, a dry etching method or a wet etching method can be used.

[0679] Next, a conductive film to become the conductor 260a1 is formed so as to contact the top surface of the insulating film 250F, the sidewalls of the opening 126, and the exposed top surface of the conductor 205. A conductive film to become the conductor 260b1 is then formed on the conductive film. The materials and formation methods that can be used for the conductive film to become the conductor 260a1 and the conductive film to become the conductor 260b1 can be found in the above description.

[0680] Next, the insulating film 250F, the conductive film to become the conductor 260a1, and the conductive film to become the conductor 260b1 are polished by CMP until the insulator 280_1 is exposed. In other words, the insulating film 250F, the conductive film to become the conductor 260a1, and the conductive film to become the conductor 260b1 are partially removed and exposed from the opening 122. As a result, the insulator 250_1 and the conductor 260_1 (conductor 260a1 and conductor 260b1) ( Figure 57C ).

[0681] Through the above steps, the conductor 205 and the conductor 260_1 can be electrically connected.

[0682] Next, proceed Figures 37B to 42B The process described in .

[0683] Then, by performing Figures 57A to 57C The described process can form the conductor 260_2 and electrically connect the conductor 260_2 and the conductor 260_1 at the same time.

[0684] By repeating the above steps, Figure 13B The formation of the transistor 200_3 in the semiconductor device 200 is shown.

[0685] <Example 3 of Method for Manufacturing Semiconductor Device>

[0686] Reference Figures 58A to 104BManufacturing Figures 15 to 17 The case of the semiconductor device 200 shown will be described as an example.

[0687] In FIG. 58 to FIG. 104, A of each figure is along Figure 15 The cross-sectional view along the dotted line A1-A2 is also a cross-sectional view along the channel length direction of each transistor included in the semiconductor device 200. Figure 15 The cross-sectional view taken along the dashed line A3 - A4 is also a cross-sectional view of each transistor included in the semiconductor device 200 in the channel width direction.

[0688] First, a substrate (not shown) is prepared, and on this substrate, an insulator 215 is deposited. The materials and formation methods that can be used for the insulator 215 can refer to the above description.

[0689] Next, an insulator 216 is deposited on the insulator 215 ( Figure 58A and Figure 58B The materials and formation methods that can be used for the insulator 216 can refer to the above description.

[0690] Next, two openings 121 ( Figure 59A and Figure 59B The method for forming the opening 121 may refer to the above description.

[0691] A conductive film to be the conductor 205a is deposited after forming the opening 121. The material and formation method of the conductive film to be the conductor 205a can be referred to the above description.

[0692] Next, a conductive film to be the conductor 205b is deposited. The material and formation method of the conductive film to be the conductor 205b can be referred to the above description.

[0693] Next, a CMP treatment is performed to remove a portion of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, thereby exposing the insulator 216 ( Figure 60A and Figure 60B ). As a result, the conductors 205a and 205b remain only in the opening 121. Note that part of the insulator 216 may be removed by this CMP treatment.

[0694] Next, an insulator 222_1 is deposited on the insulator 216 and the conductor 205 (the conductor 205a and the conductor 205b). The materials and formation methods that can be used for the insulator 222_1 can be referred to the above description.

[0695] Next, an insulating film 270F1 ( Figure 61Aand Figure 61B For example, the insulating film 270F1 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. For example, the insulating material that can be used for the insulator 280 described above can be used as the insulating film 270F1.

[0696] For example, silicon oxide is preferably deposited as the insulating film 270F1 using a sputtering method. By depositing the insulating film 270F1 using a sputtering method in an oxygen-containing atmosphere, the insulating film 270F1 can be formed to contain excess oxygen. Furthermore, by using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating film 270F1 can be reduced. This allows excess oxygen contained in the insulating film 270F1 to be supplied to the oxide 230_1 formed in a subsequent step. Furthermore, the supply of hydrogen from the insulating film 270F1 to the oxide 230_1 can be suppressed.

[0697] Strictly speaking, the insulating film 270F1 is not limited to insulating materials. For example, a metal oxide with high insulating properties may be used. For example, the metal oxides that can be used for the oxide 230 may also be used.

[0698] Next, the insulating film 270F1 is processed into an island shape by photolithography to form an insulator 270_1 ( Figure 62A and Figure 62B ). The insulator 270_1 is formed in a manner that has an area overlapping with both sides of the two opposing conductors 205 in the channel width direction of each transistor included in the semiconductor device 200. In addition, in the channel length direction of the transistor, the insulator 270_1 can be provided in each transistor, or it can be provided in a manner that extends in the A1-A2 direction and is commonly used by each transistor. Note that the insulator 270_1 is preferably formed in a manner in which its side surface is perpendicular or approximately perpendicular to the top surface of the insulator 222_1. Thus, when the oxide film 230F1 later deposited on the insulator 270_1 is processed by anisotropic etching, the oxide 230_1 in contact with the side surface of the insulator 270_1 can be formed with high precision. In addition, when a plurality of transistors are provided within the substrate surface, the transistors can be reduced in area and increased in density. By performing this processing, the insulating film 270F1 on the area where the oxide 230_1 is later provided is removed.

[0699] Next, an oxide film 230F1 is deposited on the insulator 270_1 and the insulator 222_1 ( Figure 63A and Figure 63B The oxide film 230F1 has a region in contact with the top surface and side surfaces of the insulator 270_1 and the top surface of the insulator 222_1. As the oxide film 230F1, a metal oxide corresponding to the above-described oxide 230 can be used.

[0700] The formation method of the oxide film 230F1 can refer to the above-described formation methods of the oxide film 230A1 and the oxide film 230B1. For example, the oxide film 230F1 is preferably deposited using ALD. By depositing the oxide film 230F1 using ALD, the oxide film 230F1 can be formed with high coverage on the side surfaces of the insulator 270_1.

[0701] Next, heat treatment is preferably performed. The conditions of the heat treatment can refer to the description of the heat treatment that can be performed after the oxide film 230A1 and the oxide film 230B1 are deposited.

[0702] Next, the oxide film 230F1 is processed by anisotropic etching to remove the region in contact with the top surface of the insulator 270_1 and the region in contact with the top surface of the insulator 222_1. Thus, the oxide 230_1 ( Figure 64A and Figure 64B ).

[0703] Next, remove the insulator 270_1 ( Figure 65A and Figure 65B ) As a result, two island-shaped oxides 230_1 facing each other in the channel width direction of the transistor remain on the insulator 222_1 overlapping the conductor 205 .

[0704] Next, the A1 side end portion and the A2 side end portion of the oxide 230_1 are processed by photolithography. Figure 65A The oxide 230_1 shown is processed into an island shape ( Figure 66A and Figure 66B ). In addition, the oxide 230_1 also has a region overlapping with the conductor 205 after this processing. Note that Figure 26 In the case of the oxide 230_1 having the shape shown, this treatment is not necessary.

[0705] Although the above description shows that the process of removing the insulator 270_1 is performed ( Figure 65A and Figure 65B ) and then the oxide 230_1 is processed into an island shape ( Figure 66A and Figure 66B ) is an example, but is not limited thereto. In one embodiment of the present invention, the size of the oxide 230_1 may be reduced ( Figure 66A and Figure 66B ) and then remove the insulator 270_1 ( Figure 65A and Figure 65B ).

[0706] When the island oxide 230_1 is formed using photolithography, the channel width (W) of the oxide 230_1 is set according to the exposure limit of the photolithography technique. However, in this embodiment, the channel width (W) of the oxide 230_1 can be set according to the thickness of the oxide film 230F1. Therefore, the channel width of the transistor 200_1 can be set to a very small value, that is, a value below the exposure limit of the photolithography technique (for example, 0.1 nm to 60 nm, 1 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm). This allows for miniaturization of the transistor.

[0707] Next, a conductive film 242F1 is deposited to cover the oxide 230_1 and the insulator 222_1. Figure 67A and Figure 67B The conductive film 242F1 has a region in contact with the top and side surfaces of the oxide 230_1 and the top surface of the insulator 222_1. Conductors corresponding to the above-described conductors 242a and 242b can be used as the conductive film 242F1. The materials and formation methods that can be used for the conductive film 242F1 can be referred to above.

[0708] Next, the conductive film 242F1 is processed by photolithography to form an island-shaped conductive body 242_1 ( Figure 68A and Figure 68B The conductor 242_1 is formed to cover the island-shaped oxide 230_1. The conductor 242_1 has a region in contact with the top surface and side surfaces of the oxide 230_1 and the top surface of the insulator 222_1.

[0709] Next, an insulator 275_1 is deposited to cover the conductor 242_1 and the insulator 222_1 ( Figure 69A and Figure 69B ). The insulator 275_1 is preferably in contact with the top surface of the insulator 222_1.

[0710] The materials and formation methods that can be used for the insulator 275_1 can refer to the above description.

[0711] Next, an insulator 280_1 is deposited on the insulator 275_1. The materials and formation methods of the insulator 280_1 can be referred to the above description.

[0712] After the insulator 280_1 is deposited, the top surface of the insulator 280_1 is preferably planarized by CMP. Figure 70A and Figure 70BFor example, silicon nitride may be deposited on the insulator 280_1 by sputtering, and the silicon nitride may be subjected to CMP until it reaches the insulator 280_1.

[0713] Next, the conductor 242_1, the insulator 275_1, and the insulator 280_1 are processed by photolithography to form two openings 122 ( Figure 71A and Figure 71B The opening 122 that reaches the oxide 230_1 is provided in a region where the oxide 230_1 overlaps with the conductor 205 .

[0714] The above description can be referred to for the method of forming the opening 122. By performing this processing, the conductor 242_1 is divided into island-shaped conductors 242a1 and 242b1.

[0715] Next, an insulating film, which will become the insulator 250_1, is deposited on the oxide 230_1 and the insulator 280_1. This insulating film is formed so as to contact the sidewalls and bottom surface of the opening 122. The materials and formation methods that can be used for this insulating film can be referred to above.

[0716] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. The conditions for the microwave treatment can refer to the above description.

[0717] Next, a conductive film to be the conductor 260a1 and a conductive film to be the conductor 260b1 are sequentially deposited. The materials and formation methods that can be used for the conductive film to be the conductor 260a1 and the conductive film to be the conductor 260b1 can be referred to the above descript...

Claims

1. A semiconductor device comprising: a first transistor; a second transistor; a first insulator; a first electrical conductor; a second electrical conductor; as well as The third conductor, The first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator and a second gate electrode. The second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator and a third gate electrode. The first gate insulator is disposed on the first gate electrode, The first semiconductor layer is provided on the first gate insulator in a manner such that the first semiconductor layer has a region overlapping with the first gate electrode. The second gate insulator is disposed on the first semiconductor layer, The second gate electrode is provided on the second gate insulator in a manner having an area overlapping with the first gate electrode. The first source electrode and the first drain electrode are provided on the first semiconductor layer so as to sandwich the second gate electrode when viewed from a planar perspective. The first insulator is provided on the second gate electrode, The second semiconductor layer is provided on the first insulator in such a manner as to have a region overlapping with the first semiconductor layer. The third gate insulator is disposed on the second semiconductor layer, The third gate electrode is provided on the third gate insulator in such a manner as to have a region overlapping with the second gate electrode. The second source electrode and the second drain electrode are provided on the second semiconductor layer so as to sandwich the third gate electrode when viewed from a planar perspective. The first conductor is provided so as to penetrate the second source electrode and the second semiconductor layer and have a region in contact with the first source electrode. The second conductor is provided so as to penetrate the second drain electrode and the second semiconductor layer and have a region in contact with the first drain electrode. Furthermore, the third conductor is provided so as to have a region in contact with the first gate electrode, the second gate electrode, and the third gate electrode.

2. The semiconductor device according to claim 1, The first transistor and the second transistor include metal oxide in the semiconductor layer.

3. The semiconductor device according to claim 1 or 2, further comprising a second insulator covering the first transistor and a third insulator covering the second transistor. wherein the third insulator, the second source electrode, the second semiconductor layer, and the second insulator have a first opening that reaches the first source electrode, The third insulator, the second drain electrode, the second semiconductor layer, and the second insulator have a second opening that reaches the first drain electrode. The second conductor is arranged in contact with the sidewall and bottom surface of the first opening. Furthermore, the third conductor is provided in contact with the sidewalls and bottom surface of the second opening.

4. The semiconductor device according to claim 1 or 2, The length of the third gate electrode in the channel width direction is shorter than the length of the second gate electrode in the channel width direction.

5. The semiconductor device according to claim 1 or 2, The width between the first source electrode and the first drain electrode and the width between the second source electrode and the second drain electrode are both less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm or less than 10nm and are greater than 1nm or greater than 5nm.

6. The semiconductor device according to claim 1 or 2, further comprising a second insulator covering the first transistor and a third insulator covering the second transistor. wherein the second insulator has a first opening between the first source electrode and the first drain electrode that reaches the first semiconductor layer, The third insulator has a second opening between the second source electrode and the second drain electrode that reaches the second semiconductor layer. The second gate insulator is provided in a manner of contacting the sidewalls and bottom surface of the first opening, The second gate electrode is disposed on the second gate insulator in a manner of being embedded in the first opening. The third gate insulator is provided in a manner of contacting the sidewalls and bottom surface of the second opening, The third gate electrode is provided on the third gate insulator in a manner of being embedded in the second opening, The height of the top surface of the second gate insulator is substantially the same as the height of the top surface of the second gate electrode. Furthermore, the height of the topmost surface of the third gate insulator is substantially consistent with the height of the top surface of the third gate electrode.

7. The semiconductor device according to claim 1 or 2, wherein the side surfaces of the first source electrode and the first drain electrode that do not face the second gate electrode are substantially aligned with the side surfaces of the first semiconductor layer, Furthermore, side surfaces of the second source electrode and the second drain electrode that do not face the third gate electrode are substantially aligned with side surfaces of the second semiconductor layer.

8. A semiconductor device comprising: a first transistor; a second transistor; a first insulator; a first electrical conductor; a second electrical conductor; as well as The third conductor, The first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator and a second gate electrode. The second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator and a third gate electrode. The first gate insulator is disposed on the first gate electrode, The first semiconductor layer is provided on the first gate insulator in a manner such that the first semiconductor layer has a region overlapping with the first gate electrode. The second gate insulator is disposed on the first semiconductor layer, The second gate electrode is provided on the second gate insulator in a manner having an area overlapping with the first gate electrode. The first source electrode and the first drain electrode are provided on the first semiconductor layer so as to sandwich the second gate electrode when viewed from a planar perspective. The first insulator is provided on the second gate electrode, The second semiconductor layer is provided on the first insulator in such a manner as to have a region overlapping with the first semiconductor layer. The third gate insulator is disposed on the second semiconductor layer, The third gate electrode is provided on the third gate insulator in such a manner as to have a region overlapping with the second gate electrode. The second source electrode and the second drain electrode are provided on the second semiconductor layer so as to sandwich the third gate electrode when viewed from a planar perspective. The first conductor is provided in contact with a side surface of the first semiconductor layer, a side surface of the first source electrode, a side surface of the second semiconductor layer, and a side surface of the second source electrode. The second conductor is provided in contact with a side surface of the first semiconductor layer, a side surface of the first drain electrode, a side surface of the second semiconductor layer, and a side surface of the second drain electrode. Furthermore, the third conductor is provided so as to have a region in contact with the top surface of the first gate electrode, the top surface of the second gate electrode, and the top surface of the third gate electrode.

9. A semiconductor device comprising: a first transistor; a second transistor; a first insulator; a first electrical conductor; as well as the second conductor, The first transistor includes a first gate electrode, a first gate insulator, a first semiconductor layer, a first source electrode, a first drain electrode, a second gate insulator and a second gate electrode. The second transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, a third gate insulator and a third gate electrode. The first gate insulator is disposed on the first gate electrode, The first semiconductor layer is provided on the first gate insulator in a manner such that the first semiconductor layer has a region overlapping with the first gate electrode. The second gate insulator is disposed on the first semiconductor layer, The second gate electrode is provided on the second gate insulator in a manner having a region overlapping with the first gate electrode and having a region in contact with a top surface of the first gate electrode through openings provided in the first gate insulator and the second gate insulator, The first source electrode and the first drain electrode are provided on the first semiconductor layer so as to sandwich the second gate electrode when viewed from a planar perspective. The first insulator is provided on the second gate electrode, The second semiconductor layer is provided on the first insulator in such a manner as to have a region overlapping with the first semiconductor layer. The third gate insulator is disposed on the second semiconductor layer, The third gate electrode is provided on the third gate insulator so as to have a region overlapping with the second gate electrode and has a region in contact with a top surface of the second gate electrode through openings provided in the first insulator and the third gate insulator. The second source electrode and the second drain electrode are provided on the second semiconductor layer so as to sandwich the third gate electrode when viewed from a planar perspective. The first conductor is provided so as to penetrate the second source electrode and the second semiconductor layer and have a region in contact with the first source electrode. Furthermore, the second conductor is provided so as to penetrate the second drain electrode and the second semiconductor layer and have a region in contact with the first drain electrode.

10. The semiconductor device according to claim 9, The end of the second gate electrode is substantially aligned with the end of the third gate electrode when viewed from a plane.

11. A semiconductor device comprising: a first electrical conductor; a first insulator on the first electrical conductor; a first oxide on the first insulator; a second insulator, a second conductor, and a third conductor on the first oxide; a fourth conductor on the second insulator; a third insulator on the second insulator and the fourth conductor; a second oxide on the third insulator; a fourth insulator, a fifth conductor, and a sixth conductor on the second oxide; a seventh conductor on the fourth insulator; an eighth conductor penetrating the fifth conductor and the second oxide and contacting the second conductor; a ninth conductor penetrating the sixth conductor and the second oxide and contacting the third conductor; as well as a tenth conductor in contact with the top surface of the first conductor, the top surface of the fourth conductor, and the top surface of the seventh conductor, wherein the first conductor and the fourth conductor overlap with each other via the first oxide, The fourth conductor overlaps with the seventh conductor via the second oxide. The second conductor is electrically connected to the fifth conductor, The third conductor is electrically connected to the sixth conductor, The first conductor, the fourth conductor, and the seventh conductor are electrically connected, Furthermore, the third insulator has a region in contact with a top surface of the second insulator and a top surface of the fourth conductor.

12. The semiconductor device according to claim 11, The height of the top surface of the second insulator is substantially the same as the height of the top surface of the fourth conductor. Furthermore, the height of the top surface of the fourth insulator is substantially consistent with the height of the top surface of the seventh conductor.

13. The semiconductor device according to claim 11 or 12, wherein the side surfaces of the second conductor and the third conductor that are not facing the fourth conductor are substantially aligned with the side surfaces of the first oxide, Furthermore, the side surfaces of the fifth conductor and the sixth conductor that do not face the seventh conductor are substantially aligned with the side surfaces of the second oxide.

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