Thin film transistor and electronic device

Abstract

The thin film transistor includes: a substrate; an insulating layer containing oxygen, the insulating layer being formed on the substrate; an oxide semiconductor layer including a plurality of crystal grains, the oxide semiconductor layer being provided in contact with the insulating layer; a gate electrode provided over the oxide semiconductor layer; and a gate insulating layer that is provided between the oxide semiconductor layer and the gate electrode, and that obtains crystal orientation at each of a plurality of measurement points of the oxide semiconductor layer on the basis of an electron diffraction pattern obtained by transmitting an electron beam irradiated from a direction intersecting the film thickness direction of the oxide semiconductor layer through the oxide semiconductor layer. The average value of the KAM values calculated at the plurality of measurement points is 0.4 DEG or more.

Description

Technical Field

[0001] One embodiment of the present invention relates to a thin film transistor including an oxide semiconductor (Poly-OS) film having a polycrystalline structure. Another embodiment of the present invention relates to an electronic device including the thin film transistor. Background Art

[0002] In recent years, the development of thin-film transistors using oxide semiconductor films as channels, replacing silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon, has continued to advance (for example, see Patent Documents 1 to 6). Such thin-film transistors including oxide semiconductor films can be formed with a simple structure and low-temperature processes, similar to thin-film transistors including amorphous silicon films. Furthermore, thin-film transistors including oxide semiconductor films are known to have higher field-effect mobility than thin-film transistors including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Laid-Open No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Laid-Open No. 2021-108405 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] However, the field-effect mobility of conventional thin-film transistors including oxide semiconductor films is not that high even when using crystalline oxide semiconductor films. Therefore, it is desirable to improve the crystal structure of oxide semiconductor films used in thin-film transistors to increase the field-effect mobility of thin-film transistors.

[0013] In view of the above problems, one object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide an electronic device including a thin film transistor.

[0014] Means for solving problems

[0015] A thin film transistor according to one embodiment of the present invention includes: a substrate; an insulating layer containing oxygen, formed on the substrate; an oxide semiconductor layer containing multiple crystal grains, provided in contact with the insulating layer; a gate electrode provided on the oxide semiconductor layer; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein, when the crystal orientation at each of multiple measurement points of the oxide semiconductor layer is obtained based on an electron diffraction pattern obtained by transmitting an electron beam irradiated in a direction intersecting with the film thickness direction of the oxide semiconductor layer through the oxide semiconductor layer, an average value of KAM values calculated at the multiple measurement points is greater than 0.4°.

[0016] An electronic device according to one embodiment of the present invention includes the above-mentioned thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [ Figure 1 ] is a schematic cross-sectional view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0018] [ Figure 2 ] is a schematic top view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0019] [ Figure 3 ] is a schematic diagram illustrating the TEM-ED mapping method.

[0020] [ Figure 4 ] is a flowchart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0021] [ Figure 5 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0022] [ Figure 6 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0023] [ Figure 7 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0024] [ Figure 8 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0025] [ Figure 9 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0026] [ Figure 10] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0027] [ Figure 11 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0028] [ Figure 12 ] is a schematic diagram of an electronic device involved in one embodiment of the present invention.

[0029] [ Figure 13 ] is the inverse pole figure of the oxide semiconductor layer (Poly-OS film) of the embodiment sample.

[0030] [ Figure 14 ] is an IPF diagram of the oxide semiconductor layer (Poly-OS film) of the embodiment sample.

[0031] [ Figure 15 ] is a KAM diagram of the oxide semiconductor layer (Poly-OS film) of the embodiment sample.

[0032] [ Figure 16 ] is a graph showing the distribution of KAM values of the oxide semiconductor layer (Poly-OS film) of the example samples.

[0033] [ Figure 17 ] is a graph showing the depth average value of the KAM value in the oxide semiconductor layer (Poly-OS film) of the example sample. DETAILED DESCRIPTION

[0034] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are of course included in the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual way. However, the shape shown in the figure is merely an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, the same reference numerals are marked for the same components as those described in the accompanying drawings, and the detailed description is sometimes appropriately omitted.

[0035] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for the sake of convenience, the above or below statements are used for description, but for example, the upper and lower relationship between the substrate and the oxide semiconductor layer can also be configured in a direction different from that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the upper and lower relationship between the substrate and the oxide semiconductor layer as described above, and other components can also be arranged between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure in which multiple layers are stacked. In the case of expressing the pixel electrode above the thin film transistor, it can also be a positional relationship in which the thin film transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing the pixel electrode vertically above the thin film transistor, it means a positional relationship in which the thin film transistor and the pixel electrode overlap when viewed from above.

[0036] In this specification, the term "film" and the term "layer" can be interchanged depending on circumstances.

[0037] In this specification, a "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (such as polarizing components, backlight sources, touch panels, etc.) relative to a display unit. As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to display devices including the other electro-optical layers mentioned above.

[0038] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a combination of multiple elements from A to C. Furthermore, the above expressions do not exclude the case where α includes other elements.

[0039] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0040] <First embodiment>

[0041] Reference Figures 1 to 11A thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0042] [1. Configuration of Thin Film Transistor 10]

[0043] Reference Figure 1 and Figure 2 The structure of a thin film transistor 10 according to one embodiment of the present invention will be described. Figure 1 Schematic cross-sectional view showing the structure of a thin film transistor 10 according to one embodiment of the present invention. Figure 2 1 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 1 It is along Figure 2 A cross-sectional view obtained by cutting along the line A-A'.

[0044] like Figure 1 As shown, the thin film transistor 10 includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light shielding layer 105 is disposed on the substrate 100. The first insulating layer 110 covers the upper surface and end surfaces of the light shielding layer 105 and is disposed on the substrate 100. The second insulating layer 120 is disposed on the first insulating layer 110. The oxide semiconductor layer 140 is disposed on the second insulating layer 120. The oxide semiconductor layer 140 is in contact with the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is disposed on the second insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is disposed on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end faces of the gate electrode 160 and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. Openings 171 and 173 are provided in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180, respectively, to expose a portion of the upper surface of the oxide semiconductor layer 140. The source electrode 201 is provided on the fourth insulating layer 180 and within the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and within the opening 173, and is in contact with the oxide semiconductor layer 140. It should be noted that, hereinafter, when the source electrode 201 and the drain electrode 203 are not specifically distinguished, they may sometimes be collectively referred to as the source / drain electrode 200.

[0045] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes a channel region CH that overlaps with the gate electrode 160, and a source region S and a drain region D that do not overlap with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the electrical conductivity of the source region S and the drain region D is greater than that of the channel region CH. The source electrode 201 and the drain electrode 203 are respectively in contact with the source region S and the drain region D and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 can have a single-layer structure or a stacked structure.

[0046] like Figure 2 As shown, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction and extend along the D2 direction, which is orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The channel region CH completely overlaps with the light shielding layer 105. In the thin film transistor 10, the D1 direction corresponds to the direction in which current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0047] The substrate 100 can support each layer constituting the thin film transistor 10. As the substrate 100, for example, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a silicone resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can also be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0048] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 is configured to have an area larger than the channel region CH of the oxide semiconductor layer 140, so that it can block external light incident on the channel region CH. As the light-shielding layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys or compounds thereof can be used. In addition, as the light-shielding layer 105, it is not necessary to include metal when conductivity is not required. For example, as the light-shielding layer 105, a black matrix composed of black resin can also be used. In addition, the light-shielding layer 105 can be a single-layer structure or a stacked structure. For example, the light-shielding layer 105 can also be a stacked structure of a red filter, a green filter and a blue filter.

[0049] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (such as water) intruding from the outside. As the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) etc. Here, silicon nitride oxide (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are silicon compounds and aluminum compounds containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a silicon compound or an aluminum compound containing oxygen at a ratio less than nitrogen (x>y). In addition, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single layer structure or a stacked structure.

[0050] The second insulating layer 120 is preferably silicon oxide (SiO x ) and silicon nitride oxide (SiO x N y ) such as an insulating layer containing oxygen. That is, when the second insulating layer 120 has a single-layer structure, silicon oxide (SiO x ) or silicon nitride oxide (SiO x N y ), when the second insulating layer 120 has a stacked structure, silicon oxide (SiO x ) or silicon nitride oxide (SiO x N y ).

[0051] Each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarization function or a function of releasing oxygen through heat treatment. For example, if the second insulating layer 120 has a function of releasing oxygen through heat treatment, oxygen can be released from the second insulating layer 120 during the heat treatment performed during the manufacturing process of the thin film transistor 10 and supplied to the oxide semiconductor layer 140.

[0052] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof, can be used as the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a stacked structure.

[0053] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) etc. The gate insulating layer 150 preferably has a composition close to the stoichiometric ratio. Furthermore, the gate insulating layer 150 preferably has few defects. For example, an oxide having no defects observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.

[0054] Next, an oxide semiconductor film having a novel crystal structure used in the oxide semiconductor layer 140 is described.

[0055] [2. Structure of Oxide Semiconductor Film]

[0056] [2-1. Composition of Oxide Semiconductor Film]

[0057] The oxide semiconductor film contains indium (In) and at least one or more metal elements (M) other than indium. The composition ratio of the oxide semiconductor film is preferably such that the atomic ratio of indium to at least one or more metal elements satisfies formula (1). In other words, the ratio of indium in the oxide semiconductor film relative to all metal elements is preferably 50% or more. By increasing the ratio of indium, a crystalline oxide semiconductor film can be formed. In addition, the crystal structure of the oxide semiconductor film preferably has a pyroxenite structure. By increasing the ratio of indium, an oxide semiconductor film having a pyroxenite structure can be formed.

[0058] [Mathematical formula 1]

[0059]

[0060] It should be noted that the metal elements other than indium are not limited to one metal element, but may include multiple metal elements.

[0061] The detailed manufacturing method of the oxide semiconductor film will be described later, and the oxide semiconductor film can be formed using a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. As a sputtering target having the above composition, an oxide semiconductor film having no composition deviation of the metal elements can be formed by sputtering. Therefore, the composition of the metal elements (indium and other metal elements) of the oxide semiconductor film can also be the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be determined based on the composition of the metal elements of the sputtering target. It should be noted that the oxygen contained in the oxide semiconductor film will change according to the process conditions of the sputtering, etc., and is therefore not limited to this.

[0062] In addition, the composition of the metal elements of the oxide semiconductor film can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. In addition, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film can also be determined using X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by the XRD method.

[0063] [2-2. Crystal Structure of Oxide Semiconductor Film]

[0064] The oxide semiconductor film has a polycrystalline structure containing multiple crystal grains. As will be described in detail later, the use of Poly-OS (Poly-crystalline Oxide Semiconductor) technology enables the formation of an oxide semiconductor film having a novel polycrystalline structure, unlike conventional oxide semiconductor films. Therefore, hereinafter, to distinguish it from conventional oxide semiconductor films having a polycrystalline structure, the oxide semiconductor film having a polycrystalline structure according to this embodiment may be referred to as a Poly-OS film.

[0065] The crystal grains contained in the poly-OS film can be obtained from a plurality of microcrystals. The microcrystal diameter is not particularly limited, but is preferably 1 nm or more, more preferably 10 nm or more, and even more preferably 15 nm or more. The microcrystal diameter can be obtained using electron beam diffraction or XRD.

[0066] The crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbyite structure. The crystal structure of the Poly-OS film can be determined using an XRD method or an electron beam diffraction method.

[0067] It should be noted that in the Poly-OS film, the plurality of crystal grains may have one crystal structure or multiple crystal structures. When the Poly-OS film has multiple crystal structures, preferably one of the multiple crystal structures is a bixbyite structure.

[0068] The crystal structure of the Poly-OS film is different from the crystal structure of the oxide semiconductor film with a polycrystalline structure in the past. Specifically, the inventors of the present application found that the grains contained in the Poly-OS film have characteristics different from those of the grains contained in the previous oxide semiconductor film. The characteristics of such a Poly-OS film can be obtained by measuring the crystal orientation (vertical direction relative to the crystal plane) of the electron diffraction pattern. Specifically, the characteristics of the Poly-OS film can be measured using the TEM-ED mapping (Transmission Electron Microscopy Electron Diffraction Mapping) method. It should be noted that the TEM-ED mapping method is sometimes referred to as the ACOM-TEM (Automated Crystal Orientation Mapping Transmission Electron Microscopy) method. Below, the measurement of the oxide semiconductor film based on the TEM-ED mapping method is described.

[0069] [2-2-1. TEM-ED mapping method]

[0070] Figure 3 This is a schematic diagram illustrating the TEM-ED mapping method. The TEM-ED mapping method is an analytical method that irradiates a measurement area of an object to be measured with an electron beam, analyzes the electron diffraction pattern observed through the object to be measured, and measures the crystal orientation within the measurement area of the object to be measured. By continuously analyzing the electron diffraction pattern at multiple measurement points within the measurement area, information related to the crystal orientation within or between grains can be obtained. In the TEM-ED mapping method, a TEM sample 500 is used as the object to be measured. Therefore, compared to the EBSD (Electron Back Scattered Diffraction) method using an SEM sample, the TEM-ED mapping method can obtain information related to the crystal orientation within a small measurement area.

[0071] It should be noted that when the TEM-ED mapping method is applied to the oxide semiconductor layer 140 of the thin film transistor 10, a thin film sample including a cross section of the oxide semiconductor layer 140 of the thin film transistor 10 is used as the TEM sample 500. In addition, the TEM-ED mapping method is a measurement using a small area of the TEM sample, and the step interval of the measurement points for observing the electron beam diffraction pattern is, for example, 1 nm or more, but is not limited thereto. Among them, in the measurement of the crystal orientation, it is preferred that the number of measurement points in the film thickness direction of the oxide semiconductor layer 140 is large. For example, the step interval is less than 1 / 5 of the film thickness of the oxide semiconductor layer, preferably less than 1 / 10, and more preferably less than 1 / 30.

[0072] In the TEM-ED mapping method, Figure 3 As shown, a coordinate system (ND (Normal Direction), TD (Transverse Direction), and RD (Reference Direction)) based on TEM specimen 500 is used. In the coordinate system based on TEM specimen 500, the normal direction relative to the surface of TEM specimen 500 is ND. ND, TD, and RD are orthogonal to each other. The electron beam is irradiated from ND toward TEM 500.

[0073] exist Figure 3 ] shows a coordinate system based on the TEM sample 500 and a coordinate system (x-axis, y-axis, and z-axis) based on the thin film transistor 10 (or oxide semiconductor layer 140). In the coordinate system based on the thin film transistor 10, the thickness direction of the oxide semiconductor layer 140 is the z-axis. The x-axis, y-axis, and z-axis are orthogonal to each other. Therefore, the x-axis and y-axis are in-plane directions of the oxide semiconductor layer 140.

[0074] Therefore, ND, TD, and RD in the TEM-ED mapping method correspond to the y-axis, x-axis, and z-axis of the thin film transistor 10, respectively.

[0075] [2-2-2. Antipolar Figure]

[0076] An inverse pole figure (IPF) is an image that graphically illustrates the crystal orientation in a specific direction of a coordinate system based on TEM specimen 500. The IPF shows the ratio of crystal orientation in each direction of the coordinate system of TEM specimen 500, according to a specified index. Typically, the ratio of crystal orientation in a specific direction is coded using a color key.

[0077] [2-2-3.IPF diagram]

[0078] An IPF map is an image that graphically displays the crystal orientation in a specific direction of a coordinate system based on TEM sample 500 as the distribution of crystal orientations on the surface of TEM sample 500. In the IPF map, the crystal orientations at multiple measurement points are distinguished according to a predetermined index representing the crystal orientation in each direction of the coordinate system of TEM sample 500. Typically, the crystal orientations are distinguished by color using a color key.

[0079] [2-2-4. Grains]

[0080] A grain is a crystalline region surrounded by grain boundaries. TEM-ED mapping provides information about crystal orientation, allowing grain boundaries to be defined based on that orientation. Generally, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, a grain boundary is defined as existing between the two points. Therefore, this definition also applies to Poly-OS films.

[0081] The TEM-ED mapping method is a measurement within a tiny measurement area. In addition, as the TEM sample 500, a thin film sample is used in which the cross section along the film thickness direction is used as the surface, so it is difficult to define the grain diameter of the grains extending within the plane of the oxide semiconductor layer 140. Therefore, in this embodiment, instead of the grain diameter, the length of the grain obtained based on the cross section of the oxide semiconductor layer 140 in the measurement area is defined as the grain length. Specifically, the distance between two grain boundaries obtained in the cross section of the oxide semiconductor layer 140 is defined as the grain length. The grain length defined in this way may be calculated to be smaller than the grain diameter. However, the grain diameter of the grains contained in the Poly-OS film is much larger than the grain diameter of the grains contained in the conventional oxide semiconductor film. That is, the grain length defined as described above in the Poly-OS film can be obtained as a value larger than the grain diameter of the grains contained in the conventional oxide semiconductor film. Therefore, the grain length defined as described above can be used to compare the Poly-OS film with the conventional oxide semiconductor film. In the Poly-OS film, the grain length is 100 nm or more, preferably 300 nm or more, and more preferably 500 nm or more. The upper limit of the grain length is not particularly limited, but is 50 μm or less. It should be noted that the grain length is preferably measured at the center of the film thickness.

[0082] As described above, the crystal grains included in the Poly-OS film have a large grain length, and one crystal grain may form a portion of the upper surface and a portion of the lower surface of the Poly-OS film.

[0083] [2-2-5.KAM value]

[0084] The KAM (Kernel Average Misorientation) value is the average value of the crystal orientation differences between a measurement point within a grain and all adjacent measurement points. The crystal orientation difference between two adjacent measurement points sandwiching a grain boundary is excluded from the calculation of the KAM value.

[0085] The KAM value represents the variation in crystal orientation within a grain. As mentioned above, a grain boundary is identified when the crystal orientation difference between a measurement point and another adjacent measurement point exceeds 5°. Therefore, the KAM value calculated based on adjacent measurement points within a grain ranges from 0° to 5°. A high KAM value indicates significant local variation in crystal orientation within the grain, indicating a grain with significant distortion.

[0086] The KAM value is calculated at multiple measurement points. Therefore, a distribution diagram of the KAM value within the grain can be made. In addition, the average value and standard deviation of the KAM value can be calculated. The average value of the KAM value is a value that represents one of the properties of the grains contained in the Poly-OS film. Since the Poly-OS film includes a large number of crystals with large variations in crystal orientation and large distortion, the average value of the KAM value is larger than that of the conventional oxide semiconductor film with a polycrystalline structure. The average value of the KAM value in the Poly-OS film is greater than 0.4°, preferably greater than 0.45°, and more preferably greater than 0.5°. Similarly, the standard deviation of the KAM value is also a value that represents one of the properties of the grains contained in the Poly-OS film. In Poly-OS, the standard deviation of the KAM value is greater than 0.3°, preferably greater than 0.35°, and more preferably greater than 0.4°.

[0087] Furthermore, in Poly-OS films, the average KAM value increases as the step interval between measurement points increases. This is due to the large variations in crystal orientation within the grains contained in Poly-OS films. This tendency for the average KAM value to increase with increasing step interval is also a characteristic of Poly-OS films.

[0088] It should be noted that the average value of the KAM values mentioned above is the total average value of the KAM values calculated using the KAM values of all the measurement points in the measurement area (KAM AVE(total) In this specification, unless otherwise specified, the average value of the KAM value refers to the total average value of the KAM value (KAM AVE(total) On the other hand, the average value of the KAM value can be calculated using a portion of the multiple measurement points within the measurement area. For example, the film thickness of the Poly-OS film can be divided and the average value of the KAM values of the measurement points included in the divided area can be calculated. The average value of the KAM values calculated using a portion of the measurement points is equal to the total average value of the KAM values (KAM AVE(total) The average value of the KAM value calculated by distinguishing the film thickness of the Poly-OS film is the average value of the distance (depth) that depends on the film thickness of the Poly-OS film. Therefore, in this specification, it is different from the total average value of the KAM value (KAM AVE(total) ) are distinguished and sometimes recorded as the depth average of the KAM value (KAM AVE(depth) ).

[0089] As described above, since the grain length of the Poly-OS film is large, it can be formed from one grain from the upper surface to the lower surface of the Poly-OS film. In the Poly-OS film, the crystal orientation also changes significantly in the film thickness direction of the Poly-OS film. Specifically, at the upper and lower ends of the Poly-OS film (referring to the vicinity of the interface, such as the area within 3nm from the interface) and the central part (referring to the vicinity of the center, such as the area within 5nm equidistant from the upper and lower ends), the depth average value of the KAM value (KAM AVE(depth) The depth average KAM value (KAM) at the upper and lower ends of the Poly-OS film is different. AVE(depth) ) is 0.4° or more and less than 5.0°, preferably 0.5° or more and less than 5.0°, and more preferably 0.6° or more and less than 5.0°. On the other hand, the depth average value of the KAM value at the center of the Poly-OS film (KAM AVE(depth) ) is less than 0.5°. In addition, the depth average KAM value (KAM) of the upper end or lower end and the central part of the Poly-OS film AVE(depth) ) is 0.05° or more, preferably 0.1° or more, and more preferably 0.15° or more.

[0090] Sometimes, the upper and lower surfaces of the Poly-OS film have unevenness. In this case, the number of measurement points at the upper and lower ends is reduced, and the depth average value of the KAM value at the upper and lower ends (KAM AVE(depth) Therefore, the area where the number of measurement points included in the divided area is 90% or more of the number of measurement points in the central part (or 90% or more of the maximum number of measurement points) can be used as a valid area to calculate the depth average value (KAM) of the KAM values at the upper end, lower end, and central part of the Poly-OS film. AVE(depth) In an effective Poly-OS film, the depth average value (KAM) of the KAM value at the upper end and the lower end can be calculated without being affected by the unevenness formed on the upper and lower surfaces. AVE(depth) ).

[0091] As described above, TEM-ED mapping can be used to obtain information about the crystal orientation within the grains contained in the Poly-OS film. For example, when the Poly-OS film has a bixbyite structure, TEM-ED mapping can reveal that the Poly-OS film contains grains with a crystal orientation of <001>, <101>, or <111>.

[0092] Here, the crystal orientation <001> represents

[001] and its equivalents

[100] and

[010] . Furthermore, the crystal orientation <101> represents

[101] and its equivalents

[110] and

[011] . Furthermore, the crystal orientation <111> represents

[111] . Furthermore, in each orientation, "1" may also be "-1" and is considered to be an axis equivalent to that orientation.

[0093] In addition, in addition to <001>, <101> and <111>, there are <hk0> (h≠k, h and k are natural numbers), <hhl> (h≠l, h and l are natural numbers) and <hkl> (h≠k≠l, h, k and l are natural numbers).

[0094] The crystal grains contained in the Poly-OS film have the characteristic that the crystal orientation changes greatly within the crystal grains. If the characteristics of such a Poly-OS film are digitized using the TEM-ED method, the average value of the KAM value of the Poly-OS film is above 0.4°. In the case of previous oxide semiconductor films, if the change in the crystal orientation within the crystal grains is large, crystal dislocations are likely to occur, resulting in a decrease in the grain diameter of the crystal grains. However, in the Poly-OS film, although the change in the crystal orientation within the crystal grains is large, the grain length (or grain diameter) of the crystal grains is large as described above. The characteristics of such a Poly-OS film are completely different from those of the previous oxide semiconductor films. The inventors of the present application conducted trial and error and discovered a Poly-OS film with a new crystal structure. The Poly-OS film contains crystal grains with a large grain length (or grain diameter) and is therefore not easily affected by grain boundaries. Therefore, in the thin film transistor 10 including the Poly-OS film as the channel, the channel is not easily affected by the grain boundaries, grain boundary scattering is suppressed, and the field effect mobility is improved.

[0095] Note that details of the crystal orientation of crystal grains included in the Poly-OS film will be described later together with examples.

[0096] The structure of the thin film transistor 10 has been described above. The thin film transistor 10 is a so-called top-gate transistor. The thin film transistor 10 can be deformed in various ways. For example, when the light shielding layer 105 is conductive, the thin film transistor 10 can also be a structure in which the light shielding layer 105 functions as a gate electrode and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin film transistor 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 105 is conductive, the light shielding layer 105 can also be a floating electrode and can also be connected to the source electrode 201. In addition, the thin film transistor 10 can also be a so-called bottom-gate transistor in which the light shielding layer 105 functions as the main gate electrode.

[0097] [2. Method for Manufacturing Thin Film Transistor 10]

[0098] Reference Figures 4 to 11 A method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 4 1 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figures 5 to 11 Schematic cross-sectional views illustrating a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0099] like Figure 4 As shown, the method for manufacturing the thin film transistor 10 includes steps S1010 to S1110. Hereinafter, steps S1010 to S1110 will be described in order, but the order of the steps may be reversed. Furthermore, the method for manufacturing the thin film transistor 10 may include other steps.

[0100] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned using photolithography. In addition, a first insulating layer 110 and a second insulating layer 120 are formed on the light shielding layer 105 (see FIG. 1 ). Figure 5 The first insulating layer 110 and the second insulating layer 120 are formed using a CVD method. For example, silicon nitride and silicon oxide can be formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block impurities that diffuse from the substrate 100 side to the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen through heat treatment.

[0101] In step S1020, an oxide semiconductor film 145 is formed on the second insulating layer 120 (see Figure 6 The oxide semiconductor film 145 is formed by sputtering. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and more preferably not less than 15 nm and not more than 40 nm.

[0102] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order to make the oxide semiconductor layer 140 have a uniform polycrystalline structure within the substrate surface, the oxide semiconductor film 145 is preferably amorphous after film formation and before heat treatment. Therefore, the film forming conditions of the oxide semiconductor film 145 are preferably conditions that prevent the oxide semiconductor film 145 from crystallizing as much as possible immediately after film formation. In the case of forming the oxide semiconductor film 145 by sputtering, the oxide semiconductor film 145 is formed while the temperature of the object to be film-formed (the substrate 100 and the layer formed on the substrate 100) is controlled to be below 100°C, preferably below 80°C, and more preferably below 50°C. In addition, the oxide semiconductor film 145 is formed under conditions of low oxygen partial pressure. The oxygen partial pressure is above 2% and below 20%, preferably above 3% and below 15%, and more preferably above 3% and less than 10%.

[0103] In step S1030, the oxide semiconductor film 145 is patterned (see Figure 7 The oxide semiconductor film 145 is patterned using photolithography. The oxide semiconductor film 145 can be etched using wet etching or dry etching. Wet etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etchant.

[0104] In step S1040, the oxide semiconductor film 145 is heat-treated. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing". In the OS annealing, the oxide semiconductor film 145 is maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300°C to 500°C, preferably 350°C to 450°C. In addition, the predetermined time (holding time) at the reaching temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. Through the OS annealing, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 including a Poly-OS film).

[0105] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see Figure 8 The gate insulating layer 150 is formed using a CVD method. For example, a silicon oxide film is formed as the gate insulating layer 150. To reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film forming temperature of 350°C or higher. The thickness of the gate insulating layer 150 is not less than 50 nm and not more than 300 nm, preferably not less than 60 nm and not more than 200 nm, and more preferably not less than 70 nm and not more than 150 nm.

[0106] In step S1060, the oxide semiconductor layer 140 is subjected to a heat treatment. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. During the oxidation annealing, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, thereby repairing the oxygen vacancies.

[0107] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see Figure 9 The gate electrode 160 is formed by sputtering or atomic layer deposition, and patterning of the gate electrode 160 is performed using photolithography.

[0108] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see Figure 9 ). The source region S and the drain region D are formed by ion implantation. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. As the impurities to be implanted, for example, argon (Ar), phosphorus (P) or boron (B) is used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated by ion implantation, and hydrogen is captured in the generated oxygen vacancies. As a result, the resistance of the source region S and the drain region D is reduced. On the other hand, in the channel region CH that overlaps with the gate electrode 160, since impurities are not implanted, oxygen vacancies are not generated, and the resistance of the channel region CH is not reduced.

[0109] Note that, in the thin film transistor 10 , since impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150 , the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0110] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see Figure 10 The third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the fourth insulating layer 180 is also not less than 50 nm and not more than 500 nm.

[0111] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see FIG. Figure 11). By forming the openings 171 and 173 , the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0112] In step S1110, the source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and the drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed in the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning one of the formed conductive films. Through the above steps, a Figure 1 The thin film transistor 10 is shown.

[0113] The method for manufacturing the thin film transistor 10 has been described above, but the method for manufacturing the thin film transistor 10 is not limited thereto.

[0114] In the thin film transistor 10 involved in this embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. The Poly-OS film includes crystal grains with large changes in crystal orientation and large grain length (or grain diameter). Therefore, in the thin film transistor 10 including the Poly-OS film as a channel, the channel as a whole is not easily affected by grain boundaries. In addition, it is believed that the result of changing the crystal orientation within the grains in a manner that improves lattice matching at the grain boundaries is that grain boundaries with fewer defects are generated. As a result, in the thin film transistor 10 including the Poly-OS film as a channel, grain boundary scattering is suppressed and field effect mobility is improved.

[0115] <Second embodiment>

[0116] Reference Figure 12 An electronic device according to an embodiment of the present invention will be described.

[0117] Figure 12 Schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Figure 12 , a smartphone is shown as an example of electronic device 1000. Electronic device 1000 includes a display device 1100 with curved sides. Display device 1100 includes a plurality of pixels for displaying images, and these pixels are controlled by pixel circuits and driver circuits. The pixel circuits and driver circuits include the thin-film transistor 10 described in the first embodiment. Thin-film transistor 10 has high field-effect mobility, thereby improving the responsiveness of the pixel circuits and driver circuits, thereby enhancing the performance of electronic device 1000.

[0118] It should be noted that the electronic device 1000 of this embodiment is not limited to smartphones. The electronic device 1000 also includes electronic devices with a display device, such as clocks, tablet computers, laptop computers, car navigation systems, and televisions. Furthermore, the thin-film transistor 10 described in the first embodiment is independent of the presence or absence of a display device and can be applied to all electronic devices.

[0119] Example

[0120] The oxide semiconductor layer (specifically, the Poly-OS film) will be described in further detail based on the manufactured thin film transistor.

[0121] [1. Manufacturing of Thin Film Transistors]

[0122] A thin film transistor is manufactured using the manufacturing method described in the first embodiment. In the sputtering process for forming the oxide semiconductor layer, a sputtering target in which indium is 70% in atomic ratio relative to all metal elements contained in the sintered body is used to form a 30nm oxide semiconductor layer. The oxygen partial pressure during film formation is 5%, and the substrate temperature is controlled so that the substrate temperature is below 100°C. In the OS annealing process, the reaching temperature is controlled between 350°C and 450°C in an atmospheric atmosphere and maintained at the reaching temperature for 60 minutes. The chemical composition of the oxide semiconductor layer after the OS annealing process is the same as that of the sputtering target.

[0123] [2. Crystal orientation analysis based on TEM-ED mapping]

[0124] A TEM sample (hereinafter referred to as an "example sample") was prepared by sampling a cross section of a region including an oxide semiconductor layer of a thin film transistor using FIB processing, and the crystal orientation of the Poly-OS film contained in the oxide semiconductor layer was analyzed using the TEM-ED mapping method. The measurement conditions of the TEM-ED mapping method are shown in Table 1. The analysis of the crystal orientation was performed using ASTAR manufactured by NanoMegas. The orientation of the crystal structure was determined using PDF (Powder Diffraction File) 04-024-4517 of ICDD (International Centre for Diffraction Data).

[0125] [Table 1]

[0126] Device JEM-ARM200F manufactured by NEC Corporation Accelerating voltage 200kV Measurement area 60nm×1200nm Step interval 1nm

[0127] [2-1. Inverse pole figure]

[0128] Figure 13is the inverse pole figure of the oxide semiconductor layer (Poly-OS film) of the example sample. Figure 13 The inverse pole figures under ND, TD and RD conditions are shown in Figure 2. The ratio of crystal orientation under ND, TD and RD conditions is as follows: Figure 14 The value of the indicator shown increases (for example, the indicator can be a color key, and when it changes from blue to red (the wavelength of visible light becomes longer) the proportion of the crystal orientation increases). It can be seen that in TD and RD, there are regions with large values (regions A1 and A2), and there are specific crystal orientations with a large proportion. In addition, it can be seen that in ND and RD, there are regions with relatively large values (regions A3 and A4), and there are specific crystal orientations with a relatively large proportion. For example, in TD corresponding to the direction orthogonal to the film thickness direction of the oxide semiconductor layer, the crystal orientation <111> The proportion of crystal orientation <001> and crystal orientation <101> The proportion is large.

[0129] The main crystal orientation under the conditions of ND, TD and RD is not particularly limited, but it is preferred that the crystal orientation in any direction of ND, TD and RD is <001> , crystal orientation <101> and the crystal orientation <111> account for a large proportion.

[0130] [2-2. IPF diagram]

[0131] Figure 14 This is an IPF diagram of the oxide semiconductor layer (Poly-OS film) of the example sample. Figure 14 The IPF diagrams under ND, TD and RD conditions are shown in FIG. Figure 14 In the figure, crystal orientation <001>, crystal orientation <101>, crystal orientation <111> and crystal orientation <011> are distinguished according to the indicators in the figure.

[0132] exist Figure 14 In the regions B1 and B2 shown, the crystal orientation changes discontinuously and significantly. The discontinuous change in crystal orientation corresponds to a grain boundary. In regions B1 and B2, a grain boundary formed from the upper surface toward the lower surface (or from the lower surface toward the upper surface) of the oxide semiconductor layer is confirmed. The grain length of a single crystal grain between the grain boundary in region B1 and the grain boundary in region B2 is 832 nm. In addition, a single crystal grain forms a portion of the upper surface and a portion of the lower surface of the oxide semiconductor layer. That is, the grain length is more than 10 times the film thickness of the oxide semiconductor layer.

[0133] The crystal orientation within the grains in the IPF diagram corresponds to the ratio of the crystal orientation in the inverse pole figure described above. For example, the main crystal orientation of the grains in the TD is the crystal orientation <111>.

[0134] Although not shown in the drawings, grain boundaries can also be confirmed in the TEM image in the regions B1 and B2.

[0135] [2-3.KAM value]

[0136] Figure 15 is a KAM diagram of the oxide semiconductor layer (Poly-OS film) of the example sample. Figure 15 The KAM values of each measurement point in the measurement area are calculated according to Figure 15 The KAM value is distinguished by the value of the indicator shown (for example, the indicator can be a color key, and as the color changes from blue to red (the wavelength of visible light becomes longer), the KAM value increases from 0° to 5°). It should be noted that when the crystal orientation difference between two adjacent measurement points exceeds 5°, it is regarded as a grain boundary, so the upper limit of the KAM value is 5°. In addition, Figure 16 This is a graph showing the distribution of KAM values of oxide semiconductor layers (Poly-OS films) of example samples.

[0137] like Figure 15 As shown, in the oxide semiconductor layer, there are not only regions with KAM values near 0° (since they correspond to the regions indicated by blue in the color key, they are referred to as "blue regions" for the sake of convenience), but also regions with KAM values other than near 0° (since they correspond to the regions indicated by green in the color key, they are referred to as "green regions" for the sake of convenience). As an overall trend, the blue region extends in the central part of the oxide semiconductor layer, and the green region extends near the surface of the oxide semiconductor layer (near the upper and lower ends). As shown in FIG. Figure 16 As can be understood, there are many measurement points with KAM values near 0°, and there are also many measurement points with KAM values other than 0°. The total average KAM value (KAM) calculated using the KAM values of all measurement points is AVE(total) ) is 0.493°. In addition, the standard deviation (σ) of the KAM value is 0.399. It should be noted that since the KAM values at two adjacent measurement points gradually change, if the step interval increases, there will be an average value of the KAM value and a total average value of the KAM value (KAM AVE(total) ) tends to become larger.

[0138] The TEM-ED mapping method is a measurement in a tiny area, but in the case of the Poly-OS film, the total average value and standard deviation of the KAM value in such a tiny area are also large. This means that the crystal orientation within the grains of the Poly-OS film varies greatly. Although the grains contained in the Poly-OS film have a large grain length (or grain diameter), the local crystal orientation varies greatly. This is one of the characteristics of the Poly-OS film that cannot be seen in the oxide semiconductor film with a polycrystalline structure in the past.

[0139] Figure 17 : This is a graph showing the depth average value of the KAM value in the oxide semiconductor layer (Poly-OS film) of the example sample. As described above, it is observed that there is a difference in the distribution of the KAM value in the central part and near the surface (near the upper end and the lower end) of the oxide semiconductor layer. Therefore, the KAM values of the measurement points are summed according to the distance from the interface between the gate insulating layer and the oxide semiconductor layer (the depth of the oxide semiconductor layer), and the depth average value of the KAM value (KAM) is calculated as the average value. AVE(depth) The depth average of KAM values (KAM AVE(depth) ) is the average value of the KAM values of a portion of the measurement points divided according to the depth of the oxide semiconductor layer. It should be noted that in order to exclude the influence of the unevenness of the surface of the oxide semiconductor layer, the area where the number of measurement points included in the divided area is 90% or more of the number of measurement points in the central part is regarded as the effective area, and the depth average value of the KAM value of the oxide semiconductor layer (KAM AVE(depth) ). Figure 17 The graph shown plots the depth average value of the KAM value (KAM) in the thickness direction of the oxide semiconductor layer. AVE(depth) ).

[0140] like Figure 17 As shown, compared with the central portion of the oxide semiconductor layer, the depth average value (KAM) of the KAM value at the upper end portion near the interface between the oxide semiconductor layer and the gate insulating layer and the lower end portion near the interface between the oxide semiconductor layer and the second insulating layer is AVE(depth) The depth average KAM values (KAM) of the center (depth 15nm), upper end (depth 0nm) and lower end (depth 32nm) are AVE(depth) ) are 0.418°, 0.641° and 0.484° respectively. The depth average of KAM values (KAM AVE(depth) ) is greater than 0.2° between the upper end and the central portion. AVE(depth) ) is greater than 0.05° between the lower end portion and the central portion.

[0141] The above results show that the change in crystal orientation near the interface of the oxide semiconductor layer is large. In the Poly-OS film, the change in local crystal orientation in the film thickness direction is also large. In the previous oxide semiconductor film with a polycrystalline structure, the grain length (or grain diameter) is reduced to alleviate the distortion within the grain, and it is difficult to form the upper surface to the lower surface of the oxide semiconductor film with a single grain. On the other hand, in the Poly-OS film, it is possible to form the upper surface to the lower surface using a single grain with a large change in crystal orientation. This is one of the characteristics of the Poly-OS film that cannot be seen in the previous oxide semiconductor film with a polycrystalline structure.

[0142] [3. Electrical characteristics]

[0143] The electrical characteristics of the manufactured thin film transistor were measured. The field effect mobility calculated from the electrical characteristics was 20.7 cm 2 / Vs. It can be seen that if the Poly-OS film is used as the channel of the thin film transistor, a voltage of more than 20cm can be obtained. 2 / Vs field-effect mobility (field-effect mobility in the saturation region).

[0144] The various embodiments described above as embodiments of the present invention can be implemented in appropriate combinations as long as they do not contradict each other. In addition, solutions obtained by those skilled in the art by appropriately adding, deleting, or changing the design of components based on the various embodiments, or by adding, omitting, or changing the conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0145] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0146] Description of Reference Numerals

[0147] 10: Thin-film transistor, 100: Substrate, 105: Light-shielding layer, 110: First insulating layer, 120: Second insulating layer, 140: Oxide semiconductor layer, 145: Oxide semiconductor film, 150: Gate insulating layer, 160: Gate electrode, 170: Third insulating layer, 171: Opening, 173: Opening, 180: Fourth insulating layer, 200: Source / drain electrodes, 201: Source electrode, 203: Drain electrode, 500: TEM sample, 1000: Electronic device, 1100: Display device

Claims

1. A thin film transistor comprising: substrate; an insulating layer containing oxygen, formed on the substrate; an oxide semiconductor layer including a plurality of crystal grains, disposed in contact with the insulating layer; a gate electrode disposed on the oxide semiconductor layer; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, When the crystal orientation at each of multiple measurement points of the oxide semiconductor layer is obtained based on an electron diffraction pattern obtained by transmitting an electron beam irradiated in a direction intersecting with the film thickness direction of the oxide semiconductor layer through the oxide semiconductor layer, the average value of the KAM values calculated at the multiple measurement points is greater than 0.4°.

2. The thin film transistor according to claim 1, wherein observing the electron diffraction pattern at each of the plurality of measurement points at a predetermined step interval, The predetermined step interval is 1 nm or more.

3. The thin film transistor according to claim 2, wherein: The predetermined step interval is less than or equal to 1 / 5 of the thickness of the oxide semiconductor layer. The thin film transistor according to claim 2 , wherein: As the prescribed step interval increases, the average value becomes larger. The thin film transistor according to claim 1 , wherein: At least one of two crystal grains adjacent to each other across a grain boundary forms a portion of the upper surface and a portion of the lower surface of the oxide semiconductor layer. The thin film transistor according to claim 5 , wherein: When the difference in crystal orientation between two adjacent measurement points exceeds 5°, the area between the two adjacent measurement points is defined as the grain boundary.

7. The thin film transistor according to claim 1, wherein The depth average value of the KAM value at each of the upper end portion and the lower end portion of the oxide semiconductor layer is 0.45° or greater.

8. The thin film transistor according to claim 1, wherein A difference between a depth average of a KAM value at an upper end portion or a lower end portion of the oxide semiconductor layer and a depth average of a KAM value at a central portion is 0.05° or more.

9. The thin film transistor according to claim 1, wherein The ratio of the crystal orientation in the direction intersecting the film thickness direction of the oxide semiconductor layer is greater for the crystal orientation <111> than for the crystal orientation <001> and the crystal orientation <101>.

10. The thin film transistor according to claim 1, wherein At least one of the plurality of crystal grains has a crystal grain length of 100 nm or more in the direction intersecting the film thickness direction of the oxide semiconductor layer. The thin film transistor according to claim 1 , wherein: The oxide semiconductor layer includes: Indium; and At least one metal element other than the indium, The ratio of the indium to the indium and the at least one metal element is 50% or more.

12. The thin film transistor according to claim 1, wherein The insulating layer is silicon oxide or silicon nitride oxide.

13. The thin film transistor according to claim 1, wherein The crystal structure of the oxide semiconductor layer is a bixbyite structure. 14 . An electronic device comprising the thin film transistor according to claim 1 .

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