Consumable chip, consumable box and imaging device

Abstract

The invention relates to a consumable chip, a consumable box and an imaging device. The consumable chip comprises at least two signal terminals; the function unit comprises a power input port positive electrode and a power input port negative electrode; the positive pole of the power input port is connected with the power terminal; the negative electrode of the power input port is connected with at least one first signal terminal through the one-way conduction module. The one-way conduction module is used for pulling down the negative electrode of the power supply input port to a low level when the first signal terminal has the low level; the first power supply module and the second power supply module are connected in parallel; the first power supply module is used for discharging when the time when the first signal terminal is at the high level is within a first time period; the second power supply module is used for discharging when the time when the first signal terminal is at the high level exceeds a first time period; according to the invention, normal work of the consumable chip can be ensured when there is no grounding terminal and the first signal terminal is at a high level for a long time.

Description

[0001] This application claims priority to the Chinese patent applications filed with the China Patent Office on November 25, 2024, with application number 202411701940.3 and application name “A consumable chip and consumable box”, and the Chinese patent application filed with the China Patent Office on December 26, 2024, with application number 202411946731.5 and application name “A consumable chip and consumable box”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of image forming technology, and in particular to a consumable chip, a consumable box and an imaging device. Background Art

[0003] During the printing and imaging process, the printing device needs the assistance of the imaging auxiliary information of the consumable box to complete the imaging process. In addition to being recorded in the printing device, the imaging auxiliary information of the printing device is also recorded on the consumable chip. The consumable chip can be installed on the consumable box, which can be an ink cartridge filled with ink or a toner cartridge filled with toner. The ink cartridge and toner are recording materials. The function of the consumable chip is to control the authentication and data matching between the consumable box and the printing device, and to provide imaging auxiliary information in the subsequent imaging process. The consumable chip is provided with a wafer and terminals that are electrically connected to the contact pins of the printing device. The wafer stores relevant information such as toner quantity information, manufacturer information, serial number, etc.

[0004] Patent application CN201420575859.0 discloses a prior art method for omitting a ground terminal from a consumable chip. When the chip select signal, clock signal, and data signal are simultaneously high, a capacitor or battery is connected in parallel between the positive and negative terminals of the power input port to create a voltage differential. This allows the consumable chip to operate normally even without a ground terminal electrically connected to the printing device. However, this solution, using only a capacitor, does not provide sufficient charge to maintain the voltage differential for an extended period of time. Summary of the Invention

[0005] In view of this, the present application provides a consumable chip, a consumable box and an imaging device, which can ensure the normal operation of the consumable chip when there is no ground terminal and the first signal terminal is at a high level for a long time.

[0006] In a first aspect, an embodiment of the present invention provides a consumable chip, wherein the consumable chip is mounted on a consumable box, and the consumable box is detachably mounted on a printing device, and the consumable chip includes:

[0007] At least two signal terminals, including a power terminal and a first signal terminal; the first signal terminal does not include a ground terminal;

[0008] The functional unit includes a positive electrode of a power input port and a negative electrode of a power input port; the positive electrode of the power input port is connected to the power terminal; the negative electrode of the power input port is connected to the first signal terminal via a unidirectional conduction module;

[0009] A unidirectional conduction module, whose input end is connected to the negative electrode of the power input port, and whose output end is connected to the first signal terminal, is used to pull the negative electrode of the power input port down to a low level when the first signal terminal has a low level;

[0010] A first power supply module and a second power supply module connected in parallel, one end of which is connected to the positive electrode of the power input port, and the other end of which is connected to the negative electrode of the power input port;

[0011] The first power supply module is configured to discharge when the first signal terminal is at a high level within a first time period;

[0012] The second power supply module is configured to discharge when the time when the first signal terminal is at a high level exceeds a first time period.

[0013] Furthermore, the first power supply module includes an energy storage circuit;

[0014] The energy storage circuit is configured to be charged by using the power signal received from the power terminal when the first signal terminal has a low level;

[0015] The energy storage circuit is further configured to discharge when the first signal terminal is at a high level within the first time period.

[0016] As a specific implementation manner, when the discharging time of the energy storage circuit reaches the first time period, the voltage difference between the positive electrode of the power input port and the negative electrode of the power input port is equal to the minimum operating voltage;

[0017] The minimum operating voltage is the minimum voltage at which the functional unit operates normally.

[0018] As a specific implementation method,

[0019] The second power supply module includes a power supply circuit and a first power supply control circuit connected in series;

[0020] The first power supply control circuit is in a cut-off state when the first signal terminal is at a low level or the first signal terminal is at a high level within the first time period;

[0021] The first power supply control circuit is in an on state when the time when the first signal terminal is at a high level exceeds the first time period.

[0022] As a specific embodiment, the first power supply control circuit includes a unidirectional conducting element; the input end of the unidirectional conducting element is connected to the power supply circuit, and the output end is connected to the positive pole of the power input port, and is used to be in a reverse cutoff state when there is a low level at the first signal terminal or the time when the first signal terminal is at a high level is within a first time period, and is also used to be in a forward conducting state when the time when the first signal terminal is at a high level exceeds the first time period.

[0023] As a specific implementation, the second power supply module further includes at least one controlled switch connected in series to the second power supply module; a controlled end of the controlled switch is connected to the first signal terminal, and is configured to be turned on or off under the control of the first signal terminal.

[0024] As a specific implementation, the first signal terminal includes a chip select terminal; the chip select terminal is connected to the controlled end of the controlled switch to control the controlled switch to be turned on or off.

[0025] As a specific implementation manner, the first signal terminal includes a data terminal, a clock terminal and a chip select terminal; the data terminal, the clock terminal and the chip select terminal are at a high level simultaneously once or multiple times;

[0026] The times when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for multiple times are not all equal, and the longest time when they are simultaneously at high levels is longer than the first time period, or the times when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for multiple times are equal, and the time when they are simultaneously at high levels is longer than the first time period, or the time when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for a single time is longer than the first time period.

[0027] An embodiment of the present application also provides a consumables box, comprising the consumables chip described in any one of the first aspects.

[0028] An embodiment of the present application further provides an imaging device, comprising the consumables box described in the second aspect.

[0029] The consumable chip, consumable box, and imaging device of the embodiments of the present application have at least the following beneficial effects:

[0030] This application can achieve battery power supply only at certain times when the chip select signal, clock signal, and data signal are all at a high level, thereby reducing the capacity of the battery on the consumable chip. While not including a ground terminal electrically connected to the ground contact pin of the printing device, it can also maintain a long-term voltage difference between the negative and positive poles of the power input port to enable normal operation. In addition, when using battery power, it can avoid unnecessary premature discharge of the battery. In addition, it can also reduce the static power consumption of the battery in the consumable chip and increase the service life of the consumable chip.

[0031] Specifically, when there is a low level at the first signal terminal of the consumable chip, the voltage difference between the high-level power supply voltage received at the positive pole of the power input port and the low level is used to provide a voltage difference greater than or equal to the minimum operating voltage for the positive pole of the power input port and the negative pole of the power input port; and when the time when the first signal terminal is at a high level is within a first time period, the first power supply module is used to provide a voltage difference greater than or equal to the minimum operating voltage for the positive pole of the power input port and the negative pole of the power input port; and when the time when the first signal terminal is at a high level exceeds the first time period, the second power supply module is used to provide a voltage difference greater than or equal to the minimum operating voltage for the positive pole of the power input port and the negative pole of the power input port, so that the consumable chip does not need to be set with a ground terminal and can work normally, solving the problem in the prior art that the consumable chip is positionally offset compared to the contact pin, resulting in unstable contact between the ground terminal and the imaging device, and the consumable chip cannot be grounded or the grounding is unstable. At the same time, when the time when the first signal terminal is at a high level is within a first time period, the first energy storage element in the first power supply module is used to discharge, and when it exceeds the first time period, the battery in the second power supply module is used to discharge, so that the first energy storage element can be a small-capacity energy storage element, thereby improving the charging speed of the first energy storage element and facilitating the consumable chip to quickly enter the working state; the second power supply module adopts a unidirectional conductive element so that the battery is discharged only when the time when the first signal terminal is at a high level exceeds the first time period. Compared with the instant discharge of the battery when the first signal terminal is at a high level, the capacity of the battery on the consumable chip can be reduced, avoiding unnecessary premature discharge of the battery, and extending the service life of the consumable chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A communication structure diagram of a printing device and a consumable chip in the prior art;

[0033] Figure 2 A schematic diagram of a stylus holder of a printing device;

[0034] Figure 3 An enlarged view of a first stylus on a stylus holder of a printing device;

[0035] Figure 4 A schematic diagram of a consumable chip in the prior art.

[0036] Figure 5 Schematic diagram of a consumables box in the prior art.

[0037] Figure 6 This is a schematic diagram of the consumable chip of this application.

[0038] Figure 7 This is the communication timing diagram of the consumable chip of this application.

[0039] Figure 8 This is a schematic diagram of a circuit structure of Example 1 of the present application.

[0040] Figure 9 This is a schematic diagram of another circuit structure of Example 1 of the present application.

[0041] Figure 10 This is a schematic diagram of a circuit structure of Example 2 of the present application.

[0042] Figure 11 This is a schematic diagram of another circuit structure of Example 2 of the present application.

[0043] Figure 12 This is a schematic diagram of a circuit structure of Example 3 of the present application.

[0044] Figure 13 This is a structural diagram of another circuit structure of Example 3 of the present application.

[0045] The accompanying drawings in the specific implementation manner are as follows:

[0046] 1-printing device, 10-communication port, 11-stylus holder, 111-upper end face of stylus holder, 112-front end face of stylus holder,

[0047] 1101 - first contact pin, 1102 - second contact pin, 1103 - third contact pin, 1104 - fourth contact pin, 1105 - fifth contact pin,

[0048] 2-consumables box, 20-interface module, 21'-consumables chip of the prior art, 201-upper surface of the consumables box, 202-front surface of the consumables box,

[0049] 21-consumable chips,

[0050] 210- first substrate,

[0051] 2101-first plane, 21011-first signal terminal, data terminal, 21012-second terminal, chip select terminal, 21013-third terminal, clock terminal, 21014-fourth terminal, power terminal,

[0052] 21021-first device, 211-energy storage circuit, 212-power supply circuit, 214-functional unit, 2141-positive pole of power input port, 2142-negative pole of power input port,

[0053] 215 - first power supply control circuit, 216 - second power supply control circuit, 217 - third power supply control circuit. DETAILED DESCRIPTION

[0054] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0055] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0056] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0057] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0058] See also Figure 1 In the prior art, a communication port 10 is provided on the printing device 1, and an interface module 20 is provided on the prior art chip 21'. A communication link is established between the communication port 10 and the interface module 20. The printing device 1 and Figure 5 The prior art consumable chip 21' on the consumable box 2 can transmit information through a communication link. For example, during the imaging process, the prior art consumable chip 21' is used to provide identity recognition information and recording material (such as ink cartridges or toner) usage status information. When the printing device 1 sends a signal to the prior art consumable chip 21', the printing device 1 is the sender and the prior art consumable chip 21' is the receiver; and when the prior art consumable chip 21' sends a signal to the printing device 1, the prior art consumable chip 21' is the sender and the printing device 1 is the receiver. The information transmission process between the printing device 1 and the prior art consumable chip 21' is achieved by physical electrical contact between the contact pins on the printing device 1 and the contact parts of the terminals of the prior art consumable chip 21'.

[0059] like Figure 2As shown, the printing device 1 includes a stylus holder 11, which includes an upper end surface 111 of the stylus holder in the direction of the Y-axis arrow, a front end surface 112 of the stylus holder in the direction of the X-axis arrow, and a first stylus 1101, a second stylus 1102, a third stylus 1103, a fourth stylus 1104, and a fifth stylus 1105 staggered along the Z-axis. Specifically, the first stylus 1101, the second stylus 1102, the third stylus 1103, the fourth stylus 1104, and the fifth stylus 1105 are respectively a data stylus, a chip select stylus (also called a reset stylus), a clock stylus, a power supply stylus, and a ground stylus, which are respectively connected to the Z-axis. Figure 4 The consumable chip 21 ′ of the prior art includes a data contact portion SDA, a chip select contact portion RST (also called a reset contact portion), a clock contact portion SCL, a power contact portion VCC, and a ground contact portion GND.

[0060] The printing device 1 sends a data signal to the consumable chip 21' of the prior art through the data contact part SDA, the printing device 1 sends a chip select signal to the consumable chip 21' of the prior art through the chip select contact part RST, the printing device 1 sends a periodic low-level and high-level alternating and repeated clock signal to the consumable chip 21' of the prior art through the clock contact part SCL, the printing device 1 provides an operating voltage for the consumable chip 21' of the prior art through the power contact part VCC, and the printing device 1 provides a unified reference low level for receiving and sending data between the printing device 1 and the consumable chip 21' of the prior art through the ground contact part GND, thereby ensuring the correctness and stability of the communication process.

[0061] like Figure 3 As shown, the first stylus 1101 includes a first stylus top 11011, a first stylus front end 11012, a first stylus oblique end 11013, and a first stylus tip 11014, all of which can form contact with the contact portion of the terminal on the consumable chip to form an electrical connection. In this way, the consumable chip of the consumable box can communicate with the printing device through the stylus. In the prior art, the first stylus 1101, the second stylus 1102, the third stylus 1103, the fourth stylus 1104, and the fifth stylus 1105 are all connected to the terminal through the stylus tips. Figure 4 The planar terminals of the consumable chip shown are connected to a data contact SDA, a chip select contact RST, a clock contact SCL, a power contact VCC, and a ground contact GND. Each contact is connected to a first device on the consumable chip to enable data transmission and storage. The first device includes a storage unit and a control unit.

[0062] In the prior art, the consumable box is detachably mounted on the carriage. During the process of the printing device 1 driving the carriage to move back and forth, the detachable connection relationship may be unstable, resulting in the possibility of displacement between the position of the consumable chip 21' and the contact pin in the carriage. When the position between the consumable chip 21' and the contact pin is offset, the ground contact portion GND on the consumable chip 21' may not be able to contact the ground contact pin for grounding, resulting in the consumable chip being unable to be grounded or being unstable in grounding. In order to solve this problem, there is a prior art that improves the above-mentioned consumable chip: the consumable chip does not include a ground contact portion. When the chip select signal, clock signal, and data signal are simultaneously in a high-level state, a voltage difference is formed by connecting a capacitor or battery in parallel between the positive and negative poles of the power input port, so that the consumable chip can work normally even when there is no ground terminal electrically connected to the printing device.

[0063] However, the charge generated by the capacitor when using only the prior art solution is not enough to maintain the voltage difference for a long time; in addition, when using only batteries, the required battery capacity may be too large; in addition, when using batteries for power supply, the batteries are often discharged unnecessarily in advance; in addition, when the printing device is on standby, the battery is still discharged to the outside, which will generate static consumption and is not conducive to the service life of the consumable chip.

[0064] Example 1

[0065] See also Figure 6 , which is a structural schematic diagram of a consumable chip 21 provided in an embodiment of the present invention. The consumable chip 21 is installed on a consumable box, and the consumable box is detachably installed on the imaging device. The consumable box can be an ink cartridge filled with ink or a toner cartridge filled with toner, and the ink and toner are recording materials. The imaging device includes a printing device, a copying device, a fax device, etc., which is used to image the information to be imaged onto a recording medium such as paper through a recording material. The consumable chip 21 is used to control the authentication and data matching between the consumable box and the imaging device, and to provide imaging auxiliary information during the imaging process. The imaging auxiliary information includes toner amount information, manufacturer information, serial number, etc.

[0066] See also Figure 6 The consumable chip 21 provided in the present application includes at least two signal terminals, and the at least two signal terminals are used to receive signals sent by the printing device; the consumable chip 21 includes a first substrate 210, and the first substrate 210 includes a first plane 2101 and a second plane ( Figure 6(not shown in the figure), the second plane and the first plane 2101 are located on opposite sides of the consumable chip 21; the first plane 2101 includes the at least two signal terminals mentioned above; specifically, the signal terminals on the consumable chip 21 include a data terminal 21011, a chip select terminal 21012 (also called a reset terminal), a clock terminal 21013, and a power terminal 21014, which are electrically connected to the data contact pin, chip select contact pin, clock contact pin, and power contact pin of the printing device, respectively. The consumable chip 21 does not include a ground terminal electrically connected to the ground contact pin of the printing device, or the ground terminal is blocked by an electrically insulating component, or the ground terminal on the consumable chip is open to the ground pin on the consumable chip for transmitting the ground signal.

[0067] In this embodiment, no ground terminal is provided on the consumable chip 21, which can solve the problem in the prior art that the consumable chip is offset from the contact pin, resulting in unstable contact between the ground terminal and the imaging device, and the consumable chip cannot be grounded or the grounding is unstable.

[0068] In this application, the consumable chip 21 includes a functional unit 214, a unidirectional conduction module, a first power supply module, and a second power supply module. The functional unit 214 is electrically connected to the printing device to achieve communication. The functional unit 214 includes a positive power input port 2141, a negative power input port 2142, and a first device 21021. The positive power input port 2141 is connected to the power terminal 21014 for receiving a power signal VCC; the negative power input port 2142 is connected to the first signal terminal via the unidirectional conduction module. The first device 21021 is disposed on the second plane and is connected to the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 via wires. The first device 21021 receives data transmitted by the imaging device or sends data to the imaging device via the data terminal 21011, and receives the chip select signal and clock signal transmitted by the imaging device via the chip select terminal 21012 and the clock terminal 21013, respectively. The input end of the unidirectional conduction module is connected to the negative electrode 2142 of the power input port, and the output end is connected to the first signal terminal, and is used to pull the negative electrode 2142 of the power input port down to a low level when the first signal terminal is at a low level, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, wherein the minimum operating voltage is the minimum voltage when the first device 21021 is working normally, that is, the minimum voltage when the consumable chip 21 is working normally, so that the consumable chip 21 can work normally; the first power supply module and the second power supply module are connected in parallel; one end of the first power supply module is connected to the positive electrode 2141 of the power input port, and the other end is connected to the power input port The first power supply module is connected to the negative electrode 2142 of the power input port, and is used for discharging when the time when the first signal terminal is at a high level is within a first time period, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can work normally; one end of the second power supply module is connected to the positive electrode 2141 of the power input port, and the other end is connected to the negative electrode 2142 of the power input port, and is used for discharging when the time when the first signal terminal is at a high level exceeds the first time period, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can work normally.

[0069] In a specific embodiment, the first signal terminal includes a data terminal 21011, a chip select terminal 21012 and a clock terminal 21013; the presence of a low level at the first signal terminal means that at least one of the data terminal 21011, the chip select terminal 21012 and the clock terminal 21013 is at a low level.

[0070] In another specific embodiment, the first signal terminal includes two of the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013. For example, the first signal terminal includes the data terminal 21011 and the chip select terminal 21012, and the presence of a low level at the first signal terminal means that at least one of the data terminal 21011 and the chip select terminal 21012 is at a low level. For another example, the first signal terminal includes the data terminal 21011 and the clock terminal 21013, and the presence of a low level at the first signal terminal means that at least one of the data terminal 21011 and the clock terminal 21013 is at a low level. For another example, the first signal terminal includes the chip select terminal 21012 and the clock terminal 21013, and the presence of a low level at the first signal terminal means that at least one of the chip select terminal 21012 and the clock terminal 21013 is at a low level.

[0071] In another specific embodiment, the first signal terminal includes one of a data terminal 21011, a chip select terminal 21012, and a clock terminal 21013. For example, if the first signal terminal includes the data terminal 21011, a low level at the first signal terminal means that the data terminal 21011 is at a low level. For another example, if the first signal terminal includes the chip select terminal 21012, a low level at the first signal terminal means that the chip select terminal 21012 is at a low level. For another example, if the first signal terminal includes the clock terminal 21013, a low level at the first signal terminal means that the clock terminal 21013 is at a low level.

[0072] The first signal terminal provided in the present application does not include a power terminal and a ground terminal. Preferably, the first signal terminal includes a data terminal 21011, a chip select terminal 21012 and a clock terminal 21013. The present application does not limit the number of terminals included in the first signal terminal, and may include one or more. The consumable chip 21 provided in the present application connects the negative pole 2141 of the power input port to the first signal terminal through a unidirectional conduction module, and connects the first power supply module and the second power supply module in parallel between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port, so that the consumable chip 21 does not need to be provided with a ground terminal and can also work normally. Specifically, when the first signal terminal is at a low level, for example, at least one of the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 is at a low level, the unidirectional conduction module pulls the negative electrode 2142 of the power input port down to a low level, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can work normally; when the time when the first signal terminal is at a high level is within a first time period, for example, when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level is within the first time period, the first power supply module discharges, so that the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port are at a high level. The voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can work normally; when the time when the first signal terminal is at a high level exceeds the first time period, for example, when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level exceeds the first time period, the second power supply module discharges so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can work normally, even if the first signal terminals, such as the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013, maintain a high level for a long time at the same time, the first device 21021 can still work normally.

[0073] like Figure 9As shown, in a specific embodiment, the unidirectional conduction module includes diodes D1, D2 and D3, and the anodes of the diodes D1, D2 and D3 are all connected to the cathode 2142 of the power input port; the cathodes of the diodes D1, D2 and D3 are respectively connected to the data terminal 21011, the clock terminal 21013 and the chip select terminal 21012 in a one-to-one correspondence; wherein, when the data signal SDA received by the data terminal 21011 is at a low level, the diode D1 is forward-conducted, and the cathode 2142 of the power input port can be pulled down to a low level, and when the data signal SDA received by the data terminal 21011 is at a high level, the diode D1 is forward-conducted, and the cathode 2142 of the power input port can be pulled down to a low level, and when the data signal SDA received by the data terminal 21011 is at a high level Normally, the diode D1 is reverse-blocked; when the clock signal CLK received by the clock terminal 21013 is at a low level, the diode D2 is forward-conducted, which can pull the negative electrode 2142 of the power input port down to a low level, and when the clock signal CLK received by the clock terminal 21013 is at a high level, the diode D2 is reverse-blocked; when the chip select signal RST received by the chip select terminal 21012 is at a low level, the diode D3 is forward-conducted, which can pull the negative electrode 2142 of the power input port down to a low level, and when the chip select signal RST received by the chip select terminal 21012 is at a high level, the diode D3 is reverse-blocked.

[0074] In other specific embodiments, the unidirectional conduction module includes two diodes, for example, the unidirectional conduction module includes diodes D1 and D2, the positive poles of the diodes D1 and D2 are both connected to the negative pole 2142 of the power input port, and the negative poles are respectively connected to the data terminal 21011 and the clock terminal 21013; for another example, the unidirectional conduction module includes diodes D1 and D3, the positive poles of the diodes D1 and D3 are both connected to the negative pole 2142 of the power input port, and the negative poles are respectively connected to the data terminal 21011 and the chip select terminal 21012; for another example, the unidirectional conduction module includes diodes D2 and D3, the positive poles of the diodes D2 and D3 are both connected to the negative pole 2142 of the power input port, and the negative poles are respectively connected to the clock terminal 21013 and the chip select terminal 21012.

[0075] In other specific embodiments, the unidirectional conduction module includes only one diode. For example, the unidirectional conduction module includes a diode D1, with the anode of diode D1 connected to the cathode of the power input port 2142 and the cathode connected to the data terminal 21011. In another example, the unidirectional conduction module includes a diode D2, with the anode of diode D2 connected to the cathode of the power input port 2142 and the cathode connected to the clock terminal 21013. In another example, the unidirectional conduction module includes a diode D3, with the anode of diode D3 connected to the cathode of the power input port 2142 and the cathode connected to the chip select terminal 21012.

[0076] The negative electrode 2142 of the power input port of the consumable chip 21 provided in the present application uses three diodes D1, D2, and D3 to be connected to the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013, respectively, so that as long as one of the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 is at a low level, the negative electrode 2142 of the power input port can be pulled down to a low level, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, and the first device 21021 can operate normally without the need for the first power supply module and the second power supply module to discharge. Compared with the case where the negative electrode 2142 of the power input port is connected to only one terminal with one diode, or two terminals with two diodes, the probability of one of the three terminals being at a low level is greater, and accordingly, the probability of not needing the first power supply module and the second power supply module to discharge is greater, which can save the electric energy of the first power supply module and the second power supply module and extend the service life of the consumable chip 21.

[0077] In some cases, the first device 21021 may also be set on the first plane 2101.

[0078] like Figure 7 When any of the data signals SDA, RST, and CLK received from the printing device by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013, respectively, is at a low level (e.g., 0V), the diodes conduct in the forward direction and block in the reverse direction; the negative electrode 2142 of the power input port can receive a low level through the data terminal 21011, the chip select terminal 21012, or the clock terminal 21013 connected via diodes D1, D2, or D3. The power supply voltage VCC received by the positive electrode 2141 of the power input port is at a high level. As long as the voltage difference between the high-level power supply voltage VCC received by the positive electrode 2141 of the power input port and the low-level power supply voltage received by the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage of the consumable chip 21, the consumable chip 21 can operate normally without a ground terminal.

[0079] In a specific embodiment, D1, D2, or D3 uses a diode with a 0.2V voltage drop. When any of the data signal SDA, chip select signal RST, and clock signal CLK received by the data terminal 21011, chip select terminal 21012, and clock terminal 21013 from the printing device is at a low level (e.g., 0V), the voltage at the negative electrode 2142 of the power input port is 0.2V. Thus, the negative electrode 2142 of the power input port can serve as a virtual ground signal for the consumable chip 21. For example, if the power supply voltage VCC is 3.3V, i.e., the positive electrode 2141 of the power input port provides a voltage of 3.3V, the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is 3.1V, which is greater than the minimum operating voltage of the consumable chip 21 (e.g., 2.1V), allowing the consumable chip 21 to operate normally.

[0080] Preferably, the diodes D1 , D2 and D3 are low voltage drop devices, such as 1N4148 diodes with a voltage drop of 0.2V.

[0081] In the embodiment provided by the present application, when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 respectively receive the data signal SDA, the chip select signal RST, and the clock signal CLK from the printing device and are simultaneously high, the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously high; according to the characteristics of the diode being forward conductive and reverse cutoff, the diodes D1, D2, and D3 are in a reverse cutoff state; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously high is within the first time period, the first power supply module discharges, so that the current between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is high. The voltage difference is greater than or equal to the voltage difference of the minimum operating voltage of the consumable chip 21, so that the consumable chip 21 can still work normally within the first time period when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level at the same time; when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level at the same time exceeds the first time period, the second power supply module is discharged so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally after the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level at the same time exceeds the first time period.

[0082] In some specific embodiments, the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high multiple times, and the time of each simultaneous high level is not equal; the shortest time and the longest time that the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high are recorded as tmin and tmax, respectively. When the first power supply module and the second power supply module are applied to the consumable chip 21, the following application scenarios are included:

[0083] Application scenario one: the data signal SDA, chip select signal RST, and clock signal CLK are all at high levels at the same time, that is, the shortest time tmin during which the data terminal 21011, the chip select terminal 21013, and the clock terminal 21013 are all at high levels at the same time is less than the first time period, and the maximum time tmax during which the data signal SDA, the chip select signal RST, and the clock signal CLK are all at high levels at the same time is less than or equal to the first time period; when the data signal SDA, the chip select signal RST, and the clock signal CLK are all at high levels at the same time for multiple times, the first power supply module is always used for discharge, so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so as to ensure that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at high levels at the same time for multiple times.

[0084] Application scenario two: the shortest time tmin during which the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously at a high level is less than the first time period, and the longest time tmax during which the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously at a high level is greater than the first time period; when the time during which the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously at a high level is greater than or equal to the shortest time tmin, and less than or equal to the first time period, the first power supply module discharges, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage; when the time during which the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously at a high level is greater than the first time period, and less than or equal to the longest time tmax, the second power supply module discharges, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously at a high level for multiple times.

[0085] Application scenario three: the shortest time tmin for the data signal SDA, the chip select signal RST, and the clock signal CLK to be high at the same time is equal to the first time period, and the longest time tmax for the data signal SDA, the chip select signal RST, and the clock signal CLK to be high at the same time is greater than the first time period; when the time for the data signal SDA, the chip select signal RST, and the clock signal CLK to be high at the same time is the shortest time tmin, the first power supply module discharges, so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage; when the time for the data signal SDA, the chip select signal RST, and the clock signal CLK to be high at the same time is greater than the shortest time tmin and less than or equal to the longest time tmax, the second power supply module discharges, so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, ensuring that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are high at the same time for multiple times.

[0086] Application scenario four: the shortest time tmin of the data signal SDA, the chip select signal RST, and the clock signal CLK being high at the same time is greater than the first time period, and the longest time tmax of the data signal SDA, the chip select signal RST, and the clock signal CLK being high at the same time is greater than the first time period; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are high at the same time is within the first time period, the first power supply module discharges, so that the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port are connected. The voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012 and the clock terminal 21013 are simultaneously at a high level for multiple times.

[0087] In other specific embodiments, the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high multiple times, and the time of each simultaneous high level is equal. When the first power supply module and the second power supply module are applied to the consumable chip 21, the following application scenarios are included:

[0088] Application scenario five: The time when the data signal SDA, chip select signal RST, and clock signal CLK are all high at the same time is less than or equal to the first time period. When the data signal SDA, chip select signal RST, and clock signal CLK are all high at the same time for multiple times, the first power supply module is always used for discharge, so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so as to ensure that the consumable chip 21 can still work normally when the data terminal 21011, chip select terminal 21012, and clock terminal 21013 are all high at the same time for multiple times.

[0089] Application scenario six: the time when the data signal SDA, the chip select signal RST, and the clock signal CLK are all high is greater than the first time period; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high is within the first time period, the first power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high exceeds the first time period, the second power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high for multiple times.

[0090] In some other specific embodiments, the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high only once. The first power supply module and the second power supply module are applied to the consumable chip 21 in the following application scenarios:

[0091] Application scenario seven: The time when the data signal SDA, chip select signal RST, and clock signal CLK are all high at the same time is less than or equal to the first time period. When the data signal SDA, chip select signal RST, and clock signal CLK are all high at the same time for multiple times, the first power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage to ensure that the consumable chip 21 can still work normally when the data terminal 21011, chip select terminal 21012, and clock terminal 21013 are all high at the same time for multiple times.

[0092] Application scenario eight: the time when the data signal SDA, the chip select signal RST, and the clock signal CLK are all high is greater than the first time period; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high is within the first time period, the first power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage; when the time when the signals received by the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high exceeds the first time period, the second power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high at the same time for multiple times.

[0093] like Figure 7 As shown, in a specific embodiment, the time when the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high is consistent with the time when the clock signal CLK is at a high level in one cycle (such as the time period t1 to t2, the time period t3 to t4); if the time when the clock signal CLK is at a high level in one cycle is less than or equal to the first time period, then when the data signal SDA, the chip select signal RST, and the clock signal CLK are simultaneously high, the first power supply module is always discharged to make the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port greater than or equal to the minimum operating voltage; if the time when the clock signal CLK is at a high level in one cycle is greater than the first time period, then When the time when the data signal SDA, the chip select signal RST, and the clock signal CLK are all high levels is within the first time period, the first power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage; when the time when the data signal SDA, the chip select signal RST, and the clock signal CLK are all high levels exceeds the first time period, the second power supply module discharges so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, so that the consumable chip 21 can still work normally when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all high levels.

[0094] like Figure 8In a specific embodiment, the first power supply module includes an energy storage circuit 211. The two ends of the energy storage circuit 211 are respectively connected to the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port, and are used to charge using the power supply voltage VCC received from the positive electrode 2141 of the power input port when the first signal terminal is at a low level, such as when at least one of the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 is at a low level; the energy storage circuit 211 is also used to discharge when the first signal terminal is at a high level and the time of the high level is within a first time period, such as when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level at the same time within the first time period, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage, ensuring that when the time of the first signal terminal being at a high level is within the first time period, the consumable chip 21 can still operate normally. The working principle of the first power supply module is as follows:

[0095] Charging process: When the first signal terminal has a low level, for example, when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 receive the data signal SDA, the chip select signal RST, and the clock signal CLK from the printing device respectively, any one of the three signals is low (for example, 0V), the diode corresponding to the low level signal is turned on; the energy storage circuit 211 and the functional unit 214 form a circuit loop; the positive electrode 2141 of the power input port receives the power supply voltage VCC, for example, 3.3V, Figure 8 The voltage at point A in the middle; the energy storage circuit 211 is charged with the power supply voltage VCC; the current flowing through the first device 21021 will be accumulated at the negative electrode 2142 of the power input port, and then released through any low-level terminal of the chip select terminal 21012, the data terminal 21011 or the clock terminal 21013; since the diode is forward-conducting, that is, the diode D1 or the diode D2 or the diode D3 provides a voltage drop of 0.2V when forward-conducting, the voltage at the negative electrode 2142 of the power input port can be released to 0.2V; the voltage difference between the negative electrode 2142 of the power input port and the positive electrode 2141 of the power input port (connected to the power terminal 21014, for example, 3.3V) is 3.1V, which is greater than the minimum operating voltage of the consumable chip 21 (for example, 2.1V), and the consumable chip 21 works normally;

[0096] Discharge process: When the first signal terminal is at a high level, such as the chip select signal RST, the clock signal CLK, and the data signal SDA are all at a high level at the same time, the diodes D1, D2, and D3 are all reverse cutoff; the negative electrode 2142 of the power input port can no longer release the current flowing through the first device 21021 through the diodes D1, D2, and D3, and the positive charges brought by these currents will accumulate at the negative electrode 2142 of the power input port. The voltage of the negative electrode 2142 of the power input port will increase as the consumable chip 21 continues to work. Since the voltage of the positive electrode 2141 of the power input port remains at the power supply voltage VCC (for example, 3.3V), the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port decreases accordingly. This process can be understood as the energy storage circuit 211 discharging; if the energy storage circuit 211 discharges to the point where the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is less than the minimum operating voltage, the first power supply module will not be able to meet the normal operation of the consumable chip 21. For example, if the consumable chip 21 is only powered by the first power supply module, after a certain period of time, the voltage of the negative pole 2142 of the power input port increases from 0.2V to 1.3V, then the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is 2V, which cannot meet the minimum voltage (for example, 2.1V) when the consumable chip is working normally.

[0097] To ensure the normal operation of the consumable chip 21, it is necessary to ensure that when the discharge time of the energy storage circuit 211 reaches the first time period, that is, when the time when the first signal terminal is at a high level reaches the first time period, the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port is greater than or equal to the minimum operating voltage. Accordingly, when the time when the first signal terminal is at a high level is within the first time period, the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port must be greater than or equal to the minimum operating voltage, and the consumable chip 21 can operate normally. When the time when the first signal terminal is at a high level exceeds the first time period, the second power supply module can discharge the power, so that the voltage difference between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port continues to be greater than or equal to the minimum operating voltage; that is, when the time when the first signal terminal is at a high level for a long time, the first power supply module and the second power supply module discharge the power in sequence, thereby ensuring the normal operation of the consumable chip 21.

[0098] In some specific embodiments, when the time when the first signal terminal is at a high level reaches a first time period, for example, when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously at a high level reaches a first time period, the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is equal to the minimum operating voltage, and the electric energy stored in the energy storage circuit 211 during the charging process can be reasonably utilized.

[0099] like Figure 9 In a specific embodiment, the energy storage circuit 211 includes a first energy storage element; the first energy storage element includes a first capacitor C1, the positive terminal of the first capacitor C1 being connected to the positive electrode 2141 of the power input port, and the negative terminal being connected to the negative electrode 2142 of the power input port. In order to slow down the voltage rise rate at the negative electrode 2142 of the power input port, that is, to extend the time during which the first power supply module provides a voltage difference greater than or equal to the minimum operating voltage between the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port, one method is to increase the capacitance of the first capacitor C1 in the energy storage circuit 211, so that the energy storage circuit 211 can retain more electrical energy (that is, the value of the first time period is related to the capacitance value of the first capacitor C1). However, this will result in a longer charging time for the first capacitor C1 in the energy storage circuit 211, resulting in a slow rise in the voltage of the power signal VCC of the printing device at the positive electrode 2141 of the power input port, which is likely to prevent the consumable chip 21 from quickly entering the working state, thereby being considered abnormal by the printing device.

[0100] It is understandable that the larger the capacitance value of the first capacitor C1, the more electrical energy the first capacitor C1 can store when charging, and the longer the discharge time. Accordingly, the larger the value of the first time period, the longer the first power supply module provides electrical energy; the larger the capacitance value of the first capacitor C1, the more electrical energy the first capacitor C1 can store when charging, and the longer the charging time will be, which may cause the consumable chip 21 to be unable to quickly enter the working state, thereby being considered abnormal by the printing device, and a capacitor with too high a capacity cannot be set in the energy storage circuit 211. Those skilled in the art can set the capacitance value of the first capacitor C1 according to actual design requirements, as long as the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously high is within the first time, the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage, and it will not be considered abnormal by the printing device due to the long charging time. This application does not limit the specific capacitance value of the first capacitor C1.

[0101] In some embodiments, in order to increase the charging speed of the first capacitor C1 and enable the consumable chip 21 to quickly enter the working state, the first capacitor C1 is a small-capacity capacitor, preferably, the capacitor may have a capacitance value of 10 μF.

[0102] In other specific embodiments, the energy storage circuit 211 includes a plurality of capacitors connected in series or in parallel, or the energy storage circuit 211 includes a combination structure of at least one capacitor and at least one resistor. The present application does not limit the specific circuit structure of the energy storage circuit 211, and those skilled in the art can set the elements included in the energy storage circuit 211 and the connection method of each element according to the functional requirements of the energy storage circuit 211.

[0103] like Figure 8 As shown, in a specific embodiment, the second power supply module includes a power supply circuit 212 and a first power supply control circuit 215 connected in series; the anode of the first power supply control circuit 215 is connected to the positive pole of the second power supply module 212, and the cathode is connected to the positive pole 2141 of the power input port; the cathode of the second power supply module 212 is connected to the negative pole 2142 of the power input port; wherein, when the first signal terminal has a low level or the time when the first signal terminal is a high level is within a first time period, the first power supply control circuit 215 is in an off state; when the time when the first signal terminal is a high level exceeds the first time period, the first power supply control circuit 215 changes from an off state to an on state, and the power supply circuit 212 is discharged, so that the voltage difference between the positive pole 2141 of the power input port and the negative pole 2142 of the power input port is greater than or equal to the minimum operating voltage.

[0104] In some specific embodiments, the first power supply control circuit 215 includes a unidirectional conductive element; the input end of the unidirectional conductive element is connected to the power supply circuit 212, and the output end is connected to the positive pole 2141 of the power input port; the unidirectional conductive element is in a reverse cutoff state when the first signal terminal has a low level or the time when the first signal terminal is a high level is within a first time period; the unidirectional conductive element is in a forward conductive state when the time when the first signal terminal is a high level exceeds the first time period.

[0105] In a specific embodiment, the on-state voltage of the unidirectional conductive element is recorded as U4, the voltage provided by the power supply circuit 212 is recorded as UBA, and the minimum operating voltage is recorded as Umin; when the time when the first signal terminal is at a high level reaches the first time period, the voltage of the negative electrode 2142 of the power input port is recorded as U-; the on-state voltage U4 of the unidirectional conductive element and the voltage difference UBA between the positive and negative electrodes of the second energy storage element satisfy: U4 = (UBA + U-) - VCC, where VCC - U- = Umin, and U4 = UBA - Umin.

[0106] In an embodiment of the present application, on the one hand, the unidirectional conducting element is turned on when the time when the first signal terminal is at a high level exceeds a first time period. For example, the unidirectional conducting element is turned on when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously at a high level exceeds a first time period, so that the second power supply module only supplies power when the first power supply module is discharged and the power supply is insufficient, thereby delaying the power supply time of the power supply circuit 212, avoiding premature discharge of the power supply circuit 212, extending the service life of the power supply circuit 212, and thereby extending the service life of the consumable chip 21; on the other hand, the unidirectional conducting element is also used to prevent current backflow, avoid reverse charging of the power supply circuit 212 by the power signal VCC and the first power supply module, and protect the power supply circuit 212.

[0107] like Figure 9 As shown, in a specific embodiment, the power supply circuit 212 includes a second energy storage element; the second energy storage element includes a battery BA; the unidirectional conductive element includes a diode D4; the cathode of the diode D4 is connected to the positive electrode 2141 of the power input port, the anode is connected to the positive electrode of the battery BA, and the cathode of the battery BA is connected to the negative electrode 2142 of the power input port. The threshold voltage (conduction voltage) of the diode D4 can be 0.2V or higher. If the external voltage received by the power terminal 21014 is 3.3V, the voltage of the node A of the energy storage circuit 211 is 3.3V, and the voltage of the battery BA in the power supply circuit 212 is 3V, and the negative end of the power supply circuit 212 is not connected to the loop, that is, when at least one of the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 is at a low level or the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level within the first time period, the voltage of the node C is also 3V. Since the voltage difference between the node C and the node A does not exceed the threshold voltage of the diode D4, the diode D4 is cut off, preventing the power supply circuit 212 from discharging prematurely. When the negative end of the power supply circuit 212 is connected to the loop, that is, the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are all at a high level exceeds the first time period, the signal at node B is connected to the power supply circuit 212. When the chip select signal RST, the clock signal CLK, and the data signal SDA are all at a high level at the same time, the diodes D1, D2, and D3 are all reverse cutoff. The voltage at the negative pole 2142 of the power input port, that is, at node B, will continue to increase as the consumable chip 21 works. For example, after a certain period of time, it will increase from 0.2V to 0.5V. At this time, the voltage at node C is no longer the voltage of battery BA, but the voltage at node B plus the voltage of battery BA itself, that is, 3.5V. At this time, the voltage difference between node C and node A reaches the threshold voltage of diode D4, and diode D4 is turned on, so that the power supply circuit 212 starts to discharge through diode D4.

[0108] Thus, the diode D4 in the first power supply control circuit 215 can delay the discharge of the battery BA in the power supply circuit 212, starting discharge at 0.3V at node B and delaying discharge until node B rises to 0.5V. This prevents the power supply circuit 212 from discharging when the first signal terminal is briefly high, such as when the chip select signal RST, the clock signal CLK, and the data signal SDA are briefly high simultaneously, thereby extending the service life of the consumable chip 21. Obviously, if the minimum operating voltage of the consumable chip 21 is low, the number of diodes in the first power supply control circuit 215 can be increased, or diodes with higher threshold voltages can be selected. For example, if the minimum operating voltage of the consumable chip 21 is 2.1V, then the consumable chip 21 will not function until the corresponding maximum voltage at node B is 3.3-2.1=1.2V. In this case, the number of diodes in the first power supply control circuit 215 can be increased to two, three, or even six connected in series, thereby prioritizing the use of energy in the energy storage circuit 211 and reducing discharge in the power supply circuit 212.

[0109] In one specific embodiment, battery BA may be composed of two button cells connected in series. In other embodiments, battery BA may include one or more button cells connected in series, or battery BA may include a miniature lithium battery, or battery BA may include a thin-film battery. This application does not limit the type of battery BA, and those skilled in the art may configure battery BA based on actual power supply requirements.

[0110] In other specific embodiments, the unidirectional conducting element may be a series structure of multiple diodes, a combination of diodes and MOS transistors, or a combination of MOS transistors, as long as it can achieve forward conduction when the time when the data terminal 21011, the chip select terminal 21012, and the clock terminal 21013 are simultaneously at a high level exceeds the first time period, and reverse conduction at other times. This application does not limit the specific structure of the unidirectional conducting element.

[0111] In the present application, when the first signal terminal is at a high level for a long time, for example, when the chip select signal RST, the clock signal CLK, and the data signal SDA are all at a high level for a long time, the power supply circuit 212 participates in the loop to discharge to the outside, which takes into account the normal operation of the consumable chip 21 and extends the service life of the consumable chip 21.

[0112] The consumable chip 21 provided in the present application uses the voltage difference between the high-level power supply voltage VCC received by the positive electrode 2141 of the power input port and the low level to provide a voltage difference greater than or equal to the minimum operating voltage for the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port when the first signal terminal has a low level; and when the time when the first signal terminal is at a high level is within a first time period, the first power supply module is used to provide a voltage difference greater than or equal to the minimum operating voltage for the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port; and when the time when the first signal terminal is at a high level exceeds the first time period, the second power supply module is used to provide a voltage difference greater than or equal to the minimum operating voltage for the positive electrode 2141 of the power input port and the negative electrode 2142 of the power input port; the consumable chip 21 does not need to be provided with a ground terminal and can also work normally, which can solve the problem in the prior art that the consumable chip is offset from the contact pin, resulting in unstable contact between the ground terminal and the imaging device, and the consumable chip cannot be grounded or the grounding is unstable. At the same time, the consumable chip 21 provided in the present application utilizes the first energy storage element C1 in the first power supply module to discharge when the time when the first signal terminal is at a high level is within the first time period, and utilizes the battery BA in the second power supply module to discharge when the time exceeds the first time period, so that the first energy storage element C1 can be a small-capacity energy storage element, thereby increasing the charging speed of the first energy storage element C1 and facilitating the consumable chip 21 to quickly enter the working state. In addition, the second power supply module uses a unidirectional conductive element so that the battery BA is discharged only when the time when the first signal terminal is at a high level exceeds the first time period. Compared with the battery BA discharging immediately when the first signal terminal is at a high level, the capacity of the battery on the consumable chip 21 can be reduced, and the battery BA can be prevented from being discharged unnecessarily in advance, thereby extending the service life of the consumable chip 21.

[0113] In the present application, the first device 21021 may specifically include a control unit and a storage unit. The storage unit may be a common non-volatile storage unit, such as an EPROM, EEPROM, FLASH, ferroelectric storage unit, phase change storage unit, etc., or a volatile storage unit plus a power supply, such as an SRAM plus a battery or capacitor, or a DRAM plus a battery or capacitor. The control unit is used to control the communication between the consumable chip 21 and the printing device, and the printing device reads information from and stores information to the first device 21021. The control unit may specifically be a single-chip microcomputer (MCU), a microcontroller, an FPGA, an ASIC, etc. The type of components of the first device 21021 can be selected according to actual needs and is not limited here.

[0114] An embodiment of the present invention further provides a consumables box, comprising the consumables chip in any of the above embodiments.

[0115] An embodiment of the present invention further provides an imaging device including the above-mentioned consumables box.

[0116] Example 2

[0117] The difference between this embodiment and the first embodiment is that the second power supply module further includes a controlled switch connected in series to the second power supply module; the controlled end of the controlled switch is connected to the first signal terminal and is used to be turned on or off under the control of the first signal terminal.

[0118] Preferably, the control terminal of the controlled switch is connected to a chip select terminal among the first signal terminals, and is configured to be turned on or off under the control of the chip select terminal. Specifically, when the chip select terminal is at a high level, the controlled switch is in an on state, and when the chip select terminal is at a low level, the controlled switch is in an off state. This prevents the second power supply module from supplying power when the printing device is in a standby state, thereby reducing static power consumption of the power supply circuit 212, extending the power supply time of the power supply circuit 212, and increasing the lifespan of the consumable chip.

[0119] In other embodiments, the control terminal of the controlled switch is connected to a data terminal in the first signal terminal, and is configured to be turned on or off under the control of the data terminal. Specifically, when the data terminal is at a high level, the controlled switch is in the on state, and when the data terminal is at a low level, the controlled switch is in the off state. This allows the unidirectional conduction module to pull the negative electrode 2142 of the power input port to a low level, and the second power supply module will not supply power when it is not needed, thereby reducing the static loss of the power supply circuit 212 and extending the service life of the consumable chip 21.

[0120] In other embodiments, the control terminal of the controlled switch is connected to a clock terminal in the first signal terminal, and is configured to be turned on or off under the control of the clock terminal. Specifically, when the clock terminal is at a high level, the controlled switch is in the on state, and when the clock terminal is at a low level, the controlled switch is in the off state. This allows the unidirectional conduction module to pull the negative electrode 2142 of the power input port to a low level, and the second power supply module will not supply power when it does not need to, thereby reducing the static loss of the power supply circuit 212 and extending the service life of the consumable chip 21.

[0121] like Figure 10 As shown, the controlled switch includes a second power supply control circuit 216. In one specific embodiment, the second power supply control circuit 216 includes a MOS transistor structure, which is controlled to be turned on or off by a chip select terminal. In other specific embodiments, the second power supply control circuit 216 may also be a transmission gate, a tri-state gate, or a transistor, which can be turned on or off under the control of a certain signal.

[0122] like Figure 11As shown, in a specific embodiment, the NMOS transistor structure of the second power supply control circuit 216 includes a first field effect transistor Q1. Preferably, the first field effect transistor Q1 is an NMOS transistor, with its source connected to the negative electrode 2142 of the power input port, its drain connected to the negative electrode of the battery BA, and its gate connected to the chip select terminal 21012. In other words, the control terminal of the second power supply control circuit 216 is controlled by the chip select signal RST and can be used to control the on and off states of the power supply circuit 212, that is, to control the on and off states of the second power supply module. When the chip select signal RST received by the chip select terminal 21012 from the printing device is at a high level, the first field effect transistor Q1 is turned on, and the power supply circuit 212 can provide power to the energy storage circuit 211 or the first device 21021 of the functional unit 214. This solves the problem of the battery BA still charging the energy storage circuit 211 or discharging it through the power terminal 21014 when the printing device is in standby mode, avoids static power consumption, extends the power supply time of the battery BA, and increases the life of the consumable chip 21.

[0123] In other embodiments, the NMOS transistor structure of the second power supply control circuit 216 includes multiple NMOS transistors, such as a series structure of multiple NMOS transistors, a parallel structure of multiple NMOS transistors, or a series-parallel structure of multiple NMOS transistors, as long as the NMOS transistors are in an on state when the corresponding controlled first signal terminal is at a high level and in an off state when the corresponding controlled first signal terminal is at a low level. This application does not limit the specific structure of the NMOS transistor structure in the second power supply control circuit 216.

[0124] In other embodiments, the second power supply control circuit 216 may also be provided between the energy storage circuit 211 and the first power supply control circuit 215 , or between the first power supply control circuit 215 and the power supply circuit 212 , which can also achieve the same effect.

[0125] In other embodiments, the second power supply control circuit 216 can also be controlled to be turned on or off by other terminals, such as the data terminal 21011 or the clock terminal 21013. For example, the data terminal 21011 is connected to the gate of the first field effect transistor Q1. When the data terminal 21011 receives a high-level signal from the printing device, the first field effect transistor Q1 is turned on; when the data terminal 21011 receives a low-level signal from the printing device, the first field effect transistor Q1 is turned off. For another example, the clock terminal 21013 is connected to the gate of the first field effect transistor Q1. When the clock terminal 21013 receives a high-level signal from the printing device, the first field effect transistor Q1 is turned on; when the clock terminal 21013 receives a low-level signal from the printing device, the first field effect transistor Q1 is turned off.

[0126] The first device 21021 may specifically include a control unit and a storage unit. The storage unit may be a common non-volatile storage unit, such as an EPROM, EEPROM, FLASH, ferroelectric memory cell, phase change memory cell, etc., or a volatile storage unit plus a power supply, such as an SRAM plus a battery or capacitor, or a DRAM plus a battery or capacitor. The control unit is used to control communication between the consumable chip and the printing device, and the printing device reads information from and stores information to the first device. The control unit may specifically be a single-chip microcomputer (MCU), a microcontroller, an FPGA, an ASIC, etc. The type of components of the first device can be selected according to actual needs and is not limited here.

[0127] An embodiment of the present application also provides a consumables box, comprising the consumables chip of any of the above embodiments.

[0128] An embodiment of the present application further provides an imaging device, comprising the above-mentioned consumables box.

[0129] Example 3

[0130] This embodiment differs from Example 2 in that the second power supply module includes two controlled switches connected in series. The controlled ends of the two controlled switches are connected to the first signal terminal and are turned on or off under the control of the first signal terminal. Compared to Example 2, the two controlled switches further enhance current cutoff capability, further reduce static losses in the power supply circuit 212, extend the power supply time of the power supply circuit 212, and increase the lifespan of the consumable chip.

[0131] In one specific embodiment, the control terminals of both controlled switches are connected to a chip select terminal among the first signal terminals, and are configured to be turned on or off under the control of the chip select terminal. Specifically, when the chip select terminal is at a high level, the controlled switches are in an on state, and when the chip select terminal is at a low level, the controlled switches are in an off state. This prevents the second power supply module from supplying power when the printing device is in standby mode, thereby reducing static losses in the power supply circuit 212 and extending the service life of the consumable chip 21.

[0132] In other embodiments, the control terminal of one controlled switch is connected to the chip select terminal, and the other is connected to the data terminal; or the control terminal of one controlled switch is connected to the chip select terminal, and the control terminal of the other controlled switch is connected to the clock terminal. Figure 12As shown, the two controlled switches include a second power supply control circuit 216 and a third power supply control circuit 217. The structure and function of the second power supply control circuit 216 have been described in Example 2 and will not be repeated here. The third power supply control circuit 217 includes a MOS transistor structure, which is controlled to be turned on or off by a chip select terminal. In other specific embodiments, the second power supply control circuit 216 may also utilize a transmission gate, a tri-state gate, or a transistor, which can be turned on or off under certain signal control.

[0133] like Figure 13 As shown, in a specific embodiment, the MOS transistor structure of the third power supply control circuit 217 includes a second field effect transistor Q2. Preferably, the second field effect transistor is an NMOS transistor, whose drain is connected to the positive electrode 2141 of the power input port, the source is connected to the diode D4, and the gate is connected to the chip select terminal 21012. In other words, the control end of the third power supply control circuit 216 is controlled by the chip select signal RST. When the chip select terminal 21012 receives the chip select signal RST from the printing device and is at a high level, the second field effect transistor Q2 is turned on, and the power supply circuit 212 provides power to the energy storage circuit 211 or the first device of the functional unit 214. Compared with Example 2, the addition of the second field effect transistor Q2 can further enhance the current cutoff capability, reduce the probability of static power consumption, extend the power supply time of the battery BA, that is, the power supply circuit 212, and increase the life of the consumable chip 21.

[0134] In other embodiments, the NMOS transistor structure of the third power supply control circuit 217 includes multiple NMOS transistors, such as a series structure of multiple NMOS transistors, a parallel structure of multiple NMOS transistors, or a series-parallel structure of multiple NMOS transistors, as long as the NMOS transistors are in an on state when the corresponding first signal terminal is at a high level and in an off state when the first signal terminal is at a low level. This application does not limit the specific structure of the NMOS transistor structure in the third power supply control circuit 217.

[0135] In other embodiments, the third power supply control circuit 217 may also be disposed between the first power supply control circuit 215 and the power supply circuit 212 , thereby achieving the same effect.

[0136] In other embodiments, the third power supply control circuit 217 can also be controlled to be turned on or off by other first signal terminals. That is, the control terminal of the third power supply control circuit 217 is connected to other first signal terminals, such as the data terminal 21011 or the clock terminal 21013. For example, the data terminal 21011 is connected to the gate of the second field-effect transistor Q2. When the data terminal 21011 receives a high-level signal from the printing device, the second field-effect transistor Q2 is turned on; when the data terminal 21011 receives a low-level signal from the printing device, the second field-effect transistor Q2 is turned off. For another example, the clock terminal 21013 is connected to the gate of the second field-effect transistor Q2. When the clock terminal 21013 receives a high-level signal from the printing device, the second field-effect transistor Q2 is turned on; when the clock terminal 21013 receives a low-level signal from the printing device, the second field-effect transistor Q2 is turned off.

[0137] In other embodiments, the second power supply module includes a plurality of controlled switches connected in series to the second power supply module. Controlled ends of the plurality of controlled switches are connected to the first signal terminal and are turned on or off under the control of the first signal terminal.

[0138] Preferably, the second power supply module includes three controlled switches, the controlled end of the first controlled switch is connected to the chip select terminal, the controlled end of the second controlled switch is connected to the clock terminal, and the controlled end of the third controlled switch is connected to the data terminal, so that the second power supply module will not supply power when the printing device is in standby state, and the second power supply module will not supply power when the unidirectional conduction module can pull the negative pole 2142 of the power input port to a low level, further reducing the static loss of the power supply circuit 212, extending the power supply time of the power supply circuit 212, and increasing the life of the consumable chip.

[0139] The first device 21021 may specifically include a control unit and a storage unit. The storage unit may be a common non-volatile storage unit, such as an EPROM, EEPROM, FLASH, ferroelectric memory cell, phase change memory cell, etc., or a volatile storage unit plus a power supply, such as an SRAM plus a battery or capacitor, or a DRAM plus a battery or capacitor. The control unit is used to control communication between the consumable chip and the printing device, and the printing device reads information from and stores information to the first device. The control unit may specifically be a single-chip microcomputer (MCU), a microcontroller, an FPGA, an ASIC, etc. The type of components of the first device can be selected according to actual needs and is not limited here.

[0140] The consumable chip of the present application does not include a ground terminal electrically connected to the ground contact pin of the printing device, but can also maintain a long-term voltage difference between the negative pole 2141 of the power input port and the positive pole 2142 of the power input port, so that it can work normally; in addition, it can avoid unnecessary premature discharge of the battery BA; in addition, it can also reduce the static consumption of the battery BA in the consumable chip 21 and improve the service life of the consumable chip.

[0141] An embodiment of the present application also provides a consumables box, comprising the consumables chip of any of the above embodiments.

[0142] An embodiment of the present application further provides an imaging device, comprising the above-mentioned consumables box.

[0143] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A consumable chip, characterized in that: include: At least two signal terminals, including a power terminal and a first signal terminal; the first signal terminal does not include a ground terminal; The functional unit includes a positive electrode of a power input port and a negative electrode of a power input port; the positive electrode of the power input port is connected to the power terminal; the negative electrode of the power input port is connected to the first signal terminal via a unidirectional conduction module; A unidirectional conduction module, whose input end is connected to the negative electrode of the power input port, and whose output end is connected to the first signal terminal, is used to pull the negative electrode of the power input port down to a low level when the first signal terminal has a low level; A first power supply module and a second power supply module connected in parallel, one end of which is connected to the positive electrode of the power input port, and the other end of which is connected to the negative electrode of the power input port; The first power supply module is configured to discharge when the first signal terminal is at a high level within a first time period; The second power supply module is configured to discharge when the time when the first signal terminal is at a high level exceeds a first time period.

2. The consumable chip according to claim 1, characterized in that: The first power supply module includes an energy storage circuit; The energy storage circuit is configured to be charged by using the power signal received from the power terminal when the first signal terminal has a low level; The energy storage circuit is further configured to discharge when the first signal terminal is at a high level within the first time period.

3. The consumable chip according to claim 2, characterized in that: When the discharging time of the energy storage circuit reaches the first time period, the voltage difference between the positive electrode of the power input port and the negative electrode of the power input port is equal to the minimum operating voltage; The minimum operating voltage is the minimum voltage at which the functional unit operates normally.

4. The consumable chip according to claim 1, characterized in that: The second power supply module includes a power supply circuit and a first power supply control circuit connected in series; The first power supply control circuit is in a cut-off state when the first signal terminal is at a low level or the first signal terminal is at a high level within the first time period; The first power supply control circuit is in an on state when the time when the first signal terminal is at a high level exceeds the first time period.

5. The consumable chip according to claim 4, characterized in that: The first power supply control circuit includes a unidirectional conductive element; the input end of the unidirectional conductive element is connected to the power supply circuit, and the output end is connected to the positive pole of the power input port, and is used to be in a reverse cutoff state when the first signal terminal has a low level or the time when the first signal terminal is a high level is within a first time period, and is also used to be in a forward conductive state when the time when the first signal terminal is a high level exceeds the first time period.

6. The consumable chip according to claim 4, characterized in that: The second power supply module further includes at least one controlled switch connected in series to the second power supply module; a controlled end of the controlled switch is connected to the first signal terminal, and is configured to be turned on or off under the control of the first signal terminal.

7. The consumable chip according to claim 6, characterized in that: The first signal terminal includes a chip select terminal; the chip select terminal is connected to the controlled end of the controlled switch to control the controlled switch to be turned on or off.

8. The consumable chip according to any one of claims 1 to 7, characterized in that: The first signal terminal includes a data terminal, a clock terminal and a chip select terminal; the data terminal, the clock terminal and the chip select terminal are high level at one time or multiple times simultaneously; The times when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for multiple times are not all equal, and the longest time when they are simultaneously at high levels is longer than the first time period, or the times when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for multiple times are equal, and the time when they are simultaneously at high levels is longer than the first time period, or the time when the data terminal, clock terminal and chip select terminal are simultaneously at high levels for a single time is longer than the first time period.

9. A consumables box, characterized in that: The consumable chip comprises the consumable chip according to any one of claims 1 to 8.

10. An imaging device, characterized in that: Including the consumables box according to claim 9.

Images