Preparation method of flexible nano SOI substrate epitaxial antimonide material

Abstract

The invention discloses a preparation method of an epitaxial antimonide material of a flexible nano SOI (Silicon On Insulator) substrate, which relates to the technical field of semiconductors and comprises the following steps: oxidizing a top silicon layer of the SOI substrate; performing nanometer stripe etching on the SiO2 layer at the upper part of the top silicon layer; anisotropic wet etching is carried out on the lower Si layer; corroding off the residual part of the SiO2 layer at the upper part and reactants; performing dry etching on the top silicon layer according to the designed holes; performing isotropic wet etching on the buried oxide layer from the exposed holes; a nucleating layer and an antimonide quantum well heterojunction are sequentially grown on a flexible nano SOI substrate. According to the invention, the thickness of the top silicon layer is reduced through oxidation and etching technologies, anisotropic wet etching is carried out on the lower Si layer to form nano stripes, isotropic wet etching is carried out on the buried oxide layer to form a flexible structure, penetration dislocation and anti-phase domain are inhibited, the defect density is reduced, and the quality of an epitaxial material is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an epitaxial antimonide material on a flexible nano-SOI substrate. Background Art

[0002] Silicon (Si) offers good thermal conductivity, low cost, and mature CMOS processing, but its luminescence efficiency is low, and its low carrier mobility makes it difficult to meet the requirements of high-speed electronic devices. Antimonide materials, formed from Group III elements such as Ga, In, and Al and Group V elements such as Sb and As, exhibit high electron mobility and electron saturation drift velocity, but their manufacturing costs are high, raw materials are scarce, and device fabrication technology is immature. Existing research has considered epitaxially growing antimonide quantum well heterojunctions on Si substrates to combine the advantages of both materials. However, the technology for epitaxially growing antimonide quantum well heterojunctions on Si substrates is still immature and presents issues with lattice mismatch, thermal mismatch, and polarity mismatch. Lattice mismatch and thermal mismatch manifest as threading dislocations in Si-based epitaxial materials, while polarity mismatch manifests as antiphase domains in Si-based epitaxial materials. These can form non-radiative recombination centers in the active region of electronic devices, trapping minority carriers and significantly reducing device lifetime.

[0003] To address these issues, researchers have conducted extensive research. In recent years, two main approaches have emerged for obtaining Si-based antimonide quantum well heterojunctions. The first involves heterojunction integration, which uses ion lift-off and wafer bonding techniques to transfer an antimonide quantum well heterojunction grown on substrates such as GaAs, InP, or GaSb to a Si substrate. This is then used to fabricate various optoelectronic devices for integration with silicon-based devices. While the donor substrate for this technique can be recycled, reducing costs, the process is relatively complex, and reports on the use of this technique for the fabrication of Si-based antimonide quantum well heterojunctions are limited. The second approach involves heteroepitaxy, which involves directly growing antimonide materials on Si substrates. By controlling the formation and extension of defects, high-quality Si-based antimonide quantum well heterojunctions can be achieved, allowing for the fabrication of various optoelectronic devices. Currently, methods used to eliminate defects in Si-based antimonide epitaxial layers include selective epitaxy, direct buffer layer growth, two-step or three-step growth, thermal cycle annealing, and the use of off-angle silicon substrates. These methods have greatly promoted the development of Si-based antimonide devices. Compared with the complex heterojunction integration technology, direct epitaxial antimonide quantum well heterojunction on Si is the most ideal solution to achieve low-cost and compatible silicon-based integration.

[0004] However, the current Si-based antimonide quantum well heterojunction epitaxial materials have a high defect density and poor quality due to threading dislocations and antiphase domains caused by lattice mismatch, thermal mismatch and polarity mismatch. It is still some distance away from being able to prepare them into optoelectronic devices for practical applications. Summary of the Invention

[0005] The present application provides a method for preparing epitaxial antimonide materials on flexible nano-SOI substrates, which is used to solve the problems of high defect density and poor quality of epitaxial materials caused by threading dislocations and antiphase domains in existing Si-based antimonide quantum well heterojunction epitaxial materials due to lattice mismatch, thermal mismatch and polarity mismatch.

[0006] In one aspect, the present application provides a method for preparing an epitaxial antimonide material on a flexible nano-SOI substrate, comprising the following steps:

[0007] Step 1: Cleaning the SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top.

[0008] Step 2: oxidize the top silicon layer of the SOI substrate to convert the top silicon layer into a lower Si layer and an upper SiO2 layer.

[0009] Step three: performing nano-stripe etching on the upper SiO2 layer of the top silicon layer to expose the lower Si layer of the top silicon layer.

[0010] Step 4: Anisotropically wet-etch the lower Si layer to expose the lower Si layer. <111> crystal plane, forming a Si surface with nano-stripes.

[0011] Step 5: Etch away the remaining portion of the upper SiO2 layer and the reactants, converting the top silicon layer into a Si layer with nano-stripes, thereby forming an SOI substrate with nano-stripes.

[0012] Step six: designing hole units with different hole diameters and different hole spacings, wherein the spacing between different hole units is greater than 50 μm, and dry-etching the top silicon layer according to the designed holes to expose the buried oxide layer.

[0013] Step seven: performing isotropic wet etching on the buried oxide layer through the exposed holes of the top silicon layer to form a plurality of cavities in the buried oxide layer, thereby obtaining a flexible nano-SOI substrate.

[0014] Step eight, sequentially growing a nucleation layer and an antimonide quantum well heterojunction on the flexible nano-SOI substrate to obtain a flexible nano-SOI substrate epitaxial antimonide material.

[0015] In a possible implementation, in step 1, the thickness of the bottom silicon layer is 300-700 μm, the thickness of the buried oxide layer is 50-1000 nm, and the thickness of the top silicon layer is 50-500 nm.

[0016] In a possible implementation, in step 2, oxidizing the top silicon layer of the SOI substrate includes oxidizing the top silicon layer of the SOI substrate at 900-1100° C. for 2 minutes to 12 hours.

[0017] In one possible implementation, in step three, nano-stripe etching of the upper SiO2 layer of the top silicon layer includes: using a photolithography machine to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer, and then performing dry etching or wet etching, wherein the wet etching is to place the upper SiO2 layer into a BOE etching solution for etching.

[0018] In a possible implementation, in step 4, the etching solution used in the anisotropic wet etching consists of 23.4 wt % KOH, 13.3 wt % C 3 H 8 O, and 63.3 wt % H 2 O.

[0019] In a possible implementation, in step five, the remaining portion of the upper SiO 2 layer and the reactants are etched away using a BOE etching solution.

[0020] In a possible implementation, in step six, the diameters of the different holes are between 1 and 10 μm, and the spacing between the different holes is between 2 and 10 μm.

[0021] The top silicon layer is dry-etched using an inductively coupled plasma etcher according to the designed holes.

[0022] In a possible implementation, in step seven, the isotropic wet etching uses a BOE etching solution.

[0023] In a possible implementation, in step eight, the growth material of the nucleation layer is: AlSb, GaSb or GaAs.

[0024] The growth material of the antimonide quantum well heterojunction is: InAs / AlSb, InAsSb / AlInSb or InSb / AlInSb.

[0025] In one possible implementation, in step eight, the structure of the epitaxial antimonide material on the flexible nano-SOI substrate includes: a bottom silicon layer, a buried oxide layer, a top silicon layer, a nucleation layer, and an antimonide quantum well heterojunction layer stacked in sequence from bottom to top; wherein the buried oxide layer is a SiO2 layer with several cavities, and the top silicon layer is a Si layer with nano-stripes.

[0026] The method for preparing a flexible nano-SOI substrate epitaxial antimonide material in this application has the following advantages:

[0027] The thickness of the top silicon layer is thinned by oxidation and etching technology, the lower Si layer is anisotropically wet-etched to form nano-stripes, and the buried oxide layer is isotropically wet-etched to form a flexible structure, which suppresses threading dislocations and antiphase domains, reduces defect density, and improves the quality of epitaxial materials.

[0028] Among them, thinning the thickness of the top silicon layer makes the top silicon layer have the flexibility of a nano-thin film, which can release the strain caused by lattice mismatch and thermal mismatch and reduce threading dislocations.

[0029] The flexible structure formed by isotropic wet etching of the buried oxide layer has a large degree of freedom, and the slight bending of the flexible film can further avoid threading dislocations caused by strain. The cavity structure of this flexible nano-SOI substrate prevents the top silicon layer from being suspended, thus preventing the collapse of the top silicon layer.

[0030] Anisotropic wet etching of the lower Si layer to form nanostripes can increase the number of diatomic steps and achieve the suppression of antiphase domains. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 A schematic flow chart of a method for preparing an epitaxial antimonide material on a flexible nano-SOI substrate provided in an embodiment of the present application;

[0033] Figure 2 Schematic diagram of the SOI substrate after step 1 provided in an embodiment of the present application;

[0034] Figure 3 Schematic diagram of the SOI substrate after step 2 provided in an embodiment of the present application;

[0035] Figure 4 Schematic diagram of the SOI substrate after step 3 provided in an embodiment of the present application;

[0036] Figure 5 Schematic diagram of the SOI substrate after step 4 provided in an embodiment of the present application;

[0037] Figure 6 Schematic diagram of the SOI substrate after step five provided in an embodiment of the present application;

[0038] Figure 7 Schematic diagram of the SOI substrate after step 6 provided in an embodiment of the present application;

[0039] Figure 8 Schematic diagram of the flexible nano-SOI substrate after step seven provided in an embodiment of the present application;

[0040] Figure 9 Schematic diagram of epitaxial antimonide material on a flexible nano-SOI substrate after step eight provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] like Figure 1 As shown, the embodiment of the present application provides a method for preparing an epitaxial antimonide material on a flexible nano-SOI substrate, comprising the following steps:

[0043] like Figure 2 As shown, in step 1, the SOI substrate is cleaned, and the SOI substrate includes a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top.

[0044] like Figure 3 As shown, in step 2, the top silicon layer of the SOI substrate is oxidized to convert the top silicon layer into a lower Si layer and an upper SiO2 layer.

[0045] like Figure 4 As shown, in step three, the upper SiO2 layer of the top silicon layer is subjected to nano-stripe etching to expose the lower Si layer of the top silicon layer.

[0046] like Figure 5 As shown, in step 4, the lower Si layer is anisotropically wet-etched to expose the lower Si layer. <111> crystal plane, forming a Si surface with nano-stripes.

[0047] like Figure 6 As shown, in step five, the remaining portion of the upper SiO2 layer and the reactants are etched away, and the top silicon layer is converted into a Si layer with nano-stripes, thereby forming an SOI substrate with nano-stripes.

[0048] like Figure 7 As shown, in step six, hole units with different hole diameters and different hole spacings are designed, and the spacing between different hole units is greater than 50 μm. The top silicon layer is dry-etched according to the designed holes to expose the buried oxide layer.

[0049] like Figure 8As shown, in step seven, the buried oxide layer is isotropically wet-etched from the exposed holes of the top silicon layer to form a plurality of cavities in the buried oxide layer, thereby obtaining a flexible nano-SOI substrate.

[0050] like Figure 9 As shown, in step eight, a nucleation layer and an antimonide quantum well heterojunction are sequentially grown on the flexible nano-SOI substrate to obtain an epitaxial antimonide material on the flexible nano-SOI substrate.

[0051] Illustratively, in step 1, the thickness of the bottom silicon layer is 300-700 μm, the thickness of the buried oxide layer is 50-1000 nm, and the thickness of the top silicon layer is 50-500 nm.

[0052] Specifically, in step 1, the SOI substrate is first ultrasonically cleaned with acetone and alcohol for 5 minutes in sequence, and then rinsed with deionized water to remove impurities such as organic matter on the surface of the SOI substrate.

[0053] Illustratively, in step 2, oxidizing the top silicon layer of the SOI substrate includes: oxidizing the top silicon layer of the SOI substrate at 900-1100° C. for an oxidation time of 2 minutes to 12 hours.

[0054] Specifically, the upper SiO2 layer with different thicknesses can be obtained by optimizing the oxidation temperature and oxidation time.

[0055] Exemplarily, in step three, nano-stripe etching of the upper SiO2 layer of the top silicon layer includes: using a photolithography machine to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer, and then performing dry etching or wet etching, wherein wet etching is to place the upper SiO2 layer in a BOE etching solution for etching.

[0056] Specifically, the ratio of NH4F:HF in the BOE etching solution is 6:1. The chemical reaction of the BOE etching solution etching SiO2 can be expressed as:

[0057] SiO2+6HF→H2SiF6+2H2O

[0058] Illustratively, in step 4, the etching solution used in the anisotropic wet etching consists of 23.4 wt % KOH, 13.3 wt % C 3 H 8 O, and 63.3 wt % H 2 O.

[0059] Specifically, the etching solution used in the anisotropic wet etching is <111> The etching rate along the crystal plane is <111> The etching rate of the crystal surface is about 100 times higher. Using the upper SiO2 layer as a mask layer, anisotropic wet etching is performed to expose the lower Si layer. <111> Crystal plane, Si surface with nano-stripes, can enhance the number of diatomic steps and achieve the suppression of antiphase domains.

[0060] Illustratively, in step five, the remaining portion of the upper SiO2 layer and the reactants are etched away using a BOE etching solution.

[0061] Specifically, compared to the V-shaped grooves formed using conventional aspect ratio trapping (ART) technology, epitaxial growth of III-V materials results in larger surface undulations along the groove extension direction, resulting in an uneven surface topography. This is due to the effect of retaining the SiO2 barrier layer during epitaxial growth. In this application, the upper SiO2 layer is used as a mask layer to etch the lower Si layer to form nanostripes. A BOE etching solution is then used to etch away the remaining portion of the upper SiO2 layer, while also cleaning away some chemical reaction products, ultimately forming an SOI substrate with nanostripes.

[0062] Illustratively, in step six, the diameters of the different holes are between 1 and 10 μm, and the spacing between the different holes is between 2 and 10 μm.

[0063] The top silicon layer is dry-etched using an inductively coupled plasma etcher according to the designed holes.

[0064] Specifically, an inductively coupled plasma etcher is used to perform dry etching on the top silicon layer to expose the buried oxide layer, thereby providing a channel for subsequent isotropic wet etching of the buried oxide layer.

[0065] Illustratively, in step seven, the isotropic wet etching uses a BOE etching solution.

[0066] Specifically, the BOE etching solution has a high selectivity for Si materials, and thus can fully etch the SiO2 material of the buried oxide layer. By controlling the time of isotropic wet etching, cavities of different sizes can be obtained, ultimately forming a flexible nano-SOI substrate.

[0067] Illustratively, in step eight, the growth material of the nucleation layer is: AlSb, GaSb or GaAs.

[0068] The growth material of the antimonide quantum well heterojunction is: InAs / AlSb, InAsSb / AlInSb or InSb / AlInSb.

[0069] Specifically, this application uses a molecular beam epitaxy device (MBE device) to pre-deoxidize the flexible nano-SOI substrate at 1000-1100°C to reconstruct the substrate surface, and then grows a nucleation layer in the range of a growth temperature of 480-550°C, a growth rate of 0.1ML / s-5ML / s, and a V / III ratio of 10-20; then the MBE device is used to continue to grow the antimonide quantum well heterojunction.

[0070] Illustratively, in step eight, the structure of the epitaxial antimonide material on the flexible nano-SOI substrate includes: a bottom silicon layer, a buried oxide layer, a top silicon layer, a nucleation layer, and an antimonide quantum well heterojunction layer stacked in sequence from bottom to top; wherein the buried oxide layer is a SiO2 layer with several cavities, and the top silicon layer is a Si layer with nano-stripes.

[0071] Example 1:

[0072] In this embodiment, in step 1, the thickness of the bottom silicon layer is 300 μm, the thickness of the buried oxide layer is 50 nm, and the thickness of the top silicon layer is 50 nm.

[0073] In this embodiment, in step 2, an RTO rapid thermal oxidation process is used, the oxidation temperature of the top silicon layer is 900° C., and the oxidation time is 2 minutes, so that the thickness of the upper SiO 2 layer is 35 nm.

[0074] In this embodiment, in step three, a photolithography machine is used to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer. The spacing of the nano-stripe pattern is 14 nm. The nano-stripe etching adopts wet etching of the upper SiO2 layer. The etching solution is BOE etching solution and the etching time is 3.5 s.

[0075] In this embodiment, in step 4, the anisotropic wet etching employs an etching solution composed of 23.4 wt% KOH, 13.3 wt% C₃H₂O, and 63.3 wt% H₂O. The lower top silicon layer is anisotropically etched at an etching rate of 0.6 μm / min, an etching time of 1 s, and a vertical etching depth of 10 nm, forming a nanostriped top silicon surface.

[0076] In this embodiment, in step five, the remaining portion of the upper SiO 2 layer and the reactants are etched, and the BOE etching solution contains NH 4 F:HF=6:1.

[0077] In this embodiment, in step six, the hole diameter is 1 μm and the hole spacing is 2 μm.

[0078] In this embodiment, in step seven, the isotropic wet etching uses a BOE etching solution at an etching rate of about 10 nm / s, and the SiO2 material of the buried oxide layer is etched for 5 seconds to form a flexible nano-SOI substrate.

[0079] In this embodiment, in step eight, the flexible nano-SOI substrate is pre-deoxidized at 1000°C using an MBE device to reconstruct the substrate surface, and then an AlSb nucleation layer is grown at a growth temperature of 480°C, a growth rate of 0.1ML / s, and a V / III ratio of 10; thereafter, an InAs / AlSb antimonide quantum well heterojunction is continued to be grown using an MBE device.

[0080] Example 2:

[0081] In this embodiment, in step 1, the thickness of the bottom silicon layer is 500 μm, the thickness of the buried oxide layer is 500 nm, and the thickness of the top silicon layer is 200 nm.

[0082] In this embodiment, in step 2, a high-temperature furnace dry oxygen process is used, the oxidation temperature of the top silicon layer is 1000° C., and the oxidation time is 6 hours, so that the thickness of the upper SiO 2 layer is 180 nm.

[0083] In this embodiment, in step three, a photolithography machine is used to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer. The spacing of the nano-stripe pattern is 22nm. The nano-stripe etching adopts dry etching of the upper SiO2 layer. The etching gas is CF4, the etching rate is 25nm / min, and the etching time is 7.2min.

[0084] In this embodiment, in step 4, the anisotropic wet etching employs an etching solution composed of 23.4 wt% KOH, 13.3 wt% C₃H₂O, and 63.3 wt% H₂O. The lower top silicon layer is anisotropically etched at an etching rate of 0.6 μm / min, an etching time of 1.5 s, and a vertical etching depth of 15 nm, forming a nanostriped top silicon surface.

[0085] In this embodiment, in step five, the remaining portion of the upper SiO2 layer and the reactants are etched, and the BOE etching solution contains NH4F:HF=6:1.

[0086] In this embodiment, in step six, the hole diameter is 5 μm and the hole spacing is 5 μm.

[0087] In this embodiment, in step seven, the isotropic wet etching uses a BOE etching solution at an etching rate of about 10 nm / s, and the SiO2 material of the buried oxide layer is etched for 50 seconds to form a flexible nano-SOI substrate.

[0088] In this embodiment, in step eight, the flexible nano-SOI substrate is pre-deoxidized at 1050°C using an MBE device to reconstruct the substrate surface, and then a GaSb nucleation layer is grown at a growth temperature of 500°C, a growth rate of 0.5ML / s, and a V / III ratio of 15; thereafter, an InSb / AlInSb antimonide quantum well heterojunction is continued to be grown using an MBE device.

[0089] Example 3:

[0090] In this embodiment, in step 1, the thickness of the bottom silicon layer is 700 μm, the thickness of the buried oxide layer is 1000 nm, and the thickness of the top silicon layer is 500 nm.

[0091] In this embodiment, in step 2, a high-temperature furnace dry oxygen process is used, the oxidation temperature of the top silicon layer is 1100° C., and the oxidation time is 12 hours, so that the thickness of the upper SiO 2 layer is 480 nm.

[0092] In this embodiment, in step three, a photolithography machine is used to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer. The spacing of the nano-stripe pattern is 24nm. The nano-stripe etching adopts dry etching of the upper SiO2 layer. The etching gas is CF4, the etching rate is 25nm / min, and the etching time is 19.2min.

[0093] In this embodiment, in step 4, the anisotropic wet etching employs an etching solution composed of 23.4 wt% KOH, 13.3 wt% C₃H₂O, and 63.3 wt% H₂O. The lower top silicon layer is anisotropically etched at an etching rate of 0.6 μm / min, an etching time of 1.7 s, and a vertical etching depth of 15 nm, forming a nanostriped top silicon surface.

[0094] In this embodiment, in step five, the remaining portion of the upper SiO 2 layer and the reactants are etched, and the BOE etching solution contains NH 4 F:HF=6:1.

[0095] In this embodiment, in step six, the hole diameter is 10 μm and the hole spacing is 10 μm.

[0096] In this embodiment, in step seven, the isotropic wet etching uses a BOE etching solution at an etching rate of about 10 nm / s, and the SiO2 material of the buried oxide layer is etched for 100 s to form a flexible nano-SOI substrate.

[0097] In this embodiment, in step eight, the flexible nano-SOI substrate is pre-deoxidized at 1100°C using an MBE device to reconstruct the substrate surface, and then a GaAs nucleation layer is grown at a growth temperature of 550°C, a growth rate of 5 ML / s, and a V / III ratio of 20; thereafter, an InAsSb / AlInSb antimonide quantum well heterojunction is continued to be grown using an MBE device.

[0098] In the embodiment of the present application, the thickness of the top silicon layer is thinned by oxidation and etching technology, the lower Si layer is anisotropically wet-etched to form nano-stripes, and the buried oxide layer is isotropically wet-etched to form a flexible structure, thereby suppressing threading dislocations and antiphase domains, reducing defect density, and improving the quality of epitaxial materials.

[0099] Among them, thinning the thickness of the top silicon layer makes the top silicon layer have the flexibility of a nano-thin film, which can release the strain caused by lattice mismatch and thermal mismatch and reduce threading dislocations.

[0100] The flexible structure formed by isotropic wet etching of the buried oxide layer has a large degree of freedom, and the slight bending of the flexible film can further avoid threading dislocations caused by strain. The cavity structure of this flexible nano-SOI substrate prevents the top silicon layer from being suspended, thus preventing the collapse of the top silicon layer.

[0101] Anisotropic wet etching of the lower Si layer to form nanostripes can increase the number of diatomic steps and achieve the suppression of antiphase domains.

[0102] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0103] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for preparing an epitaxial antimonide material on a flexible nano-SOI substrate, characterized in that: The following steps are involved: Step 1: Cleaning the SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top; Step 2: oxidizing the top silicon layer of the SOI substrate to convert the top silicon layer into a lower Si layer and an upper SiO2 layer; Step 3, performing nano-striping etching on the upper SiO2 layer of the top silicon layer to expose the lower Si layer of the top silicon layer; Step 4: Anisotropically wet-etch the lower Si layer to expose the lower Si layer. <111> crystal plane, forming a Si surface with nano-stripes; Step 5: etching away the remaining portion of the upper SiO2 layer and the reactants, converting the top silicon layer into a Si layer with nano-stripes, thereby forming an SOI substrate with nano-stripes; Step 6: Design hole units with different hole diameters and different hole spacings, where the spacing between different hole units is greater than 50 μm, and dry-etch the top silicon layer according to the designed holes to expose the buried oxide layer; Step seven, performing isotropic wet etching on the buried oxide layer through the exposed holes of the top silicon layer to form a plurality of cavities in the buried oxide layer to obtain a flexible nano-SOI substrate; Step eight, sequentially growing a nucleation layer and an antimonide quantum well heterojunction on the flexible nano-SOI substrate to obtain a flexible nano-SOI substrate epitaxial antimonide material.

2. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step 1, the thickness of the bottom silicon layer is 300-700 μm, the thickness of the buried oxide layer is 50-1000 nm, and the thickness of the top silicon layer is 50-500 nm.

3. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step 2, oxidizing the top silicon layer of the SOI substrate includes oxidizing the top silicon layer of the SOI substrate at 900-1100° C. for 2 minutes to 12 hours.

4. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step three, nano-stripe etching is performed on the upper SiO2 layer of the top silicon layer, including: using a photolithography machine to form a nano-stripe pattern on the upper SiO2 layer of the top silicon layer, and then performing dry etching or wet etching, wherein the wet etching is to place the upper SiO2 layer into a BOE etching solution for etching.

5. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step 4, the etching solution used in the anisotropic wet etching consists of 23.4 wt % KOH, 13.3 wt % C 3 H 8 O, and 63.3 wt % H 2 O.

6. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step five, the remaining portion of the upper SiO2 layer and the reactants are etched away using a BOE etching solution.

7. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step 6, the diameters of the different holes are between 1 and 10 μm, and the spacing between the different holes is between 2 and 10 μm; The top silicon layer is dry-etched using an inductively coupled plasma etcher according to the designed holes.

8. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step seven, the isotropic wet etching uses a BOE etching solution.

9. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step eight, the growth material of the nucleation layer is: AlSb, GaSb or GaAs; The growth material of the antimonide quantum well heterojunction is: InAs / AlSb, InAsSb / AlInSb or InSb / AlInSb.

10. The method for preparing a flexible nano-SOI substrate epitaxial antimonide material according to claim 1, characterized in that: In step eight, the structure of the epitaxial antimonide material on the flexible nano-SOI substrate includes: a bottom silicon layer, a buried oxide layer, a top silicon layer, a nucleation layer, and an antimonide quantum well heterojunction layer stacked in sequence from bottom to top; wherein the buried oxide layer is a SiO2 layer with several cavities, and the top silicon layer is a Si layer with nano-stripes.

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