Abnormal data detection circuit and equipment of gap sensor

Abstract

The invention discloses an abnormal data detection circuit and equipment of a gap sensor, which are applied to the technical field of sensors, and comprise an analog-to-digital converter and a processor, the analog-to-digital converter converts a voltage signal collected by the gap sensor into a digital signal, and outputs a data bit of gap data in the digital signal through a first output end; the sign bit of the gap data and the sign bit of the temperature data in the digital signal are output through a second output end; the processor controls the second controllable input end to be conducted to output a corresponding preset abnormal gap value under the condition that at least one of the sign bit of the gap data and the sign bit of the temperature data is 1; under the condition that the sign bit of the gap data and the sign bit of the temperature data are both 0, the first controllable input end is controlled to be switched on, the data bit of the gap data is obtained, and a gap value corresponding to the data bit of the gap data is output; according to the invention, the abnormal data of the gap sensor can be quickly identified, the detection efficiency is high, the abnormal data does not need to be programmed, and the resource waste is reduced.

Description

Technical Field

[0001] The present invention relates to the field of sensor technology, and in particular to an abnormal data detection circuit and device for a gap sensor. Background Art

[0002] During the calibration process of gap sensors for high-speed maglev trains, there are cases where the calibration data is abnormal due to various reasons, such as test bench software failure, poor contact of sensor boards, failure of resistors and capacitors, and circuit failure of the main control board. The current solution to these abnormal calibration data is to perform an accuracy test after the calibration data is burned, determine the function of the sensor based on the accuracy test results, and confirm whether the calibration data is normal based on the accuracy test results. However, this method can only determine whether the calibration data is abnormal after the calibration data is burned. In other words, even if the calibration data is abnormal, the entire calibration and burning process still needs to be completed. The calibration process is time-consuming, and the abnormal data cannot be erased after burning, resulting in a waste of storage resources of the memory chip.

[0003] In view of this, how to improve the abnormal data detection efficiency of the gap sensor and reduce resource waste has become a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a gap sensor abnormal data detection circuit and device, which can improve the abnormal data detection efficiency of the gap sensor and reduce resource waste during use.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] In one aspect, the present invention provides an abnormal data detection circuit for a gap sensor, comprising an analog-to-digital converter and a processor, wherein:

[0007] The input end of the analog-to-digital converter is used to connect to the output end of the gap sensor, the first output end of the analog-to-digital converter is connected to the first controllable input end of the processor, the second output end of the analog-to-digital converter is connected to the logic input end of the processor, and the second controllable input end of the processor is used to receive a preset voltage signal;

[0008] The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, and output the data bits of the gap data in the digital signal through a first output terminal, and output the sign bits of the gap data and the temperature data in the digital signal to the logic input terminal of the processor through a second output terminal;

[0009] The processor is configured to control the second controllable input terminal to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output a corresponding preset abnormal gap value; and to control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data are 0, and obtain the data bit of the gap data through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data.

[0010] In one embodiment, the system further includes a memory, wherein the first output terminal of the analog-to-digital converter is connected to the input terminal of the memory, and the output terminal of the memory is connected to the first controllable input terminal of the processor;

[0011] The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, and send the data bits of the gap data in the digital signal to the memory for storage via the first output terminal, and output the sign bits of the gap data and the temperature data in the digital signal to the logic input terminal of the processor via the second output terminal;

[0012] The processor is configured to control the second controllable input terminal to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output a corresponding preset abnormal gap value; and to control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data are 0, and obtain the data bit of the gap data stored in the memory through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data.

[0013] In one embodiment, the first output terminal of the analog-to-digital converter includes a first sub-output terminal and a second sub-output terminal, and the logic input terminal of the processor includes a first logic input terminal and a second logic input terminal, the first logic input terminal is connected to the first sub-output terminal, and the second logic input terminal is connected to the second sub-output terminal, wherein:

[0014] The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, output the data bit of the gap data in the digital signal corresponding to the first gap channel through the second output terminal, and output the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the first gap channel to the first logic input terminal of the processor through the first sub-output terminal;

[0015] outputting the data bit of the gap data in the digital signal corresponding to the second gap channel through the second output terminal, and outputting the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the second gap channel to the second logic input terminal of the processor through the second sub-output terminal;

[0016] The processor is configured to control the second controllable input terminal to be turned on when at least one of a sign bit of the gap data and a sign bit of the temperature data corresponding to the first gap channel is 1, and output a first preset abnormal gap value corresponding to the first gap channel; and control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are 0, obtain a data bit of the gap data corresponding to the first gap channel stored in the memory through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data;

[0017] When at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, the second controllable input terminal is controlled to be turned on, and the second preset abnormal gap value corresponding to the second gap channel is output; when the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel are both 0, the first controllable input terminal is controlled to be turned on, and the data bit of the gap data corresponding to the second gap channel stored in the memory is obtained through the first controllable input terminal, and the gap value corresponding to the data bit of the gap data is output.

[0018] In one embodiment, the processor includes an OR gate, multiple dual-input trigger modules, a dual-channel selector, and a processing module. The first input of the OR gate is connected to the first sub-output of the analog-to-digital converter as the first logic input of the processor, the second input of the OR gate is connected to the second sub-output of the analog-to-digital converter as the second logic input of the processor, and the output of the OR gate is connected to the logic control terminal of each of the dual-input trigger modules; the first controllable input of each of the dual-input trigger modules serves as the first controllable input of the processor and is connected to the output of the memory; the second controllable inputs of at least two dual-input trigger modules are connected to a power supply; the second controllable inputs of at least two other dual-input trigger modules are connected to the output of the dual-channel selector, the input of the dual-channel selector is connected to the first preset voltage signal corresponding to the first gap channel or the second preset voltage signal corresponding to the second gap channel; the second controllable input of one other dual-input trigger module is grounded; the output of each of the dual-input trigger modules is connected to the input of the processing module, and the output of the processing module serves as the output of the processor;

[0019] The OR gate is configured to output 1 when at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel is 1, and output 0 when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are 0; or to output 1 when at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, and output 0 when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel are 0;

[0020] The dual-channel selector is configured to receive a first preset voltage signal corresponding to the first gap channel when data is obtained at the first input end of the OR gate; and receive a second preset voltage signal corresponding to the second gap channel when data is obtained at the second input end of the OR gate;

[0021] Each of the dual-input trigger modules is configured to control its own second controllable input terminal to be turned on and output a corresponding numerical value based on a value of 1 output by the OR gate; or, based on a value of 0 output by the OR gate, control its own first controllable input terminal to be turned on and obtain a data bit of the gap data corresponding to the first gap channel stored in the memory, or obtain a data bit of the gap data corresponding to the second gap channel, and output the data corresponding to the data bit;

[0022] The processing module is configured to obtain a target data sequence based on the values output by each of the dual-input trigger modules when the output of the OR gate is 1, and to match and output a corresponding preset abnormal gap value based on a pre-established correspondence between the data sequence and the preset abnormal gap value; wherein the first preset abnormal gap value corresponds to the first gap channel, and the second preset abnormal gap value corresponds to the second gap channel;

[0023] It is used to obtain and output a corresponding gap value based on data corresponding to a corresponding gap channel when the output of the OR gate is 0.

[0024] In one embodiment, the number of the dual-input trigger modules is determined based on the model of the analog-to-digital converter.

[0025] In one embodiment, the processor is a processor implemented based on a programmable logic device.

[0026] In one embodiment, the programmable logic device is an FPGA.

[0027] In one embodiment, a first preset abnormal gap value corresponding to the first gap channel and a second preset abnormal gap value corresponding to the second gap channel are both greater than 22 mm, wherein the first preset abnormal gap value and the second preset abnormal gap value have different values.

[0028] In one embodiment, the processor further includes a clock signal input terminal and a reset terminal, wherein the clock signal input terminal is used to receive a clock signal, and the reset terminal is used to receive a reset signal.

[0029] Another aspect of the present invention provides an abnormal data detection device for a gap sensor, comprising the abnormal data detection circuit for the gap sensor as described above.

[0030] It can be seen from the above technical solutions that the embodiments of the present invention have the following advantages:

[0031] An embodiment of the present invention provides an abnormal data detection circuit for a gap sensor, comprising an analog-to-digital converter and a processor, wherein: an input end of the analog-to-digital converter is connected to an output end of the gap sensor, a first output end of the analog-to-digital converter is connected to a first controllable input end of the processor, a second output end of the analog-to-digital converter is connected to a logic input end of the processor, and the second controllable input end of the processor is connected to a preset voltage signal; the analog-to-digital converter is configured to convert a voltage signal collected by the gap sensor into a digital signal, output data bits of gap data in the digital signal through the first output end, and output sign bits of gap data and temperature data in the digital signal to the logic input end of the processor through the second output end; the processor is configured to control the second controllable input end to conduct when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output a corresponding preset abnormal gap value; and control the first controllable input end to conduct when both the sign bit of the gap data and the sign bit of the temperature data are 0, obtain data bits of the gap data through the first controllable input end, and output a gap value corresponding to the data bits of the gap data.

[0032] It can be seen that the analog-to-digital converter in the embodiment of the present invention converts the voltage signal collected by the gap sensor into a digital signal to obtain a digital bit and a sign bit, wherein when the voltage is negative or the data storage overflows, the sign bit is 1, and the data collected by the gap sensor includes a gap voltage signal and a temperature voltage signal. The analog-to-digital converter converts the gap voltage signal to obtain the data bit and sign bit of the gap data, and converts the temperature voltage signal to obtain the data bit and sign bit of the temperature data. The data bit of the gap data can reflect the gap value, and the sign bit of the gap data can reflect whether the gap data is abnormal. When the gap data is normal, the sign bit of the gap data is 0, and when the gap data is abnormal, the sign bit of the gap data is 1. Similarly, the sign bit of the temperature data can reflect whether the temperature data is abnormal. When the temperature data is normal, the sign bit of the temperature data is 0, and when the temperature data is abnormal, the sign bit of the temperature data is 1; the processor obtains the gap data sign bit according to the logic input terminal. The sign bit of the gap number and the sign bit of the temperature data are used to determine which control input terminal is turned on. If the sign bit of the gap number and the sign bit of the temperature data are both 0, it means that the data collected by the gap sensor is normal. At this time, the first controllable input terminal can be controlled to be turned on. The processor can obtain the data bit corresponding to the gap data obtained by the analog-to-digital converter through the first controllable input terminal, and obtain the corresponding gap value according to the data bit for output; if one of the sign bit of the gap data and the sign bit of the temperature data is 1, it means that there is an abnormality in the data. At this time, the processor controls the second controllable input terminal to be turned on. The second controllable input terminal of the processor is connected to a preset voltage signal. The processor can output the corresponding preset abnormal gap value according to the preset voltage signal. The staff can determine that the data currently collected by the gap sensor is abnormal based on the preset abnormal gap value, thereby quickly identifying the abnormal data of the gap sensor, with high detection efficiency, and no need to burn the abnormal data, reducing resource waste.

[0033] In addition, the present invention also provides an abnormal data detection device for a gap sensor, which has the same advantages as the abnormal data detection circuit for the gap sensor.

[0034] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic structural diagram of an abnormal data detection circuit for a gap sensor provided by an embodiment of the present invention;

[0037] Figure 2 A schematic structural diagram of an abnormal data detection circuit for another gap sensor provided by an embodiment of the present invention;

[0038] Figure 3 A schematic structural diagram of an abnormal data detection circuit for another gap sensor provided by an embodiment of the present invention;

[0039] Figure 4 A schematic structural diagram of another abnormal data detection circuit for a gap sensor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] An embodiment of the present invention provides an abnormal data detection circuit for a gap sensor, which can improve detection efficiency and reduce resource waste during use.

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0042] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an abnormal data detection circuit for a gap sensor provided by an embodiment of the present invention. The abnormal data detection circuit for the gap sensor includes an analog-to-digital converter 1 and a processor 2, wherein:

[0043] The input end of the analog-to-digital converter 1 is connected to the output end of the gap sensor, the first output end of the analog-to-digital converter 1 is connected to the first controllable input end b of the processor 2, the second output end of the analog-to-digital converter 1 is connected to the logic input end a of the processor 2, and the second controllable input end c of the processor 2 is used to receive a preset voltage signal;

[0044] an analog-to-digital converter 1 for converting a voltage signal collected by the gap sensor into a digital signal, outputting the data bits of the gap data in the digital signal through a first output terminal, and outputting the sign bits of the gap data and the temperature data in the digital signal through a second output terminal to a logic input terminal of the processor 2;

[0045] Processor 2 is used to control the second controllable input terminal c to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output the corresponding preset abnormal gap value; control the first controllable input terminal b to be turned on when the sign bit of the gap data and the sign bit of the temperature data are both 0, and obtain the data bit of the gap data through the first controllable input terminal b, and output the gap value corresponding to the data bit of the gap data.

[0046] It should be noted that in the embodiment of the present invention, the gap sensor has two channels, each of which can collect two types of data: temperature data and gap data. For the voltage signal corresponding to the data collected by any channel of the gap sensor (including the gap voltage signal and the temperature voltage signal), the analog-to-digital converter 1 converts the voltage signal collected by the gap sensor into a digital signal to obtain the digit and sign bits of the gap data and the digit and sign bits of the temperature data. When the gap data voltage is negative or the data overflows, it indicates that the gap data is abnormal, and the gap data sign bit is set to 1. When the gap data voltage is positive or the data does not overflow, it indicates that the gap data is normal, and the gap data sign bit is set to 0. When the temperature data voltage is negative or the data overflows, it indicates that the temperature data is abnormal, and the temperature data sign bit is set to 1. When the temperature data voltage is positive or the data does not overflow, it indicates that the temperature data is normal, and the temperature data sign bit is set to 0. Therefore, in the embodiment of the present invention, the gap data sign bit in the analog-to-digital converter 1 can indicate whether the gap data is abnormal, and the temperature data sign bit can indicate whether the temperature data is abnormal.

[0047] The processor 2 in the embodiment of the present invention can further determine which control input terminal is turned on through the gap data sign bit and the temperature data sign bit obtained by the logic input terminal. If the sign bit of the gap number and the sign bit of the temperature data are both 0, it means that the gap sensor collects the gap data and temperature data normally. At this time, the first controllable input terminal of the processor 2 can be controlled to be turned on. The processor 2 can obtain the data bit corresponding to the gap data in the data converted by the analog-to-digital converter 1 through the first controllable input terminal b, and obtain the corresponding gap value according to the data bit for output, so that the real gap value collected by the gap sensor can be output; if one of the sign bit of the gap data and the sign bit of the temperature data is 1, it means that At least one of the gap data or the temperature data is abnormal. At this time, the processor 1 controls the second controllable input terminal c to be turned on, and the second controllable input terminal c of the processor 1 is connected to a preset voltage signal. The size of the preset voltage signal can be set according to the preset abnormal gap value. Therefore, the processor 1 can output the corresponding preset abnormal gap value according to the preset voltage signal, so that the staff can determine that the data currently collected by the gap sensor is abnormal based on the preset abnormal gap value output by the processor 23. The embodiment of the present invention can quickly identify the abnormal data of the gap sensor by identifying the sign bit of the gap data of the analog-to-digital converter 1 and the sign bit of the temperature data. The detection efficiency is high, and there is no need to burn the abnormal data, reducing resource waste.

[0048] In one embodiment, see Figure 2 , the circuit may further include a memory 3, the first output terminal of the analog-to-digital converter 1 is connected to the input terminal of the memory 3, and the output terminal of the memory 3 is connected to the first controllable input terminal b of the processor 2;

[0049] Analog-to-digital converter 1, used to convert the voltage signal collected by the gap sensor into a digital signal, and send the data bits of the gap data in the digital signal to the memory for storage through the first output terminal, and output the sign bits of the gap data and the temperature data in the digital signal to the logic input terminal of the processor 2 through the second output terminal;

[0050] Processor 2 is used to control the second controllable input terminal to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output the corresponding preset abnormal gap value; control the first controllable input terminal to be turned on when the sign bit of the gap data and the sign bit of the temperature data are both 0, and obtain the data bit of the gap data stored in the memory through the first controllable input terminal, and output the gap value corresponding to the data bit of the gap data.

[0051] It should be noted that after the analog-to-digital converter 1 in the embodiment of the present invention converts the voltage signal collected by the gap sensor into a digital signal, in order to facilitate the processor 2 to obtain the real gap data, the data bits corresponding to the gap data in the digital signal can be sent to the memory 3 through the first output end for storage, and the sign bit of the gap data and the sign bit of the temperature data in the digital signal can be output through the second output end to the logic input end a of the processor 2 for logical judgment.

[0052] When the processor 2 determines that at least one of the sign bit of the gap data and the sign bit of the temperature data is 1 based on the sign bit of the gap data and the sign bit of the temperature data, the processor 2 can control the second controllable input terminal c to be turned on and output a preset abnormal gap value corresponding to the preset voltage signal; when it is determined that the sign bit of the gap data and the sign bit of the temperature data are both 0, the processor 1 can control the first controllable input terminal b to be turned on. Since the first controllable input terminal b is connected to the memory 1, the processor 1 can obtain the data bit of the gap data stored in the memory 1 through the first controllable input terminal b, and by converting the data, obtain the gap value corresponding to the data bit of the gap data, and output the gap value.

[0053] In practical applications, the gap sensor has two channels, each of which can collect a set of temperature data and gap data. In order to reduce equipment costs, the abnormal data identification of the two channels can be integrated into a set of abnormal data detection circuits. Figure 3 The first output terminal of the analog-to-digital converter 1 in the abnormal data detection circuit includes a first sub-output terminal and a second sub-output terminal, and the logic input terminal a of the processor 2 includes a first logic input terminal a1 and a second logic input terminal a2, the first logic input terminal a1 is connected to the first sub-output terminal, and the second logic input terminal a2 is connected to the second sub-output terminal, wherein:

[0054] The analog-to-digital converter 1 can convert the voltage signal collected by the gap sensor into a digital signal, and output the data bit of the gap data in the digital signal corresponding to the first gap channel to the memory 3 through the second output terminal, and output the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the first gap channel to the first logic input terminal a1 of the processor 2 through the first sub-output terminal;

[0055] Outputting the data bit of the gap data in the digital signal corresponding to the second gap channel to the memory 3 through the second output terminal, and outputting the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the second gap channel to the second logic input terminal a2 of the processor 2 through the second sub-output terminal;

[0056] Processor 2 receives the sign bit of gap data and the sign bit of temperature data corresponding to the first gap channel via a first logic input a1. Upon determining that at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel is 1, processor 2 controls port c1 of a second controllable input terminal to conduct. The second controllable input terminal is connected to a power supply signal VCC1. VCC1 can be determined based on a first preset abnormal gap value corresponding to the first gap channel. Therefore, processor 2 can output the first preset abnormal gap value corresponding to the first gap channel. Upon determining that the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are both 0, processor 2 controls the first controllable input terminal to conduct. Since processor 2 obtains the sign bit of the gap data and the sign bit of the temperature data via the first sub-logic input terminal, processor 2 can determine that this set of sign bits corresponds to the first gap channel of the gap sensor. Therefore, upon determining that the first controllable input terminal is controlled to conduct, processor 2 can obtain data bits of the gap data corresponding to the first gap channel stored in the memory via the first controllable input terminal and output the gap value corresponding to the data bits of the gap data.

[0057] Processor 2 receives the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel via a second logic input a2. When determining that at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, processor 2 controls port c2 of the second controllable input terminal to conduct. The second controllable input terminal is connected to a power supply signal VCC2. VCC2 can be determined based on a second preset abnormal gap value corresponding to the second gap channel. Therefore, processor 2 can output the second preset abnormal gap value corresponding to the second gap channel. When processor 2 determines that the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel are both 0, processor 2 can determine that this set of sign bits corresponds to the second gap channel of the gap sensor because processor 2 obtained the sign bit of the gap data and the sign bit of the temperature data via the second sub-logic input terminal. Therefore, when determining that the first controllable input terminal is to be conducted, processor 2 can control the first controllable input terminal to conduct, obtain the data bits of the gap data corresponding to the second gap channel stored in the memory via the first controllable input terminal, and output the gap value corresponding to the data bits of the gap data.

[0058] In one embodiment, the processor 2 includes an OR gate 21, a plurality of dual-input trigger modules 22, a dual-channel selector 23 and a processing module 24. In practical applications, since the analog-to-digital converter 1 is 12 bits, the first 11 bits are data bits and the 12th bit is a sign bit. The data bits are stored in the memory 3. In order to accurately detect abnormal data of the dual-channel gap sensor in the embodiment of the present invention, please refer to Figure 4The number of dual-input trigger modules in the embodiment of the present invention can be determined based on the model of the analog-to-digital converter 1. For example, the analog-to-digital converter in this application uses a 12-bit analog-to-digital converter with 8 data bits, so the number of dual-input trigger modules can be 8. The processor 2 is a programmable logic device, specifically an FPGA (Field Programmable Gate Array).

[0059] Specifically, in the embodiment of the present invention, the first input terminal of the OR gate 21 is connected to the first sub-output terminal of the analog-to-digital converter 1 as the first logic input terminal of the processor 2, the second input terminal of the OR gate 21 is connected to the second sub-output terminal of the analog-to-digital converter 1 as the second logic input terminal of the processor 2, and the output terminal of the OR gate 21 is connected to the logic control terminal of each dual-input trigger module; the first controllable input terminal of each dual-input trigger module 22 serves as the first controllable input terminal of the processor 2 and the output terminal of the memory 3; the second controllable input terminals of at least two dual-input trigger modules 22 are connected to the power supply VCC0; the second controllable input terminals of at least two other dual-input trigger modules 22 are connected to the output terminal of the dual-channel selector 23, such as Figure 4 From top to bottom, the dual-input trigger modules 22 are numbered ①, ②, ③, ④, ⑤, ⑥, ⑦, and ⑧. The second controllable input terminals of two dual-input trigger modules ③ and ⑤ can be connected to the output terminal of the dual-channel selector 23. The input terminal of the dual-channel selector 23 is connected to the first preset voltage signal corresponding to the first gap channel or the second preset voltage signal corresponding to the second gap channel, and can switch the preset voltage signals. The second controllable input terminal of another dual-input trigger module 22 is grounded (for example, the second controllable input terminal of the dual-input trigger module ⑧ is grounded). The output terminal of each dual-input trigger module 22 is connected to the input terminal of the processing module 24, and the output terminal of the processing module 24 serves as the output terminal of the processor 2.

[0060] When the OR gate 21 determines that at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel is 1, it outputs 1 to the logic control terminal of each dual-input trigger module 22. Each dual-input trigger module 22 controls its own second controllable input terminal to be turned on according to the value 1 output by the OR gate 21. The second controllable input terminals of the dual-input trigger modules ①, ②, ④, ⑥, and ⑦ are all connected to the power supply signal VCC0. When VCC0 is high, the dual-input trigger modules ①, ②, ④, ⑥, and ⑦ all output the value 1. The second controllable input terminals of the dual-input trigger modules ③ and ⑤ are connected to the output terminal of the dual-channel selector 23. Since the dual-channel selector 23 receives the first preset voltage signal corresponding to the first gap channel when the first input terminal of the OR gate 21 obtains data, The second controllable input terminals of the dual-input trigger modules ③ and ⑤ are both connected to the first preset voltage signal. It can be pre-agreed that when the second controllable input terminals of the dual-input trigger modules ③ and ⑤ are connected to the first preset voltage signal, the outputs of the dual-input trigger modules ③ and ⑤ are both 1 (or both output 0, as long as it is the opposite of when the second preset voltage signal is connected). For example, it is pre-agreed that when the second controllable input terminals of the dual-input trigger modules ③ and ⑤ are connected to the first preset voltage signal, the outputs of the dual-input trigger modules ③ and ⑤ are both 1. Since the second controllable input terminal of the dual-input trigger module ⑧ is grounded, the output value of the dual-input trigger module ⑧ is 0. At this time, the processing module 24 can obtain the target data sequence of 11111110 based on the respective numerical values output by the dual-input trigger modules ①, ②, ③, ④, ⑤, ⑥, ⑦, and ⑧.

[0061] The OR gate 21 outputs 1 when it determines that at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, and controls the second controllable input terminals of each of the two-input trigger modules ①, ②, ④, ⑥, and ⑦ to be turned on. The second controllable input terminals of the two-input trigger modules ①, ②, ④, ⑥, and ⑦ are all connected to the power supply signal VCC0. When VCC0 is high, the two-input trigger modules ①, ②, ④, ⑥, and ⑦ all output the value 1. The second controllable input terminals of the two-input trigger modules ③ and ⑤ are connected to the output terminal of the dual-channel selector 23. Since the dual-channel selector 23 receives the second preset voltage signal corresponding to the second gap channel when the two-input selector 23 obtains data at the second input terminal of the OR gate 21, the second controllable input terminals of the two-input trigger modules ③ and ⑤ are both connected to the output terminal of the dual-channel selector 23. The second preset voltage signal can be pre-agreed that when the second controllable input terminals of the dual-input trigger modules ③ and ⑤ are connected to the second preset voltage signal, the outputs of the dual-input trigger modules ③ and ⑤ are both 0 (or both output 1, as long as it is the opposite of when connected to the first preset voltage signal). For example, it is pre-agreed that when the second controllable input terminals of the dual-input trigger modules ③ and ⑤ are connected to the second preset voltage signal, the outputs of the dual-input trigger modules ③ and ⑤ are both 0. Since the second controllable input terminal of the dual-input trigger module ⑧ is grounded, the output value of the dual-input trigger module ⑧ is 0. At this time, the processing module 24 can obtain the target data sequence of 11010110 based on the respective values output by the dual-input trigger modules ①, ②, ③, ④, ⑤, ⑥, ⑦, and ⑧.

[0062] The processing module 24 can pre-establish a correspondence between a data sequence and a preset abnormal gap value. For example, the first preset abnormal gap value corresponds to the first gap channel, and the second preset abnormal gap value corresponds to the second gap channel. That is, the first preset abnormal gap value corresponds to the first data sequence (11111110), and the second preset abnormal gap value corresponds to the second data sequence (11010110). The first preset abnormal gap value corresponding to the first gap channel and the second preset abnormal gap value corresponding to the second gap channel can both be greater than 22 mm, and the first preset abnormal gap value and the second preset abnormal gap value have different values. The screenshot values of the first preset abnormal gap value and the second preset abnormal gap value can be set according to the actual circuit structure, for example, according to the following example. Figure 4In the circuit structure shown (which is simple in design and easy to implement), the first preset abnormal gap value can be 24.8 mm, and the second preset abnormal gap value can be 32.8 mm. Therefore, when processing module 24 determines that target data sequence 11111110 is the first data sequence (11111110), it can output the first preset abnormal gap value (e.g., 24.8 mm). Upon observing that the gap value output by processing module 24 is 24.8 mm, a worker can determine that the data collected by the first gap channel of the gap sensor is abnormal. When processing module 24 determines that target data sequence 11010110 is the second data sequence (11010110), it can output the second preset abnormal gap value (e.g., 32.8 mm). Upon observing that the gap value output by processing module 24 is 32.8 mm, a worker can determine that the data collected by the second gap channel of the gap sensor is abnormal.

[0063] When determining that the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are both 0, the OR gate 21 outputs 0, outputs 0 to the logic control terminal of each dual-input trigger module 22, controls the conduction of each first controllable input terminal, and obtains the data bit of the gap data corresponding to the first gap channel stored in the memory, thereby obtaining the real gap data, and outputs the real gap data to the processing module 24. The processing module 24 converts the data to obtain the gap value corresponding to the first gap channel and outputs the gap value.

[0064] When determining that the sign bit of the gap data corresponding to the second gap channel and the sign bit of the temperature data are both 0, the OR gate 21 outputs 0, outputs 0 to the logic control terminal of each dual-input trigger module 22, controls the conduction of each first controllable input terminal, and obtains the data bit of the gap data corresponding to the second gap channel stored in the memory, thereby obtaining the real gap data, and outputs the real gap data to the processing module 24. The processing module 24 converts the data to obtain the gap value corresponding to the second gap channel and outputs the gap value.

[0065] In addition, if Figure 4 As shown, the processor 2 further includes a clock signal input terminal and a reset terminal. The clock signal input terminal is used to receive a clock signal, and the reset terminal is used to receive a reset signal, thereby facilitating maintenance and management of the abnormal data detection circuit.

[0066] It should be noted that the analog-to-digital converter 1 can be implemented using two ADC chips, and the structure of each ADC chip is as follows: Figure 3As shown, an ADC chip acquires the gap voltage and temperature of one gap channel of the gap sensor. Abnormal data is identified by inputting the sign bit D11 (MSB) of the two ADC chips into the FPGA. An OR gate then ORs the sign bits of the gap data and the temperature data to produce the output signal ERR. Furthermore, if the processor determines that the data corresponding to the first gap channel is abnormal, it outputs the value 214 and the corresponding gap value of 24.8 mm, and reports an error. If the data corresponding to the second gap channel is abnormal, it outputs the value 254 and the corresponding gap value of 32.8 mm, and reports an error. Because the normal data output by the gap sensor to the host computer is 0-200 (corresponding to 0-22 mm), characteristic values can be used to determine whether the data is abnormal and which gap channel is abnormal. The host computer gap conversion protocol: The sensor and host computer communicate via the 485 bus. When the gap is less than 18 mm, one byte corresponds to 0.1 mm; when the gap is greater than 18 mm, one byte corresponds to 0.2 mm.

[0067] It should be noted that the normal input voltage of the analog-to-digital converter ADC is positive, and it can functionally collect negative voltage (collection range -12V to 12V). Therefore, when the input voltage is negative in certain cases, the circuit can work normally but the calibration data is unavailable. Therefore, the present invention inputs the sign bit of AD into the FPGA and performs real-time error detection through software. When abnormal data is found during the calibration process, the characteristic value can be reported, which solves the problem that abnormal data cannot be monitored during the calibration process, thereby saving the labor cost of the calibration process and reducing the waste of non-erasable storage chips caused by burning abnormal data.

[0068] It can be seen that the analog-to-digital converter in the embodiment of the present invention converts the voltage signal collected by the gap sensor into a digital signal to obtain a digital bit and a sign bit, wherein when the voltage is negative or the data storage overflows, the sign position is 1, and the data collected by the gap sensor includes a gap voltage signal and a temperature voltage signal. The analog-to-digital converter converts the gap voltage signal to obtain the data bit and sign bit of the gap data, and converts the temperature voltage signal to obtain the data bit and sign bit of the temperature data. The data bit of the gap data can reflect the gap value, and the sign bit of the gap data can reflect whether the gap data is abnormal. When the gap data is normal, the sign bit of the gap data is 0, and when the gap data is abnormal, the sign bit of the gap data is 1. Similarly, the sign bit of the temperature data can reflect whether the temperature data is abnormal. When the temperature data is normal, the sign bit of the temperature data is 0, and when the temperature data is abnormal, the sign bit of the temperature data is 1; the processor 2 obtains the gap data sign bit according to the logic input terminal. The processor 2 controls the second controllable input terminal to be turned on, and the second controllable input terminal of the processor 2 is connected to the preset voltage signal. The processor 2 can output the corresponding preset abnormal gap value according to the preset voltage signal. The staff can determine that the data currently collected by the gap sensor is abnormal based on the preset abnormal gap value, thereby quickly identifying the abnormal data of the gap sensor. The detection efficiency is high, and there is no need to burn the abnormal data, thereby reducing resource waste.

[0069] In practical applications, you can also consider using an ADC chip with a larger sampling range and that does not collect negative voltages. The start bit of the collected data can be raised through FPGA software. For example, if the collection range is 0-4096 and the range required for the actual resolution is 2000 bits, the collection range can be configured to 1000-3000 by writing an FPGA program. Even if the data is offset, it will not cause overflow and data abnormality, which can fundamentally avoid data abnormalities caused by collecting negative voltages or ADC value overflows.

[0070] Based on the above embodiments, the present invention further provides a gap sensor abnormal data detection device, including the above-described gap sensor abnormal data detection circuit. This detection device has the same beneficial effects as the above-described detection circuit. For a detailed description of the detection circuit involved in the embodiments of the present invention, please refer to the above embodiments, and this application will not elaborate on it here.

[0071] It should be noted that the abnormal data detection device of the gap sensor in the embodiment of the present invention has the same beneficial effects as the abnormal data detection circuit of the gap sensor provided in the above embodiment, and for the specific introduction of the abnormal data detection circuit of the gap sensor involved in the embodiment of the present invention, please refer to the above embodiment, and this application will not go into details here.

[0072] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0073] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0074] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An abnormal data detection circuit for a gap sensor, characterized in that: Includes an analog-to-digital converter and a processor, including: The input end of the analog-to-digital converter is used to connect to the output end of the gap sensor, the first output end of the analog-to-digital converter is connected to the first controllable input end of the processor, the second output end of the analog-to-digital converter is connected to the logic input end of the processor, and the second controllable input end of the processor is used to receive a preset voltage signal; The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, and output the data bits of the gap data in the digital signal through a first output terminal, and output the sign bits of the gap data and the temperature data in the digital signal to the logic input terminal of the processor through a second output terminal; The processor is configured to control the second controllable input terminal to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output a corresponding preset abnormal gap value; and to control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data are 0, and obtain the data bit of the gap data through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data.

2. The abnormal data detection circuit of the gap sensor according to claim 1, characterized in that: Also comprising a memory, wherein the first output terminal of the analog-to-digital converter is connected to the input terminal of the memory, and the output terminal of the memory is connected to the first controllable input terminal of the processor; The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, and send the data bits of the gap data in the digital signal to the memory for storage via the first output terminal, and output the sign bits of the gap data and the temperature data in the digital signal to the logic input terminal of the processor via the second output terminal; The processor is configured to control the second controllable input terminal to be turned on when at least one of the sign bit of the gap data and the sign bit of the temperature data is 1, and output a corresponding preset abnormal gap value; and to control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data are 0, and obtain the data bit of the gap data stored in the memory through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data.

3. The abnormal data detection circuit of the gap sensor according to claim 2, characterized in that: The first output terminal of the analog-to-digital converter includes a first sub-output terminal and a second sub-output terminal, and the logic input terminal of the processor includes a first logic input terminal and a second logic input terminal, the first logic input terminal is connected to the first sub-output terminal, and the second logic input terminal is connected to the second sub-output terminal, wherein: The analog-to-digital converter is configured to convert the voltage signal collected by the gap sensor into a digital signal, output the data bit of the gap data in the digital signal corresponding to the first gap channel through the second output terminal, and output the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the first gap channel to the first logic input terminal of the processor through the first sub-output terminal; outputting the data bit of the gap data in the digital signal corresponding to the second gap channel through the second output terminal, and outputting the sign bit of the gap data and the sign bit of the temperature data in the digital signal corresponding to the second gap channel to the second logic input terminal of the processor through the second sub-output terminal; The processor is configured to control the second controllable input terminal to be turned on when at least one of a sign bit of the gap data and a sign bit of the temperature data corresponding to the first gap channel is 1, and output a first preset abnormal gap value corresponding to the first gap channel; and control the first controllable input terminal to be turned on when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are 0, obtain a data bit of the gap data corresponding to the first gap channel stored in the memory through the first controllable input terminal, and output a gap value corresponding to the data bit of the gap data; When at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, the second controllable input terminal is controlled to be turned on, and the second preset abnormal gap value corresponding to the second gap channel is output; when the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel are both 0, the first controllable input terminal is controlled to be turned on, and the data bit of the gap data corresponding to the second gap channel stored in the memory is obtained through the first controllable input terminal, and the gap value corresponding to the data bit of the gap data is output.

4. The abnormal data detection circuit of the gap sensor according to claim 3, characterized in that: The processor includes an OR gate, a plurality of dual-input trigger modules, a dual-channel selector, and a processing module. The first input end of the OR gate is connected to the first sub-output end of the analog-to-digital converter as the first logic input end of the processor, the second input end of the OR gate is connected to the second sub-output end of the analog-to-digital converter as the second logic input end of the processor, and the output end of the OR gate is connected to the logic control end of each of the dual-input trigger modules. The first controllable input terminal of each of the dual-input trigger modules serves as the first controllable input terminal of the processor and the output terminal of the memory; the second controllable input terminals of at least two dual-input trigger modules are connected to a power supply; the second controllable input terminals of at least two other dual-input trigger modules are connected to the output terminal of a dual-channel selector, and the input terminal of the dual-channel selector is connected to a first preset voltage signal corresponding to the first gap channel or a second preset voltage signal corresponding to the second gap channel; The second controllable input terminal of another dual-input trigger module is grounded; the output terminal of each dual-input trigger module is connected to the input terminal of the processing module, and the output terminal of the processing module serves as the output terminal of the processor; The OR gate is configured to output 1 when at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel is 1, and output 0 when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the first gap channel are 0; or to output 1 when at least one of the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel is 1, and output 0 when both the sign bit of the gap data and the sign bit of the temperature data corresponding to the second gap channel are 0; The dual-channel selector is configured to receive a first preset voltage signal corresponding to the first gap channel when data is obtained at the first input end of the OR gate; and receive a second preset voltage signal corresponding to the second gap channel when data is obtained at the second input end of the OR gate; Each of the dual-input trigger modules is configured to control its own second controllable input terminal to be turned on and output a corresponding numerical value based on a value of 1 output by the OR gate; or, based on a value of 0 output by the OR gate, control its own first controllable input terminal to be turned on and obtain a data bit of the gap data corresponding to the first gap channel stored in the memory, or obtain a data bit of the gap data corresponding to the second gap channel, and output the data corresponding to the data bit; The processing module is configured to obtain a target data sequence based on the values output by each of the dual-input trigger modules when the output of the OR gate is 1, and to match and output a corresponding preset abnormal gap value based on a pre-established correspondence between the data sequence and the preset abnormal gap value; wherein the first preset abnormal gap value corresponds to the first gap channel, and the second preset abnormal gap value corresponds to the second gap channel; It is used to obtain and output a corresponding gap value based on data corresponding to a corresponding gap channel when the output of the OR gate is 0.

5. The abnormal data detection circuit of the gap sensor according to claim 4, characterized in that: The number of the dual-input trigger modules is determined based on the model of the analog-to-digital converter.

6. The abnormal data detection circuit of the gap sensor according to any one of claims 1 to 5, characterized in that: The processor is a processor implemented based on a programmable logic device.

7. The abnormal data detection circuit of the gap sensor according to claim 6, characterized in that: The programmable logic device is an FPGA.

8. The abnormal data detection circuit of the gap sensor according to claim 6, characterized in that: A first preset abnormal gap value corresponding to the first gap channel and a second preset abnormal gap value corresponding to the second gap channel are both greater than 22 mm, wherein the first preset abnormal gap value and the second preset abnormal gap value have different values.

9. The abnormal data detection circuit of the gap sensor according to claim 6, characterized in that: The processor further includes a clock signal input terminal and a reset terminal, wherein the clock signal input terminal is used to receive a clock signal, and the reset terminal is used to receive a reset signal.

10. An abnormal data detection device for a gap sensor, characterized in that: An abnormal data detection circuit comprising a gap sensor as described in any one of claims 1 to 9.

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