Voltage control system for a multi-channel dc power supply

Abstract

The application discloses a voltage control system of a multi-channel direct current source, and relates to the technical field of quantum computers. The system comprises an FPGA motherboard for outputting output parameters of each channel of the direct current source, and at least two DAC subboards for executing the output parameters; each DAC subboard is provided with a voltage reference chip and a plurality of DAC output channels, each DAC output channel executes the output parameters based on a reference voltage signal provided by the voltage reference chip; the FPGA mother board is provided with a voltage compensation module, and the voltage compensation module compensates the output parameters executed by each DAC subboard based on a reference voltage signal of the DAC, so as to improve the consistency of the output voltage of the multi-channel direct current source.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum computers, and in particular to a voltage control system of a multi-channel direct current source. Background Art

[0002] In a trapped ion quantum computer, each ion must independently control its quantum state, using a dedicated electrode combination to create a localized electric field to achieve high-fidelity single-qubit gates. To achieve ion movement and separation / combination, adjacent electrode groups must coordinately apply a gradual voltage gradient to ensure submicron positioning accuracy during ion migration.

[0003] Furthermore, to overcome the limitations of traditional linear ion chains, a honeycomb electrode array was constructed in the XY plane to support two-dimensional ion confinement. Each ion requires six adjacent electrodes to form a three-dimensional confinement field. To suppress micromotion caused by the radio frequency electric field, a compensation electrode array is deployed at the bottom of the chip. Phase synchronization technology is used to control ion displacement within λ / 20 (λ is the laser wavelength).

[0004] Furthermore, the generation of a microwave standing wave field by a distributed electrode array enables consistent coupling strength between different ions, supporting high-fidelity two-qubit gate operations. Redundant electrodes are configured to compensate for ambient magnetic field drift in real time, helping to reduce frequency drift in ion hyperfine level transitions.

[0005] Based on the above reasons, the dense electrode architecture enables the ion trap system to simultaneously meet multiple requirements such as high-precision quantum manipulation, large-scale quantum bit expansion, and dynamic reconstruction, supporting its quantum computing breakthroughs under large-scale ion matrices. For example, the current advanced 512-bit ion chip requires the integration of more than 1,500 electrodes.

[0006] The multi-channel DC source used to control the electrodes of trapped ion quantum computing chips uses different output references. Therefore, when outputting voltages with the same parameter conditions, the actual output voltages of different output channels may vary to varying degrees from the specified voltages due to environmental interference. This reduces the consistency of the actual output voltages of each output channel. This can lead to nonlinear voltage gradients between electrodes due to differences in the references of different output channels, disrupting the uniform arrangement of ion chains and causing axial spacing deviations. Deviations in the DC source output voltage disrupt the equilibrium binding of ions in the radial dimension, causing ions to stray from the laser cooling region, increasing thermal noise, and shortening the decoherence time of the qubit. Voltage differences between adjacent electrodes can alter the strength of the exchange interaction between ions, shifting the resonance condition of the two-qubit gate and reducing gate fidelity.

[0007] Furthermore, differences in references can introduce cross-interference through parasitic capacitance between electrodes, generating noise in specific frequency bands and shortening the quantum state coherence time. Differences in the temperature drift coefficients of reference sources in different output channels can cause the trapped potential well stiffness to drift, increasing the ion vibration frequency offset and hindering the timing synchronization of multi-bit operations.

[0008] Therefore, a technical solution is needed to improve the consistency of the output voltages of various output channels. Summary of the Invention

[0009] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to provide a voltage control system for a multi-channel DC source to improve the consistency of the output voltage of the multi-channel DC source.

[0010] According to a first aspect of an embodiment of the present invention, there is provided a voltage control system for a multi-channel DC source, the system comprising an FPGA motherboard for outputting output parameters of each channel of the DC source, and at least two DAC daughterboards for executing the output parameters;

[0011] Each DAC daughter board is provided with a voltage reference chip and a plurality of DAC output channels, and each DAC output channel performs the output parameter based on a reference voltage signal provided by the voltage reference chip;

[0012] The FPGA motherboard is provided with a voltage compensation module, and the voltage compensation module compensates the output parameters executed by the DAC daughter board based on the reference voltage signal of each DAC.

[0013] Optionally, the total load of the reference voltage signal required by the DAC output channels of all DAC daughter boards is greater than the rated load of one of the voltage reference chips.

[0014] Optionally, the total load of the reference voltage signal required by the DAC output channel of each DAC daughter board is equal to the rated load of one of the voltage reference chips.

[0015] Optionally, the output parameter includes an output voltage, and the FPGA motherboard or the DAC daughterboard obtains an initial voltage code according to the output voltage and a nominal voltage value of the voltage reference chip;

[0016] The voltage compensation module compensates the initial voltage code to obtain a compensated voltage code.

[0017] Optionally, the nominal voltage value of the voltage reference chip of each DAC daughter board is set to a uniform value.

[0018] Optionally, the voltage compensation module compensates the initial voltage code according to the nominal voltage value of the voltage reference chip and the measured voltage value of the reference voltage signal to obtain a compensated voltage code.

[0019] Optionally, the compensation voltage code is determined in the following manner:

[0020]

[0021] in, Indicates the compensation voltage code; Indicates the initial voltage code; Indicates the nominal voltage value; Indicates the measured voltage value.

[0022] Optionally, the system includes an ADC module for measuring the actual voltage value of the reference voltage signal, and the number of bits of the ADC module is greater than 20.

[0023] Optionally, the ADC module is provided on the FPGA motherboard, and each voltage reference chip is connected in parallel to the ADC module;

[0024] The ADC module controls the reception of a reference voltage signal provided by a voltage reference chip in an on state based on a switch element.

[0025] Optionally, the voltage reference chip in the non-connected state is grounded via a resistor having a similar resistance value to that of the ADC module.

[0026] Optionally, each DAC daughter board is provided with a temperature monitoring device;

[0027] The temperature monitoring device is used to monitor the temperature of the voltage reference chip of the DAC sub-board on which the temperature monitoring device is installed; if the monitored temperature change exceeds a preset temperature threshold, it triggers the update of the measured voltage value of the reference voltage signal installed on the same DAC sub-board; if the monitored temperature change does not exceed the preset temperature threshold, the measured voltage value of the reference voltage signal installed on the same DAC sub-board is used.

[0028] Optionally, the measured voltage value of the reference voltage signal of each DAC sub-board is obtained at a certain period, and the initial voltage encoding performed by the DAC sub-board is compensated using the latest measured voltage value of the reference voltage signal.

[0029] Optionally, the period is set to be smaller than the shortest variation interval of the output parameters of the DAC output channels of all DAC sub-boards.

[0030] Optionally, the system includes a system clock chip, and the period is generated based on a local clock signal provided by the system clock chip;

[0031] The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

[0032] According to a second aspect of an embodiment of the present invention, an ion trap quantum computing DC electrode system is provided, comprising any one of the voltage control systems of the multi-channel DC source described above.

[0033] According to a third aspect of an embodiment of the present invention, an ion trap quantum computing system is provided, comprising the voltage control system of the multi-channel DC source described in any one of the above items.

[0034] According to the solution provided by an embodiment of the present invention, a voltage reference chip disposed on a daughterboard provides a reference voltage signal, which implements an output parameter to control the voltage value of the output current of the multi-channel DC source. When the current is actually output, the output parameter implemented by the DAC daughterboard is compensated based on the reference voltage signal of each DAC, thereby ensuring that the voltage value of the output current of each channel remains consistent with the reference voltage signal, that is, the voltage values ​​are exactly the same, or the adjusted voltage values ​​maintain a preset proportional relationship, thereby improving the consistency of the output voltage of the multi-channel DC source.

[0035] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic structural diagram of a voltage control system of a first multi-channel DC source provided by an embodiment of the present invention;

[0037] Figure 2 1 is a schematic structural diagram of a voltage control system of a second multi-channel DC source provided by an embodiment of the present invention;

[0038] Figure 3 1 is a schematic structural diagram of a voltage control system of a third multi-channel DC source provided by an embodiment of the present invention;

[0039] Figure 4 This is a structural diagram of an FPGA development board provided by an embodiment of the present invention;

[0040] Figure 5 It is a structural diagram of a clock control system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0042] The voltage control system of a multi-channel DC source according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0043] In one embodiment of the present invention, see Figure 1 , provides a voltage control system for a multi-channel DC source, including an FPGA (Field Programmable Gate Array) motherboard for outputting output parameters of each channel of the DC source, and at least two DAC (Digital-to-Analog Converter) daughterboards for executing the output parameters; each DAC daughterboard is equipped with a voltage reference chip and multiple DAC output channels, and each DAC output channel executes the output parameter based on a reference voltage signal provided by the voltage reference chip;

[0044] The FPGA motherboard is provided with a voltage compensation module, which compensates the output parameters executed by the DAC daughter board based on the reference voltage signal of each DAC.

[0045] In the above system, the FPGA motherboard refers to a circuit board developed based on FPGA, and the DAC daughterboard refers to a circuit board connected to the motherboard and including a DAC module. Figure 1 As an example, only one DAC daughter board is shown to be connected to the motherboard. If there are two or more DAC daughter boards, each DAC daughter board should be connected according to Figure 1 The method shown is to connect to the FPGA motherboard and multi-channel DC source. Figure 2 The multi-channel DAC refers to the DAC daughter board. The FPGA motherboard and the DAC daughter board can be connected through the motherboard connector. The motherboard connector integrates various communication interfaces, such as digital power supply, analog power supply interface, SPI (Serial Peripheral Interface), transmission reference voltage signal Interface for measuring voltage value, etc.

[0046] Figure 2 The voltage reference chip can provide reference voltage signals to the multi-channel DAC and to the FPGA motherboard through the motherboard connector. The measured voltage value of the reference voltage signal is , the output form is an analog signal.

[0047] like Figure 2As shown, the multi-channel DAC module outputs analog signals, and different initial voltage codes can represent different voltages. For example, if the voltage code has 20 bits, it can represent The output current of the designated DAC output channel of the multi-channel DC source is controlled to have a voltage value represented by the initial voltage code.

[0048] For example Figure 2 , through D-Sub connector, ~ 39 represents 40 DAC output channels, which correspondingly control 40 output voltages of the multi-channel DC source.

[0049] The comparison result can be specifically as follows: .

[0050] The above output parameters include output voltage. The FPGA motherboard or DAC daughterboard obtains the initial voltage code based on the output voltage and the nominal voltage value of the voltage reference chip:

[0051] The FPGA motherboard or DAC daughterboard obtains an initial voltage code according to the output voltage and the nominal voltage value of the voltage reference chip;

[0052] The voltage compensation module compensates the initial voltage code to obtain a compensated voltage code.

[0053] For example, if the output voltage is 5V and the nominal voltage value is 1V, the FPGA motherboard or DAC daughterboard obtains 5 times the nominal voltage value as the initial voltage code.

[0054] Specifically, the voltage compensation module compensates the initial voltage code according to the nominal voltage value of the voltage reference chip and the measured voltage value of the reference voltage signal to obtain the compensated voltage code.

[0055] In one embodiment, the compensation voltage code is determined as follows:

[0056]

[0057] in, Indicates the compensation voltage code; Indicates the initial voltage code; Indicates the nominal voltage value; Indicates the measured voltage value.

[0058] The nominal voltage value refers to the voltage value expected to be output by the voltage reference voltage signal, while the measured voltage value is the measurement data obtained by actually measuring the voltage value of the reference voltage signal after controlling the voltage value of the output current of a specified output channel of the multi-channel DC source according to the received reference voltage signal.

[0059] In one embodiment, the system comprises an ADC (Analog-to-Digital Converter) module for measuring the actual voltage value of the reference voltage signal, and the number of bits of the ADC module is greater than 20.

[0060] The initial voltage code of each channel is determined according to the voltage value of the output current of each channel, the nominal voltage value, and the DAC resolution. The DAC resolution refers to the number of bits of the voltage code.

[0061] For the case where there are multiple DAC sub-boards, the nominal voltage value of the voltage reference chip of each DAC sub-board is set to a uniform value.

[0062] If the preset nominal voltage values corresponding to each sub-board are similar, the following processing can be performed. The similar nominal voltage values can mean that each nominal voltage value is within a specified value range, or the difference between the maximum and minimum values does not exceed a preset nominal value threshold, etc.

[0063] If the similar condition is met, the processing method can be to set the nominal voltage value of any sub-board to randomly, or set it to the average of each nominal voltage value. Then, when calculating the voltage code of each channel, the nominal value of the reference voltage signal is set to . In this way, since the adjustment of the compensation voltage code is performed according to the ratio of the comparison results , even if the voltage value of the output current of each channel after adjustment has a deviation relative to the nominal value set by the sub-board itself, the compensation voltage code obtained by the comparison results calculated by the above ratio is offset and adjusted according to a specific ratio, which makes the output voltage values of each channel in each sub-board maintain a preset proportional relationship, so that the voltage gradient between electrodes can still remain linear, thereby improving the consistency of the output voltage.

[0064] After the voltage reference chip on any sub-board provides the reference voltage signal to the voltage compensation module, the comparison result obtained by the voltage compensation module using the reference voltage signal is the comparison result corresponding to the voltage reference chip of the sub-board.

[0065] In one case, a calculation module is provided on the mother board, the compensation voltage code is calculated according to the above formula, and then sent to the DAC module of the sub-board, so that the DAC module of the sub-board can obtain the compensation voltage code. In this case, the output parameter output by the FPGA mother board includes the output voltage represented by the compensation voltage code; in another case, a calculation module can also be provided on the sub-board, and the compensation voltage code is calculated according to the above formula after obtaining the comparison result sent by the mother board. In this case, the output parameter includes the comparison result.

[0066] The DAC sub-boards perform output parameters, including passing through the DAC modules, the compensation voltage codes can be converted into analog signals, and based on the obtained analog signals, the output channels specified above output currents with voltage values represented by the compensation voltage codes, so as to realize compensation.

[0067] As can be seen from the above, according to the scheme provided by the embodiment of the application, the reference voltage signals are provided by the voltage reference chips arranged on the sub-boards, the reference voltage signals perform output parameters, and the voltage values of the output currents of the multi-channel direct current sources are controlled. In the case of actually outputting the currents, the output parameters performed by each DAC sub-board are compensated based on the reference voltage signals of the DAC, so that the voltage values of the output currents of each channel can be kept consistent with respect to the reference voltage signals, that is, the voltage values are completely the same, or the voltage values after adjustment keep a preset proportional relationship, so that the consistency of the output voltages of the multi-channel direct current sources can be improved.

[0068] As shown in Figure 3 , the ADC module is arranged on the FPGA mother board, and each voltage reference chip is connected in parallel with the ADC module; the ADC module controls the reference voltage signals provided by the voltage reference chips in the on state based on the switching elements.

[0069] The ADC module is used for converting the reference voltage signals sent by each DAC module into digital signals, so that the voltage compensation module receives the digital signals.

[0070] In this way, the voltage compensation module can perform calculation based on the digital signals to obtain a comparison result.

[0071] In one embodiment, referring to Figure 3 , the ADC module is a high-precision ADC in Figure 3 , and the voltage reference chips in the off state are grounded via resistors R with similar resistance values to the ADC module, that is, the GND line in the figure. The switching elements control the connection and disconnection of each DAC sub-board and the mother board, so that when the system needs to obtain the comparison result of the reference voltage signals of any DAC sub-board, the high-precision DAC is controlled to turn on the voltage reference chip of the DAC sub-board, and the reference voltage signal sent by the voltage reference chip belonging to the DAC sub-board is obtained from , , …… .

[0072] The similar resistance values refer to the same resistance values as the ADC module or the resistance values different from the resistance values of the ADC module by less than a preset resistance threshold.

[0073] In Figure 3In the DAC, the switching element can be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). When the reference voltage signals of the daughter boards connected in parallel to the high-precision ADC are not connected to the high-precision ADC, they are connected to GND through a bypass resistor R. By selecting resistors R with the same or similar resistance values, the load variation of the voltage reference chips of the DAC daughter boards when connecting and disconnecting from the high-precision ADC can be reduced to a certain extent, thereby reducing the jitter of the reference voltage signal caused by the load variation, that is, improving the stability of the reference voltage signals of each daughter board.

[0074] In one embodiment of the present invention, for each DAC daughter board, a voltage reference chip disposed on the DAC daughter board generates multiple reference voltage signals, wherein each reference voltage signal controls a preset number of designated output channels in the multi-channel DC source.

[0075] For example, for a DAC on a single daughterboard, the DAC's corresponding output channels can be divided into several groups, with each group receiving a reference voltage signal. For example, for a DAC with 40 output channels, the 40 output channels can be divided into five groups, with eight output channels in each group.

[0076] For high-precision voltage reference chips, their load has a certain limit.

[0077] Specifically, the total load of the reference voltage signal required by the DAC output channels of all DAC daughter boards is greater than the rated load of a voltage reference chip, or the total load of the reference voltage signal required by the DAC output channels of each DAC daughter board is equal to the rated load of a voltage reference chip. The above load can be expressed in power.

[0078] For example, if five daughterboards are provided to achieve a 200-channel DC source output, at least 25 reference voltage signals need to be introduced, which clearly exceeds the load range of the voltage reference chip. Therefore, it is not possible to provide a voltage reference chip on the FPGA motherboard to ensure the output voltage consistency of each output channel of each daughterboard. In contrast, in the implementation scheme of the present application, a separate voltage reference chip is provided on each daughterboard, and the reference voltage signals are introduced in a grouped manner. This can reduce the load of a single voltage reference chip and a single reference voltage signal, reducing the impact on the accuracy of voltage control.

[0079] For voltages with the same parameter conditions, for example, if the voltage reference chip is planned to output a voltage of 5V, the voltage value output by each output channel will float with 5V as the nominal voltage value.

[0080] In one embodiment of the present invention, each DAC daughter board is provided with a temperature monitoring device;

[0081] A temperature monitoring device is used to monitor the temperature of the voltage reference chip of the DAC daughter board on which the temperature monitoring device is installed; if the monitored temperature change exceeds a preset temperature threshold, it triggers an update of the measured voltage value of the reference voltage signal installed on the same DAC daughter board; if the monitored temperature change does not exceed the preset temperature threshold, the measured voltage value of the reference voltage signal installed on the same DAC daughter board is used.

[0082] like Figure 2 As shown, the temperature monitoring device is the temperature sampling chip in the figure. When the temperature detected exceeds the temperature threshold, a signal is transmitted through the motherboard connector, so that the voltage compensation module provides a comparison result based on the updated measured voltage value, triggering the DAC module to update the compensation voltage code according to the above formula, so that the specified output channel can be refreshed using the updated compensation voltage code.

[0083] The temperature sampling chip can also send temperature data to the voltage reference chip, so that the voltage reference chip calculates the voltage value to be output according to the temperature drift coefficient.

[0084] Because the components connected to the DAC daughterboard and the voltage reference chip are affected by temperature, their electrical parameters change, which will also affect the output of the voltage reference chip to a certain extent. Therefore, through monitoring by the temperature monitoring device, the specified output channel is refreshed when the temperature changes significantly, thereby reducing the impact of temperature abnormalities on the voltage value of the output current.

[0085] In the above scheme, if the time interval between the execution time of controlling the output current of a specified output channel according to the reference voltage signal and the refresh time of the compensation voltage code is long, the drift change of the voltage reference chip at the actual output time of the DC source output channel cannot be accurately compensated;

[0086] In this case, the measured voltage value of the reference voltage signal of each DAC daughter board is obtained at a certain period, and the initial voltage encoding performed by the DAC daughter board is compensated using the latest measured voltage value of the reference voltage signal. In this way, by controlling the cycle length, the above-mentioned time interval can be avoided from being too long.

[0087] Continue to use the above Figure 3In the embodiment of the application, the high-precision ADC and the reference voltage chip of the different sub-boards are sequentially connected in one cycle, the measured values of the latest reference voltage signals of the sub-boards are recorded, the voltage code of each channel output voltage of the input sub-board is compensated by calculating the compensation voltage code, for example, the measured values are compensated by the above-mentioned refreshing step when the measured values change, and the consistency of the output of each channel of the direct current source can be improved to a certain extent.

[0088] In one embodiment, the above-mentioned cycle is set to be less than the shortest change interval of the output parameters of the DAC output channels of all the DAC sub-boards.

[0089] For example, the influencing factors of the shortest change interval are the shortest operation cycle or the preset working period.

[0090] For the output channel with high time resolution output voltage operation, the control cycle is less than the shortest operation cycle, wherein the operation cycle refers to the execution cycle of the output voltage operation, and the voltage value of the output current of the output channel is adjusted once for each output voltage operation.

[0091] If there is an output channel that maintains a stable value during the working period, the output parameter refreshing cycle can be set to be less than or equal to the working period.

[0092] In one embodiment, the above-mentioned system comprises a system clock chip, and the cycle is generated based on a local clock signal provided by the system clock chip;

[0093] In one embodiment of the application, the FPGA mother board controls the local clock signal and the external clock signal to be in phase.

[0094] In one embodiment of the application, a voltage control system of a multi-channel direct current source for an ion trap quantum computing direct current electrode system is also provided.

[0095] In one embodiment of the application, a voltage control system of a multi-channel direct current source for an ion trap quantum computing system is also provided.

[0096] In the following embodiment, the implementation of the FPGA mother board controlling the local clock signal and the external clock signal to be in phase is indicated.

[0097] In one embodiment of the application, a clock control system is provided, which is used for quantum measurement and control, and is used for an FPGA mother board, a synchronous sampling source and a system clock chip. Figure 5 The FPGA mother board comprises a time interval measurement module and a PID control module.

[0098] The system clock chip is used for providing a local clock signal to the time interval measurement module.

[0099] A synchronous sampling source, used for providing a measurement clock signal to the time interval measurement module;

[0100] a time interval measurement module, configured to obtain frequency and / or phase information of an external clock signal and a local clock signal based on a measurement clock signal;

[0101] A PID control module, configured to output a clock adjustment signal based on frequency and / or phase information of an external clock signal and a local clock signal;

[0102] The system clock chip is further configured to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

[0103] The quantum measurement and control process includes multi-channel DC source control based on ion trap quantum computing. The FPGA motherboard is used to output the output parameters of each channel of the DC source. The system also includes a DAC daughterboard for executing the output parameters.

[0104] The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

[0105] In one embodiment, the output parameter includes an output voltage, and the DAC sub-board refreshes the output voltage of each channel of the DC source at a certain period;

[0106] The period is generated based on a local clock signal output by a clock control system.

[0107] This embodiment refers to the aforementioned voltage control system and will not be described in detail here. Figure 4 In the FPGA motherboard, the voltage compensation module, motherboard connector, high-precision ADC and the above Figure 1 The same effect is achieved in the embodiment, such as Figure 4 As shown, the measured voltage value can be processed The motherboard connector is also connected to the power supply.

[0108] A clock signal is a periodically changing electrical signal that can be expressed as alternating high and low levels. In the above system, the local clock signal and the measurement clock signal are clock signals provided by the system clock chip and the synchronous sampling source, respectively.

[0109] The period is set to be smaller than the shortest change interval of the output parameter in each channel of the DC source.

[0110] The external clock signal refers to the clock signal of the ion trap monitoring or signal detection related system.

[0111] When a measurement clock signal and a local clock signal are obtained, the phase information can include the phase difference between the two. This phase difference reflects the timing deviation between the local and measurement clock signals. The phase difference between the two clock signals can be measured using Digital Dual-Mixing Time-to-Digital Converter (DDDMTD). DDMTD utilizes fully digital processing, enabling algorithms such as Kalman filtering to be implemented on an FPGA motherboard to suppress burst noise. DDMTD supports real-time phase adjustment at the nanosecond level, such as temperature drift compensation. DDMTD can simultaneously measure the phase difference of multiple clocks, enabling cluster device synchronization. Therefore, this architecture is particularly suitable for boards in quantum manipulation systems.

[0112] The phase difference can be specifically obtained by calculating the delay time of the local clock signal edge relative to the measured clock signal. Once the phase difference is obtained, the frequency of the local clock signal can be derived based on the phase difference and the frequency of the measured clock signal. In this embodiment, the synchronous sampling source can be configured to output a fixed-frequency clock signal, thereby calculating the frequency and / or phase information of the local clock signal and the frequency and / or phase information of the external clock signal using a unified standard.

[0113] The calculation method of the frequency and phase information of the external clock signal is similar to that of the frequency and phase information of the local clock signal. The only difference is the replacement of the names of the external clock signal and the local clock signal.

[0114] Figure 4 This is a schematic diagram of the overall structure of the FPGA motherboard in the solution provided by an embodiment of the present invention, wherein the synchronous sampling source directly outputs a measurement clock signal to the time interval measurement module.

[0115] The system also includes a frequency synthesizer that outputs an external clock signal to the time interval measurement module. The frequency synthesizer is used to receive and adjust the external clock signal to make it have the same frequency as the local clock signal, thereby outputting an external clock signal with the same frequency as the local clock signal.

[0116] A frequency synthesizer can generate a clock signal with a target frequency through PLL (Phase-Locked Loop) feedback regulation or DDS (Direct Digital Synthesizer) phase accumulation. By setting the target frequency to the frequency of the local clock signal, an external clock signal with the same frequency as the local clock signal can be output.

[0117] The core of DDMTD is to measure the phase difference between two clocks using a dual-mixer structure. However, this technology requires that the two input signals have strictly identical frequencies. If the external clock signal and the local clock signal have different frequencies, mixing will produce a difference frequency signal, making it impossible to directly quantify the phase difference. A frequency synthesizer converts the external clock to the local clock frequency domain—that is, to the same frequency—so that the two signals meet the phase difference detection requirements.

[0118] Figure 4 The PID in the figure represents the PID control module. According to the requirements of quantum measurement and control, if the local clock signal needs to be adjusted to be in phase with the external clock signal, the phase information of the external clock signal and the local clock signal is used.

[0119] Specifically, the phase difference between the local clock signal and the external clock signal can be calculated through the phase information of the external clock signal and the phase information of the local clock signal. The clock adjustment signal is a PID control signal output according to the phase difference. By constructing a PID formula of the phase difference and the output and performing parameter adjustment to control the relationship between the output and the phase difference, the PID control signal is obtained, and then the PID control signal is converted into a reference clock signal.

[0120] Alternatively, if the local clock signal needs to be adjusted to have the same frequency and phase as the external clock signal, the phase information of the external clock signal and the local clock signal, as well as the frequency of the external clock signal and the local clock signal are used as inputs for PID control, thereby outputting a PID control signal.

[0121] In this way, the two clock signals can have the same frequency and a constant phase difference, or the two clock signals can have different frequencies and the change in phase difference conforms to a trigonometric function relationship or other function relationship, thereby achieving coherence between the local clock signal and the external clock signal.

[0122] The system clock chip can choose a high-performance clock generator chip such as LMK04828 or HMC7044. By setting up an additional system clock chip, it is avoided to develop a module that provides a local clock signal on the FPGA motherboard, thereby reducing development costs.

[0123] In the above embodiment, the specific implementation of the PID control module controlling the system clock chip is as follows: the PID control module outputs a PID control signal as a clock adjustment signal to control the voltage-controlled crystal oscillator. Figure 4 , the clock control system further includes: a second DAC and a voltage-controlled crystal oscillator;

[0124] The voltage-controlled crystal oscillator is used to provide a reference clock signal for the system clock chip to control the system clock chip to adjust the frequency and / or phase of the local clock signal;

[0125] The second DAC is used to convert the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output a reference clock signal.

[0126] The second described in the second DAC is only used to distinguish it from the DAC sub-board in the aforementioned embodiment, so as to indicate that it is a different DAC device.

[0127] The frequency and / or phase information of the local clock signal output by the system clock chip is controlled by a voltage-controlled crystal oscillator, which is in turn controlled by a clock adjustment signal. Since the voltage-controlled crystal oscillator is controlled by an analog signal, and the PID control module, as part of the FPGA, outputs a digital signal, a DAC is required to convert the digital signal into an analog signal.

[0128] In one embodiment of the present invention, the clock control system further comprises a first crystal oscillator;

[0129] The first crystal oscillator is used to provide a system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard starts running and establishes an SPI connection with the system clock chip to obtain a local clock signal.

[0130] The FPGA circuit board refers to the FPGA motherboard in the above-mentioned embodiments. The system configuration clock signal is a clock signal with a preset frequency. Providing the system configuration clock signal to the FPGA circuit board and providing the same system configuration clock signal to the system clock chip allows the FPGA circuit board and the system clock chip to communicate with each other according to consistent timing.

[0131] The clock control system includes a synchronous sampling source and a first crystal oscillator. The reason for setting up independent clock signal sources is that the DDMTD achieves high-precision alignment by measuring the phase difference between the two clocks. If the first crystal oscillator is used directly as the sampling clock, internal logic noise in the first crystal oscillator, such as power supply jitter and cross-clock domain interference, will contaminate the measurement results and degrade phase noise. Setting up an independent synchronous sampling source prevents FPGA digital noise from entering the measurement chain. Furthermore, the first crystal oscillator, which serves as the system configuration clock, has a large clock path delay and is susceptible to temperature and voltage drift, making it unable to meet the DDMTD's stringent sampling clock phase consistency requirements.

[0132] In one embodiment of the present invention, the clock control system further includes a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storing quantum measurement and control instructions received by the communication module;

[0133] The system clock chip is also used to provide a local clock signal to the DDR so that the DDR performs data processing operations based on the local clock signal.

[0134] In one embodiment, the clock control system further comprises:

[0135] FLASH used to store system firmware. After the system is powered on, the system firmware is loaded from FLASH to the FPGA motherboard;

[0136] The clock control system also includes an EEPROM for storing the version number and factory number of the software and hardware.

[0137] like Figure 4 As shown, the FPGA motherboard is connected to FLASH (flash memory), DDR, and EEPROM (Electrically Erasable Programmable Read-Only Memory). FLASH can be NAND FLASH (Not AND Flash, a flash memory with a NAND logic gate array structure), used as a large-capacity storage device. DDR can be any RAM (Random Access Memory) device, used as a system operation cache. EEPROM can be any ROM device or NOR FLASH (or NOR flash memory with a NOR logic gate array structure), used as a system firmware device. Specifically, FLASH can store system firmware, which is loaded from FLASH to the FPGA motherboard after the system is powered on. DDR can store the timing information for sending the output voltage of the multi-channel DC source.

[0138] The instructions issued by DDR storage directly serve quantum computing tasks. The DDR controller uses the local clock signal provided by the system clock chip for control, ensuring that the data read and write operations of DDR are synchronized with the quantum measurement and control core. Using the same clock domain can ensure low-latency synchronization of instruction reading and quantum measurement and control, avoiding data errors or performance bottlenecks caused by clock switching, and reducing the timing risks brought by cross-clock domains; it also simplifies the data path design inside the FPGA, such as the depth control of the FIFO buffer, thereby improving the overall efficiency of the system.

[0139] In one embodiment, the local clock signal provided by the system clock chip includes a parallel coherent measurement signal, a system global signal, and a DDR control signal;

[0140] The coherent measurement signal is provided to the time interval measurement module;

[0141] The system's global signals are used to control quantum measurement and control operations;

[0142] DDR control signals are used to provide DDR.

[0143] Figure 4 In the example, the system clock chip provides four line connections, among which the SPI connection is used to connect to the FPGA. The measurement line sends a coherent measurement signal to measure whether the local clock signal is coherent with the external clock signal. If not, the PID control module is used to adjust the local clock signal until coherence is achieved as shown in the above embodiment. The Global connection represents the system global signal.

[0144] The coherent measurement signal is parallel and isolated from other signals, so that the measurement process can be as free from interference from other signals as possible.

[0145] DDR stands for DDR control signal, which is used to:

[0146] Output processing operations performed by the DDR interface, including read / write operations, require strict alignment of the clock and data. Due to path delay differences, the global clock signal cannot directly meet the setup / hold time requirements of the DDR interface, and its phase must be independently adjusted through a dedicated clock network. The DDR clock duty cycle must be close to 50%, but the global clock may cause waveform distortion due to load changes during long-distance transmission. In contrast, providing a separate local clock signal can reduce such distortion by setting up a local clock buffer (such as BUFR). In addition, the independent DDR clock path can reduce crosstalk from high-speed switching signals on the global clock network, improving system stability.

[0147] In one embodiment of the present invention, the clock control system further includes a communication module;

[0148] The first crystal oscillator is also used to provide a system configuration clock signal to the communication module.

[0149] The communication module includes an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol, and a system configuration clock signal is provided to the serial transceiver.

[0150] The communication module can be Figure 4 The serial transceiver and Ethernet port communicate based on the SGMII (Serial Gigabit Media Independent Interface) communication protocol.

[0151] The system configures the clock for SPI connections and Ethernet serial transceiver-to-physical layer operations, which are lower-priority or asynchronous communication tasks. Because data communication typically has a low correlation with the timing of DC power supply output operations, and the clock signal provided by the crystal oscillator does not require coherent adjustment, its frequency and phase are relatively stable, ensuring stable and smooth data communication.

[0152] like Figure 4 ,The first crystal oscillator divides the system configuration clock signal into two ,paths through the clock distribution module, one path is provided to the FPGA motherboard and ,the other path is provided to the serial transceiver.

[0153] In one embodiment of the present invention, an ion trap quantum computing DC electrode system is provided, comprising the clock control system described in any of the above embodiments.

[0154] In one embodiment of the present invention, an ion trap quantum computing system is provided, comprising the clock control system described in any one of the above embodiments.

[0155] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0156] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0157] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0158] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0159] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0160] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0161] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0162] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A voltage control system for a multi-channel DC source, characterized in that: The system includes an FPGA motherboard for outputting output parameters of each channel of a DC source, and at least two DAC daughterboards for executing the output parameters; Each DAC daughter board is provided with a voltage reference chip and a plurality of DAC output channels, and each DAC output channel performs the output parameter based on a reference voltage signal provided by the voltage reference chip; The FPGA motherboard is provided with a voltage compensation module, which compensates the output parameters executed by the DAC daughter board based on the reference voltage signal of each DAC, so that the voltage value of the output current of each channel remains consistent with the reference voltage signal; The total load of the reference voltage signal required by the DAC output channels of all DAC daughter boards is greater than the rated load of one of the voltage reference chips; The output parameter includes an output voltage, and the FPGA motherboard or the DAC daughterboard obtains an initial voltage code according to the output voltage and the nominal voltage value of the voltage reference chip; The voltage compensation module compensates the initial voltage code to obtain a compensated voltage code; The voltage compensation module compensates the initial voltage code according to the nominal voltage value of the voltage reference chip and the measured voltage value of the reference voltage signal to obtain a compensated voltage code; The compensation voltage coding is determined in the following manner: in, Indicates the compensation voltage code; Indicates the initial voltage code; Indicates the nominal voltage value; Indicates the measured voltage value; The output parameter is the compensation voltage code or comparison result ; The DAC sub-board determines the compensation voltage code according to the output parameter, converts the compensation voltage code into an analog signal, and controls the specified output channel to output a current having a voltage value represented by the compensation voltage code based on the obtained analog signal, and the adjusted voltage value maintains a preset proportional relationship.

2. The system according to claim 1, wherein: The total load of the reference voltage signal required by the DAC output channel of each DAC daughter board is equal to the rated load of one of the voltage reference chips.

3. The system according to claim 1, wherein: The nominal voltage value of the voltage reference chip of each DAC daughter board is set to a uniform value.

4. The system according to claim 1, wherein: The system includes an ADC module for measuring the actual voltage value of the reference voltage signal, and the number of bits of the ADC module is greater than 20.

5. The system according to claim 4, characterized in that The ADC module is provided on the FPGA motherboard, and each voltage reference chip is connected in parallel with the ADC module; The ADC module controls the reception of a reference voltage signal provided by a voltage reference chip in an on state based on a switch element.

6. The system according to claim 5, characterized in that The voltage reference chip in a non-connected state is grounded via a resistor having a similar resistance value to that of the ADC module.

7. The system according to claim 1, wherein: Each DAC daughter board is equipped with a temperature monitoring device; The temperature monitoring device is used to monitor the temperature of the voltage reference chip of the DAC daughter board on which the temperature monitoring device is disposed; if the monitored temperature change exceeds a preset temperature threshold, it triggers an update of the measured voltage value of the reference voltage signal disposed on the same DAC daughter board; If the monitored temperature change does not exceed the preset temperature threshold, the measured voltage value of the reference voltage signal arranged on the same DAC daughter board is used.

8. The system according to claim 1, wherein: The measured voltage value of the reference voltage signal of each DAC sub-board is obtained at a certain period, and the initial voltage encoding executed by the DAC sub-board is compensated using the latest measured voltage value of the reference voltage signal.

9. The system according to claim 8, characterized in that The period is set to be smaller than the shortest variation interval of the output parameters of the DAC output channels of all DAC sub-boards.

10. The system according to claim 9, characterized in that The system includes a system clock chip, and the period is generated based on a local clock signal provided by the system clock chip; The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

11. An ion trap quantum computing DC electrode system, characterized in that: A voltage control system comprising the multi-channel DC source according to any one of claims 1 to 10.

12. An ion trap quantum computing system, characterized in that: A voltage control system comprising the multi-channel DC source according to any one of claims 1 to 10.

Images