Asymmetric memory configuration method and device

Abstract

The embodiment of the invention provides an asymmetric memory configuration method and device, and relates to the technical field of memorizers, and the method comprises the following steps: obtaining configuration information of each memory port of a current memory; and for any memory port, determining the number of address cascades and the number of data cascades corresponding to each memory port according to the configuration information. Then determining to carry out data distribution according to the data bit width of each memory port and the number of data cascades corresponding to the memory port; and finally, distributing the initial value to the memories of each cascade according to the number of corresponding address cascade, thereby obtaining the asymmetrical double-end memory after optimal configuration. On the basis, the design complexity of the asymmetric double-end memory can be simplified, configuration of the number of address cascades and the number of data cascades needed by the two ends of the asymmetric double-end memory can be completed, the situation that in the prior art, inconsistency of multi-end address bit width and data bit width cannot be effectively processed is overcome, the resource utilization rate of the memory is increased, and the memory performance is improved. And occupation of chip resources is avoided.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an asymmetric memory configuration method and device. Background Art

[0002] Field-Programmable Gate Array (FPGA) chips contain a large number of logic units, digital signal processing (DSP) units, and memory resources. These memory resources can be used to implement various storage functions, such as first-input first-output (FIFO), cache, and register files. In FPGA design, random access memory (RAM) is the core resource for data caching and storage. FPGA chips typically have fixed-size RAM blocks with fixed capacity and port configuration (for example, 36Kb single-port / dual-port RAM).

[0003] Typically, when a user designs a memory requiring larger capacity or a more complex structure, it is achieved by cascading multiple random access memory blocks. At the same time, as demands for performance ratios increase, the demand for asymmetric dual-end random access memory is also increasing. However, existing memory cascading technology is mainly targeted at symmetric address dual-end memories, that is, where the address bit width and data bit width at both ends are the same. Due to the difference in the number of address cascades and data cascades required at both ends of an asymmetric dual-end memory, as well as the differences in the operations of address division, data allocation, and access control, existing cascading solutions are not compatible with implementing the functions of an asymmetric dual-end random access memory.

[0004] Based on this, there is an urgent need for a cascade configuration scheme for an asymmetric dual-terminal memory to overcome the problem that the existing technology cannot effectively handle the inconsistency between the address bit width and the data bit width at the two ends. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide an asymmetric memory configuration method and device. Taking an asymmetric dual-end memory as an example, the present invention can configure the number of address cascades and data cascades required at both ends of the asymmetric dual-end memory, while simplifying the design complexity of the asymmetric dual-end memory, thereby overcoming the problem in the prior art that it is unable to effectively handle the inconsistency of multi-end address bit width and data bit width, improve memory resource utilization, and avoid chip resource occupation.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0007] In a first aspect, the present invention provides an asymmetric memory configuration method. For any asymmetric memory, the configuration method includes:

[0008] Obtain configuration information of each memory port under the current memory; wherein the configuration information includes multiple data pairs, and each data pair includes an address configuration and a data configuration;

[0009] For any memory port, determine the number of address cascades and the number of data cascades corresponding to each memory port according to the configuration information;

[0010] Determine the bit mapping relationship between the memory ports according to the data bit width of each memory port and the number of data cascades corresponding to itself, and distribute data according to the bit mapping relationship;

[0011] The initial value is distributed to each cascade memory according to the address cascade number corresponding to each memory port, thereby obtaining an asymmetric dual-port memory after optimized configuration.

[0012] Optionally, the step of determining the number of address cascades and the number of data cascades corresponding to each memory port according to the configuration information includes:

[0013] Obtaining initial information of each memory port under the current memory; wherein the initial information includes address bit width and data bit width;

[0014] For any memory port, determine the target data pair that matches the current memory port from multiple data pairs based on its own address bit width;

[0015] Calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information;

[0016] The initial address cascade number and the initial data cascade number corresponding to each memory port are adjusted to obtain the final address cascade number and the final data cascade number, so that the effective storage capacity corresponding to each memory port is consistent.

[0017] Optionally, the step of determining a target data pair matching the current memory port from a plurality of data pairs according to its own address bit width includes:

[0018] Sort each memory port according to the value of its own address bit width from large to small, and number each memory port;

[0019] Sort each data pair from largest to smallest according to the value configured by its own address, and number each data pair;

[0020] A data pair with the same label as that corresponding to the memory port is selected from each data pair as the target data pair corresponding to the current memory port.

[0021] Optionally, when the asymmetric memory includes two data ports, the data ports include a first data port and a second data port; wherein the address bit width of the first data port itself is greater than the address bit width of the second data port itself; the step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information includes:

[0022] Determine the initial address cascade number and the initial data cascade number of the first data port according to the initial information of the first data port and the corresponding target data pair;

[0023] The initial address cascade number and the initial data cascade number are determined according to the initial information of the second data port and the corresponding target data pair.

[0024] Optionally, the step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information further includes:

[0025] Taking the initial address cascade number of the first data port as the final address cascade number;

[0026] Adjusting the number of initial address cascades in the second data port so that the final number of address cascades in the second data port is equal to the final number of address cascades in the first data port;

[0027] Determining the effective capacity corresponding to the second data port according to the final address cascade number of the second data port;

[0028] The number of data cascades corresponding to the first data port is adjusted according to the effective capacity corresponding to the second data port to obtain the final number of data cascades of the first data port.

[0029] Optionally, the calculation method of the number of cascaded initial addresses of the first data port satisfies:

[0030] A=2 |a-b| ;

[0031] Wherein, A is the number of cascaded initial addresses of the first data port; a is the address bit width of the first data port itself; b is the address configuration corresponding to the first data port; |.| is the absolute value operator;

[0032] The calculation method of the number of initial data cascades of the first data port satisfies:

[0033] B = c / d;

[0034] Among them, B is the initial data cascade number of the first data port; c is the data bit width of the first data port itself; and d is the data configuration corresponding to the first data port.

[0035] Optionally, the step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information further includes:

[0036] Determining the external chip select address of the first data port according to the address bit width of the first data port itself and the corresponding address configuration;

[0037] The external chip select address of the second data port is determined according to the external chip select address of the first data port, so that the number of address cascades of the first data port and the second data port is the same.

[0038] Optionally, the step of determining the external chip select address of the first data port according to the address bit width of the first data port and the corresponding address configuration includes:

[0039] Determine the difference between the address width of the first data port itself and the corresponding address configuration;

[0040] According to the order of high addresses from top to bottom, with the difference as the screening number, high address bits of the same number as the difference are screened from the first data port as the external chip select addresses of the first data port.

[0041] Optionally, when the configuration information includes two groups of matching data pairs, and the two groups of matching data pairs include a first matching data pair and a second matching data pair, the step of obtaining the configuration information of each memory port under the current memory includes:

[0042] Determine the upper and lower limits of the address bit width and the upper and lower limits of the data bit width based on the storage capacity of the current memory;

[0043] Matching the upper limit value of the address bit width with the lower limit value of the data bit width to obtain a first matching data pair;

[0044] The lower limit value of the address bit width is matched with the upper limit value of the data bit width to obtain a second matching data pair.

[0045] In a second aspect, the present invention further provides an electronic device comprising a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the asymmetric memory configuration method described in any one of the above-mentioned first aspects.

[0046] The asymmetric memory configuration method and device provided by the embodiments of the present invention have the following beneficial effects:

[0047] The present invention provides an asymmetric memory configuration method, which includes obtaining configuration information of each memory port under the current memory; for any memory port, determining the number of address cascades and the number of data cascades corresponding to each memory port based on the configuration information; determining the bit mapping relationship between the data bit widths of each memory port based on the data bit width of each memory port and the number of data cascades corresponding to itself, and performing data allocation based on the bit mapping relationship; allocating initial values to each cascade memory based on the number of address cascades corresponding to each memory port itself, thereby obtaining an optimized configured asymmetric dual-terminal memory. Based on this, taking the asymmetric dual-terminal memory as an example, the present invention can configure the number of address cascades and the number of data cascades required at both ends of the asymmetric dual-terminal memory, simplifying the design complexity of the asymmetric dual-terminal memory, thereby overcoming the problem in the prior art of being unable to effectively handle the inconsistency of the address bit widths and data bit widths of multiple terminals, while improving the utilization of memory resources and avoiding the occupation of chip resources.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 A flowchart showing the steps of the asymmetric memory configuration method provided by an embodiment of the present invention is shown;

[0051] Figure 2 A step-by-step flow chart of step 100 in an embodiment of the present invention is shown;

[0052] Figure 3 A step-by-step flow chart of step 200 in an embodiment of the present invention is shown;

[0053] Figure 4 A step-by-step flow chart of step 202 in an embodiment of the present invention is shown;

[0054] Figure 5 FIG1 shows one of the step-by-step flow charts of step 203 in an embodiment of the present invention;

[0055] Figure 6 FIG2 shows a second step-by-step flow chart of step 203 in an embodiment of the present invention;

[0056] Figure 7A step-by-step flow chart of step 2033 in an embodiment of the present invention is shown;

[0057] Figure 8 A schematic structural diagram of a server provided by an embodiment of the present invention is shown.

[0058] Icon: 10-Server. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0061] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0062] As described in the background technology, the existing memory cascading technology is mainly aimed at symmetric address dual-port RAM. For example, since the address bit width and data bit width at both ends of the symmetric address dual-port RAM are the same, the number of RAM blocks required for cascading can be calculated based on the configuration of the address bit width and data bit width of the chip RAM. However, for asymmetric dual-port RAM, the number of address cascades and data cascades required at both ends are different, and the operations of address division, data allocation and access control are also different. The existing cascading technology cannot meet the cascading needs of asymmetric address dual-port RAM at all.

[0063] Although the existing technology can realize the function of asymmetric dual-port RAM by utilizing logic circuits, it will lead to increased resource usage and increased design complexity.

[0064] Based on this, please refer to Figure 1 , Figure 1 A flowchart of an asymmetric memory configuration method provided by the present invention is shown. For any asymmetric memory, the method includes steps 100 to 400.

[0065] Step 100: Obtain configuration information of each memory port under the current memory.

[0066] The configuration information is used to represent the threshold value of the number of data lines and address lines corresponding to the current memory. In this embodiment, the configuration information includes multiple data pairs, and each data pair includes an address configuration and a data configuration.

[0067] Step 200: For any memory port, determine the number of address cascades and the number of data cascades corresponding to each memory port according to configuration information.

[0068] Step 300: Determine a bit mapping relationship between the data bit widths of each memory port according to the data bit width of each memory port and the number of data cascades corresponding to the memory port, and perform data allocation according to the bit mapping relationship.

[0069] Step 400 : Allocate initial values to memories of each cascade according to the number of address cascades corresponding to each memory port, thereby obtaining an asymmetric dual-port memory after optimized configuration.

[0070] In this embodiment, the asymmetric memory configuration method performs threshold configuration based on the threshold value of the number of data lines and address lines corresponding to the current memory, obtains the configuration information of each memory port under the current memory, and then adjusts the initial address bit width and initial data bit width corresponding to each memory port based on the configuration information, so that the effective capacity corresponding to each memory port is the same. After obtaining the corresponding number of address cascades and the number of data cascades, data is allocated based on the bit correspondence of the data bit width corresponding to each memory port, and the initial value is allocated to different RAM blocks based on the allocation of external chip select signals and data bit widths to ensure data consistency, thereby obtaining an asymmetric dual-end memory after optimized configuration. Based on this, the present invention provides an asymmetric memory configuration method that can meet the cascading needs of asymmetric address dual-end RAM, and overcome the problem that although the existing technology can realize the functions of asymmetric dual-end RAM through logic circuits, it will lead to increased resource occupation and increased design complexity.

[0071] In one possible implementation, since the chip memory capacity is fixed, the address width configuration and data width configuration have upper and lower limits. Based on this, please Figure 1 Based on the reference Figure 2 , Figure 21 is a flowchart of step 100 in this embodiment; step 100 in this embodiment includes steps 101 to 103.

[0072] Step 101: Determine upper and lower limits of address bit width and upper and lower limits of data bit width according to the storage capacity of the current memory.

[0073] Step 102: Match the upper limit value of the address bit width with the lower limit value of the data bit width to obtain a first matching data pair.

[0074] Step 103: Match the lower limit value of the address bit width with the upper limit value of the data bit width to obtain a second matching data pair.

[0075] It should be noted that in this embodiment, the upper limit of the address bit width corresponds to the lower limit of the data bit width, and the upper limit of the data bit width corresponds to the lower limit of the address bit width; based on this, the upper and lower limits of the address bit width and the upper and lower limits of the data bit width can be determined according to the storage capacity of the current memory, and the upper limit of the address bit width and the lower limit of the data bit width can be configured to obtain a first matching data pair; similarly, the lower limit of the address bit width and the upper limit of the data bit width are configured to obtain a second matching data pair.

[0076] This embodiment uses an asymmetric dual-port memory as an example. The upper limit of the address width is set to 14 and the lower limit is set to 10; the upper limit of the data width is set to 16 and the lower limit is set to 1. Correspondingly, the first matching data pair can be represented as (14, 1), and the second matching data pair can be represented as (10, 16). After obtaining the first and second matching data pairs, the data and address widths of the corresponding memory ports can be adjusted based on the corresponding configuration constraints in the matching data pairs.

[0077] After obtaining the configuration information of each memory port under the current memory, Figure 1 Based on the reference Figure 3 , Figure 3 A step-by-step flow chart of step 200 in this embodiment is shown, where step 200 includes steps 201 to 204 .

[0078] Step 201: Obtain initial information of each memory port under the current memory.

[0079] The initial information includes the address bit width and the data bit width.

[0080] Step 202: For any memory port, determine a target data pair that matches the current memory port from multiple data pairs based on its own address bit width.

[0081] Step 203 : Calculate the number of initial address cascades and the number of initial data cascades required by each memory port based on the target data pair of each memory port and its own initial information.

[0082] Step 204 : Adjust the initial address concatenation number and the initial data concatenation number corresponding to each memory port to obtain the final address concatenation number and the final data concatenation number, so as to make the effective storage capacity corresponding to each memory port consistent.

[0083] To facilitate understanding of the setting process in this embodiment, an asymmetric dual-port memory is taken as an example. For clarity of description, it is assumed that the asymmetric dual-port memory includes a first data port A and a second data port B. The initial information of each memory port under the current memory described in step 201 is the address bit width and data bit width corresponding to the first data port A, and the address bit width and data bit width corresponding to the second data port B. In this embodiment, the address bit width ADDR_A corresponding to the first data port A is set to 16, and the data bit width DATA_A is set to 2; the address bit width ADDR_B corresponding to the second data port B is set to 11, and the data bit width DATA_B is set to 64.

[0084] Based on this, please Figure 3 Based on the reference Figure 4 , Figure 4 A step-by-step flow chart of step 202 in this embodiment is shown. In this embodiment, step 202 includes steps 2021 to 2023.

[0085] Step 2021: Sort the memory ports from large to small according to the numerical value of their own address bit widths, and number the memory ports.

[0086] Step 2022: Sort each data pair from large to small according to the numerical value configured by its own address, and number each data pair.

[0087] Step 2023: Filter the data pairs with the same label as the corresponding memory port from each data pair as the target data pair corresponding to the current memory port.

[0088] For any memory port, this embodiment can match the data pair under the above configuration information by comparing its corresponding address bit width. For example, in the above asymmetric dual-port memory, the address bit width ADDR_A corresponding to the first data port A is larger than the address bit width ADDR_B corresponding to the second data port B. At this time, the first data port A can be matched with the data pair with the larger corresponding address configuration under the configuration information, that is, the first data port A corresponds to the first matching data pair; the second data port B corresponds to the second matching data pair, thereby obtaining the target data pair corresponding to each memory port.

[0089] At this time, the address bit width ADDR_A corresponding to the first data port A is 16, the data bit width DATA_A is 2, the address configuration CONFIG_ADDR_A is 14, and the data configuration CONFIG_DATA_A is 1; the address bit width ADDR_B corresponding to the second data port B is 11, the data bit width DATA_B is 64, the address configuration CONFIG_ADDR_B is 10, and the data configuration CONFIG_DATA_B is 16.

[0090] After matching the corresponding target data pair, please Figure 3 Based on the reference Figure 5 , Figure 5 A step-by-step flow chart of step 203 in this embodiment is shown; step 203 in this embodiment includes steps 2031 to 2032.

[0091] Step 2031: Determine the initial address cascade number and the initial data cascade number of the first data port according to the initial information of the first data port and the corresponding target data pair.

[0092] Step 2032: Determine the initial address concatenation number and the initial data concatenation number of the second data port according to the initial information of the second data port and the corresponding target data pair.

[0093] In this embodiment, please Figure 5 Based on the reference Figure 6 , Figure 6 Another sub-step flow chart of step 203 in this embodiment is shown; step 203 also includes step 2033 and step 2034.

[0094] Step 2033: Determine the external chip select address of the first data port according to the address bit width of the first data port and the corresponding address configuration.

[0095] Step 2034: Determine the external chip select address of the second data port according to the external chip select address of the first data port, so that the number of address cascades of the first data port and the second data port is the same.

[0096] In a possible implementation, in the above step 203 , the execution order of steps 2031 , 2032 and 2033 may be parallel execution, while the execution order of steps 2033 and 2034 may be sequential.

[0097] In this embodiment, please Figure 6 Based on the reference Figure 7 , Figure 7 A step-by-step flow chart of step 2033 in this embodiment is shown; step 2033 also includes step 2033-1 and step 2033-2.

[0098] Step 2033 - 1 : Determine the difference between the address bit width of the first data port itself and the corresponding address configuration.

[0099] Step 2033-2: In descending order of the high addresses, with the difference as the screening number, select the corresponding number of high address bits with the same difference as the address bit width in the first data port as the external chip select address of the first data port.

[0100] In this embodiment, the above execution method is specifically as follows:

[0101] Taking the asymmetric dual-port memory in the above embodiment as an example, taking the first data port as an example, the address bit width ADDR_A in this port is 16, and the data bit width DATA_A is 2; the corresponding configuration information is (14, 1). At this time, due to the difference between the address bit width corresponding to the first data port and the address bit width in the configuration information, the upper two bits of the address corresponding to the difference value can be used to construct an external chip select structure. That is, from the first data port, in descending order of high address, the difference is used as the screening number, and the corresponding number of high address bits within the address bit width of the first data port that are the same as the difference are screened as the external chip select address of the first data port. The above calculation process is expressed as: ADDR_A-CONFIG_ADDR_A=16-14=2.

[0102] Furthermore, in this embodiment, the calculation method of the number of cascaded initial addresses of the first data port satisfies:

[0103] A=2 |a-b| ;

[0104] Among them, A is the number of initial address cascades of the first data port; a is the address bit width of the first data port itself, that is, the above-mentioned ADDR_A; b is the address configuration corresponding to the first data port, that is, the above-mentioned CONFIG_ADDR_A; |.| is the absolute value operator.

[0105] The calculation method of the number of initial data cascades of the first data port satisfies:

[0106] B = c / d;

[0107] Among them, B is the initial data cascade number of the first data port; c is the data bit width of the first data port itself, that is, the above-mentioned DATA_A; d is the data configuration corresponding to the first data port, that is, the above-mentioned CONFIG_DATA_A.

[0108] Based on this, in this embodiment, the calculation process of the first data port address cascade number A (or ADDR_CASC_A) satisfies: ADDR_CASC_A=2 16-14=4; correspondingly, the calculation process of the number of data cascades B (or DATA_CASC_A) satisfies: DATA_CASC_A=2 / 1=2.

[0109] To ensure that the effective capacity of the first data port and the second data port are consistent, the number of address cascades between the first data port and the second data port can be made the same. It should be noted that in this case, the upper two bits of the second data port address must also be used to construct the external chip select structure. In this case, based on the above formula, the address cascade number ADDR_CASC_B of the second data port can be calculated to be 4, and the data cascade number DATA_CASC_B is 4. The above address cascade numbers and data cascade numbers are the initial address cascade numbers and initial data cascade numbers of the first data port itself, as described in this embodiment, and the initial address cascade numbers and initial data cascade numbers of the second data port itself.

[0110] After obtaining the initial data cascade number and address cascade number corresponding to the first data port and the second data port respectively, the address cascade number and final data cascade number corresponding to each data port can be further adjusted to make the effective storage capacity corresponding to each memory port consistent.

[0111] Specifically, after determining the number of address cascades corresponding to the first data port and the second data port respectively (that is, according to the above setting method, the ADDR_CASC_A and ADDR_CASC_B corresponding to the address cascade numbers of the first data port and the second data port of the asymmetric dual-port memory in this embodiment are both 4), since the configuration corresponding to the second data port in the current memory is (10, 16), according to the above calculation equation for the number of address cascades, the address configuration corresponding to the second data port should actually be (9, 16). At this time, the effective storage capacity of the second data port is only half of the storage capacity. In order to ensure that the effective storage capacity corresponding to each memory port is consistent, this embodiment can compare the initial data cascade numbers calculated in the first data port and the second data port, and use the initial data cascade number corresponding to the maximum value as the final data cascade number at both ends, that is, change the data cascade number DATA_CASC_A of the first data port from 2 to 4.

[0112] Furthermore, to ensure that the effective storage capacity corresponding to each memory port is consistent, a corresponding address bit in the high address can be selected as a control signal to adjust the writing of the two data inputs of the first data port. In this embodiment, the confirmation formula of the address bit L of the control signal can be expressed as: L = log2(DATA_B / (DATA_CASC_B / DATA_CASC_A)). Based on this, in this embodiment, the fifth bit of the address A in the first data port can be used as the control position to control the writing of the first data port.

[0113] In summary, in this embodiment, the final number of address cascades and the final number of data cascades corresponding to the first data port are both 4; the final number of address cascades and the final number of data cascades corresponding to the second data port are both 4. At this time, the total number of cascades of the current memory is 16.

[0114] In addition, this embodiment also provides a control bit acquisition method:

[0115] Determine the data expansion multiple M of the first data port. In this embodiment, the ratio between the final number of data concatenations of the first data port and the initial number of data concatenations may be used as the corresponding data expansion multiple. Based on this, the data expansion multiple of the first data port is 2.

[0116] At this time, the calculation formula for the start bit of the write control signal of the first data port satisfies: The number of bits satisfies the calculation formula: log2M. After substituting the values, we can see that the start bit of the write control signal of the first data port is 5 bits and the number of bits is 1. Based on this, the write control signal satisfies: That is, addr_A[4].

[0117] After determining the number of data cascades and address cascades corresponding to each memory port, data allocation needs to be performed. The implementation process of step 300 in this embodiment is as follows:

[0118] In this embodiment, the data bit width of the second data port is 64 bits, and the data bit width of the first data port is 2 bits. Since the number of cascades corresponding to the first and second data ports is 4, the RAMs in each cascade can be named R0 / RAM0, R0 / RAM1, R0 / RAM2, and R0 / RAM3. R0 / RAM0 is used as an example to represent the first address cascade position / first data cascade position. It should be noted that in this embodiment, data allocation and address cascade do not have a corresponding relationship, and the connection relationship between each level of address cascade is the same.

[0119] In one possible implementation, the bit mapping relationship between the data bit widths of the memory ports may be determined as follows:

[0120] The mapping relationship of the first data port is expressed as:

[0121] The i-th data bit data_A[i] under the first data port corresponds to [RAM iM ,RAM (i+1)M-1 ], M represents the data expansion multiple.

[0122] It can be understood that the second data bit data_A[1] under the first data port corresponds to the third data cascade position RAM2 and the fourth data cascade position RAM3, which is expressed as: data_A[1]→[RAM2, RAM3]).

[0123] Similarly, the first data bit data_A[0] under the first data port corresponds to the first data cascade position RAM0 and the second data cascade position RAM1, which is expressed as: data_A[1]→[RAM0, RAM1]).

[0124] The mapping relationship between the second data port and the first data port satisfies:

[0125] Use the serial number corresponding to the data bit under the second data port to modulo the data bit width under the first data port, then use the modulo value to divide the data configuration value corresponding to the first data port, and then determine the RAM serial number in the first data port that needs to be connected based on the quotient value.

[0126] For example, data bit 15 of the second data port, data_B

[15] , corresponds to data bit 1 of the first data port, data_A[1], and is connected to the third data concatenation position RAM2 and the fourth data concatenation position RAM3.

[0127] The implementation process of step 400 in this embodiment is as follows:

[0128] The initial value of the original asymmetric dual-port memory is expressed as INITVAL[2 16 *2-1:0]. Since there are four address cascades, the initial value can be divided into four parts to correspond to the four address cascades. The initial value is assigned to one end, for example, the first data port. In this case, the initial value corresponding to the Nth bit (data_A[N]) in the first data port can be expressed as: INITVAL[n:0]%DATA_A; where % is the modulo calculation formula. Based on this, each RAM is assigned an initial value at the original data_A location according to the data input of the connected first data port A.

[0129] Based on this, the present invention provides an asymmetric memory configuration method, which relates to the field of memory technology. The method includes: obtaining the configuration information of each memory port under the current memory; for any memory port, determining the number of address cascades and the number of data cascades corresponding to each memory port based on the configuration information. Then, data allocation is determined based on the data bit width of each memory port and the number of data cascades corresponding to itself; finally, the initial value is allocated to each cascade memory based on the corresponding number of address cascades to obtain an asymmetric dual-end memory after optimized configuration. Based on this, the present invention can simplify the design complexity of the asymmetric dual-end memory, complete the configuration of the number of address cascades and the number of data cascades required at both ends of the asymmetric dual-end memory, overcome the problem in the prior art that it is unable to effectively handle the inconsistency of the address bit width and data bit width of multiple terminals, improve the utilization rate of memory resources, and avoid the occupation of chip resources.

[0130] Following the same principle as the previous embodiment, the present invention further provides an electronic device comprising a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the asymmetric memory configuration method described in any one of the first aspects above, namely: obtaining configuration information of each memory port under the current memory; for any memory port, determining the number of address cascades and the number of data cascades corresponding to each memory port based on the configuration information. Then, data allocation is determined based on the data bit width of each memory port and the number of data cascades corresponding to itself; finally, initial values are allocated to each cascaded memory based on the corresponding number of address cascades, thereby obtaining an optimized asymmetric dual-port memory.

[0131] The same idea as the previous embodiment, please refer to Figure 8 , Figure 8 A block diagram of a server in this embodiment is shown. The server includes a memory, a processor, and a communication module. The memory, processor, and communication module are electrically connected to each other, directly or indirectly, to enable data transmission or exchange. For example, these components can be electrically connected via one or more communication buses or signal lines.

[0132] The memory is used to store programs or data. The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0133] The processor is used to read / write data or programs stored in the memory and execute corresponding functions.

[0134] The communication module is used to establish a communication connection between the server and other communication terminals through the network, and to send and receive data through the network.

[0135] It should be understood that Figure 8 The structure shown is only a schematic diagram of the server structure, and the server may also include Figure 8 More or fewer components than shown, or with Figure 8 Different configurations shown. Figure 8 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0137] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0138] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0139] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An asymmetric memory configuration method, characterized in that: For any asymmetric memory, the asymmetric memory configuration method includes: Obtaining configuration information of each memory port under the current memory; wherein the configuration information includes a plurality of data pairs, and any of the data pairs includes an address configuration and a data configuration; For any memory port, determining the number of address cascades and the number of data cascades corresponding to each memory port according to the configuration information; Determining a bit mapping relationship between the memory ports according to the data bit width of each memory port and the number of data cascades corresponding to the memory port, and allocating data according to the bit mapping relationship; The initial value is distributed to each cascade memory according to the number of address cascades corresponding to each memory port itself, thereby obtaining an asymmetric dual-port memory after optimized configuration.

2. The asymmetric memory configuration method according to claim 1, wherein: The step of determining the number of address cascades and the number of data cascades corresponding to each of the memory ports according to the configuration information includes: Acquire initial information of each memory port under the current memory; wherein the initial information includes address bit width and data bit width; For any memory port, determine a target data pair that matches the current memory port from the multiple data pairs according to its own address bit width; Calculating the number of initial address cascades and the number of initial data cascades required for each memory port according to the target data pair of each memory port and its own initial information; The initial address cascade number and the initial data cascade number corresponding to each of the memory ports are adjusted to obtain a final address cascade number and a final data cascade number, so that the effective storage capacity corresponding to each of the memory ports is consistent.

3. The asymmetric memory configuration method according to claim 2, wherein: The step of determining a target data pair matching the current memory port from the multiple data pairs based on the address bit width of the memory port comprises: Sort the memory ports according to the numerical values of their own address bit widths from large to small, and number the memory ports; Sort the data pairs from largest to smallest according to the numerical values configured at their addresses, and number the data pairs; A data pair with the same label as that corresponding to the memory port is selected from each of the data pairs as a target data pair corresponding to the current memory port.

4. The asymmetric memory configuration method according to claim 2 or 3, characterized in that: When the asymmetric memory includes two data ports, the data ports include a first data port and a second data port; wherein the address bit width of the first data port is greater than the address bit width of the second data port; the step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information includes: Determining the initial address concatenation number and the initial data concatenation number of the first data port according to the initial information of the first data port and the corresponding target data pair; The initial address cascade number and the initial data cascade number of the second data port are determined according to the initial information of the second data port and the corresponding target data pair.

5. The asymmetric memory configuration method according to claim 4, wherein: The step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information further includes: Taking the initial address cascade number of the first data port as the final address cascade number; Adjusting the number of initial address cascades in the second data port so that the final number of address cascades in the second data port is equal to the final number of address cascades in the first data port; determining an effective capacity corresponding to the second data port according to the final address cascade number of the second data port; The number of data cascades corresponding to the first data port is adjusted according to the effective capacity corresponding to the second data port to obtain the final number of data cascades of the first data port.

6. The asymmetric memory configuration method according to claim 4, wherein: The calculation method of the number of cascaded initial addresses of the first data port satisfies: A＝2 |a-b| ； Wherein, A is the number of cascaded initial addresses of the first data port; a is the address bit width of the first data port itself; b is the address configuration corresponding to the first data port; |.| is the absolute value operator; The calculation method of the number of initial data cascades of the first data port satisfies: B = c / d; Among them, B is the initial data cascade number of the first data port; c is the data bit width of the first data port itself; and d is the data configuration corresponding to the first data port.

7. The asymmetric memory configuration method according to claim 4, wherein: The step of calculating the number of initial address cascades and the number of initial data cascades required for each memory port based on the target data pair of each memory port and its own initial information further includes: determining an external chip select address of the first data port according to an address bit width of the first data port and a corresponding address configuration; The external chip select address of the second data port is determined according to the external chip select address of the first data port, so that the number of address cascades of the first data port and the second data port is the same.

8. The asymmetric memory configuration method according to claim 7, wherein: The step of determining the external chip select address of the first data port according to the address bit width of the first data port and the corresponding address configuration includes: Determine a difference between an address bit width of the first data port itself and a corresponding address configuration; In order of high addresses from top to bottom, with the difference as the screening number, high address bits of the same number as the difference are screened from the first data port as the external chip select addresses of the first data port.

9. The asymmetric memory configuration method according to claim 1, wherein: When the configuration information includes two groups of matching data pairs, and the two groups of matching data pairs include a first matching data pair and a second matching data pair, the step of obtaining the configuration information of each memory port under the current memory includes: Determining upper and lower limits of the address bit width and upper and lower limits of the data bit width according to the storage capacity of the current memory; Matching the upper limit value of the address bit width with the lower limit value of the data bit width to obtain the first matching data pair; The lower limit value of the address bit width is matched with the upper limit value of the data bit width to obtain the second matching data pair.

10. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the asymmetric memory configuration method according to any one of claims 1 to 9.

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