Server and server control method

Abstract

The present application discloses a server and a control method for the server, relating to the technical field of servers, comprising a memory, a controller, a processor and a switch; the memory comprises a first storage space, a second storage space and a third storage space, the first storage space storing a control program, the second storage space storing a processing program, and the third storage space storing a backup processing program; the controller is used to establish a first data transmission link with the memory through the switch after power-on, and read the control program through the first data transmission link; if it is determined through the control program that the processing program has no abnormality or that the processing program has an abnormality but the backup processing program has no abnormality, a second data transmission link is established between the processor and the memory through the switch; the processor is used to read the processing program or the backup processing program through the second data transmission link, thereby solving the technical problems of high cost and large size of the server.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a server and a method for controlling the server. Background Art

[0002] With the development of server technology, servers are typically equipped with a central processing unit (CPU), a complex programmable logic device (CPLD), and at least three memories. When the server is powered on, the CPLD can access its external memory to read the corresponding program. The CPU can first access its external main memory to read the corresponding program. If an exception occurs in the program stored in the main memory, the CPU can also access its external backup memory to read the corresponding program, thereby achieving power-on.

[0003] In this way, at least three memories need to be provided in the server, resulting in a higher cost and a larger size of the server. Summary of the Invention

[0004] The present application provides a server and a method for controlling the server to at least solve the problem of high cost and large size of the server in the related art.

[0005] A first aspect of the present application provides a server, comprising: a memory, a controller, a processor, and a switch, wherein the switch is communicatively connected to the memory, the controller, and the processor, respectively, and the controller is further communicatively connected to the processor;

[0006] The memory includes a first storage space, a second storage space and a third storage space, the first storage space is used to store the control program, the second storage space is used to store the processing program, and the third storage space is used to store the backup processing program;

[0007] The controller is configured to establish a first data transmission link with the memory through the switch after power-on, and read the control program through the first data transmission link; if the control program determines that the processing program has not been abnormal or the processing program has been abnormal but the backup processing program has not been abnormal, establish a second data transmission link between the processor and the memory through the switch;

[0008] The processor is configured to read the processing program through the second data transmission link if no exception occurs in the processing program, and to read the backup processing program through the second data transmission link if no exception occurs in the processing program but no exception occurs in the backup processing program.

[0009] A second aspect of the present application further provides a server control method, which is applied to the controller in the server of the first aspect, wherein the method includes:

[0010] After power-on, a first data transmission link is established with the memory through the switch, and a control program is read through the first data transmission link;

[0011] If the control program determines that the processing program has no exception or the processing program has an exception but the backup processing program has no exception, a second data transmission link is established between the processor and the memory through the switch to control the processor to read the processing program or the backup processing program through the second data transmission link.

[0012] According to the present application, the server includes a memory, a controller, a processor and a switch, the switch is communicatively connected to the memory, the controller and the processor respectively, and the controller is also communicatively connected to the processor; the memory includes a first storage space, a second storage space and a third storage space, the first storage space is used to store the control program, the second storage space is used to store the processing program, and the third storage space is used to store the backup processing program; the controller is used to establish a first data transmission link with the memory through the switch after power-on, and read the control program through the first data transmission link, if it is determined through the control program that the processing program has no exception or the processing program has an exception but the backup processing program has no exception, establish a second data transmission link between the processor and the memory through the switch; the processor is used to read the processing program through the second data transmission link if the processing program has no exception, and read the backup processing program through the second data transmission link if the processing program has an exception but the backup processing program has no exception. It can be seen that by adopting the above technical solution, the control program, the processing program and the backup processing program can be stored in the same memory, and the controller can control the processor to read the backup processing program when an exception occurs in the processing program. In this way, there is no need to disperse the control program, the processing program and the backup processing program in three different memories as in the related art. In this way, the number of memories configured in the server can be reduced, and the technical problem of high server cost and large size can be solved, thereby achieving the technical effect of reducing server cost and reducing server size. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic diagram of the structure of a server provided for related technologies;

[0015] Figure 2A schematic diagram of the structure of a server provided in an embodiment of the present application;

[0016] Figure 3 A schematic diagram of the structure of another server provided in an embodiment of the present application;

[0017] Figure 4 A flow chart of a method for controlling a server provided in an embodiment of the present application;

[0018] Figure 5 A flowchart of an example of server control provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0021] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0022] Research has found that servers are usually equipped with a central processing unit (CPU), a complex programmable logic device (CPLD), and at least three memories. For example, Figure 1 A schematic diagram of the structure of a server provided for related technologies, such as Figure 1As shown in the figure, when the server boots up, the CPLD accesses its external memory (i.e., FLASH2) via the Serial Peripheral Interface (SPI) bus to read the corresponding program. The CPU then accesses its external main memory (i.e., FLASH0) via the SPI bus to read the stored program. If the program stored in the main memory fails, the CPU can also access its external backup memory (i.e., FLASH1) via the SPI bus to read the corresponding program, thereby booting the server. The SPI bus has four signal lines: MOSI, MISO, SCLK, and CS. MOSI and MISO are data lines, SCLK is the clock line, and CS is the chip select line. The signal transmitted on CS determines which memory the SPI bus accesses. This requires at least three memory devices in the server, resulting in high server cost and size. Furthermore, in the early stages of debugging, to facilitate program debugging, a base is soldered to the memory when processing the server's single board. The memory is then placed in the base. When the memory needs to be re-burned, the memory is removed from the base and placed in a jig for burning. This requires at least three bases for the memory on the single board, which also results in high server costs and a large size. After the online upgrade function is implemented, the memory can be directly soldered to the single board instead of the base when processing the server. This is especially true after official mass production, when the base must be removed to prevent user misoperation. If the program corresponding to the CPU or CPLD needs to be upgraded after mass production, it can be upgraded online after powering on. However, users may encounter situations where the system freezes halfway through the upgrade or the power is accidentally cut off during the upgrade, making it impossible to use the online upgrade. Therefore, when returning the system for repair, the memory must first be removed from the single board for offline burning and then soldered, significantly increasing repair time and cost.

[0023] Based on the above problems, this application proposes a server that uses a single memory to implement redundant design and online upgrade. For example, Figure 2 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. Figure 1 As shown, the server includes: a memory 110, a controller 120, a processor 130 and a switch 140, the switch 140 is respectively connected to the memory 110, the controller 120 and the processor 130, and the controller 120 is also connected to the processor 130;

[0024] The memory 110 includes a first storage space, a second storage space, and a third storage space. The first storage space is used to store the control program, the second storage space is used to store the processing program, and the third storage space is used to store the backup processing program.

[0025] The controller 120 is configured to establish a first data transmission link with the memory 110 through the switch 140 after power-on, and read the control program through the first data transmission link. If the control program determines that the processing program has not experienced an abnormality, or that the processing program has experienced an abnormality but the backup processing program has not experienced an abnormality, a second data transmission link is established between the processor 130 and the memory 110 through the switch 140.

[0026] The processor 130 is configured to read the processing program through the second data transmission link if the processing program is normal, and read the backup processing program through the second data transmission link if the processing program is abnormal but the backup processing program is normal.

[0027] Specifically, the memory 110 can be any device with a storage function. For example, Figure 3 A schematic diagram of another server structure provided in an embodiment of the present application is shown in FIG. Figure 2 and Figure 3 As shown, the memory 110 may be FLASH. Of course, the memory 110 may also be EEPROM, etc., but is not limited thereto.

[0028] It should be noted that the specific sizes of the first, second, and third storage spaces may be set by those skilled in the art based on practical circumstances and are not limited herein. Furthermore, the specific sizes of the first, second, and third storage spaces may be fixed or dynamically variable (e.g., the size of the first storage space may vary with the size of the control program stored therein, the size of the second storage space may vary with the size of the processing program stored therein, and the size of the third storage space may vary with the size of the backup processing program stored therein). This application does not impose any limitations on this.

[0029] Specifically, the controller 120 is a hardware control unit of the server, focusing on hardware management and control tasks (such as power on and off sequence control). For example, the controller 120 can be a CPLD (such as Figure 3 As shown), of course, the controller 120 can also be FPGA, etc., but is not limited to this.

[0030] Specifically, the control program is data written by a developer to define the internal logical functions of the controller 120 , that is, it specifies how to implement a specific digital circuit design on the programmable resources of the controller 120 .

[0031] Specifically, the processor 130 is the core processing unit of the server, focusing on executing software instructions and processing various computing tasks. Figure 2 and Figure 3 As shown, the processor 130 may be a CPU. Currently, the processor may also be an ARM, etc., but is not limited thereto.

[0032] Specifically, a processing program is a set of software instructions written by a developer that is loaded and executed by processor 130 upon startup to perform specific functions or computing tasks. Exemplary processing programs include, but are not limited to, Basic Input / Output System (BIOS).

[0033] The “backed-up processing program” stored in the third storage space is a backup of the “processing program” in the second storage space.

[0034] Specifically, the switch 140 is used to selectively establish a data transmission link with the memory 110 between the processor 130 and the controller 120 .

[0035] It should be noted that the specific link type of the data transmission link can be set by those skilled in the art according to actual conditions and is not limited here. For example, the link type of the data transmission link may include an SPI link (such as Figure 3 as shown), or II2C link, etc., but is not limited to these.

[0036] It should also be noted that there are many specific implementations of "selectively establishing a data transmission link with the memory 110 between the processor 130 and the controller 120". The following is an explanation of a typical example, but it does not constitute a limitation of this application. For example, the switch 140 can receive an external selection signal (such as Figure 3 As shown) or according to a preset logic, the connection relationship between the processor 130 and the memory 110, and the controller 120 and the memory 110 is switched to ensure that only one device (the processor 130 or the controller 120) can access the memory 110 at the same time.

[0037] Accordingly, the present application provides a server control method, which is applied to the controller 120 in the server. Figure 4 A flow chart of a method for controlling a server provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the method includes:

[0038] S110 , after power-on, establishing a first data transmission link with the memory through the switch, and reading the control program through the first data transmission link.

[0039] Specifically, after the server is powered on, the switch 140 can establish a data transmission link (i.e., a first data transmission link) between the controller 120 and the memory 110. In this way, the controller 120 can access the first storage space of the memory 110 through the first data transmission link to read the control program.

[0040] S120. If the control program determines that the processing program has no abnormality or the processing program has an abnormality but the backup processing program has no abnormality, a second data transmission link is established between the processor and the memory through the switch to control the processor to read the processing program or the backup processing program through the second data transmission link.

[0041] Specifically, when the controller 120 runs the control program, the control program causes the controller 120 to perform the following steps: determine whether an abnormality occurs in the processing program stored in the second storage space; if no abnormality occurs in the processing program, establish a second data transmission link between the processor 130 and the memory 110 through the switch 140, and control the processor 130 to read the processing program through the second data transmission link; if an abnormality occurs in the processing program, determine whether an abnormality occurs in the backup processing program in the third storage space; if no abnormality occurs in the backup processing program, establish a second data transmission link between the processor 130 and the memory 110 through the switch 140, and control the processor 130 to read the backup processing program through the second data transmission link.

[0042] It should be noted that there are many specific implementation methods of "determining whether an exception occurs in a processing program" and "determining whether an exception occurs in a backup processing program". Typical examples are described below, but they do not constitute a limitation on this application.

[0043] In some embodiments, determining whether the processing program is abnormal includes: the controller 120 reading the processing program in the second storage space and detecting whether the processing program is abnormal through static code analysis or other methods. Similarly, determining whether the backup processing program is abnormal includes: the controller 120 reading the backup processing program in the third storage space and detecting whether the backup processing program is abnormal through static code analysis or other methods.

[0044] In other embodiments, the control program includes first verification information of the processing program;

[0045] The first storage space is further configured to store second verification information of the processing program. The controller 120 is further configured to read the second verification information after reading the control program via the first data transmission link. If the first verification information and the second verification information are the same, it is determined that no abnormality has occurred in the processing program. Otherwise, it is determined that an abnormality has occurred in the processing program.

[0046] The second storage space is also used to store the third verification information of the backup processing program. The controller 120 is also used to read the third verification information after determining that an abnormality has occurred in the processing program. If the first verification information and the third verification information are the same, it is determined that the backup processing program has not occurred an abnormality; otherwise, it is determined that an abnormality has occurred in the backup processing program.

[0047] Specifically, the verification information is used to verify the integrity, security and / or uniqueness of the processing program. Exemplarily, the first verification information may include a checksum, CRC, or Hash, but is not limited thereto.

[0048] The first verification information is verification information of a processing program that has been successfully debugged by a developer.

[0049] The second verification information is the verification information of the “processing program actually stored” in the second storage space after the “processing program successfully debugged” is written into the second storage space.

[0050] The third verification information is verification information of the “processing program actually stored (used as a backup)” in the third storage space after the “processing program successfully debugged” is written into the third storage space.

[0051] Accordingly, S120 includes: reading the second inspection information, and if the first inspection information and the second inspection information are the same, determining that no abnormality occurs in the processing program; otherwise, determining that an abnormality occurs in the processing program;

[0052] If the processing program does not have an abnormality, a second data transmission link is established between the processor 130 and the memory 110 through the switch 140, and the processor 130 is controlled to read the processing program through the second data transmission link;

[0053] If the backup processing program is abnormal, the third verification information is read, and if the first verification information and the third verification information are the same, it is determined that the backup processing program is not abnormal, otherwise it is determined that the backup processing program is abnormal;

[0054] If the backup processing program does not have any abnormality, a second data transmission link is established between the processor 130 and the memory 110 through the switch 140, and the processor 130 is controlled to read the backup processing program through the second data transmission link.

[0055] Specifically, since the control program includes the first verification information, the controller 120 can extract the first verification information therefrom. Furthermore, the controller 120 can access the second storage space to read the second verification information. Furthermore, the controller 120 compares the consistency of the first verification information with the second verification information to determine whether the processing program stored in the second storage space has an anomaly.

[0056] Specifically, if the processing program does not have an abnormality, the switch 140 can establish a data transmission link (i.e., a second data transmission link) between the processor 130 and the memory 110. In this way, the processor 130 can access the second storage space through the second data transmission link to read the processing program.

[0057] Specifically, if the backup processing program is abnormal, the controller 120 can access the third storage space to read the third verification information, and then compare the consistency of the first verification information and the third verification information to determine whether the backup processing program stored in the third storage space is abnormal.

[0058] Specifically, if the backup processing program does not have an abnormality, the switch 140 can establish a second data transmission link between the processor 130 and the memory 110, so that the processor 130 can access the third storage space through the second data transmission link to read the backup processing program.

[0059] It can be understood that by checking the information to determine whether the handler and the backup handler have an abnormality, the controller 120 does not need to read the entire handler and the backup handler and perform anomaly detection. In this way, the anomaly detection of the handler and the backup handler can be simpler, more efficient and convenient.

[0060] Optional, such as Figure 2 As shown, the server further includes an alarm 150 , which is in communication with the controller 120 ;

[0061] The controller 120 is further configured to control the alarm 150 to sound an alarm when an abnormality occurs in the confirmed processing program and / or an abnormality occurs in the backup processing program.

[0062] Specifically, the specific implementation of the alarm 150 can be set by those skilled in the art according to actual conditions and is not limited here. Figure 2 and Figure 3 As shown, the alarm 150 may include an LED. Of course, the alarm 150 may also include a buzzer, etc., but is not limited thereto.

[0063] Accordingly, the method further includes: after determining that the processing program is abnormal, controlling the alarm 150 to sound an alarm;

[0064] And / or, after determining that the backup processing program is abnormal, the alarm device 150 is controlled to sound an alarm.

[0065] Optionally, the alarm modes when the processing program and the backup processing program are abnormal are different. In this way, it is easy to distinguish whether the current abnormality occurs in the processing program or the backup processing program.

[0066] Specifically, the specific differences in the alarm modes can be set by those skilled in the art according to actual circumstances and are not limited here. For example, if the alarm 150 includes an LED, the lighting pattern and / or lighting duration of the LED may be different when an abnormality occurs in the processing program and an abnormality occurs in the backup processing program; if the alarm 150 includes a buzzer, the beeping pattern and / or beeping duration of the buzzer may be different when an abnormality occurs in the processing program and an abnormality occurs in the backup processing program, but the present invention is not limited thereto.

[0067] In the embodiment of the present application, the control program, the processing program and the backup processing program can be stored in the same memory 110, and the controller 120 can control the processor 130 to read the backup processing program when an abnormality occurs in the processing program. In this way, there is no need to disperse the control program, the processing program and the backup processing program in three different memories 110 as in the related art. In this way, the number of memories 110 configured in the server can be reduced, and the technical problem of high server cost and large size can be solved, thereby achieving the technical effect of reducing server cost and reducing server size.

[0068] In other embodiments of the present application, Figure 2 As shown, the controller 120 includes a first communication interface and a second communication interface, and the first communication interface and the second communication interface are both communicatively connected to the switch 140;

[0069] When the controller 120 establishes a first data transmission link with the memory 110 through the switch 140 after power-on, the controller 120 is configured to establish a first data transmission link between the first communication interface and the memory 110 through the switch 140 after power-on;

[0070] When the controller 120 reads the second inspection information, the controller 120 is configured to establish a third data transmission link between the second communication interface and the memory 110 through the switch 140 and read the second inspection information through the third data transmission link;

[0071] When the controller 120 reads the third verification information, the controller 120 is configured to read the third verification information through the third data transmission link.

[0072] Specifically, the specific types of the first communication interface and the second communication interface can be set by those skilled in the art according to actual conditions and are not limited here. For example, the first communication interface includes SPI (such as Figure 3 As shown), SPI simulated by GPIO, or IIC, etc., the second communication interface includes SPI, SPI simulated by GPIO (as shown Figure 3 As shown), or IIC, etc., but not limited to these.

[0073] Optional, such as Figure 2As shown, the controller 120 further includes a third communication interface, which is communicatively connected to the switch 140;

[0074] The third communication interface is used to output a selection signal, and the selection signal is used to control the switch 140 to switch among the first data transmission link, the second data transmission link, and the third data transmission link.

[0075] Exemplarily, when the selection signal is LL, the switch 140 establishes the first data link, when the selection signal is HL, the switch 140 switches to the third data link, and when the selection signal is HH, the switch 140 switches to the third data link, but is not limited thereto.

[0076] It is understood that clearly distinguishing between the first communication interface for reading the control program and the second communication interface for reading the verification information helps simplify the software design and debugging process of the controller 120. Furthermore, when reading the verification information, the risk of malicious tampering of the control program can be prevented to a certain extent. Similarly, when reading the control program, the risk of malicious tampering of the verification information can be prevented to a certain extent.

[0077] In another embodiment of the present application, the controller 120 is also used to establish a first data transmission link with the memory 110 through the switch 140 during the online upgrade of the control program, and write the upgrade data of the control program into the first storage space through the first data transmission link.

[0078] Specifically, the upgrade data of the control program is used to update the new version data content of the control program, with the purpose of allowing the controller 120 to have new functions, fix known problems, or improve performance and safety.

[0079] Accordingly, the method further includes: during the online upgrade process of the control program, establishing a first data transmission link with the memory 110 via the switch 140, and writing the upgrade data of the control program into the first storage space via the first data transmission link.

[0080] Optionally, the controller 120 is further configured to establish a second data transmission link between the processor 130 and the memory 110 via the switch 140 during an online upgrade of the processing program;

[0081] The processor 130 is configured to write the upgraded data of the processing program into the second storage space and the third storage space through the second data transmission link.

[0082] Specifically, the upgrade data of the control program is used to update the new version data content of the processing program, with the purpose of allowing the processor 130 to have new functions, fix known problems, or improve performance and security.

[0083] Accordingly, the method further includes: establishing a second data transmission link between the processor 130 and the memory 110 via the switch 140 during the online upgrade of the processing program;

[0084] The control processor 130 writes the upgrade data of the processing program into the second storage space and the third storage space through the second data transmission link.

[0085] Optionally, after the processing program is upgraded online, a first data transmission link is established with the memory 110 through the switch 140, and the first inspection information in the control program is updated through the first data transmission link, wherein the updated first inspection information is the inspection information of the upgraded processing program.

[0086] It is understandable that by setting up online upgrades for control programs and processing programs, users do not need to return to the factory for repairs to achieve upgrades, and once the control programs and processing programs have new functions, performance improvements or security patches released, users can immediately upgrade online, reducing waiting time and improving user experience.

[0087] In another embodiment of the present application, Figure 2 and Figure 3 As shown, the server further includes a test terminal 160, which is communicatively connected to the memory 110;

[0088] The test terminal 160 is used to transfer the upgrade data of the control program provided by the peripheral device to the first storage space during the offline upgrade process of the control program;

[0089] The test terminal 160 is further used to transfer the upgrade data of the processing program provided by the peripheral device to the second storage space and the third storage space during the offline upgrade process of the processing program.

[0090] Specifically, the test terminal 160 may be connected to the memory 110 via a PCB trace or a jumper, but is not limited thereto.

[0091] Optionally, the test terminal 160 includes a pad, a jumper pin, etc., but is not limited thereto.

[0092] It is understandable that in the early debugging stage or when returning to the factory for repair later, the burner (i.e., peripheral device) can be connected to the test terminal 160 so that the burner can burn the upgrade data of the control program and / or processing program into the memory 110. In this way, there is no need to set up a base on the single board of the server, further saving server area and cost.

[0093] The following describes in detail the server control method provided in this application with reference to a specific example. Figure 5 A flow chart of an example of server control provided in an embodiment of the present application is shown as follows: Figure 3 and Figure 5As shown, when the server boots up, the default select signal is low (LL). The switch opens the first data transmission link. The CPLD pulls the CS pin of SPI0 low to load the control program stored in the first memory space of the Flash. The CPLD then sets the select signal to HL, and the switch switches to the third data transmission link. The CPLD pulls the CS pin of the GPIO-emulated SPI (GPIO_SPI) low to read the checksum (second verification information) stored in the second memory space of the Flash and compares it with the checksum (first verification information) extracted from the control program. If the first and second verification information match, the processing program stored in the second memory space is normal. The CPLD then transmits the address of the processing program in the second memory space to the CPU via the IIC bus and sets the select signal high (HH). The switch switches to the second data transmission link, and the CPU loads the processing program stored in the second memory space. If the first and second verification information differ, the processing program stored in the second memory space has an error. The CPLD then reads the checksum (third verification information) stored in the third memory space of the Flash and compares it with the checksum (first verification information) extracted from the control program. If the first and third verification information match, the backup program stored in the third memory space is normal. The CPLD then transmits the corresponding address of the backup program in the third memory space to the CPU via the IIC bus and sets the select signal high (HH). The SWITCH then switches to the second data transmission link, and the CPU loads the backup program from the third memory space. If the first and third verification information differ, the backup program stored in the third memory space is abnormal. The CPLD illuminates an LED to alert the operator that the program and the backup program are abnormal and require factory repair or offline flash programming. Furthermore, the first data transmission link can also be used for online program upgrades: the CPLD controls the SWITCH to open the first data transmission link, and the CPLD writes the control program upgrade data to the first memory space of the flash memory by pulling the CS pin of SPI0 low. The second data transmission link can also be used for online program upgrades: the CPU notifies the CPLD via the IIC bus that an online upgrade is required. The CPLD sets the select signal high (HH), and the CPU writes the program upgrade data to the second and third memory spaces of the flash memory.In addition, test points (i.e., test terminals) are added to the server to facilitate offline burning of FLASH for offline upgrading of control programs and processing programs. Specifically, parallel traces are drawn from both sides or one side of the FLASH, and small-sized test terminals are added to these traces. In this way, during the early debugging stage or later maintenance, the burner can be connected to the DuPont line, and a robot arm or other personnel can be used to assist in contacting the DuPont line with the test terminal to achieve offline upgrading. No base is required, which further saves server space and saves costs.

[0094] The embodiments of the present application utilize hardware circuits and software programs to implement online upgrades and offline programming of processing and control programs, resulting in simple operation. A single FLASH memory allows for CPU firmware redundancy, significantly reducing costs. Furthermore, the provision of test terminals allows for offline programming after mass production or during maintenance, facilitating both early stage FLASH debugging and later maintenance, saving maintenance time, difficulty, and costs.

[0095] Professionals may further appreciate that the algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0096] The above is a detailed introduction to a server and a method for controlling the server provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A server, characterized in that: include: A memory, a controller, a processor, and a switch, wherein the switch is communicatively connected to the memory, the controller, and the processor respectively, and the controller is also communicatively connected to the processor; The memory includes a first storage space, a second storage space, and a third storage space, wherein the first storage space is used to store a control program, the second storage space is used to store a processing program, and the third storage space is used to store a backup processing program; The controller is configured to establish a first data transmission link with the memory through the switch after power-on, and read the control program through the first data transmission link; if it is determined through the control program that the processing program has not been abnormal or that the processing program has been abnormal but the backup processing program has not been abnormal, establish a second data transmission link between the processor and the memory through the switch; The processor is configured to read the processing program through the second data transmission link if no exception occurs in the processing program, and read the backup processing program through the second data transmission link if no exception occurs in the processing program but no exception occurs in the backup processing program; The control program includes first inspection information of the processing program; The first storage space is further configured to store second verification information of the processing program, and the controller is further configured to read the second verification information after reading the control program via the first data transmission link, and determine that no abnormality has occurred in the processing program if the first verification information and the second verification information are the same; otherwise, determine that an abnormality has occurred in the processing program; The second storage space is further configured to store third verification information of the backup processing program, and the controller is further configured to read the third verification information after determining that an abnormality occurs in the processing program, and if the first verification information and the third verification information are the same, determine that no abnormality occurs in the backup processing program; otherwise, determine that an abnormality occurs in the backup processing program; The controller includes a first communication interface and a second communication interface, wherein the first communication interface and the second communication interface are both communicatively connected to the switch; When the controller establishes the first data transmission link with the memory through the switch after power-on, the controller is used to establish the first data transmission link between the first communication interface and the memory through the switch after power-on; When the controller reads the second verification information, the controller is configured to establish a third data transmission link between the second communication interface and the memory through the switch, and read the second verification information through the third data transmission link; When the controller reads the third verification information, the controller is configured to read the third verification information through the third data transmission link.

2. The server according to claim 1, wherein: The controller further includes a third communication interface, wherein the third communication interface is communicatively connected to the switch; The third communication interface is used to output a selection signal, and the selection signal is used to control the switch to switch among the first data transmission link, the second data transmission link, and the third data transmission link.

3. The server according to claim 1, wherein: Also included is an alarm, the alarm being communicatively connected to the controller; The controller is further configured to control the alarm to sound an alarm when it is confirmed that an abnormality occurs in the processing program and / or an abnormality occurs in the backup processing program.

4. The server according to claim 3, wherein: The alarm modes when an abnormality occurs in the processing program and an abnormality occurs in the backup processing program are different.

5. The server according to claim 1, wherein: The controller is further configured to establish the first data transmission link with the memory through the switch during the online upgrade of the control program, and write the upgrade data of the control program into the first storage space through the first data transmission link.

6. The server according to claim 1, wherein: The controller is further configured to establish the second data transmission link between the processor and the memory via the switch during an online upgrade of the processing program; The processor is configured to write the upgrade data of the processing program into the second storage space and the third storage space through the second data transmission link.

7. The server according to claim 1, wherein: Also comprising a test terminal, the test terminal being communicatively connected to the memory; The test terminal is used to transfer the upgrade data of the control program provided by the external device to the first storage space during the offline upgrade process of the control program; The test terminal is further used to transfer the upgrade data of the processing program provided by the peripheral device to the second storage space and the third storage space during an offline upgrade process of the processing program.

8. The server according to claim 7, wherein: The test terminal includes a solder pad or a jumper pin.

9. A method for controlling a server, characterized in that: A controller applied to a server according to any one of claims 1 to 8, wherein the method comprises: After power-on, a first data transmission link is established with the memory through the switch, and a control program is read through the first data transmission link; If it is determined through the control program that the processing program has not had an abnormality or that the processing program has had an abnormality but the backup processing program has not had an abnormality, a second data transmission link is established between the processor and the memory through the switch to control the processor to read the processing program or the backup processing program through the second data transmission link.

10. The method according to claim 9, characterized in that The control program includes first verification information of the processing program, the first storage space is further used to store second verification information of the processing program, and the second storage space is further used to store third verification information of the backup processing program; If it is determined through the control program that the processing program has not been abnormal or the processing program has been abnormal but the backup processing program has not been abnormal, establishing a second data transmission link between the processor and the memory through the switch to control the processor to read the processing program or the backup processing program through the second data transmission link includes: reading the second verification information, and determining that no abnormality occurs in the processing program if the first verification information and the second verification information are the same; otherwise, determining that an abnormality occurs in the processing program; If no abnormality occurs in the processing program, establishing the second data transmission link between the processor and the memory through the switch, and controlling the processor to read the processing program through the second data transmission link; If an exception occurs in the processing program, the third verification information is read, and if the first verification information and the third verification information are the same, it is determined that no exception occurs in the backup processing program; otherwise, it is determined that an exception occurs in the backup processing program; If the backup processing program does not have any abnormality, the second data transmission link is established between the processor and the memory through the switch, and the processor is controlled to read the backup processing program through the second data transmission link.

11. The method according to claim 9, characterized in that The server further includes an alarm, and the alarm is communicatively connected to the controller, wherein the method further includes: After determining that the processing program is abnormal, controlling the alarm to sound an alarm; And / or, after determining that the backup processing program is abnormal, controlling the alarm to sound an alarm.

12. The method according to claim 9, characterized in that Also includes: During the online upgrade process of the control program, the first data transmission link between the switch and the memory is established, and the upgrade data of the control program is written into the first storage space through the first data transmission link.

13. The method according to claim 9, characterized in that Also includes: During the online upgrade of the processing program, establishing the second data transmission link between the processor and the memory through the switch; The processor is controlled to write the upgrade data of the processing program into the second storage space and the third storage space through the second data transmission link.

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