Cache management method, electronic device, medium and product

Abstract

The present application provides a cache management method, electronic device, medium and product, which relate to the field of computer technology. When at least one target page requested by a read request is part of a first target data block in a first queue, the at least one target page is combined into a second target data block with a smaller data volume and stored in a second first target queue, so that the first target data block of the first target queue includes the remaining first pages except for the at least one first target page, thereby splitting the first target data block with a larger data volume and storing it in different queues. Since the data block with a smaller data volume is more likely to be hit, the present application can achieve efficient utilization of cache space.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to cache management methods, electronic devices, media, and products. Background Art

[0002] To improve SSD performance and lifespan, SSDs typically include a smaller but faster-access dynamic random-access memory (DRAM) as a data cache. By identifying and caching hot data, some I / O (Input / Output) requests from applications can be absorbed by the data cache, eliminating the need to access the underlying flash memory chips. This speeds up user access and reduces flash operations.

[0003] In related technologies, cache management methods generally only refer to temporal and spatial locality when performing hot and cold data separation. This cache management method has the problem of low utilization efficiency of limited cache space. Summary of the Invention

[0004] The present application provides a cache management method, electronic device, medium and product to at least solve the problem of low cache space utilization efficiency in related technologies.

[0005] The present application provides a cache management method, comprising: receiving a target request;

[0006] In a case where the target request is a read request, determining at least one first target page requested by the target request;

[0007] If at least one first target page is stored in the first queue, determining a first target data block to which the at least one first target page belongs, the first target data block including a plurality of first pages, and the at least one first target page being a portion of the plurality of first pages;

[0008] It is determined that at least one first target page in the first target data block constitutes a second target data block, and the second target data block is stored in a second queue.

[0009] The present application also provides a cache management device, comprising:

[0010] A receiving module, used for receiving a target request;

[0011] A first determining module, configured to determine at least one first target page requested by the target request when the target request is a read request;

[0012] a second determining module, configured to determine, if at least one first target page is stored in the first queue, a first target data block to which the at least one first target page belongs, the first target data block including a plurality of first pages, the at least one first target page being a portion of the plurality of first pages;

[0013] The third determining module is configured to determine that at least one first target page in the first target data block constitutes a second target data block, and store the second target data block in the second queue.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned cache management method when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned cache management method are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned cache management method when executed by a processor.

[0017] In an embodiment of the present application, when at least one target page requested by a read request is part of the first target data block in the first queue, the at least one target page is combined into a second target data block with a smaller data volume and stored in the second first target queue, so that the first target data block of the first target queue includes the remaining first pages except for the at least one first target page, thereby realizing the splitting of the first target data block with a larger data volume and storing it in different queues. Since data blocks with a smaller data volume are more easily hit, the present application can achieve efficient utilization of cache space. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of a cache management method provided for related technologies;

[0020] Figure 2 A schematic diagram of another cache management method provided for related technologies;

[0021] Figure 3 An application scenario diagram of a cache management method provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a cache management method provided in an embodiment of the present application Figure 1 ;

[0023] Figure 5 A schematic diagram of a data block in a cache provided in an embodiment of the present application Figure 1 ;

[0024] Figure 6 A schematic diagram of a data block in a cache provided in an embodiment of the present application Figure 2 ;

[0025] Figure 7 A schematic diagram of a data block in a cache provided in an embodiment of the present application Figure 3 ;

[0026] Figure 8 A schematic diagram of a data block in a cache provided in an embodiment of the present application Figure 3 ;

[0027] Figure 9 A schematic diagram of a cache management method provided in an embodiment of the present application Figure 2 ;

[0028] Figure 10 A schematic diagram of a data block in a cache provided in an embodiment of the present application Figure 4 ;

[0029] Figure 11 A schematic diagram of a cache management method provided in an embodiment of the present application Figure 3 ;

[0030] Figure 12 A schematic diagram of data block merging provided in an embodiment of the present application;

[0031] Figure 13 A schematic diagram of the structure of a cache management device provided in an embodiment of the present application;

[0032] Figure 14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0035] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, processing, transmission, provision, disclosure and application of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0036] Flash-based solid-state drives are typically equipped with a dynamic random access memory (DRAM) to cache hot-write data. When data access from users is localized, the corresponding data request can be directly absorbed by the DRAM cache. When the cache is full, the cache management mechanism selects and ejects some cached data to make room for new user data. Depending on the granularity of data page organization in the cache, SSD cache management solutions in related technologies can be divided into cache management based on page granularity and cache management based on data block granularity.

[0037] One cache management method is to use page as the granularity, refer to Figure 1 , the head of the queue inserts a page, and the tail of the queue pops up a page, where if a page needs to be popped up, block 0 page 2, block i represents the identifier of the data block i, page j represents the identifier of the page j, block i page j represents page j in the data block i, and i and j are both integers greater than or equal to 0. It can be understood that since the page is the most basic read and write unit in the solid-state drive, cache management with page granularity can accurately identify the access status and locality of each page, which is conducive to improving the cache hit rate. However, this cache management with page granularity is not convenient for utilizing the spatial locality between multiple pages, so it is difficult to combine temporal locality and spatial locality for cache management.

[0038] Another cache management method is based on the data block granularity, refer to Figure 2, the head of the queue inserts the data block, and the tail of the queue pops the data block, wherein, if the data block needs to be popped, block 3 is popped. It can be understood that the cache in the solid-state drive usually performs garbage collection and erase operations at the granularity of data blocks, and each cache block contains multiple pages. In order to optimize the efficiency of garbage collection and utilize the spatial locality of data, the relevant technology proposes a cache management scheme with block granularity. This type of scheme organizes the cache pages belonging to the same data block into a data block. When a page in the cache is accessed, the entire data block will be moved to the head of the queue, thereby making full use of the spatial locality between pages in the same data block. However, with the development of storage technology, the number of pages that a single data block can accommodate has increased significantly, resulting in the possibility that the same data block contains both hot pages and cold pages. Due to the large granularity of the data block granularity management strategy, cold pages will occupy cache space, thereby reducing the cache hit rate and ultimately affecting the overall cache performance. Reference Figure 2 , which is a schematic diagram of cache management based on data blocks in related technologies.

[0039] Based on the above problems, the cache management solutions based on page granularity and data block granularity mainly refer to time locality and space locality, and do not take into account the data access characteristics of users and applications themselves. For example, cached pages from small requests are more likely to be accessed repeatedly, while pages from large requests are less accessed in the cache. In order to utilize this data access feature, the present application considers time locality, space locality, and request size in a coordinated manner, and splits the first target data blocks with larger data volumes and stores them in different queues. Since data blocks with smaller data volumes are more likely to be hit, the present application can achieve efficient utilization of cache space.

[0040] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0041] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the cache management method depends, the specific application environment architecture or specific hardware architecture is described here. Figure 3 , Figure 3 This is an example diagram of the application scenario of the cache management method. Figure 3 A schematic diagram of the structure of a solid-state drive (SSD) is shown. The SSD includes flash memory and a cache. The flash memory is used for non-volatile data storage, and the cache is used to temporarily store frequently accessed data. Data ejected from the cache is stored in the flash memory. This application is applied to cache management to improve cache space utilization efficiency.

[0042] Figure 4 A flowchart of a cache management method is shown, which specifically includes the following steps:

[0043] S401, receiving a target request.

[0044] The target request is an I / O request sent by a program or an operating system to the solid-state drive. The I / O request can be a read request or a write request.

[0045] S402 : When the target request is a read request, determine at least one first target page requested by the target request.

[0046] In some embodiments, determining at least one first target page requested by the target request includes: determining the target logical page number of each first target page in the at least one first target page; determining a target physical address having a mapping relationship with the target logical page number based on the mapping relationship between the physical address and the logical page number in the metadata; and determining at least one page at the target physical address as the first target page.

[0047] It can be understood that when the target request is a read request, the target request can carry at least one target logical page number, and the target logical page number and the target physical address of the first target page have a one-to-one mapping relationship. The mapping relationship between each physical address and the logical page number is stored in the metadata, and then the target physical address can be confirmed according to the target logical page number, and then the first target page can be determined according to the target physical address.

[0048] In the embodiment of the present application, when an operation needs to be performed on the first target page, the first target page can be obtained through the mapping relationship stored in the metadata, and further corresponding operations, such as modification or deletion operations, can be performed.

[0049] S403 : If at least one first target page is stored in the first queue, determine the first target data block to which the at least one first target page belongs.

[0050] The first target data block includes a plurality of first pages, and at least one first target page is a portion of the plurality of first pages.

[0051] Reference Figure 5 , three queues can be set in the cache, namely the first queue, the second queue and the third queue, wherein the first queue includes multiple first data blocks, such as the first data block a1 (including page P M , page P M+1 , page P M+2 and page P M+3 ), the first data block a2 (including page P k , page P k+3 and page P k+4 ) and the first data block a3 (including page P R+3 and page P R+4The second queue includes multiple second data blocks, such as the second data block b1 (including page P k+1 and page P k+2 ) and the second data block b2 (including page P R , page P R+1 and page P R+2 The third queue includes multiple third data blocks, such as the third data block c1 (including page P A , page P A+1 ), the third data block c2 (including page P B ) and the third data block c3 (including page P c and page P c+1 ).

[0052] For example, if at least one first target page includes: page P M and page P M+1 , then the first target data block is determined to be the first data block a1, wherein the first data block a1 includes a plurality of first pages, namely page P M , page P M+1 , page P M+2 and page P M+3 .

[0053] In some embodiments, if the at least one first target page is all first pages in the first target data block, for example, the at least one first target page includes: page P M , page P M+1 , page P M+2 and page P M+3 , all first pages in the first target data block can be returned to the program.

[0054] S404 , determining that at least one first target page in the first target data block constitutes a second target data block, and storing the second target data block in a second queue.

[0055] The first target data block includes the remaining first pages except for the at least one first target page.

[0056] Reference Figure 6 , if at least one first target page includes: page P M , page P M+1 and page P M+2 , you can put the page P M , page P M+1 and page P M+2 , combined into the second target data block M1, the second target data block M1 is inserted into the second queue from the queue head of the second queue. At this time, the first target data block (first data block a1) includes page P M+3 .

[0057] In some embodiments, storing the second target data block in the second queue includes: storing the second target data block in the second queue when a first number of at least one first target page is greater than or equal to a page threshold, for example, when the page threshold is 3, if the at least one first target page includes: page P M , page P M+1 and page P M+2 , you can refer to Figure 6 , insert the second target data block M1 into the second queue from the queue head of the second queue.

[0058] Furthermore, the method further includes: storing the second target data block in the third queue when the first number is less than the page threshold. For example, if the page threshold is 3, if at least one first target page includes: page P M and page P M+1 , you can refer to Figure 7 , insert the second target data block M1 from the queue head of the third queue into the third queue. At this time, the first target data block (data block a1) includes page P M+2 and page P M+3 .

[0059] In the embodiment of the present application, the page threshold may be predefined or calculated in real time, and is not limited here. It is understood that the present application may store the second target data block in the second queue or the third queue according to the number of pages included in the second target data block.

[0060] It can be understood that when the first target data block in the first queue is hit (ie, a page in the first target data block is hit), it can be moved to the second queue or the third queue according to the number of pages included in the first target data block.

[0061] In some embodiments, the page threshold can be determined by: obtaining the average data volume of a preset number of historical write requests; obtaining the average page hit ratio of a preset number of popped-up data blocks, where the popped-up data blocks are popped from the third queue; obtaining the first data volume of a page; and determining the page threshold based on the average data volume, the average page hit ratio, and the first data volume.

[0062] It is understood that the preset number can be 1024 or other values, and there is no limitation on this. The historical write request is the write request closest to the current time. For example, there are n historical write requests, and the amount of data written corresponding to the kth historical write request is T k , k ranges from 0 to n, then the average data volume can be expressed as S1=(T1+T2+ … +T n ) / n.

[0063] Furthermore, the number of pages included in the qth popped data block is m, wherein the qth popped data block has g pages hit in the history, then the hit ratio of the qth popped data block is R q =g / m, and then we can get the average page hit ratio R1=(R1+ R2+ … + R n ) / n, where q ranges from 1 to n.

[0064] In addition, the first data size of each page in the cache is fixed, such as 4 kB.

[0065] In an embodiment of the present application, determining a page threshold based on the average data volume, the average page hit ratio, and the first data volume includes: determining a second product of the average data volume and the average page hit ratio; and determining the ratio of the second product to the first data volume as the page threshold. Specifically, refer to the following expression (1):

[0066] (1)

[0067] In expression (1), Indicates the page threshold, Indicates the first data amount.

[0068] In an embodiment of the present application, a dynamic page threshold can be maintained, thereby improving cache management efficiency.

[0069] In some embodiments, it also includes: if at least one first target page is stored in the second queue, determining the fourth target data block to which the at least one first target page belongs, the fourth target data block includes multiple fourth pages, and at least one first target page is a partial fourth page among the multiple fourth pages; determining a fifth target data block composed of at least one first target page, and storing the fifth target data block in the third queue.

[0070] It can be understood that, at this time, the fourth target data block includes the remaining fourth page except for the at least one first target page.

[0071] For example, refer to Figure 5 , if at least one first target page includes: page P R and page P R+1 , then the fourth target data block is determined to be the second data block a2, wherein the second data block a2 includes a plurality of fourth pages, namely pages P R , page P R+1 and page P R+2 .

[0072] Reference Figure 8, if at least one first target page includes: page P R and page P R+1 , you can put the page P R and page P R+1 , combined into the fifth target data block M2, the second target data block M2 is inserted into the third queue from the queue head of the third queue, at this time, the fourth target data block (second data block b2) includes page P R+2 .

[0073] exist Figure 8 In the process, when the third queue is full, the third data block c3 at the tail of the third queue can be popped out.

[0074] In some embodiments, if the at least one first target page is all fourth pages in the fourth target data block, for example, the at least one first target page includes: page P R , page P R+1 and page P R+2 , all first pages in the fourth target data block can be returned to the program.

[0075] In summary, when reading data from the cache, the present application can split the hit page from the original data block when a data block in the first or second queue is hit, forming a new data block stored in the other queue. This can achieve efficient cache utilization, namely improving the hit rate of data blocks in the cache, thereby reducing I / O response time. In addition, the cache management method of the present application not only utilizes the spatial locality between multiple pages, but also avoids the problem of space waste caused by the excessive number of pages in the data block.

[0076] Further, refer to Figure 9 In the case where the target request is a write request, the cache management method provided by the present application further includes the following steps:

[0077] S901: Determine a third target data block to be written by a target request.

[0078] The third target data block includes: at least one third page.

[0079] It can be understood that in the embodiment of the present application, the target request is used to request to write the third target data block in the cache.

[0080] For example, in Figure 5 Based on the reference Figure 10 The third target data block M3 includes at least one third page, and the at least one third page includes: page P w and page P w+1 .

[0081] S902 : When the second number of at least one third page is greater than or equal to the page threshold, store the third target data block in the first queue.

[0082] The method for determining the page threshold may refer to the above embodiment and will not be described in detail here.

[0083] In some embodiments, storing the third target data block in the first queue includes: inserting the third target data block at the head of the first queue.

[0084] It can be understood that the present application inserts the third target data block into the first queue from the queue head of the first queue.

[0085] S903 : When the second number is smaller than the page threshold, store the third target data block in the third queue.

[0086] In some embodiments, storing the third target data block in the third queue includes: inserting the third target data block at the head of the third queue.

[0087] It can be understood that the present application inserts the third target data block into the third queue from the queue head of the third queue.

[0088] In an embodiment of the present application, write data blocks with different page numbers can be stored in different queues, which can improve cache management efficiency.

[0089] In some embodiments, third target data blocks with any number of pages may be stored in the first queue to improve data writing efficiency.

[0090] In summary, when a write request arrives, a third target data block will be created for it. This third target data block contains all the third pages belonging to the write request. The created third target data block will be inserted into the queue head of the first queue or the third queue. Since the third pages included in a third target data block all come from the same write request, the amount of data requested can be determined based on the number of pages in the third target data block. This is different from the cache management based on data block granularity in the related art, which uses logical data blocks to group written pages and store them in the cache, and cannot confirm the amount of data requested.

[0091] Further, refer to Figure 11 The cache management method provided in this application also includes the following steps:

[0092] S1101: Determine at least one first target queue that has reached an upper capacity limit.

[0093] In some embodiments, the first target queue reaching the upper capacity limit means that the storage space of the first target queue is full.

[0094] In some other embodiments, the first target queue reaching the upper capacity limit means that a data block is to be stored in the first target queue, but the storage space of the first target queue is insufficient. Figure 5 ,If a data block containing 5 pages needs to be written into the ,first queue, but the first queue has only 4 pages of free space, it is ,determined that the first queue has reached its capacity ,limit.

[0095] In some embodiments, the at least one first target queue is at least one of a first queue, a second queue, and a third queue.

[0096] Understandable, refer to Figure 5 The number of at least one first target queue may be 1, 2 or 3. For example, the number of at least one first target queue is 2, and the at least one first target queue includes: a first queue and a third queue.

[0097] S1102 : For each first target queue of at least one first target queue, determine a sixth target data block at the tail of the first target queue.

[0098] For example, refer to Figure 5 The at least one first target queue includes: a first queue and a third queue. For the first target queue, the first queue has the sixth target data block a3. For the first target queue, the third queue has the sixth target data block c3.

[0099] S1103: If at least one seventh target data block is stored in the second target queue, combine the sixth target data block and the at least one seventh target data block to obtain an eighth target data block.

[0100] The sixth target data block and the at least one seventh target data block belong to data blocks written by the same write request.

[0101] In the embodiment of the present application, the number of the second target queues may be one or more, and the second target queue may be the same as or different from the first target queue.

[0102] For example, refer to Figure 5 , one of the target queues is the first queue, the sixth target data block of the first queue is the first data block a3, the sixth target data block and the second data block b2 in the second queue are from the data blocks written by the same write request. It can be understood that the second data block b2 is a data block split from the first data block a3, then the first data block a3 and the second data block b2 are combined to obtain the eighth target data block M4. Figure 12 .

[0103] S1104: If at least one seventh target data block is not stored in the second target queue, determine the sixth target data block as the eighth target data block.

[0104] It can be understood that in the cache, the write request corresponding to the sixth target data block only writes the pages contained in the sixth target data block, and the sixth target data block is not split into other data blocks. Therefore, it can be determined that the sixth target data block is the eighth target data block.

[0105] For example, refer to Figure 5 If the first target queue is the third queue, the sixth target data block is the third data block c3, and the third data block c3 can be confirmed as the eighth target data block M5. Figure 12 .

[0106] S1105, pop up the eighth target data block.

[0107] In an embodiment of the present application, the popped-up eighth target data block can be stored in the flash memory, and then the pages included in the eighth target data block can be deleted from the cache to make room for storing the newly written pages.

[0108] It can be understood that the cache management of the present application uses a cache pop-up mechanism based on data blocks, that is, one data block is selected each time and all the pages in it are popped out. This mechanism can write multiple pages to the flash memory at one time, which is conducive to utilizing the parallelism of multiple channels in the solid-state drive.

[0109] In some embodiments, if the number of the eighth target data blocks is greater than 1, popping out the eighth target data block includes: determining a popping order of the plurality of eighth target data blocks; and sequentially popping out the plurality of eighth target data blocks according to the popping order.

[0110] It is understandable that only one eighth target data block is popped up at a time, referring to Figure 12 , the cache needs to pop out the eighth target data block M4 and the eighth target data block M5, then it is necessary to determine the popping order of the eighth target data block M4 and the eighth target data block M5, and then pop them out in sequence, for example, first pop out the eighth target data block M4, and then pop out the eighth target data block M5.

[0111] In some embodiments, determining the pop-up order of multiple eighth target data blocks includes: determining the access frequency of the eighth target data block for each eighth target data block of the multiple eighth target data blocks; and determining the pop-up order based on the access frequency, wherein the access frequency and the pop-up order are positively correlated.

[0112] In the embodiment of the present application, the lower the access frequency, the higher the priority of popping out, so that the eighth target data block with high access frequency can be stored in the cache for a longer time, thereby improving the cache hit rate.

[0113] In some embodiments, the number of times the eighth target data block is accessed per unit time in the cache may be determined as the access frequency.

[0114] In some embodiments, determining the access frequency of the eighth target data block of the first target queue includes: obtaining the total number of times the eighth target data block is hit; obtaining the number of pages included in the eighth target data block; determining the most recent hit time and current time of the eighth target data block; and determining the access frequency of the eighth target data block based on the total number of times, the number of pages, the hit time and the current time.

[0115] In the embodiment of the present application, the eighth target data block being hit means that at least one page in the eighth target data block is hit. Figure 12 , a read request accesses only page P in the eighth target data block M4 R+3 and page P R+4 , it can be understood that the read request hits the eighth target data block M4.

[0116] For example, refer to Figure 12 The number of pages included in the eighth target data block M4 is 5, and the number of pages included in the eighth target data block M5 is 2.

[0117] In some embodiments, the access frequency of the eighth target data block is determined based on the total number of times, the number of pages, the hit moment and the current moment, including: obtaining a preset pop-up time rate and a pop-up time interval; determining a first product of the pop-up time rate and the pop-up time interval; determining a time difference between the hit moment and the current moment; determining a first value based on the first product, the number of pages and the time difference; and determining the ratio of the total number of times to the first value as the access frequency.

[0118] In this embodiment of the present application, the ejection time rate is a preset value, and the range of the ejection time rate is [0, 1]. The ejection time interval is also preset and refers to the ejection interval between two consecutive eighth target data blocks. For example, if the eighth target data block M4 is ejected first and then the eighth target data block M5 is ejected, the ejection interval between the eighth target data block M4 and the eighth target data block M5 is the preset ejection time interval.

[0119] In some embodiments, the access frequency of each eighth target data block may be determined by the following expression (2):

[0120] (2)

[0121] In expression (2), Indicates the frequency of access, Indicates the total number of times, Indicates the current moment, Indicates the hitting moment, Indicates the number of pages, Indicates the pop-up time rate, Indicates the pop-up time interval. represents the first product, Indicates the time difference. Indicates the first value.

[0122] Based on expression (2), we can understand the ejection time rate The larger the value, the smaller the access frequency and the higher the priority of popping out of the cache. Further, it can be understood that the access frequency obtained based on expression (2) is It takes into account the time discount factor.

[0123] In an embodiment of the present application, if one of the data blocks is not hit for a long time or has a low hit frequency, and the data block is at the end of the queue, it can be popped out of the cache according to the access frequency.

[0124] In the embodiment of the present application, the access frequency may also be determined by other methods, which are not limited here.

[0125] In summary, the cache management method of the present application supports cache popping based on the granularity of the data blocks written by the write request, and provides a method for merging the data blocks of the same write request and then popping them. Specifically, the data blocks in the third queue or the second queue may be split data blocks. When some data blocks are selected to be popped out of the cache, the remaining pages of the original data blocks before the split or the split pages may still be inserted into other queues. Figure 5 As shown, when the first data block a3 in the first queue is selected to be popped out of the cache, the second data block b2 split out of the second queue is still in the second queue. This application confirms that when a page in a data block is a cold page, the pages in other data blocks that belong to the same write request are also cold pages. For example, referring to Figure 5 If the page in the first data block a3 is a cold page, it can be determined that the page in the second data block b2 is also a cold page. Therefore, the two data blocks are re-merged into the original complete data block and finally popped out of the cache together, thereby realizing the page popping of the complete data block.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0127] Figure 13 This is a schematic diagram of the structure of the cache management device provided in the embodiment of the present application. Figure 13As shown, the embodiment of the present application further provides a cache management device, the cache management device 130 may include: a receiving module 131, a first determining module 132, a second determining module 133 and a third determining module 134, wherein:

[0128] Receiving module 131, used for receiving a target request;

[0129] A first determining module 132 is configured to determine at least one first target page requested by the target request when the target request is a read request;

[0130] a second determining module 133 configured to determine, if at least one first target page is stored in the first queue, a first target data block to which the at least one first target page belongs, the first target data block including a plurality of first pages, the at least one first target page being a portion of the plurality of first pages;

[0131] The third determining module 134 is configured to determine that at least one first target page in the first target data block constitutes a second target data block, and store the second target data block in the second queue.

[0132] Optionally, the third determining module 134 is specifically configured to:

[0133] storing a second target data block in a second queue if a first number of at least one first target page is greater than or equal to a page threshold;

[0134] The device also includes:

[0135] The storage module (not shown in the figure) is configured to store the second target data block in the third queue when the first number is less than the page threshold.

[0136] Optionally, when the target request is a write request, the apparatus further includes:

[0137] A fourth determining module (not shown in the figure) is configured to determine a third target data block to be written by the target request, the third target data block including: at least one third page;

[0138] The storage module is further configured to: store the third target data block in the first queue when the second number of at least one third page is greater than or equal to the page threshold; and store the third target data block in the third queue when the second number is less than the page threshold.

[0139] Optionally, the device further comprises:

[0140] An acquisition module (not shown in the figure) is used to obtain an average data volume of a preset number of historical write requests; obtain an average page hit ratio of a preset number of ejected data blocks, where the ejected data blocks are ejected from the third queue; obtain a first data volume of a page; and determine a page threshold based on the average data volume, the average page hit ratio, and the first data volume.

[0141] Optionally, the second determining module 133 is further configured to:

[0142] If the at least one first target page is stored in the second queue, determining a fourth target data block to which the at least one first target page belongs, the fourth target data block including a plurality of fourth pages, and the at least one first target page being a portion of the fourth pages;

[0143] A fifth target data block consisting of at least one first target page is determined, and the fifth target data block is stored in a third queue.

[0144] Optionally, also include:

[0145] a fifth determining module (not shown in the figure), configured to determine at least one first target queue that has reached its upper capacity limit, where the at least one first target queue is at least one of the first queue, the second queue, and the third queue; and, for each of the at least one first target queues, determine a sixth target data block at the tail of the first target queue.

[0146] a combining module (not shown in the figure), configured to combine the sixth target data block and the at least one seventh target data block to obtain an eighth target data block if at least one seventh target data block is stored in the second target queue, the sixth target data block and the at least one seventh target data block being data blocks written by the same write request;

[0147] a fifth determining module, further configured to determine that the sixth target data block is the eighth target data block if at least one seventh target data block is not stored in the second target queue;

[0148] The pop-up module (not shown in the figure) is used to pop-up the eighth target data block.

[0149] Optionally, if the number of the eighth target data block is greater than 1, a module is popped up, specifically configured to:

[0150] determining an order in which the plurality of eighth target data blocks are to be popped;

[0151] According to the popping order, a plurality of eighth target data blocks are popped out in sequence.

[0152] Optionally, determining the popping order of the plurality of eighth target data blocks includes:

[0153] determining, for each eighth target data block of the plurality of eighth target data blocks, an access frequency of the eighth target data block;

[0154] The pop-up order is determined according to the access frequency, wherein the access frequency and the pop-up order are positively correlated.

[0155] Optionally, when determining the access frequency of the eighth target data block, the pop-up module is specifically configured to:

[0156] Obtain the total number of times the eighth target data block is hit;

[0157] Obtaining the number of pages included in the eighth target data block;

[0158] Determining the most recent hit time of the eighth target data block and the current time;

[0159] The access frequency of the eighth target data block is determined according to the total number of times, the number of pages, the hit time and the current time.

[0160] Optionally, when the pop-up module determines the access frequency of the eighth target data block according to the total number of times, the number of pages, the hit time, and the current time, it is specifically configured to:

[0161] Get the preset pop-up time rate and pop-up time interval;

[0162] determining a first product of the ejection time rate and the ejection time interval;

[0163] Determine the time difference between the hit moment and the current moment;

[0164] determining a first value according to the first product, the number of pages, and the time difference;

[0165] The ratio of the total number of times to the first value is determined as the access frequency.

[0166] Optionally, when the storage module is used to store the third target data block in the first queue, it is specifically used to: insert the third target data block at the head of the first queue;

[0167] When storing the third target data block in the third queue, the storage module is specifically configured to: insert the third target data block at the queue head of the third queue.

[0168] Optionally, when determining at least one first target page requested by the target request, the first determining module 132 is specifically configured to:

[0169] determining a target logical page number of each first target page in at least one first target page;

[0170] Determine a target physical address that has a mapping relationship with the target logical page number based on a mapping relationship between the physical address and the logical page number in the metadata;

[0171] At least one page at the target physical address is determined as a first target page.

[0172] It should be noted that the cache management device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principles and beneficial effects are similar, which will not be repeated here.

[0173] Figure 14 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 14 As shown, the electronic device 140 provided in this embodiment includes: at least one processor 1401 and a memory 1402. Optionally, the electronic device 140 further includes a communication component 1403. The processor 1401, the memory 1402 and the communication component 1403 are connected via a bus.

[0174] During the specific implementation process, at least one processor 1401 executes the computer-executable instructions stored in the memory 1402, so that the at least one processor 1401 executes the above-mentioned cache management method embodiment.

[0175] The specific implementation process of the processor 1401 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0176] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0177] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), exemplarily at least one disk storage.

[0178] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0179] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above cache management method embodiments when running.

[0180] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0181] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above cache management method embodiments are implemented.

[0182] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned cache management method embodiments are implemented.

[0183] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0184] The above is a detailed introduction to a cache management method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A cache management method, characterized in that: include: Receive target request; In a case where the target request is a read request, determining at least one first target page requested by the target request; If the at least one first target page is stored in the first queue, determining a first target data block to which the at least one first target page belongs, the first target data block including a plurality of first pages, and the at least one first target page being a portion of the plurality of first pages; determining that at least one first target page in the first target data block constitutes a second target data block, and storing the second target data block in a second queue; The storing the second target data block in the second queue includes: storing the second target data block in the second queue if the first number of the at least one first target page is greater than or equal to a page threshold; The method further comprises: When the first number is smaller than the page threshold, the second target data block is stored in a third queue.

2. The cache management method according to claim 1, wherein: In the case where the target request is a write request, the method further includes: Determining a third target data block to be written by the target request, wherein the third target data block includes: at least one third page; storing the third target data block in the first queue if the second number of the at least one third page is greater than or equal to the page threshold; When the second number is smaller than the page threshold, the third target data block is stored in the third queue.

3. The cache management method according to claim 2, wherein: The method further comprises: Get the average data volume of a preset number of historical write requests; obtaining an average page hit ratio of the preset number of ejected data blocks, wherein the ejected data blocks are ejected from the third queue; Get the first data amount of a page; The page threshold is determined according to the average data volume, the average page hit ratio, and the first data volume.

4. The cache management method according to any one of claims 1 to 3, characterized in that: Also includes: If the at least one first target page is stored in the second queue, determining a fourth target data block to which the at least one first target page belongs, the fourth target data block including a plurality of fourth pages, the at least one first target page being a portion of the fourth pages; A fifth target data block composed of the at least one first target page is determined, and the fifth target data block is stored in a third queue.

5. The cache management method according to any one of claims 1 to 3, characterized in that: Also includes: Determining at least one first target queue that has reached a capacity limit, where the at least one first target queue is at least one of the first queue, the second queue, and the third queue; For each of the at least one first target queue, determining a sixth target data block at the tail of the first target queue; If at least one seventh target data block is stored in the second target queue, combining the sixth target data block and the at least one seventh target data block to obtain an eighth target data block, the sixth target data block and the at least one seventh target data block being data blocks written by the same write request; If the at least one seventh target data block is not stored in the second target queue, determining that the sixth target data block is the eighth target data block; The eighth target data block is ejected.

6. The cache management method according to claim 5, characterized in that: If the number of the eighth target data block is greater than 1, the step of popping out the eighth target data block includes: Determining an order in which the plurality of eighth target data blocks are to be popped out; According to the popping order, a plurality of the eighth target data blocks are popped out in sequence.

7. The cache management method according to claim 6, wherein: Determining the popping order of the plurality of eighth target data blocks includes: determining, for each of the plurality of eighth target data blocks, an access frequency of the eighth target data block; The ejection order is determined according to the access frequency, wherein the access frequency and the ejection order are positively correlated.

8. The cache management method according to claim 7, wherein: Determining the access frequency of the eighth target data block includes: Obtaining a total number of times the eighth target data block is hit; Obtaining the number of pages included in the eighth target data block; Determining the most recent hit time of the eighth target data block and the current time; The access frequency of the eighth target data block is determined according to the total number of times, the number of pages, the hit time and the current time.

9. The cache management method according to claim 8, characterized in that: The determining the access frequency of the eighth target data block according to the total number of times, the number of pages, the hit time, and the current time includes: Get the preset pop-up time rate and pop-up time interval; determining a first product of the ejection time rate and the ejection time interval; Determine the time difference between the hit moment and the current moment; determining a first value according to the first product, the number of pages, and the time difference; The ratio of the total number of times to the first value is determined as the access frequency.

10. The cache management method according to claim 2 or 3, characterized in that: The storing the third target data block in the first queue includes: inserting the third target data block at the head of the first queue; Storing the third target data block in the third queue includes: inserting the third target data block at the head of the third queue.

11. The cache management method according to any one of claims 1 to 3, characterized in that: The determining of at least one first target page requested by the target request includes: determining a target logical page number of each first target page in the at least one first target page; Determining a target physical address having a mapping relationship with the target logical page number according to a mapping relationship between the physical address and the logical page number in the metadata; At least one page at the target physical address is determined as the first target page.

12. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the cache management method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the cache management method according to any one of claims 1 to 11.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the cache management method according to any one of claims 1 to 11 are implemented.

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